esp_rom: override i2c_reg ops api in rom phy

components/esp_rom/CMakeLists.txt

@@ -18,9 +18,14 @@ else()
                         "patches/esp_rom_sys.c"
                         "patches/esp_rom_uart.c"
                         "patches/esp_rom_spiflash.c"
-                        "patches/esp_rom_regi2c.c"
                         "patches/esp_rom_efuse.c")
 
+
+# Override regi2c implementation in ROM
+if(EXISTS "${CMAKE_CURRENT_SOURCE_DIR}/patches/esp_rom_regi2c_${target}.c")
+    list(APPEND sources "patches/esp_rom_regi2c_${target}.c")
+endif()
+
     if(CONFIG_HEAP_TLSF_USE_ROM_IMPL AND CONFIG_ESP_ROM_TLSF_CHECK_PATCH)
         # This file shall be included in the build if TLSF in ROM is activated
         list(APPEND sources "patches/esp_rom_tlsf.c")

components/esp_rom/esp32c6/ld/esp32c6.rom.api.ld

@@ -53,8 +53,3 @@ PROVIDE ( esp_rom_spiflash_fix_dummylen = spi_dummy_len_fix );
 PROVIDE ( esp_rom_spiflash_set_drvs = SetSpiDrvs);
 PROVIDE ( esp_rom_spiflash_select_padsfunc = SelectSpiFunction );
 PROVIDE ( esp_rom_spiflash_common_cmd = SPI_Common_Command );
-
-PROVIDE ( esp_rom_regi2c_read = rom_i2c_readReg );
-PROVIDE ( esp_rom_regi2c_read_mask = rom_i2c_readReg_Mask );
-PROVIDE ( esp_rom_regi2c_write = rom_i2c_writeReg );
-PROVIDE ( esp_rom_regi2c_write_mask = rom_i2c_writeReg_Mask );

components/esp_rom/esp32c6/ld/esp32c6.rom.phy.ld

@@ -128,11 +128,7 @@ rom_get_i2c_mst0_mask = 0x400012ac;
 rom_get_i2c_hostid = 0x400012b0;
 rom_chip_i2c_readReg_org = 0x400012b4;
 rom_chip_i2c_readReg = 0x400012b8;
-rom_i2c_readReg = 0x400012bc;
 rom_chip_i2c_writeReg = 0x400012c0;
-rom_i2c_writeReg = 0x400012c4;
-rom_i2c_readReg_Mask = 0x400012c8;
-rom_i2c_writeReg_Mask = 0x400012cc;
 rom_set_txcap_reg = 0x400012d0;
 i2c_paral_set_mst0 = 0x400012d4;
 i2c_paral_set_read = 0x400012d8;

components/esp_rom/patches/esp_rom_regi2c_esp32c6.c

@@ -0,0 +1,193 @@
+/*
+ * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include "esp_rom_sys.h"
+#include "soc/lp_i2c_ana_mst_reg.h"
+#include "modem/modem_lpcon_reg.h"
+/**
+ * BB    - 0x67 - BIT0
+ * TXRF  - 0x6B - BIT1
+ * SDM   - 0x63 - BIT2
+ * PLL   - 0x62 - BIT3
+ * BIAS  - 0x6A - BIT4
+ * BBPLL - 0x66 - BIT5
+ * ULP   - 0x61 - BIT6
+ * SAR   - 0x69 - BIT7
+ * PMU   - 0x6d - BIT8
+*/
+#define REGI2C_ULP_CAL_DEVICE_EN  (BIT(6))
+#define REGI2C_SAR_I2C_DEVICE_EN  (BIT(7))
+#define REGI2C_BBPLL_DEVICE_EN    (BIT(5))
+#define REGI2C_BIAS_DEVICE_EN     (BIT(4))
+#define REGI2C_DIG_REG_DEVICE_EN  (BIT(8))
+
+#define REGI2C_RTC_BUSY           (BIT(25))
+#define REGI2C_RTC_BUSY_M         (BIT(25))
+#define REGI2C_RTC_BUSY_V         0x1
+#define REGI2C_RTC_BUSY_S         25
+
+#define REGI2C_RTC_WR_CNTL        (BIT(24))
+#define REGI2C_RTC_WR_CNTL_M      (BIT(24))
+#define REGI2C_RTC_WR_CNTL_V      0x1
+#define REGI2C_RTC_WR_CNTL_S      24
+
+#define REGI2C_RTC_DATA           0x000000FF
+#define REGI2C_RTC_DATA_M         ((I2C_RTC_DATA_V)<<(I2C_RTC_DATA_S))
+#define REGI2C_RTC_DATA_V         0xFF
+#define REGI2C_RTC_DATA_S         16
+
+#define REGI2C_RTC_ADDR           0x000000FF
+#define REGI2C_RTC_ADDR_M         ((I2C_RTC_ADDR_V)<<(I2C_RTC_ADDR_S))
+#define REGI2C_RTC_ADDR_V         0xFF
+#define REGI2C_RTC_ADDR_S         8
+
+#define REGI2C_RTC_SLAVE_ID       0x000000FF
+#define REGI2C_RTC_SLAVE_ID_M     ((I2C_RTC_SLAVE_ID_V)<<(I2C_RTC_SLAVE_ID_S))
+#define REGI2C_RTC_SLAVE_ID_V     0xFF
+#define REGI2C_RTC_SLAVE_ID_S     0
+
+/* SLAVE */
+
+#define REGI2C_BBPLL              (0x66)
+#define REGI2C_BBPLL_HOSTID       0
+
+#define REGI2C_BIAS               (0x6a)
+#define REGI2C_BIAS_HOSTID        0
+
+#define REGI2C_DIG_REG            (0x6d)
+#define REGI2C_DIG_REG_HOSTID     0
+
+#define REGI2C_ULP_CAL            (0x61)
+#define REGI2C_ULP_CAL_HOSTID     0
+
+#define REGI2C_SAR_I2C            (0x69)
+#define REGI2C_SAR_I2C_HOSTID     0
+
+/* SLAVE END */
+
+#define REGI2C_RTC_MAGIC_DEFAULT (0x1C610)
+
+static void regi2c_enable_block(uint8_t block)
+{
+    REG_SET_BIT(MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN);
+    REG_SET_BIT(LP_I2C_ANA_MST_DATE_REG, LP_I2C_ANA_MST_I2C_MAT_CLK_EN);
+
+    /* Before config I2C register, enable corresponding slave. */
+    switch (block) {
+    case REGI2C_BBPLL  :
+        REG_SET_BIT(LP_I2C_ANA_MST_DEVICE_EN_REG, REGI2C_BBPLL_DEVICE_EN);
+        break;
+    case REGI2C_BIAS   :
+        REG_SET_BIT(LP_I2C_ANA_MST_DEVICE_EN_REG, REGI2C_BIAS_DEVICE_EN);
+        break;
+    case REGI2C_DIG_REG:
+        REG_SET_BIT(LP_I2C_ANA_MST_DEVICE_EN_REG, REGI2C_DIG_REG_DEVICE_EN);
+        break;
+    case REGI2C_ULP_CAL:
+        REG_SET_BIT(LP_I2C_ANA_MST_DEVICE_EN_REG, REGI2C_ULP_CAL_DEVICE_EN);
+        break;
+    case REGI2C_SAR_I2C:
+        REG_SET_BIT(LP_I2C_ANA_MST_DEVICE_EN_REG, REGI2C_SAR_I2C_DEVICE_EN);
+        break;
+    default:
+        return;
+    }
+}
+
+static void regi2c_disable_block(uint8_t block)
+{
+    switch (block) {
+    case REGI2C_BBPLL  :
+        REG_CLR_BIT(LP_I2C_ANA_MST_DEVICE_EN_REG, REGI2C_BBPLL_DEVICE_EN);
+        break;
+    case REGI2C_BIAS   :
+        REG_CLR_BIT(LP_I2C_ANA_MST_DEVICE_EN_REG, REGI2C_BIAS_DEVICE_EN);
+        break;
+    case REGI2C_DIG_REG:
+        REG_CLR_BIT(LP_I2C_ANA_MST_DEVICE_EN_REG, REGI2C_DIG_REG_DEVICE_EN);
+        break;
+    case REGI2C_ULP_CAL:
+        REG_CLR_BIT(LP_I2C_ANA_MST_DEVICE_EN_REG, REGI2C_ULP_CAL_DEVICE_EN);
+        break;
+    case REGI2C_SAR_I2C:
+        REG_CLR_BIT(LP_I2C_ANA_MST_DEVICE_EN_REG, REGI2C_SAR_I2C_DEVICE_EN);
+        break;
+    default:
+        return;
+    }
+
+    REG_CLR_BIT(LP_I2C_ANA_MST_DATE_REG, LP_I2C_ANA_MST_I2C_MAT_CLK_EN);
+    REG_CLR_BIT(MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN);
+}
+
+uint8_t esp_rom_regi2c_read(uint8_t block, uint8_t host_id, uint8_t reg_add)
+{
+    regi2c_enable_block(block);
+
+    (void)host_id;
+    uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S)
+                    | (reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S;
+    REG_WRITE(LP_I2C_ANA_MST_I2C0_CTRL_REG, temp);
+    while (REG_GET_BIT(LP_I2C_ANA_MST_I2C0_CTRL_REG, LP_I2C_ANA_MST_I2C0_BUSY));
+    return REG_GET_FIELD(LP_I2C_ANA_MST_I2C0_DATA_REG, LP_I2C_ANA_MST_I2C0_RDATA);
+
+    regi2c_disable_block(block);
+}
+
+uint8_t esp_rom_regi2c_read_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb)
+{
+    assert(msb - lsb < 8);
+    regi2c_enable_block(block);
+
+    (void)host_id;
+    uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S)
+                    | (reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S;
+    REG_WRITE(LP_I2C_ANA_MST_I2C0_CTRL_REG, temp);
+    while (REG_GET_BIT(LP_I2C_ANA_MST_I2C0_CTRL_REG, LP_I2C_ANA_MST_I2C0_BUSY));
+    uint32_t data = REG_GET_FIELD(LP_I2C_ANA_MST_I2C0_DATA_REG, LP_I2C_ANA_MST_I2C0_RDATA);
+    return (uint8_t)((data >> lsb) & (~(0xFFFFFFFF << (msb - lsb + 1))));
+
+    regi2c_disable_block(block);
+}
+
+void esp_rom_regi2c_write(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data)
+{
+    (void)host_id;
+    regi2c_enable_block(block);
+
+    uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S)
+                    | ((reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S)
+                    | ((0x1 & REGI2C_RTC_WR_CNTL_V) << REGI2C_RTC_WR_CNTL_S) // 0: READ I2C register; 1: Write I2C register;
+                    | (((uint32_t)data & REGI2C_RTC_DATA_V) << REGI2C_RTC_DATA_S);
+    REG_WRITE(LP_I2C_ANA_MST_I2C0_CTRL_REG, temp);
+    while (REG_GET_BIT(LP_I2C_ANA_MST_I2C0_CTRL_REG, LP_I2C_ANA_MST_I2C0_BUSY));
+
+    regi2c_disable_block(block);
+}
+
+void esp_rom_regi2c_write_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data)
+{
+    (void)host_id;
+    assert(msb - lsb < 8);
+    regi2c_enable_block(block);
+
+    /*Read the i2c bus register*/
+    uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S)
+                    | (reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S;
+    REG_WRITE(LP_I2C_ANA_MST_I2C0_CTRL_REG, temp);
+    while (REG_GET_BIT(LP_I2C_ANA_MST_I2C0_CTRL_REG, LP_I2C_ANA_MST_I2C0_BUSY));
+    temp = REG_GET_FIELD(LP_I2C_ANA_MST_I2C0_DATA_REG, LP_I2C_ANA_MST_I2C0_RDATA);
+    /*Write the i2c bus register*/
+    temp &= ((~(0xFFFFFFFF << lsb)) | (0xFFFFFFFF << (msb + 1)));
+    temp = (((uint32_t)data & (~(0xFFFFFFFF << (msb - lsb + 1)))) << lsb) | temp;
+    temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S)
+            | ((reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S)
+            | ((0x1 & REGI2C_RTC_WR_CNTL_V) << REGI2C_RTC_WR_CNTL_S)
+            | ((temp & REGI2C_RTC_DATA_V) << REGI2C_RTC_DATA_S);
+    REG_WRITE(LP_I2C_ANA_MST_I2C0_CTRL_REG, temp);
+    while (REG_GET_BIT(LP_I2C_ANA_MST_I2C0_CTRL_REG, LP_I2C_ANA_MST_I2C0_BUSY));
+
+    regi2c_disable_block(block);
+}

components/esp_rom/patches/esp_rom_regi2c.c → components/esp_rom/patches/esp_rom_regi2c_esp32s2.c

@@ -9,7 +9,6 @@
 #include "esp_rom_caps.h"
 #include "sdkconfig.h"
 
-#if CONFIG_IDF_TARGET_ESP32S2
 #include "soc/syscon_reg.h"
 
 #define I2C_RTC_WIFI_CLK_EN (SYSCON_WIFI_CLK_EN_REG)
@@ -165,4 +164,3 @@ void esp_rom_regi2c_write_mask(uint8_t block, uint8_t host_id, uint8_t reg_add,
     REG_WRITE(I2C_RTC_CONFIG2, temp);
     while (REG_GET_BIT(I2C_RTC_CONFIG2, I2C_RTC_BUSY));
 }
-#endif //CONFIG_IDF_TARGET_ESP32S2