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@@ -0,0 +1,479 @@
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+/*
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+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
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+ *
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+ * SPDX-License-Identifier: Apache-2.0
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+ */
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+
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+#include "ulp_lp_core_i2c.h"
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+#include "ulp_lp_core_utils.h"
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+#include "soc/lp_i2c_reg.h"
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+#include "soc/i2c_struct.h"
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+#include "hal/i2c_ll.h"
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+
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+#define LP_I2C_FIFO_LEN SOC_LP_I2C_FIFO_LEN
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+#define LP_I2C_READ_MODE I2C_MASTER_READ
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+#define LP_I2C_WRITE_MODE I2C_MASTER_WRITE
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+#define LP_I2C_ACK I2C_MASTER_ACK
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+#define LP_I2C_NACK I2C_MASTER_NACK
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+
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+#define MIN(x, y) (((x) < (y)) ? (x) : (y))
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+
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+/* I2C LL context */
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+i2c_dev_t *dev = I2C_LL_GET_HW(LP_I2C_NUM_0);
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+
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+/* ACK check enable control variable. Enabled by default */
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+static bool s_ack_check_en = true;
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+
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+/*
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+ * The LP I2C controller uses the LP I2C HW command registers to perform read/write operations.
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+ * The cmd registers have the following format:
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+ *
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+ * 31 30:14 13:11 10 9 8 7:0
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+ * |----------|----------|---------|---------|----------|------------|---------|
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+ * | CMD_DONE | Reserved | OPCODE |ACK Value|ACK Expect|ACK Check En|Byte Num |
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+ * |----------|----------|---------|---------|----------|------------|---------|
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+ */
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+static void lp_core_i2c_format_cmd(uint32_t cmd_idx, uint8_t op_code, uint8_t ack_val,
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+ uint8_t ack_expected, uint8_t ack_check_en, uint8_t byte_num)
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+{
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+ if (cmd_idx >= sizeof(dev->command)) {
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+ /* We only have limited HW command registers.
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+ * Although unlikely, make sure that we do not write to an out of bounds index.
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+ */
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+ return;
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+ }
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+
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+ /* Form new command */
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+ i2c_ll_hw_cmd_t hw_cmd = {
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+ .done = 0, // CMD Done
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+ .op_code = op_code, // Opcode
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+ .ack_val = ack_val, // ACK bit sent by I2C controller during READ.
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+ // Ignored during RSTART, STOP, END and WRITE cmds.
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+ .ack_exp = ack_expected, // ACK bit expected by I2C controller during WRITE.
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+ // Ignored during RSTART, STOP, END and READ cmds.
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+ .ack_en = ack_check_en, // I2C controller verifies that the ACK bit sent by the
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+ // slave device matches the ACK expected bit during WRITE.
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+ // Ignored during RSTART, STOP, END and READ cmds.
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+ .byte_num = byte_num, // Byte Num
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+ };
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+
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+ /* Write new command to cmd register */
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+ i2c_ll_write_cmd_reg(dev, hw_cmd, cmd_idx);
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+}
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+
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+static inline esp_err_t lp_core_i2c_wait_for_interrupt(uint32_t intr_mask, int32_t ticks_to_wait)
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+{
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+ uint32_t intr_status = 0;
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+ uint32_t to = 0;
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+
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+ while (1) {
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+ i2c_ll_get_intr_mask(dev, &intr_status);
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+ if (intr_status & intr_mask) {
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+ if (intr_status & LP_I2C_NACK_INT_ST) {
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+ /* The ACK/NACK received during a WRITE operation does not match the expected ACK/NACK level
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+ * Abort and return an error.
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+ */
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+ i2c_ll_clear_intr_mask(dev, intr_mask);
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+ return ESP_ERR_INVALID_RESPONSE;
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+ } else if (intr_status & LP_I2C_TRANS_COMPLETE_INT_ST_M) {
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+ /* Transaction complete.
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+ * Disable and clear interrupt bits and break
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+ */
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+ i2c_ll_disable_intr_mask(dev, intr_mask);
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+ i2c_ll_clear_intr_mask(dev, intr_mask);
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+ break;
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+ } else {
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+ /* We received an I2C_END_DETECT_INT.
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+ * This means we are not yet done with the transaction.
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+ * Simply clear the interrupt bit and break.
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+ */
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+ i2c_ll_clear_intr_mask(dev, intr_mask);
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+ break;
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+ }
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+ break;
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+ }
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+
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+ if (ticks_to_wait > -1) {
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+ /* If the ticks_to_wait value is not -1, keep track of ticks and
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+ * break from the loop once the timeout is reached.
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+ */
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+ ulp_lp_core_delay_cycles(1);
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+ to++;
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+ if (to >= ticks_to_wait) {
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+ /* Disable and clear interrupt bits */
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+ i2c_ll_disable_intr_mask(dev, intr_mask);
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+ i2c_ll_clear_intr_mask(dev, intr_mask);
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+ return ESP_ERR_TIMEOUT;
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+ }
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+ }
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+ }
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+
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+ /* We reach here only if we are in a good state */
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+ return ESP_OK;
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+}
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+
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+static inline void lp_core_i2c_config_device_addr(uint32_t cmd_idx, uint16_t device_addr, uint32_t rw_mode, uint8_t *addr_len)
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+{
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+ uint8_t data_byte = 0;
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+ uint8_t data_len = 0;
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+
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+ /* 7-bit addressing mode. We do not support 10-bit addressing mode yet (IDF-7364) */
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+
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+ // Write the device address + R/W mode in the first Tx FIFO slot
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+ data_byte = (uint8_t)(((device_addr & 0xFF) << 1) | (rw_mode << 0));
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+ i2c_ll_write_txfifo(dev, &data_byte, 1);
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+ data_len++;
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+
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+ /* Update the HW command register. Expect an ACK from the device */
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+ lp_core_i2c_format_cmd(cmd_idx, I2C_LL_CMD_WRITE, 0, LP_I2C_ACK, s_ack_check_en, data_len);
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+
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+ /* Return the address length in bytes */
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+ *addr_len = data_len;
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+}
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+
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+void lp_core_i2c_master_set_ack_check_en(i2c_port_t lp_i2c_num, bool ack_check_en)
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+{
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+ (void)lp_i2c_num;
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+
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+ s_ack_check_en = ack_check_en;
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+}
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+
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+esp_err_t lp_core_i2c_master_read_from_device(i2c_port_t lp_i2c_num, uint16_t device_addr,
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+ uint8_t *data_rd, size_t size,
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+ int32_t ticks_to_wait)
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+{
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+ (void)lp_i2c_num;
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+
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+ esp_err_t ret = ESP_OK;
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+ uint32_t cmd_idx = 0;
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+
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+ if (size == 0) {
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+ // Quietly return
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+ return ESP_OK;
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+ } else if (size > UINT8_MAX) {
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+ // HW register only has an 8-bit byte-num field
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+ return ESP_ERR_INVALID_SIZE;
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+ }
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+
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+ /* Execute RSTART command to send the START bit */
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+ lp_core_i2c_format_cmd(cmd_idx++, I2C_LL_CMD_RESTART, 0, 0, 0, 0);
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+
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+ /* Write device addr and update the HW command register */
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+ uint8_t addr_len = 0;
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+ lp_core_i2c_config_device_addr(cmd_idx++, device_addr, LP_I2C_READ_MODE, &addr_len);
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+
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+ /* Enable trans complete interrupt and end detect interrupt for read/write operation */
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+ uint32_t intr_mask = (1 << LP_I2C_TRANS_COMPLETE_INT_ST_S) | (1 << LP_I2C_END_DETECT_INT_ST_S);
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+ i2c_ll_enable_intr_mask(dev, intr_mask);
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+
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+ /* Read data */
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+ uint32_t fifo_size = 0;
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+ uint32_t data_idx = 0;
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+ int32_t remaining_bytes = size;
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+
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+ /* The data is received in sequential slots of the Rx FIFO.
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+ * We must account for FIFO wraparound in case the length of data being received is greater than LP_I2C_FIFO_LEN.
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+ */
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+ while (remaining_bytes > 0) {
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+ /* Select the amount of data that fits in the Rx FIFO */
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+ fifo_size = MIN(remaining_bytes, LP_I2C_FIFO_LEN);
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+
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+ /* Update the number of bytes remaining to be read */
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+ remaining_bytes -= fifo_size;
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+
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+ /* Update HW command register to read bytes */
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+ if (fifo_size == 1) {
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+ /* Read 1 byte and send NACK */
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+ lp_core_i2c_format_cmd(cmd_idx++, I2C_LL_CMD_READ, LP_I2C_NACK, 0, 0, 1);
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+
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+ /* STOP */
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+ lp_core_i2c_format_cmd(cmd_idx++, I2C_LL_CMD_STOP, 0, 0, 0, 0);
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+ } else if ((fifo_size > 1) && (remaining_bytes == 0)) {
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+ /* This means it is the last transaction.
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+ * Read fifo_size - 1 bytes and send ACKs
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+ */
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+ lp_core_i2c_format_cmd(cmd_idx++, I2C_LL_CMD_READ, LP_I2C_ACK, 0, 0, fifo_size - 1);
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+
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+ /* Read last byte and send NACK */
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+ lp_core_i2c_format_cmd(cmd_idx++, I2C_LL_CMD_READ, LP_I2C_NACK, 0, 0, 1);
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+
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+ /* STOP */
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+ lp_core_i2c_format_cmd(cmd_idx++, I2C_LL_CMD_STOP, 0, 0, 0, 0);
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+ } else {
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+ /* This means we have to read data more than what can fit in the Rx FIFO.
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+ * Read fifo_size bytes and send ACKs
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+ */
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+ lp_core_i2c_format_cmd(cmd_idx++, I2C_LL_CMD_READ, LP_I2C_ACK, 0, 0, fifo_size);
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+ lp_core_i2c_format_cmd(cmd_idx++, I2C_LL_CMD_END, 0, 0, 0, 0);
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+ cmd_idx = 0;
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+ }
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+
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+ /* Initiate I2C transfer */
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+ i2c_ll_update(dev);
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+ i2c_ll_trans_start(dev);
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+
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+ /* Wait for the transfer to complete */
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+ ret = lp_core_i2c_wait_for_interrupt(intr_mask, ticks_to_wait);
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+ if (ret != ESP_OK) {
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+ /* Transaction error. Abort. */
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+ return ret;
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+ }
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+
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+ /* Read Rx FIFO */
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+ i2c_ll_read_rxfifo(dev, &data_rd[data_idx], fifo_size);
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+
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+ /* Update data_idx */
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+ data_idx += fifo_size;
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+ }
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+
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+ return ret;
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+}
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+
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+esp_err_t lp_core_i2c_master_write_to_device(i2c_port_t lp_i2c_num, uint16_t device_addr,
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+ const uint8_t *data_wr, size_t size,
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+ int32_t ticks_to_wait)
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+{
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+ (void)lp_i2c_num;
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+
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+ esp_err_t ret = ESP_OK;
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+ uint32_t cmd_idx = 0;
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+
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+ if (size == 0) {
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+ // Quietly return
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+ return ESP_OK;
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+ } else if (size > UINT8_MAX) {
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+ // HW register only has an 8-bit byte-num field
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+ return ESP_ERR_INVALID_SIZE;
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+ }
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+
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+ /* If SCL is busy, reset the Master FSM */
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+ if (i2c_ll_is_bus_busy(dev)) {
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+ i2c_ll_master_fsm_rst(dev);
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+ }
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+
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+ /* Reset the Tx and Rx FIFOs */
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+ i2c_ll_txfifo_rst(dev);
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+ i2c_ll_rxfifo_rst(dev);
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+
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+ /* Execute RSTART command to send the START bit */
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+ lp_core_i2c_format_cmd(cmd_idx++, I2C_LL_CMD_RESTART, 0, 0, 0, 0);
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+
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+ /* Write device addr and update the HW command register */
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+ uint8_t addr_len = 0;
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+ lp_core_i2c_config_device_addr(cmd_idx++, device_addr, LP_I2C_WRITE_MODE, &addr_len);
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+
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+ /* Enable trans complete interrupt and end detect interrupt for read/write operation */
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+ uint32_t intr_mask = (1 << LP_I2C_TRANS_COMPLETE_INT_ST_S) | (1 << LP_I2C_END_DETECT_INT_ST_S);
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+ if (s_ack_check_en) {
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+ /* Enable LP_I2C_NACK_INT to check for ACK errors */
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+ intr_mask |= (1 << LP_I2C_NACK_INT_ST_S);
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+ }
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+ i2c_ll_enable_intr_mask(dev, intr_mask);
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+
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+ /* Write data */
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+ uint32_t fifo_available = LP_I2C_FIFO_LEN - addr_len; // Initially, 1 or 2 fifo slots are taken by the device address
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+ uint32_t fifo_size = 0;
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+ uint32_t data_idx = 0;
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+ int32_t remaining_bytes = size;
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+
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+ /* The data to be sent must occupy sequential slots of the Tx FIFO.
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+ * We must account for FIFO wraparound in case the length of data being sent is greater than LP_I2C_FIFO_LEN.
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+ */
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+ while (remaining_bytes > 0) {
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+ /* Select the amount of data that fits in the Tx FIFO */
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+ fifo_size = MIN(remaining_bytes, fifo_available);
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+
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+ /* Update the number of bytes remaining to be sent */
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+ remaining_bytes -= fifo_size;
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+
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+ /* Write data to the Tx FIFO and update the HW command register. Expect ACKs from the device */
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+ i2c_ll_write_txfifo(dev, &data_wr[data_idx], fifo_size);
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+ lp_core_i2c_format_cmd(cmd_idx++, I2C_LL_CMD_WRITE, 0, LP_I2C_ACK, s_ack_check_en, fifo_size);
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+
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+ if (remaining_bytes == 0) {
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+ /* This means it is the last transaction. Insert a Stop command. */
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+ lp_core_i2c_format_cmd(cmd_idx++, I2C_LL_CMD_STOP, 0, 0, 0, 0);
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+ } else {
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+ /* This means we have to send more than what can fit in the Tx FIFO. Insert an End command. */
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+ lp_core_i2c_format_cmd(cmd_idx++, I2C_LL_CMD_END, 0, 0, 0, 0);
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+ cmd_idx = 0;
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+ }
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+
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+ /* Initiate I2C transfer */
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+ i2c_ll_update(dev);
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+ i2c_ll_trans_start(dev);
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+
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+ /* Wait for the transfer to complete */
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+ ret = lp_core_i2c_wait_for_interrupt(intr_mask, ticks_to_wait);
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+ if (ret != ESP_OK) {
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+ /* Transaction error. Abort. */
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+ return ret;
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+ }
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+
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+ /* Update data_idx */
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+ data_idx += fifo_size;
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+
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+ /* We now have the full fifo available for writing */
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+ fifo_available = LP_I2C_FIFO_LEN;
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+ }
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+
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+ return ret;
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+}
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+
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+esp_err_t lp_core_i2c_master_write_read_device(i2c_port_t lp_i2c_num, uint16_t device_addr,
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+ const uint8_t *data_wr, size_t write_size,
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+ uint8_t *data_rd, size_t read_size,
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+ int32_t ticks_to_wait)
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+{
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+ (void)lp_i2c_num;
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+
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+ esp_err_t ret = ESP_OK;
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+ uint32_t cmd_idx = 0;
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+
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+ if ((write_size == 0) || (read_size == 0)) {
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+ // Quietly return
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+ return ESP_OK;
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+ } else if ((write_size > UINT8_MAX) || (read_size > UINT8_MAX)) {
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+ // HW register only has an 8-bit byte-num field
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+ return ESP_ERR_INVALID_SIZE;
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+ }
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+
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+ /* If SCL is busy, reset the Master FSM */
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+ if (i2c_ll_is_bus_busy(dev)) {
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+ i2c_ll_master_fsm_rst(dev);
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+ }
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+
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+ /* Reset the Tx and Rx FIFOs */
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+ i2c_ll_txfifo_rst(dev);
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+ i2c_ll_rxfifo_rst(dev);
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+
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+ /* Enable trans complete interrupt and end detect interrupt for read/write operation */
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+ uint32_t intr_mask = (1 << LP_I2C_TRANS_COMPLETE_INT_ST_S) | (1 << LP_I2C_END_DETECT_INT_ST_S);
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+ if (s_ack_check_en) {
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+ /* Enable LP_I2C_NACK_INT to check for ACK errors */
|
|
|
+ intr_mask |= (1 << LP_I2C_NACK_INT_ST_S);
|
|
|
+ }
|
|
|
+ i2c_ll_enable_intr_mask(dev, intr_mask);
|
|
|
+
|
|
|
+ /* Execute RSTART command to send the START bit */
|
|
|
+ lp_core_i2c_format_cmd(cmd_idx++, I2C_LL_CMD_RESTART, 0, 0, 0, 0);
|
|
|
+
|
|
|
+ /* Write device addr and update the HW command register */
|
|
|
+ uint8_t addr_len = 0;
|
|
|
+ lp_core_i2c_config_device_addr(cmd_idx++, device_addr, LP_I2C_WRITE_MODE, &addr_len);
|
|
|
+
|
|
|
+ /* Write data */
|
|
|
+ uint32_t fifo_available = LP_I2C_FIFO_LEN - addr_len; // Initially, 1 or 2 fifo slots are taken by the device address
|
|
|
+ uint32_t fifo_size = 0;
|
|
|
+ uint32_t data_idx = 0;
|
|
|
+ int32_t remaining_bytes = write_size;
|
|
|
+
|
|
|
+ /* The data to be sent must occupy sequential slots of the Tx FIFO.
|
|
|
+ * We must account for FIFO wraparound in case the length of data being sent is greater than LP_I2C_FIFO_LEN.
|
|
|
+ */
|
|
|
+ while (remaining_bytes > 0) {
|
|
|
+ /* Select the amount of data that fits in the Tx FIFO */
|
|
|
+ fifo_size = MIN(remaining_bytes, fifo_available);
|
|
|
+
|
|
|
+ /* Update the number of bytes remaining to be sent */
|
|
|
+ remaining_bytes -= fifo_size;
|
|
|
+
|
|
|
+ /* Write data to the Tx FIFO and update the HW command register. Expect ACKs from the device */
|
|
|
+ i2c_ll_write_txfifo(dev, &data_wr[data_idx], fifo_size);
|
|
|
+ lp_core_i2c_format_cmd(cmd_idx++, I2C_LL_CMD_WRITE, 0, LP_I2C_ACK, s_ack_check_en, fifo_size);
|
|
|
+
|
|
|
+ if (remaining_bytes) {
|
|
|
+ /* This means we have to send more than what can fit in the Tx FIFO. Insert an End command. */
|
|
|
+ lp_core_i2c_format_cmd(cmd_idx++, I2C_LL_CMD_END, 0, 0, 0, 0);
|
|
|
+ cmd_idx = 0;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Initiate I2C transfer */
|
|
|
+ i2c_ll_update(dev);
|
|
|
+ i2c_ll_trans_start(dev);
|
|
|
+
|
|
|
+ /* Wait for the transfer to complete */
|
|
|
+ ret = lp_core_i2c_wait_for_interrupt(intr_mask, ticks_to_wait);
|
|
|
+ if (ret != ESP_OK) {
|
|
|
+ /* Transaction error. Abort. */
|
|
|
+ return ret;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Update data_idx */
|
|
|
+ data_idx += fifo_size;
|
|
|
+
|
|
|
+ /* We now have the full fifo available for writing */
|
|
|
+ fifo_available = LP_I2C_FIFO_LEN;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Reset command index */
|
|
|
+ cmd_idx = 0;
|
|
|
+
|
|
|
+ /* Execute RSTART command again to send a START condition for the read operation */
|
|
|
+ lp_core_i2c_format_cmd(cmd_idx++, I2C_LL_CMD_RESTART, 0, 0, 0, 0);
|
|
|
+
|
|
|
+ /* Write device addr again in read mode */
|
|
|
+ lp_core_i2c_config_device_addr(cmd_idx++, device_addr, LP_I2C_READ_MODE, &addr_len);
|
|
|
+
|
|
|
+ /* Read data */
|
|
|
+ fifo_size = 0;
|
|
|
+ data_idx = 0;
|
|
|
+ remaining_bytes = read_size;
|
|
|
+
|
|
|
+ /* The data is received in sequential slots of the Rx FIFO.
|
|
|
+ * We must account for FIFO wraparound in case the length of data being received is greater than LP_I2C_FIFO_LEN.
|
|
|
+ */
|
|
|
+ while (remaining_bytes > 0) {
|
|
|
+ /* Select the amount of data that fits in the Rx FIFO */
|
|
|
+ fifo_size = MIN(remaining_bytes, LP_I2C_FIFO_LEN);
|
|
|
+
|
|
|
+ /* Update the number of bytes remaining to be read */
|
|
|
+ remaining_bytes -= fifo_size;
|
|
|
+
|
|
|
+ /* Update HW command register to read bytes */
|
|
|
+ if (fifo_size == 1) {
|
|
|
+ /* Read 1 byte and send NACK */
|
|
|
+ lp_core_i2c_format_cmd(cmd_idx++, I2C_LL_CMD_READ, LP_I2C_NACK, 0, 0, 1);
|
|
|
+
|
|
|
+ /* STOP */
|
|
|
+ lp_core_i2c_format_cmd(cmd_idx++, I2C_LL_CMD_STOP, 0, 0, 0, 0);
|
|
|
+ } else if ((fifo_size > 1) && (remaining_bytes == 0)) {
|
|
|
+ /* This means it is the last transaction.
|
|
|
+ * Read fifo_size - 1 bytes and send ACKs
|
|
|
+ */
|
|
|
+ lp_core_i2c_format_cmd(cmd_idx++, I2C_LL_CMD_READ, LP_I2C_ACK, 0, 0, fifo_size - 1);
|
|
|
+
|
|
|
+ /* Read last byte and send NACK */
|
|
|
+ lp_core_i2c_format_cmd(cmd_idx++, I2C_LL_CMD_READ, LP_I2C_NACK, 0, 0, 1);
|
|
|
+
|
|
|
+ /* STOP */
|
|
|
+ lp_core_i2c_format_cmd(cmd_idx++, I2C_LL_CMD_STOP, 0, 0, 0, 0);
|
|
|
+ } else {
|
|
|
+ /* This means we have to read data more than what can fit in the Rx FIFO.
|
|
|
+ * Read fifo_size bytes and send ACKs
|
|
|
+ */
|
|
|
+ lp_core_i2c_format_cmd(cmd_idx++, I2C_LL_CMD_READ, LP_I2C_ACK, 0, 0, fifo_size);
|
|
|
+ lp_core_i2c_format_cmd(cmd_idx++, I2C_LL_CMD_END, 0, 0, 0, 0);
|
|
|
+ cmd_idx = 0;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Initiate I2C transfer */
|
|
|
+ i2c_ll_update(dev);
|
|
|
+ i2c_ll_trans_start(dev);
|
|
|
+
|
|
|
+ /* Wait for the transfer to complete */
|
|
|
+ ret = lp_core_i2c_wait_for_interrupt(intr_mask, ticks_to_wait);
|
|
|
+ if (ret != ESP_OK) {
|
|
|
+ /* Transaction error. Abort. */
|
|
|
+ return ret;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Read Rx FIFO */
|
|
|
+ i2c_ll_read_rxfifo(dev, &data_rd[data_idx], fifo_size);
|
|
|
+
|
|
|
+ /* Update data_idx */
|
|
|
+ data_idx += fifo_size;
|
|
|
+ }
|
|
|
+
|
|
|
+ return ret;
|
|
|
+}
|
Sudeep Mohanty