|
|
@@ -24,11 +24,9 @@ extern void IRAM_ATTR spi_flash_enable_interrupts_caches_and_other_cpu(void);
|
|
|
|
|
|
//Functions in librtc.a called by WIFI or Blutooth directly in ISR
|
|
|
#if SOC_BT_SUPPORTED
|
|
|
-extern void bt_bb_init_cmplx_reg(void);
|
|
|
extern void bt_track_pll_cap(void);
|
|
|
#endif
|
|
|
-extern void force_wifi_mode(int);
|
|
|
-extern void unforce_wifi_mode(void);
|
|
|
+
|
|
|
|
|
|
static const char* TAG = "test_phy_rtc";
|
|
|
|
|
|
@@ -56,6 +54,10 @@ static IRAM_ATTR void test_phy_rtc_cache_task(void *arg)
|
|
|
{
|
|
|
test_phy_rtc_init();
|
|
|
|
|
|
+#if CONFIG_IDF_TARGET_ESP32
|
|
|
+ extern void force_wifi_mode(int);
|
|
|
+ extern void unforce_wifi_mode(void);
|
|
|
+
|
|
|
for (int i = 0; i < 2; i++) {
|
|
|
ESP_LOGI(TAG, "Test force_wifi_mode(%d)...", i);
|
|
|
spi_flash_disable_interrupts_caches_and_other_cpu();
|
|
|
@@ -67,18 +69,38 @@ static IRAM_ATTR void test_phy_rtc_cache_task(void *arg)
|
|
|
unforce_wifi_mode();
|
|
|
spi_flash_enable_interrupts_caches_and_other_cpu();
|
|
|
}
|
|
|
+#endif //CONFIG_IDF_TARGET_ESP32
|
|
|
|
|
|
#if SOC_BT_SUPPORTED
|
|
|
+
|
|
|
+ ESP_LOGI(TAG, "Test bt_track_pll_cap()...");
|
|
|
+ spi_flash_disable_interrupts_caches_and_other_cpu();
|
|
|
+ bt_track_pll_cap();
|
|
|
+ spi_flash_enable_interrupts_caches_and_other_cpu();
|
|
|
+
|
|
|
+#if CONFIG_IDF_TARGET_ESP32
|
|
|
+ extern void bt_bb_init_cmplx_reg(void);
|
|
|
ESP_LOGI(TAG, "Test bt_bb_init_cmplx_reg()...");
|
|
|
spi_flash_disable_interrupts_caches_and_other_cpu();
|
|
|
bt_bb_init_cmplx_reg();
|
|
|
spi_flash_enable_interrupts_caches_and_other_cpu();
|
|
|
+#endif //CONFIG_IDF_TARGET_ESP32
|
|
|
|
|
|
- ESP_LOGI(TAG, "Test bt_track_pll_cap()...");
|
|
|
+#if CONFIG_IDF_TARGET_ESP32C3
|
|
|
+ extern void bt_bb_v2_init_cmplx(int print_version);
|
|
|
+ ESP_LOGI(TAG, "Test bt_bb_v2_init_cmplx()...");
|
|
|
spi_flash_disable_interrupts_caches_and_other_cpu();
|
|
|
- bt_track_pll_cap();
|
|
|
+ bt_bb_v2_init_cmplx(0);
|
|
|
spi_flash_enable_interrupts_caches_and_other_cpu();
|
|
|
-#endif
|
|
|
+
|
|
|
+ extern void coex_pti_v2(void);
|
|
|
+ ESP_LOGI(TAG, "Test coex_pti_v2()...");
|
|
|
+ spi_flash_disable_interrupts_caches_and_other_cpu();
|
|
|
+ coex_pti_v2();
|
|
|
+ spi_flash_enable_interrupts_caches_and_other_cpu();
|
|
|
+#endif //CONFIG_IDF_TARGET_ESP32C3
|
|
|
+
|
|
|
+#endif //SOC_BT_SUPPORTED
|
|
|
|
|
|
TEST_ASSERT( xSemaphoreGive(semphr_done) );
|
|
|
|
|
|
@@ -89,12 +111,11 @@ TEST_CASE("Test PHY/RTC functions called when cache is disabled", "[phy_rtc][cac
|
|
|
{
|
|
|
semphr_done = xSemaphoreCreateCounting(1, 0);
|
|
|
|
|
|
- xTaskCreatePinnedToCore(test_phy_rtc_cache_task, "phy_rtc_test_task", 2048,
|
|
|
+ xTaskCreatePinnedToCore(test_phy_rtc_cache_task, "phy_rtc_test_task", 3072,
|
|
|
NULL, configMAX_PRIORITIES-1, NULL, 0);
|
|
|
|
|
|
TEST_ASSERT( xSemaphoreTake(semphr_done, portMAX_DELAY) );
|
|
|
|
|
|
vSemaphoreDelete(semphr_done);
|
|
|
}
|
|
|
-
|
|
|
-#endif
|
|
|
+#endif //!TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2)
|