Merge branch 'bugfix/fix_rtcio_adc_driver_for_esp32' into 'release/v4.1'

rtc(adc/rtcio): fix adc rtcio driver for esp32

See merge request espressif/esp-idf!8347

components/driver/adc.c

@@ -512,8 +512,8 @@ static int hall_sensor_get_value(void)    //hall sensor without LNA
 
 int hall_sensor_read(void)
 {
-    adc_gpio_init(ADC_NUM_1, ADC1_CHANNEL_0);
-    adc_gpio_init(ADC_NUM_1, ADC1_CHANNEL_3);
+    adc_gpio_init(ADC_UNIT_1, ADC1_CHANNEL_0);
+    adc_gpio_init(ADC_UNIT_1, ADC1_CHANNEL_3);
     adc1_config_channel_atten(ADC1_CHANNEL_0, ADC_ATTEN_DB_0);
     adc1_config_channel_atten(ADC1_CHANNEL_3, ADC_ATTEN_DB_0);
     return hall_sensor_get_value();

components/soc/esp32/include/hal/adc_ll.h

@@ -199,18 +199,21 @@ static inline void adc_ll_set_pattern_table_len(adc_ll_num_t adc_n, uint32_t pat
  */
 static inline void adc_ll_set_pattern_table(adc_ll_num_t adc_n, uint32_t pattern_index, adc_ll_pattern_table_t pattern)
 {
+    /* There are 4 registers store 16 conversion rules. Each register `saradc_sar1_patt_tab` save 4 conversion rules.
+    Bit map [31:24] for `n + 1` item, [23:16] for `n + 2` item, [15:8] for `n + 3` item, [7:0] for `n + 4` item.*/
     uint32_t tab;
-    uint8_t *arg;
+    uint8_t index = pattern_index / 4;
+    uint8_t offset = (pattern_index % 4) * 8;
     if (adc_n == ADC_NUM_1) {
-        tab = SYSCON.saradc_sar1_patt_tab[pattern_index / 4];
-        arg = (uint8_t *)&tab;
-        arg[pattern_index % 4] = pattern.val;
-        SYSCON.saradc_sar1_patt_tab[pattern_index / 4] = tab;
+        tab = SYSCON.saradc_sar1_patt_tab[index];   // Read old register value
+        tab &= (~(0xFF000000 >> offset));           // clear old data
+        tab |= ((uint32_t)pattern.val << 24) >> offset; // Fill in the new data
+        SYSCON.saradc_sar1_patt_tab[index] = tab;   // Write back
     } else { // adc_n == ADC_NUM_2
-        tab = SYSCON.saradc_sar2_patt_tab[pattern_index / 4];
-        arg = (uint8_t *)&tab;
-        arg[pattern_index % 4] = pattern.val;
-        SYSCON.saradc_sar2_patt_tab[pattern_index / 4] = tab;
+        tab = SYSCON.saradc_sar2_patt_tab[index];   // Read old register value
+        tab &= (~(0xFF000000 >> offset));           // clear old data
+        tab |= ((uint32_t)pattern.val << 24) >> offset; // Fill in the new data
+        SYSCON.saradc_sar2_patt_tab[index] = tab;   // Write back
     }
 }
 

components/soc/esp32/include/soc/adc_caps.h

@@ -7,7 +7,7 @@
 #define SOC_ADC_MAX_CHANNEL_NUM         (10)
 
 #define SOC_ADC1_DATA_INVERT_DEFAULT    (1)
-#define SOC_ADC2_DATA_INVERT_DEFAULT    (0)
+#define SOC_ADC2_DATA_INVERT_DEFAULT    (1)
 
 #define SOC_ADC_FSM_RSTB_WAIT_DEFAULT       (8)
 #define SOC_ADC_FSM_START_WAIT_DEFAULT      (5)