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@@ -31,6 +31,7 @@ static const char *TAG = "rtc_init";
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static void set_ocode_by_efuse(int calib_version);
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static void calibrate_ocode(void);
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+static void set_rtc_dig_dbias(void);
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void rtc_init(rtc_config_t cfg)
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{
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@@ -55,9 +56,21 @@ void rtc_init(rtc_config_t cfg)
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REG_SET_FIELD(RTC_CNTL_TIMER6_REG, RTC_CNTL_DG_PERI_POWERUP_TIMER, rtc_init_cfg.dg_peri_powerup_cycles);
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REG_SET_FIELD(RTC_CNTL_TIMER6_REG, RTC_CNTL_DG_PERI_WAIT_TIMER, rtc_init_cfg.dg_peri_wait_cycles);
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- /* Reset RTC bias to default value (needed if waking up from deep sleep) */
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- REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG_SLEEP, RTC_CNTL_DBIAS_1V10);
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- REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG, RTC_CNTL_DBIAS_1V10);
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+ if (cfg.cali_ocode) {
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+ uint32_t rtc_calib_version = 0;
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+ esp_err_t err = esp_efuse_read_field_blob(ESP_EFUSE_BLOCK2_VERSION, &rtc_calib_version, 3);
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+ if (err != ESP_OK) {
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+ rtc_calib_version = 0;
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+ SOC_LOGW(TAG, "efuse read fail, set default rtc_calib_version: %d\n", rtc_calib_version);
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+ }
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+ if (rtc_calib_version == 1) {
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+ set_ocode_by_efuse(rtc_calib_version);
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+ } else {
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+ calibrate_ocode();
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+ }
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+ }
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+
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+ set_rtc_dig_dbias();
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if (cfg.clkctl_init) {
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//clear CMMU clock force on
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@@ -138,16 +151,6 @@ void rtc_init(rtc_config_t cfg)
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CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD);
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CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_NOISO);
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}
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- if (cfg.cali_ocode) {
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- uint32_t rtc_calib_version = 0;
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- esp_efuse_read_field_blob(ESP_EFUSE_BLOCK2_VERSION, &rtc_calib_version, 3);
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- if (rtc_calib_version == 1) {
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- set_ocode_by_efuse(rtc_calib_version);
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- } else {
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- calibrate_ocode();
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- }
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- }
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-
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REG_WRITE(RTC_CNTL_INT_ENA_REG, 0);
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REG_WRITE(RTC_CNTL_INT_CLR_REG, UINT32_MAX);
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}
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@@ -195,7 +198,9 @@ static void set_ocode_by_efuse(int calib_version)
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assert(calib_version == 1);
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// use efuse ocode.
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uint32_t ocode;
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- ESP_ERROR_CHECK(esp_efuse_read_field_blob(ESP_EFUSE_OCODE, &ocode, 8));
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+ esp_err_t err = esp_efuse_read_field_blob(ESP_EFUSE_OCODE, &ocode, 8);
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+ assert(err == ESP_OK);
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+ (void) err;
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REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_EXT_CODE, ocode);
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REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_CODE, 1);
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}
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@@ -250,3 +255,85 @@ static void calibrate_ocode(void)
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}
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rtc_clk_cpu_freq_set_config(&old_config);
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}
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+
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+static uint32_t get_dig_dbias_by_efuse(uint8_t chip_version)
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+{
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+ assert(chip_version >= 3);
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+ uint32_t dig_dbias = 28;
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+ esp_err_t err = esp_efuse_read_field_blob(ESP_EFUSE_DIG_DBIAS_HVT, &dig_dbias, 5);
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+ if (err != ESP_OK) {
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+ dig_dbias = 28;
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+ SOC_LOGW(TAG, "efuse read fail, set default dig_dbias value: %d\n", dig_dbias);
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+ }
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+ return dig_dbias;
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+}
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+
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+uint32_t get_rtc_dbias_by_efuse(uint8_t chip_version, uint32_t dig_dbias)
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+{
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+ assert(chip_version >= 3);
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+ uint32_t rtc_dbias = 0;
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+ signed int k_rtc_ldo = 0, k_dig_ldo = 0, v_rtc_bias20 = 0, v_dig_bias20 = 0;
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+ esp_err_t err0 = esp_efuse_read_field_blob(ESP_EFUSE_K_RTC_LDO, &k_rtc_ldo, 7);
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+ esp_err_t err1 = esp_efuse_read_field_blob(ESP_EFUSE_K_DIG_LDO, &k_dig_ldo, 7);
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+ esp_err_t err2 = esp_efuse_read_field_blob(ESP_EFUSE_V_RTC_DBIAS20, &v_rtc_bias20, 8);
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+ esp_err_t err3 = esp_efuse_read_field_blob(ESP_EFUSE_V_DIG_DBIAS20, &v_dig_bias20, 8);
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+ if ((err0 != ESP_OK) | (err1 != ESP_OK) | (err2 != ESP_OK) | (err3 != ESP_OK)) {
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+ k_rtc_ldo = 0;
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+ k_dig_ldo = 0;
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+ v_rtc_bias20 = 0;
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+ v_dig_bias20 = 0;
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+ SOC_LOGW(TAG, "efuse read fail, k_rtc_ldo: %d, k_dig_ldo: %d, v_rtc_bias20: %d, v_dig_bias20: %d\n", k_rtc_ldo, k_dig_ldo, v_rtc_bias20, v_dig_bias20);
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+ }
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+
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+ k_rtc_ldo = ((k_rtc_ldo & BIT(6)) != 0)? -(k_rtc_ldo & 0x3f): k_rtc_ldo;
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+ k_dig_ldo = ((k_dig_ldo & BIT(6)) != 0)? -(k_dig_ldo & 0x3f): (uint8_t)k_dig_ldo;
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+ v_rtc_bias20 = ((v_rtc_bias20 & BIT(7)) != 0)? -(v_rtc_bias20 & 0x7f): (uint8_t)v_rtc_bias20;
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+ v_dig_bias20 = ((v_dig_bias20 & BIT(7)) != 0)? -(v_dig_bias20 & 0x7f): (uint8_t)v_dig_bias20;
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+
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+ uint32_t v_rtc_dbias20_real_mul10000 = V_RTC_MID_MUL10000 + v_rtc_bias20 * 10000 / 500;
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+ uint32_t v_dig_dbias20_real_mul10000 = V_DIG_MID_MUL10000 + v_dig_bias20 * 10000 / 500;
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+ signed int k_rtc_ldo_real_mul10000 = K_RTC_MID_MUL10000 + k_rtc_ldo;
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+ signed int k_dig_ldo_real_mul10000 = K_DIG_MID_MUL10000 + k_dig_ldo;
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+ uint32_t v_dig_nearest_1v15_mul10000 = v_dig_dbias20_real_mul10000 + k_dig_ldo_real_mul10000 * (dig_dbias - 20);
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+ uint32_t v_rtc_nearest_1v15_mul10000 = 0;
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+ for (rtc_dbias = 15; rtc_dbias < 32; rtc_dbias++) {
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+ v_rtc_nearest_1v15_mul10000 = v_rtc_dbias20_real_mul10000 + k_rtc_ldo_real_mul10000 * (rtc_dbias - 20);
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+ if (v_rtc_nearest_1v15_mul10000 >= v_dig_nearest_1v15_mul10000 - 250)
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+ break;
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+ }
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+ return rtc_dbias;
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+}
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+
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+static void set_rtc_dig_dbias()
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+{
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+ /*
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+ 1. a reasonable dig_dbias which by scaning pvt to make 160 CPU run successful stored in efuse;
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+ 2. also we store some value in efuse, include:
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+ k_rtc_ldo (slope of rtc voltage & rtc_dbias);
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+ k_dig_ldo (slope of digital voltage & digital_dbias);
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+ v_rtc_bias20 (rtc voltage when rtc dbais is 20);
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+ v_dig_bias20 (digital voltage when digital dbais is 20).
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+ 3. a reasonable rtc_dbias can be calculated by a certion formula.
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+ */
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+ uint32_t rtc_dbias = 28, dig_dbias = 28;
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+ uint8_t chip_version = esp_efuse_get_chip_ver();
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+ if (chip_version >= 3) {
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+ dig_dbias = get_dig_dbias_by_efuse(chip_version);
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+ if (dig_dbias != 0) {
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+ if (dig_dbias + 4 > 28) {
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+ dig_dbias = 28;
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+ } else {
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+ dig_dbias += 4;
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+ }
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+ rtc_dbias = get_rtc_dbias_by_efuse(chip_version, dig_dbias); // already burn dig_dbias in efuse
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+ } else {
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+ dig_dbias = 28;
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+ SOC_LOGD(TAG, "not burn core voltage in efuse or burn wrong voltage value in chip version: 0%d\n", chip_version);
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+ }
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+ }
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+ else {
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+ SOC_LOGD(TAG, "chip_version is less than 3, not burn core voltage in efuse\n");
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+ }
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+ REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG, rtc_dbias);
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+ REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, dig_dbias);
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+}
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chaijie