esp32h2: update reg and struct for beta2

components/bootloader_support/src/bootloader_efuse_esp32h2.c

@@ -9,12 +9,20 @@
 
 uint8_t bootloader_common_get_chip_revision(void)
 {
+#if IDF_TARGET_ESP32H2_BETA_VERSION_1 // TODO: IDF-4337
     // should return the same value as esp_efuse_get_chip_ver()
     return REG_GET_FIELD(EFUSE_RD_MAC_SPI_SYS_3_REG, EFUSE_WAFER_VERSION);
+#else
+    return 0;
+#endif
 }
 
 uint32_t bootloader_common_get_chip_ver_pkg(void)
 {
+#if IDF_TARGET_ESP32H2_BETA_VERSION_1 // TODO: IDF-4337
     // should return the same value as esp_efuse_get_pkg_ver()
     return REG_GET_FIELD(EFUSE_RD_MAC_SPI_SYS_3_REG, EFUSE_PKG_VERSION);
+#else
+    return 0;
+#endif
 }

components/efuse/esp32h2/esp_efuse_table.c

@@ -9,7 +9,7 @@
 #include <assert.h>
 #include "esp_efuse_table.h"
 
-// md5_digest_table 6aaac59bd3f6d31bea4aef43b1f0d78a
+// md5_digest_table 8d520559b0ed30f0cef34704317f2815
 // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
 // If you want to change some fields, you need to change esp_efuse_table.csv file
 // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
@@ -24,7 +24,7 @@ static const esp_efuse_desc_t WR_DIS_RD_DIS[] = {
 };
 
 static const esp_efuse_desc_t WR_DIS_GROUP_1[] = {
-    {EFUSE_BLK0, 2, 1}, 	 // Write protection for DIS_ICACHE DIS_DOWNLOAD_ICACHE DIS_FORCE_DOWNLOAD DIS_USB DIS_CAN SOFT_DIS_JTAG DIS_DOWNLOAD_MANUAL_ENCRYPT,
+    {EFUSE_BLK0, 2, 1}, 	 // Write protection for DIS_ICACHE DIS_DOWNLOAD_ICACHE DIS_FORCE_DOWNLOAD DIS_USB DIS_TWAI SOFT_DIS_JTAG DIS_DOWNLOAD_MANUAL_ENCRYPT,
 };
 
 static const esp_efuse_desc_t WR_DIS_GROUP_2[] = {
@@ -179,8 +179,8 @@ static const esp_efuse_desc_t DIS_USB[] = {
     {EFUSE_BLK0, 45, 1}, 	 // Disable USB function,
 };
 
-static const esp_efuse_desc_t DIS_CAN[] = {
-    {EFUSE_BLK0, 46, 1}, 	 // Disable CAN function,
+static const esp_efuse_desc_t DIS_TWAI[] = {
+    {EFUSE_BLK0, 46, 1}, 	 // Disable TWAI function,
 };
 
 static const esp_efuse_desc_t JTAG_SEL_ENABLE[] = {
@@ -508,7 +508,7 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[] = {
 };
 
 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_1[] = {
-    &WR_DIS_GROUP_1[0],    		// Write protection for DIS_ICACHE DIS_DOWNLOAD_ICACHE DIS_FORCE_DOWNLOAD DIS_USB DIS_CAN SOFT_DIS_JTAG DIS_DOWNLOAD_MANUAL_ENCRYPT
+    &WR_DIS_GROUP_1[0],    		// Write protection for DIS_ICACHE DIS_DOWNLOAD_ICACHE DIS_FORCE_DOWNLOAD DIS_USB DIS_TWAI SOFT_DIS_JTAG DIS_DOWNLOAD_MANUAL_ENCRYPT
     NULL
 };
 
@@ -702,8 +702,8 @@ const esp_efuse_desc_t* ESP_EFUSE_DIS_USB[] = {
     NULL
 };
 
-const esp_efuse_desc_t* ESP_EFUSE_DIS_CAN[] = {
-    &DIS_CAN[0],    		// Disable CAN function
+const esp_efuse_desc_t* ESP_EFUSE_DIS_TWAI[] = {
+    &DIS_TWAI[0],    		// Disable TWAI function
     NULL
 };
 

components/efuse/esp32h2/esp_efuse_table.csv

@@ -16,7 +16,7 @@
     # EFUSE_RD_WR_DIS_REG #
         WR_DIS,                           EFUSE_BLK0,   0,    32,     Write protection
             WR_DIS.RD_DIS,                EFUSE_BLK0,   0,    1,      Write protection for RD_DIS_KEY0 RD_DIS_KEY1 RD_DIS_KEY2 RD_DIS_KEY3 RD_DIS_KEY4 RD_DIS_KEY5 RD_DIS_SYS_DATA_PART2
-            WR_DIS.GROUP_1,               EFUSE_BLK0,   2,    1,      Write protection for DIS_ICACHE DIS_DOWNLOAD_ICACHE DIS_FORCE_DOWNLOAD DIS_USB DIS_CAN SOFT_DIS_JTAG DIS_DOWNLOAD_MANUAL_ENCRYPT
+            WR_DIS.GROUP_1,               EFUSE_BLK0,   2,    1,      Write protection for DIS_ICACHE DIS_DOWNLOAD_ICACHE DIS_FORCE_DOWNLOAD DIS_USB DIS_TWAI SOFT_DIS_JTAG DIS_DOWNLOAD_MANUAL_ENCRYPT
             WR_DIS.GROUP_2,               EFUSE_BLK0,   3,    1,      Write protection for WDT_DELAY_SEL
             WR_DIS.SPI_BOOT_CRYPT_CNT,    EFUSE_BLK0,   4,    1,      Write protection for SPI_BOOT_CRYPT_CNT
             WR_DIS.SECURE_BOOT_KEY_REVOKE0,EFUSE_BLK0,  5,    1,      Write protection for SECURE_BOOT_KEY_REVOKE0
@@ -57,7 +57,7 @@
         DIS_USB_DEVICE,                   EFUSE_BLK0,   43,    1,     Disable USB_DEVICE
         DIS_FORCE_DOWNLOAD,               EFUSE_BLK0,   44,    1,     Disable force chip go to download mode function
         DIS_USB,                          EFUSE_BLK0,   45,    1,     Disable USB function
-        DIS_CAN,                          EFUSE_BLK0,   46,    1,     Disable CAN function
+        DIS_TWAI,                         EFUSE_BLK0,   46,    1,     Disable TWAI function
         JTAG_SEL_ENABLE,                  EFUSE_BLK0,   47,    1,     Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0.
         SOFT_DIS_JTAG,                    EFUSE_BLK0,   48,    3,     Set these bits to disable JTAG in the soft way (odd number 1 means disable). JTAG can be enabled in HMAC module.
         DIS_PAD_JTAG,                     EFUSE_BLK0,   51,    1,     Disable JTAG in the hard way. JTAG is disabled permanently.

components/efuse/esp32h2/include/esp_efuse_table.h

@@ -9,7 +9,7 @@ extern "C" {
 #endif
 
 
-// md5_digest_table 6aaac59bd3f6d31bea4aef43b1f0d78a
+// md5_digest_table 8d520559b0ed30f0cef34704317f2815
 // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
 // If you want to change some fields, you need to change esp_efuse_table.csv file
 // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
@@ -57,7 +57,7 @@ extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_ICACHE[];
 extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_DEVICE[];
 extern const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[];
 extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB[];
-extern const esp_efuse_desc_t* ESP_EFUSE_DIS_CAN[];
+extern const esp_efuse_desc_t* ESP_EFUSE_DIS_TWAI[];
 extern const esp_efuse_desc_t* ESP_EFUSE_JTAG_SEL_ENABLE[];
 extern const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[];
 extern const esp_efuse_desc_t* ESP_EFUSE_DIS_PAD_JTAG[];

components/esp_rom/CMakeLists.txt

@@ -30,18 +30,18 @@ idf_component_register(SRCS ${sources}
 
 if(target STREQUAL "esp32h2")
     if(CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_1)
-        set(ld_file "ld/rev1")
+        set(ld_folder "ld/rev1")
     elseif(CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_2)
-        set(ld_file "ld/rev2")
+        set(ld_folder "ld/rev2")
     endif()
 else()
-    set(ld_file "ld")
+    set(ld_folder "ld")
 endif()
 
 # Append a target linker script at the target-specific path,
 # only the 'name' part is different for each script
 function(rom_linker_script name)
-    target_linker_script(${COMPONENT_LIB} INTERFACE "${target}/${ld_file}/${target}.rom.${name}.ld")
+    target_linker_script(${COMPONENT_LIB} INTERFACE "${target}/${ld_folder}/${target}.rom.${name}.ld")
 endfunction()
 
 if(target STREQUAL "linux")
@@ -50,7 +50,7 @@ if(target STREQUAL "linux")
         target_compile_options(${COMPONENT_LIB} PUBLIC -Wimplicit-fallthrough=0 -Wno-shift-count-overflow)
     endif()
 else()
-    target_linker_script(${COMPONENT_LIB} INTERFACE "${target}/${ld_file}/${target}.rom.ld")
+    target_linker_script(${COMPONENT_LIB} INTERFACE "${target}/${ld_folder}/${target}.rom.ld")
     rom_linker_script("api")
     rom_linker_script("libgcc")
 endif()

components/esp_system/Kconfig

@@ -83,8 +83,8 @@ menu "ESP System Settings"
         default y if IDF_TARGET_ESP32S2
         default y if IDF_TARGET_ESP32C3
         default y if IDF_TARGET_ESP32S3
-        default y if IDF_TARGET_ESP32H2_BETA_VERSION_1
-        depends on !IDF_TARGET_ESP8684 && !IDF_TARGET_ESP32H2_BETA_VERSION_2
+        default y if IDF_TARGET_ESP32H2
+        depends on !IDF_TARGET_ESP8684
 
     config ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
         bool "Enable RTC fast memory for dynamic allocations"

components/esptool_py/esptool

@@ -1 +1 @@
-Subproject commit 8227361c9cda8f07c9b505b3b665ae69bc2fda8f
+Subproject commit 6b582c2b92d3c079098e0e296df03ff6cffeecf5

components/hal/esp32h2/include/hal/i2c_ll.h

@@ -1,16 +1,8 @@
-// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 
 // The LL layer for I2C register operations
 

components/hal/esp32h2/include/hal/rwdt_ll.h

@@ -1,19 +1,8 @@
-// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-// The LL layer for Timer Group register operations.
-// Note that most of the register operations in this layer are non-atomic operations.
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 
 #pragma once
 

components/hal/esp32h2/include/hal/systimer_ll.h

@@ -1,16 +1,8 @@
-// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 #pragma once
 
 #include <stdint.h>

components/hal/esp32h2/include/hal/uart_ll.h

@@ -1,16 +1,8 @@
-// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 
 // The LL layer for UART register operations.
 // Note that most of the register operations in this layer are non-atomic operations.

components/soc/esp32h2/CMakeLists.txt

@@ -17,13 +17,14 @@ add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" "${srcs}")
 
 target_sources(${COMPONENT_LIB} PRIVATE "${srcs}")
 
+set(inc_path "." "include")
+
 if(target STREQUAL "esp32h2")
     if(CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_1)
-        set(inc_file "include/rev1" "include/rev1/soc")
+        list(APPEND inc_path "include/rev1")
     elseif(CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_2)
-        set(inc_file "include/rev2" "include/rev2/soc")
+        list(APPEND inc_path "include/rev2")
     endif()
-    target_include_directories(${COMPONENT_LIB} PUBLIC . include ${inc_file})
-else()
-    target_include_directories(${COMPONENT_LIB} PUBLIC . include)
 endif()
+
+target_include_directories(${COMPONENT_LIB} PUBLIC ${inc_path})

components/soc/esp32h2/include/soc/clkrst_reg.h → components/soc/esp32h2/include/rev1/soc/clkrst_reg.h

@@ -1,24 +1,16 @@
-// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 #ifndef _SOC_CLKRST_REG_H_
 #define _SOC_CLKRST_REG_H_
 
+#include "soc/soc.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc.h"
 #define SYSTEM_SYSCLK_CONF_REG          (DR_REG_CLKRST_BASE + 0x0000)
 /* SYSTEM_SOC_CLK_SEL : R/W ;bitpos:[17:16] ;default: 2'h3 ; */
 /*description: */
@@ -417,12 +409,12 @@ extern "C" {
 #define SYSTEM_MSPI_DIV_NUM_M  ((SYSTEM_MSPI_DIV_NUM_V)<<(SYSTEM_MSPI_DIV_NUM_S))
 #define SYSTEM_MSPI_DIV_NUM_V  0xFF
 #define SYSTEM_MSPI_DIV_NUM_S  24
-/* SYSTEM_CAN_DIV_NUM : R/W ;bitpos:[23:16] ;default: 8'h1 ; */
+/* SYSTEM_TWAI_DIV_NUM : R/W ;bitpos:[23:16] ;default: 8'h1 ; */
 /*description: */
-#define SYSTEM_CAN_DIV_NUM  0x000000FF
-#define SYSTEM_CAN_DIV_NUM_M  ((SYSTEM_CAN_DIV_NUM_V)<<(SYSTEM_CAN_DIV_NUM_S))
-#define SYSTEM_CAN_DIV_NUM_V  0xFF
-#define SYSTEM_CAN_DIV_NUM_S  16
+#define SYSTEM_TWAI_DIV_NUM  0x000000FF
+#define SYSTEM_TWAI_DIV_NUM_M  ((SYSTEM_TWAI_DIV_NUM_V)<<(SYSTEM_TWAI_DIV_NUM_S))
+#define SYSTEM_TWAI_DIV_NUM_V  0xFF
+#define SYSTEM_TWAI_DIV_NUM_S  16
 /* SYSTEM_USB_DEVICE_DIV_NUM : R/W ;bitpos:[15:8] ;default: 8'h1 ; */
 /*description: */
 #define SYSTEM_USB_DEVICE_DIV_NUM  0x000000FF

components/soc/esp32h2/include/soc/efuse_reg.h → components/soc/esp32h2/include/rev1/soc/efuse_reg.h

@@ -1,24 +1,16 @@
-// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 #ifndef _SOC_EFUSE_REG_H_
 #define _SOC_EFUSE_REG_H_
 
+#include "soc/soc.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc.h"
 #define EFUSE_PGM_DATA0_REG          (DR_REG_EFUSE_BASE + 0x000)
 /* EFUSE_WR_DIS : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
 /*description: Disable programming of individual eFuses.*/

components/soc/esp32h2/include/soc/efuse_struct.h → components/soc/esp32h2/include/rev1/soc/efuse_struct.h

@@ -1,16 +1,8 @@
-// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 #ifndef _SOC_EFUSE_STRUCT_H_
 #define _SOC_EFUSE_STRUCT_H_
 #ifdef __cplusplus
@@ -29,7 +21,7 @@ typedef volatile struct efuse_dev_s {
             uint32_t dis_usb_device:              1;             /*Set this bit to disable usb device.*/
             uint32_t dis_force_download:          1;             /*Set this bit to disable the function that forces chip into download mode.*/
             uint32_t dis_usb:                     1;             /*Set this bit to disable USB function.*/
-            uint32_t dis_can:                     1;             /*Set this bit to disable CAN function.*/
+            uint32_t dis_twai:                     1;             /*Set this bit to disable TWAI function.*/
             uint32_t jtag_sel_enable:             1;             /*Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0.*/
             uint32_t soft_dis_jtag:               3;             /*Set these bits to disable JTAG in the soft way (odd number 1 means disable ). JTAG can be enabled in HMAC module.*/
             uint32_t dis_pad_jtag:                1;             /*Set this bit to disable JTAG in the hard way. JTAG is disabled permanently.*/
@@ -113,7 +105,7 @@ typedef volatile struct efuse_dev_s {
             uint32_t dis_usb_device:              1;             /*The value of DIS_USB_DEVICE.*/
             uint32_t dis_force_download:          1;             /*The value of DIS_FORCE_DOWNLOAD.*/
             uint32_t dis_usb:                     1;             /*The value of DIS_USB.*/
-            uint32_t dis_can:                     1;             /*The value of DIS_CAN.*/
+            uint32_t dis_twai:                     1;             /*The value of DIS_TWAI.*/
             uint32_t jtag_sel_enable:             1;             /*The value of JTAG_SEL_ENABLE.*/
             uint32_t soft_dis_jtag:               3;             /*The value of SOFT_DIS_JTAG.*/
             uint32_t dis_pad_jtag:                1;             /*The value of DIS_PAD_JTAG.*/
@@ -281,7 +273,7 @@ typedef volatile struct efuse_dev_s {
             uint32_t dis_usb_device_err:              1;         /*If DIS_USB_DEVICE is 1  then it indicates a programming error.*/
             uint32_t dis_force_download_err:          1;         /*If DIS_FORCE_DOWNLOAD is 1  then it indicates a programming error.*/
             uint32_t dis_usb_err:                     1;         /*If DIS_USB is 1  then it indicates a programming error.*/
-            uint32_t dis_can_err:                     1;         /*If DIS_CAN is 1  then it indicates a programming error.*/
+            uint32_t dis_twai_err:                     1;         /*If DIS_TWAI is 1  then it indicates a programming error.*/
             uint32_t jtag_sel_enable_err:             1;         /*If JTAG_SEL_ENABLE is 1  then it indicates a programming error.*/
             uint32_t soft_dis_jtag_err:               3;         /*If SOFT_DIS_JTAG is 1  then it indicates a programming error.*/
             uint32_t dis_pad_jtag_err:                1;         /*If DIS_PAD_JTAG is 1  then it indicates a programming error.*/

components/soc/esp32h2/include/rev1/soc/interrupt_core0_reg.h

@@ -214,13 +214,13 @@ extern "C" {
 #define INTERRUPT_CORE0_EFUSE_INT_MAP_V  0x1F
 #define INTERRUPT_CORE0_EFUSE_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_CAN_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x064)
-/* INTERRUPT_CORE0_CAN_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+#define INTERRUPT_CORE0_TWAI_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x064)
+/* INTERRUPT_CORE0_TWAI_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
 /*description: */
-#define INTERRUPT_CORE0_CAN_INT_MAP  0x0000001F
-#define INTERRUPT_CORE0_CAN_INT_MAP_M  ((INTERRUPT_CORE0_CAN_INT_MAP_V)<<(INTERRUPT_CORE0_CAN_INT_MAP_S))
-#define INTERRUPT_CORE0_CAN_INT_MAP_V  0x1F
-#define INTERRUPT_CORE0_CAN_INT_MAP_S  0
+#define INTERRUPT_CORE0_TWAI_INT_MAP  0x0000001F
+#define INTERRUPT_CORE0_TWAI_INT_MAP_M  ((INTERRUPT_CORE0_TWAI_INT_MAP_V)<<(INTERRUPT_CORE0_TWAI_INT_MAP_S))
+#define INTERRUPT_CORE0_TWAI_INT_MAP_V  0x1F
+#define INTERRUPT_CORE0_TWAI_INT_MAP_S  0
 
 #define INTERRUPT_CORE0_USB_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x068)
 /* INTERRUPT_CORE0_USB_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */

components/soc/esp32h2/include/rev1/soc/sensitive_reg.h

@@ -1464,12 +1464,12 @@ extern "C" {
 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_S))
 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_V  0x3
 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_S  14
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TWAI : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
 /*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN_S  10
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TWAI  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TWAI_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TWAI_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TWAI_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TWAI_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TWAI_S  10
 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
 /*description: */
 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL  0x00000003
@@ -1744,12 +1744,12 @@ extern "C" {
 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_S))
 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_V  0x3
 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_S  14
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
+/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TWAI : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
 /*description: */
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN  0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN_S  10
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TWAI  0x00000003
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TWAI_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TWAI_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TWAI_S))
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TWAI_V  0x3
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TWAI_S  10
 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
 /*description: */
 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL  0x00000003
@@ -2336,12 +2336,12 @@ extern "C" {
 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_S))
 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_V  0x3
 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_S  14
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
+/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TWAI : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
 /*description: */
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN  0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN_S  10
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TWAI  0x00000003
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TWAI_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TWAI_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TWAI_S))
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TWAI_V  0x3
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TWAI_S  10
 /* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
 /*description: */
 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL  0x00000003

components/soc/esp32h2/include/soc/sensitive_struct.h → components/soc/esp32h2/include/rev1/soc/sensitive_struct.h

@@ -1,24 +1,16 @@
-// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 #ifndef _SOC_SENSITIVE_STRUCT_H_
 #define _SOC_SENSITIVE_STRUCT_H_
 
+#include "soc/soc.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc.h"
 
 typedef volatile struct sensitive_dev_s {
     union {
@@ -659,7 +651,7 @@ typedef volatile struct sensitive_dev_s {
             uint32_t reserved2                     :    2;
             uint32_t reg_core_0_pif_pms_constrain_world_0_apb_ctrl:    2;  /*core_0_pif_pms_constrain_world_0_apb_ctrl*/
             uint32_t reserved6                     :    4;
-            uint32_t reg_core_0_pif_pms_constrain_world_0_can:    2;  /*core_0_pif_pms_constrain_world_0_can*/
+            uint32_t reg_core_0_pif_pms_constrain_world_0_twai:    2;  /*core_0_pif_pms_constrain_world_0_twai*/
             uint32_t reserved12                    :    2;
             uint32_t reg_core_0_pif_pms_constrain_world_0_i2s1:    2;  /*core_0_pif_pms_constrain_world_0_i2s1*/
             uint32_t reserved16                    :    6;
@@ -753,7 +745,7 @@ typedef volatile struct sensitive_dev_s {
             uint32_t reserved2:                                 2;
             uint32_t reg_core_0_pif_pms_constrain_world_1_apb_ctrl: 2;
             uint32_t reserved6:                                 4;
-            uint32_t reg_core_0_pif_pms_constrain_world_1_can:      2;
+            uint32_t reg_core_0_pif_pms_constrain_world_1_twai:      2;
             uint32_t reserved12:                                2;
             uint32_t reg_core_0_pif_pms_constrain_world_1_i2s1:     2;
             uint32_t reserved16:                                6;
@@ -1006,7 +998,7 @@ typedef volatile struct sensitive_dev_s {
             uint32_t reserved2                     :    2;
             uint32_t reg_backup_bus_pms_constrain_apb_ctrl:    2;  /*backup_bus_pms_constrain_apb_ctrl*/
             uint32_t reserved6                     :    4;
-            uint32_t reg_backup_bus_pms_constrain_can:    2;  /*backup_bus_pms_constrain_can*/
+            uint32_t reg_backup_bus_pms_constrain_twai:    2;  /*backup_bus_pms_constrain_twai*/
             uint32_t reserved12                    :    2;
             uint32_t reg_backup_bus_pms_constrain_i2s1:    2;  /*backup_bus_pms_constrain_i2s1*/
             uint32_t reserved16                    :    6;

components/soc/esp32h2/include/soc/syscon_reg.h → components/soc/esp32h2/include/rev1/soc/syscon_reg.h

@@ -1,24 +1,16 @@
-// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 #ifndef _SOC_SYSCON_REG_H_
 #define _SOC_SYSCON_REG_H_
 
+#include "soc/soc.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc.h"
 #define SYSCON_WIFI_BB_CFG_REG          (DR_REG_SYSCON_BASE + 0x00C)
 /* SYSCON_WIFI_BB_CFG : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
 /*description: */

components/soc/esp32h2/include/soc/syscon_struct.h → components/soc/esp32h2/include/rev1/soc/syscon_struct.h

@@ -1,16 +1,8 @@
-// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 #ifndef _SOC_SYSCON_STRUCT_H_
 #define _SOC_SYSCON_STRUCT_H_
 #ifdef __cplusplus

components/soc/esp32h2/include/soc/system_reg.h → components/soc/esp32h2/include/rev1/soc/system_reg.h

@@ -1,25 +1,17 @@
-// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 #ifndef _SOC_SYSTEM_REG_H_
 #define _SOC_SYSTEM_REG_H_
 
+#include "soc/soc.h"
+#include "soc/clkrst_reg.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc.h"
-#include "clkrst_reg.h"
 #define SYSTEM_CPU_PERI_CLK_EN_REG          (DR_REG_SYSTEM_BASE + 0x000)
 /* SYSTEM_CLK_EN_DEDICATED_GPIO : R/W ;bitpos:[7] ;default: 1'b0 ; */
 /*description: */

components/soc/esp32h2/include/soc/system_struct.h → components/soc/esp32h2/include/rev1/soc/system_struct.h

@@ -1,24 +1,16 @@
-// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 #ifndef _SOC_SYSTEM_STRUCT_H_
 #define _SOC_SYSTEM_STRUCT_H_
 
+#include "soc/soc.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc.h"
 
 typedef volatile struct system_dev_s {
     union {

components/soc/esp32h2/include/soc/usb_serial_jtag_reg.h → components/soc/esp32h2/include/rev1/soc/usb_serial_jtag_reg.h

@@ -1,6 +1,7 @@
-
-/** Copyright 2021 Espressif Systems (Shanghai) Co. Ltd.
- *  SPDX-License-Identifier: Apache-2.0
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
  */
 
 

components/soc/esp32h2/include/soc/usb_serial_jtag_struct.h → components/soc/esp32h2/include/rev1/soc/usb_serial_jtag_struct.h

@@ -1,24 +1,16 @@
-// Copyright 2021 Espressif Systems (Shanghai) Co. Ltd.
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 #ifndef _SOC_USB_SERIAL_JTAG_STRUCT_H_
 #define _SOC_USB_SERIAL_JTAG_STRUCT_H_
 
+#include "soc/soc.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc.h"
 
 typedef volatile struct usb_serial_jtag_dev_s {
     union {

components/soc/esp32h2/include/rev2/soc/assist_debug_reg.h

@@ -1,685 +1,896 @@
-/*
- * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
+/**
+ * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
  *
- * SPDX-License-Identifier: Apache-2.0
+ *  SPDX-License-Identifier: Apache-2.0
  */
-#ifndef _SOC_ASSIST_DEBUG_REG_H_
-#define _SOC_ASSIST_DEBUG_REG_H_
+#pragma once
 
+#include <stdint.h>
 #include "soc/soc.h"
-
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-#define ASSIST_DEBUG_CORE_0_INTR_ENA_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x0)
-/* ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: Need add description.*/
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA    (BIT(11))
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_M  (BIT(11))
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_V  0x1
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_S  11
-/* ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: Need add description.*/
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA    (BIT(10))
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_M  (BIT(10))
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_V  0x1
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_S  10
-/* ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: Need add description.*/
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA    (BIT(9))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_M  (BIT(9))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_V  0x1
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_S  9
-/* ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: Need add description.*/
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA    (BIT(8))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_M  (BIT(8))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_V  0x1
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_S  8
-/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: Need add description.*/
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA    (BIT(7))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_M  (BIT(7))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_S  7
-/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: Need add description.*/
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA    (BIT(6))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_M  (BIT(6))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_S  6
-/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: Need add description.*/
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA    (BIT(5))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_M  (BIT(5))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_S  5
-/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: Need add description.*/
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA    (BIT(4))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_M  (BIT(4))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_S  4
-/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: Need add description.*/
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA    (BIT(3))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_M  (BIT(3))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_S  3
-/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: Need add description.*/
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA    (BIT(2))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_M  (BIT(2))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_S  2
-/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Need add description.*/
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA    (BIT(1))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_M  (BIT(1))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_S  1
-/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Need add description.*/
+/** ASSIST_DEBUG_CORE_0_INTR_ENA_REG register
+ *  register description
+ */
+#define ASSIST_DEBUG_CORE_0_INTR_ENA_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0)
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA : R/W; bitpos: [0]; default: 0;
+ *  Need add description
+ */
 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA    (BIT(0))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_M  (BIT(0))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_V  0x00000001U
 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_S  0
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA : R/W; bitpos: [1]; default: 0;
+ *  Need add description
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA    (BIT(1))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_S  1
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA : R/W; bitpos: [2]; default: 0;
+ *  Need add description
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA    (BIT(2))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_S  2
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA : R/W; bitpos: [3]; default: 0;
+ *  Need add description
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA    (BIT(3))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_S  3
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA : R/W; bitpos: [4]; default: 0;
+ *  Need add description
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA    (BIT(4))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_S  4
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA : R/W; bitpos: [5]; default: 0;
+ *  Need add description
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA    (BIT(5))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_S  5
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA : R/W; bitpos: [6]; default: 0;
+ *  Need add description
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA    (BIT(6))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_S  6
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA : R/W; bitpos: [7]; default: 0;
+ *  Need add description
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA    (BIT(7))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_S  7
+/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA : R/W; bitpos: [8]; default: 0;
+ *  Need add description
+ */
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA    (BIT(8))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_S)
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_S  8
+/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA : R/W; bitpos: [9]; default: 0;
+ *  Need add description
+ */
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA    (BIT(9))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_S)
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_S  9
+/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA : R/W; bitpos: [10]; default: 0;
+ *  Need add description
+ */
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA    (BIT(10))
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_M  (ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_V << ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_S)
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_S  10
+/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA : R/W; bitpos: [11]; default: 0;
+ *  Need add description
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA    (BIT(11))
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_M  (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_S)
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_S  11
 
-#define ASSIST_DEBUG_CORE_0_INTR_RAW_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x4)
-/* ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */
-/*description: Need add description.*/
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW    (BIT(11))
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_M  (BIT(11))
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_V  0x1
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_S  11
-/* ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */
-/*description: Need add description.*/
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW    (BIT(10))
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_M  (BIT(10))
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_V  0x1
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_S  10
-/* ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */
-/*description: Need add description.*/
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW    (BIT(9))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_M  (BIT(9))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_V  0x1
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_S  9
-/* ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
-/*description: Need add description.*/
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW    (BIT(8))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_M  (BIT(8))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_V  0x1
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_S  8
-/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
-/*description: Need add description.*/
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW    (BIT(7))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_M  (BIT(7))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_S  7
-/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: Need add description.*/
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW    (BIT(6))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_M  (BIT(6))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_S  6
-/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: Need add description.*/
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW    (BIT(5))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_M  (BIT(5))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_S  5
-/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
-/*description: Need add description.*/
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW    (BIT(4))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_M  (BIT(4))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_S  4
-/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
-/*description: Need add description.*/
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW    (BIT(3))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_M  (BIT(3))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_S  3
-/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: Need add description.*/
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW    (BIT(2))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_M  (BIT(2))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_S  2
-/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Need add description.*/
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW    (BIT(1))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_M  (BIT(1))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_S  1
-/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Need add description.*/
+/** ASSIST_DEBUG_CORE_0_INTR_RAW_REG register
+ *  register description
+ */
+#define ASSIST_DEBUG_CORE_0_INTR_RAW_REG (DR_REG_ASSIST_DEBUG_BASE + 0x4)
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW : RO; bitpos: [0]; default: 0;
+ *  Need add description
+ */
 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW    (BIT(0))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_M  (BIT(0))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_V  0x00000001U
 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_S  0
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW : RO; bitpos: [1]; default: 0;
+ *  Need add description
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW    (BIT(1))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_S  1
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW : RO; bitpos: [2]; default: 0;
+ *  Need add description
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW    (BIT(2))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_S  2
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW : RO; bitpos: [3]; default: 0;
+ *  Need add description
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW    (BIT(3))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_S  3
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW : RO; bitpos: [4]; default: 0;
+ *  Need add description
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW    (BIT(4))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_S  4
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW : RO; bitpos: [5]; default: 0;
+ *  Need add description
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW    (BIT(5))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_S  5
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW : RO; bitpos: [6]; default: 0;
+ *  Need add description
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW    (BIT(6))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_S  6
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW : RO; bitpos: [7]; default: 0;
+ *  Need add description
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW    (BIT(7))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_S  7
+/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW : RO; bitpos: [8]; default: 0;
+ *  Need add description
+ */
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW    (BIT(8))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_S)
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_S  8
+/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW : RO; bitpos: [9]; default: 0;
+ *  Need add description
+ */
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW    (BIT(9))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_S)
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_S  9
+/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW : RO; bitpos: [10]; default: 0;
+ *  Need add description
+ */
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW    (BIT(10))
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_M  (ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_V << ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_S)
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_S  10
+/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW : RO; bitpos: [11]; default: 0;
+ *  Need add description
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW    (BIT(11))
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_M  (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_S)
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_S  11
 
-#define ASSIST_DEBUG_CORE_0_INTR_RLS_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x8)
-/* ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: Need add description.*/
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS    (BIT(11))
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_M  (BIT(11))
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_V  0x1
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_S  11
-/* ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: Need add description.*/
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS    (BIT(10))
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_M  (BIT(10))
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_V  0x1
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_S  10
-/* ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: Need add description.*/
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS    (BIT(9))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_M  (BIT(9))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_V  0x1
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_S  9
-/* ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: Need add description.*/
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS    (BIT(8))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_M  (BIT(8))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_V  0x1
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_S  8
-/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: Need add description.*/
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS    (BIT(7))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_M  (BIT(7))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_S  7
-/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: Need add description.*/
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS    (BIT(6))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_M  (BIT(6))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_S  6
-/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: Need add description.*/
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS    (BIT(5))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_M  (BIT(5))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_S  5
-/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: Need add description.*/
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS    (BIT(4))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_M  (BIT(4))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_S  4
-/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: Need add description.*/
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS    (BIT(3))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_M  (BIT(3))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_S  3
-/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: Need add description.*/
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS    (BIT(2))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_M  (BIT(2))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_S  2
-/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Need add description.*/
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS    (BIT(1))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_M  (BIT(1))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_S  1
-/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Need add description.*/
+/** ASSIST_DEBUG_CORE_0_INTR_RLS_REG register
+ *  register description
+ */
+#define ASSIST_DEBUG_CORE_0_INTR_RLS_REG (DR_REG_ASSIST_DEBUG_BASE + 0x8)
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS : R/W; bitpos: [0]; default: 0;
+ *  Need add description
+ */
 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS    (BIT(0))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_M  (BIT(0))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_V  0x00000001U
 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_S  0
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS : R/W; bitpos: [1]; default: 0;
+ *  Need add description
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS    (BIT(1))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_S  1
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS : R/W; bitpos: [2]; default: 0;
+ *  Need add description
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS    (BIT(2))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_S  2
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS : R/W; bitpos: [3]; default: 0;
+ *  Need add description
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS    (BIT(3))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_S  3
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS : R/W; bitpos: [4]; default: 0;
+ *  Need add description
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS    (BIT(4))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_S  4
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS : R/W; bitpos: [5]; default: 0;
+ *  Need add description
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS    (BIT(5))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_S  5
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS : R/W; bitpos: [6]; default: 0;
+ *  Need add description
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS    (BIT(6))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_S  6
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS : R/W; bitpos: [7]; default: 0;
+ *  Need add description
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS    (BIT(7))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_S  7
+/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS : R/W; bitpos: [8]; default: 0;
+ *  Need add description
+ */
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS    (BIT(8))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_S)
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_S  8
+/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS : R/W; bitpos: [9]; default: 0;
+ *  Need add description
+ */
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS    (BIT(9))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_S)
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_S  9
+/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS : R/W; bitpos: [10]; default: 0;
+ *  Need add description
+ */
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS    (BIT(10))
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_M  (ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_V << ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_S)
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_S  10
+/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS : R/W; bitpos: [11]; default: 0;
+ *  Need add description
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS    (BIT(11))
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_M  (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_S)
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_S  11
 
-#define ASSIST_DEBUG_CORE_0_INTR_CLR_REG          (DR_REG_ASSIST_DEBUG_BASE + 0xC)
-/* ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR : R/W ;bitpos:[11] ;default: 1'b0 ; */
-/*description: Need add description.*/
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR    (BIT(11))
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_M  (BIT(11))
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_V  0x1
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_S  11
-/* ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR : R/W ;bitpos:[10] ;default: 1'b0 ; */
-/*description: Need add description.*/
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR    (BIT(10))
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_M  (BIT(10))
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_V  0x1
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_S  10
-/* ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR : R/W ;bitpos:[9] ;default: 1'b0 ; */
-/*description: Need add description.*/
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR    (BIT(9))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_M  (BIT(9))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_V  0x1
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_S  9
-/* ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR : R/W ;bitpos:[8] ;default: 1'b0 ; */
-/*description: Need add description.*/
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR    (BIT(8))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_M  (BIT(8))
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_V  0x1
-#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_S  8
-/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR : R/W ;bitpos:[7] ;default: 1'b0 ; */
-/*description: Need add description.*/
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR    (BIT(7))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_M  (BIT(7))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_S  7
-/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR : R/W ;bitpos:[6] ;default: 1'b0 ; */
-/*description: Need add description.*/
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR    (BIT(6))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_M  (BIT(6))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_S  6
-/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR : R/W ;bitpos:[5] ;default: 1'b0 ; */
-/*description: Need add description.*/
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR    (BIT(5))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_M  (BIT(5))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_S  5
-/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR : R/W ;bitpos:[4] ;default: 1'b0 ; */
-/*description: Need add description.*/
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR    (BIT(4))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_M  (BIT(4))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_S  4
-/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: Need add description.*/
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR    (BIT(3))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_M  (BIT(3))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_S  3
-/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR : R/W ;bitpos:[2] ;default: 1'b0 ; */
-/*description: Need add description.*/
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR    (BIT(2))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_M  (BIT(2))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_S  2
-/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Need add description.*/
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR    (BIT(1))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_M  (BIT(1))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_V  0x1
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_S  1
-/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Need add description.*/
+/** ASSIST_DEBUG_CORE_0_INTR_CLR_REG register
+ *  register description
+ */
+#define ASSIST_DEBUG_CORE_0_INTR_CLR_REG (DR_REG_ASSIST_DEBUG_BASE + 0xc)
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR : R/W; bitpos: [0]; default: 0;
+ *  Need add description
+ */
 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR    (BIT(0))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_M  (BIT(0))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_V  0x1
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_V  0x00000001U
 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_S  0
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR : R/W; bitpos: [1]; default: 0;
+ *  Need add description
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR    (BIT(1))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_S  1
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR : R/W; bitpos: [2]; default: 0;
+ *  Need add description
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR    (BIT(2))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_S  2
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR : R/W; bitpos: [3]; default: 0;
+ *  Need add description
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR    (BIT(3))
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_S  3
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR : R/W; bitpos: [4]; default: 0;
+ *  Need add description
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR    (BIT(4))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_S  4
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR : R/W; bitpos: [5]; default: 0;
+ *  Need add description
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR    (BIT(5))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_S  5
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR : R/W; bitpos: [6]; default: 0;
+ *  Need add description
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR    (BIT(6))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_S  6
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR : R/W; bitpos: [7]; default: 0;
+ *  Need add description
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR    (BIT(7))
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_S  7
+/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR : R/W; bitpos: [8]; default: 0;
+ *  Need add description
+ */
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR    (BIT(8))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_S)
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_S  8
+/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR : R/W; bitpos: [9]; default: 0;
+ *  Need add description
+ */
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR    (BIT(9))
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_M  (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_S)
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_S  9
+/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR : R/W; bitpos: [10]; default: 0;
+ *  Need add description
+ */
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR    (BIT(10))
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_M  (ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_V << ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_S)
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_S  10
+/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR : R/W; bitpos: [11]; default: 0;
+ *  Need add description
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR    (BIT(11))
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_M  (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_S)
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_S  11
 
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x10)
-/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
-/*description: Need add description.*/
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN    0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_M  ((ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V)<<(ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V  0xFFFFFFFF
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG register
+ *  register description
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x10)
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Need add description
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V  0xFFFFFFFFU
 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S  0
 
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x14)
-/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: Need add description.*/
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX    0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_M  ((ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V)<<(ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V  0xFFFFFFFF
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG register
+ *  register description
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x14)
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX : R/W; bitpos: [31:0]; default: 0;
+ *  Need add description
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V  0xFFFFFFFFU
 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S  0
 
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x18)
-/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
-/*description: Need add description.*/
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN    0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_M  ((ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V)<<(ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V  0xFFFFFFFF
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG register
+ *  register description
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x18)
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Need add description
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V  0xFFFFFFFFU
 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S  0
 
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x1C)
-/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: Need add description.*/
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX    0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_M  ((ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V)<<(ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S))
-#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V  0xFFFFFFFF
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG register
+ *  register description
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x1c)
+/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX : R/W; bitpos: [31:0]; default: 0;
+ *  Need add description
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_M  (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S)
+#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V  0xFFFFFFFFU
 #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S  0
 
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x20)
-/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
-/*description: Need add description.*/
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN    0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_M  ((ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V)<<(ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V  0xFFFFFFFF
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG register
+ *  register description
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x20)
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Need add description
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V  0xFFFFFFFFU
 #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S  0
 
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x24)
-/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: Need add description.*/
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX    0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_M  ((ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V)<<(ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V  0xFFFFFFFF
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG register
+ *  register description
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x24)
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX : R/W; bitpos: [31:0]; default: 0;
+ *  Need add description
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V  0xFFFFFFFFU
 #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S  0
 
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x28)
-/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
-/*description: Need add description.*/
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN    0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_M  ((ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V)<<(ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V  0xFFFFFFFF
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG register
+ *  register description
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x28)
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Need add description
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V  0xFFFFFFFFU
 #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S  0
 
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x2C)
-/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: Need add description.*/
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX    0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_M  ((ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V)<<(ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S))
-#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V  0xFFFFFFFF
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG register
+ *  register description
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x2c)
+/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX : R/W; bitpos: [31:0]; default: 0;
+ *  Need add description
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_M  (ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V  0xFFFFFFFFU
 #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S  0
 
-#define ASSIST_DEBUG_CORE_0_AREA_PC_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x30)
-/* ASSIST_DEBUG_CORE_0_AREA_PC : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: Need add description.*/
-#define ASSIST_DEBUG_CORE_0_AREA_PC    0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_AREA_PC_M  ((ASSIST_DEBUG_CORE_0_AREA_PC_V)<<(ASSIST_DEBUG_CORE_0_AREA_PC_S))
-#define ASSIST_DEBUG_CORE_0_AREA_PC_V  0xFFFFFFFF
+/** ASSIST_DEBUG_CORE_0_AREA_PC_REG register
+ *  register description
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x30)
+/** ASSIST_DEBUG_CORE_0_AREA_PC : RO; bitpos: [31:0]; default: 0;
+ *  Need add description
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_PC    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_PC_M  (ASSIST_DEBUG_CORE_0_AREA_PC_V << ASSIST_DEBUG_CORE_0_AREA_PC_S)
+#define ASSIST_DEBUG_CORE_0_AREA_PC_V  0xFFFFFFFFU
 #define ASSIST_DEBUG_CORE_0_AREA_PC_S  0
 
-#define ASSIST_DEBUG_CORE_0_AREA_SP_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x34)
-/* ASSIST_DEBUG_CORE_0_AREA_SP : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: Need add description.*/
-#define ASSIST_DEBUG_CORE_0_AREA_SP    0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_AREA_SP_M  ((ASSIST_DEBUG_CORE_0_AREA_SP_V)<<(ASSIST_DEBUG_CORE_0_AREA_SP_S))
-#define ASSIST_DEBUG_CORE_0_AREA_SP_V  0xFFFFFFFF
+/** ASSIST_DEBUG_CORE_0_AREA_SP_REG register
+ *  register description
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_SP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x34)
+/** ASSIST_DEBUG_CORE_0_AREA_SP : RO; bitpos: [31:0]; default: 0;
+ *  Need add description
+ */
+#define ASSIST_DEBUG_CORE_0_AREA_SP    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_AREA_SP_M  (ASSIST_DEBUG_CORE_0_AREA_SP_V << ASSIST_DEBUG_CORE_0_AREA_SP_S)
+#define ASSIST_DEBUG_CORE_0_AREA_SP_V  0xFFFFFFFFU
 #define ASSIST_DEBUG_CORE_0_AREA_SP_S  0
 
-#define ASSIST_DEBUG_CORE_0_SP_MIN_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x38)
-/* ASSIST_DEBUG_CORE_0_SP_MIN : RW ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: Need add description.*/
-#define ASSIST_DEBUG_CORE_0_SP_MIN    0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_SP_MIN_M  ((ASSIST_DEBUG_CORE_0_SP_MIN_V)<<(ASSIST_DEBUG_CORE_0_SP_MIN_S))
-#define ASSIST_DEBUG_CORE_0_SP_MIN_V  0xFFFFFFFF
+/** ASSIST_DEBUG_CORE_0_SP_MIN_REG register
+ *  register description
+ */
+#define ASSIST_DEBUG_CORE_0_SP_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x38)
+/** ASSIST_DEBUG_CORE_0_SP_MIN : RW; bitpos: [31:0]; default: 0;
+ *  Need add description
+ */
+#define ASSIST_DEBUG_CORE_0_SP_MIN    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_SP_MIN_M  (ASSIST_DEBUG_CORE_0_SP_MIN_V << ASSIST_DEBUG_CORE_0_SP_MIN_S)
+#define ASSIST_DEBUG_CORE_0_SP_MIN_V  0xFFFFFFFFU
 #define ASSIST_DEBUG_CORE_0_SP_MIN_S  0
 
-#define ASSIST_DEBUG_CORE_0_SP_MAX_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x3C)
-/* ASSIST_DEBUG_CORE_0_SP_MAX : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
-/*description: Need add description.*/
-#define ASSIST_DEBUG_CORE_0_SP_MAX    0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_SP_MAX_M  ((ASSIST_DEBUG_CORE_0_SP_MAX_V)<<(ASSIST_DEBUG_CORE_0_SP_MAX_S))
-#define ASSIST_DEBUG_CORE_0_SP_MAX_V  0xFFFFFFFF
+/** ASSIST_DEBUG_CORE_0_SP_MAX_REG register
+ *  register description
+ */
+#define ASSIST_DEBUG_CORE_0_SP_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x3c)
+/** ASSIST_DEBUG_CORE_0_SP_MAX : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Need add description
+ */
+#define ASSIST_DEBUG_CORE_0_SP_MAX    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_SP_MAX_M  (ASSIST_DEBUG_CORE_0_SP_MAX_V << ASSIST_DEBUG_CORE_0_SP_MAX_S)
+#define ASSIST_DEBUG_CORE_0_SP_MAX_V  0xFFFFFFFFU
 #define ASSIST_DEBUG_CORE_0_SP_MAX_S  0
 
-#define ASSIST_DEBUG_CORE_0_SP_PC_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x40)
-/* ASSIST_DEBUG_CORE_0_SP_PC : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: Need add description.*/
-#define ASSIST_DEBUG_CORE_0_SP_PC    0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_SP_PC_M  ((ASSIST_DEBUG_CORE_0_SP_PC_V)<<(ASSIST_DEBUG_CORE_0_SP_PC_S))
-#define ASSIST_DEBUG_CORE_0_SP_PC_V  0xFFFFFFFF
+/** ASSIST_DEBUG_CORE_0_SP_PC_REG register
+ *  register description
+ */
+#define ASSIST_DEBUG_CORE_0_SP_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x40)
+/** ASSIST_DEBUG_CORE_0_SP_PC : RO; bitpos: [31:0]; default: 0;
+ *  Need add description
+ */
+#define ASSIST_DEBUG_CORE_0_SP_PC    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_SP_PC_M  (ASSIST_DEBUG_CORE_0_SP_PC_V << ASSIST_DEBUG_CORE_0_SP_PC_S)
+#define ASSIST_DEBUG_CORE_0_SP_PC_V  0xFFFFFFFFU
 #define ASSIST_DEBUG_CORE_0_SP_PC_S  0
 
-#define ASSIST_DEBUG_CORE_0_RCD_EN_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x44)
-/* ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN : RW ;bitpos:[1] ;default: 1'b0 ; */
-/*description: enable CPU Pdebug function, if enable, CPU will update PdebugPC.*/
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN    (BIT(1))
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_M  (BIT(1))
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_V  0x1
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S  1
-/* ASSIST_DEBUG_CORE_0_RCD_RECORDEN : RW ;bitpos:[0] ;default: 1'b0 ; */
-/*description: enable recording function, if enable, assist_debug will update PdebugPC, so you
-can read it.*/
+/** ASSIST_DEBUG_CORE_0_RCD_EN_REG register
+ *  register description
+ */
+#define ASSIST_DEBUG_CORE_0_RCD_EN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x44)
+/** ASSIST_DEBUG_CORE_0_RCD_RECORDEN : RW; bitpos: [0]; default: 0;
+ *  enable recording function, if enable, assist_debug will update PdebugPC, so you can
+ *  read it
+ */
 #define ASSIST_DEBUG_CORE_0_RCD_RECORDEN    (BIT(0))
-#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_M  (BIT(0))
-#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_V  0x1
+#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_M  (ASSIST_DEBUG_CORE_0_RCD_RECORDEN_V << ASSIST_DEBUG_CORE_0_RCD_RECORDEN_S)
+#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_V  0x00000001U
 #define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_S  0
+/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN : RW; bitpos: [1]; default: 0;
+ *  enable CPU Pdebug function, if enable, CPU will update PdebugPC
+ */
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN    (BIT(1))
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_M  (ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S)
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S  1
 
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x48)
-/* ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Need add description.*/
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC    0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_M  ((ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V)<<(ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S))
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V  0xFFFFFFFF
+/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG register
+ *  register description
+ */
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x48)
+/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC : RO; bitpos: [31:0]; default: 0;
+ *  Need add description
+ */
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_M  (ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S)
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V  0xFFFFFFFFU
 #define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S  0
 
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x4C)
-/* ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Need add description.*/
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP    0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_M  ((ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V)<<(ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S))
-#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V  0xFFFFFFFF
+/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG register
+ *  register description
+ */
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x4c)
+/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP : RO; bitpos: [31:0]; default: 0;
+ *  Need add description
+ */
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_M  (ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S)
+#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V  0xFFFFFFFFU
 #define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S  0
 
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x50)
-/* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0 : RO ;bitpos:[25] ;default: 1'b0 ; */
-/*description: Need add description.*/
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0    (BIT(25))
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_M  (BIT(25))
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_V  0x1
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_S  25
-/* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0 : RO ;bitpos:[24] ;default: 1'b0 ; */
-/*description: Need add description.*/
+/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_REG register
+ *  register description
+ */
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x50)
+/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0 : RO; bitpos: [23:0]; default: 0;
+ *  Need add description
+ */
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0    0x00FFFFFFU
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_M  (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_S)
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_V  0x00FFFFFFU
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_S  0
+/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0 : RO; bitpos: [24]; default: 0;
+ *  Need add description
+ */
 #define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0    (BIT(24))
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_M  (BIT(24))
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_V  0x1
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_M  (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_S)
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_V  0x00000001U
 #define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_S  24
-/* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0 : RO ;bitpos:[23:0] ;default: 24'b0 ; */
-/*description: Need add description.*/
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0    0x00FFFFFF
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_M  ((ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_V)<<(ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_S))
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_V  0xFFFFFF
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_S  0
+/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0 : RO; bitpos: [25]; default: 0;
+ *  Need add description
+ */
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0    (BIT(25))
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_M  (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_S)
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_S  25
 
-#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x54)
-/* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1 : RO ;bitpos:[25] ;default: 1'b0 ; */
-/*description: Need add description.*/
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1    (BIT(25))
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_M  (BIT(25))
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_V  0x1
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_S  25
-/* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1 : RO ;bitpos:[24] ;default: 1'b0 ; */
-/*description: Need add description.*/
+/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG register
+ *  register description
+ */
+#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x54)
+/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1 : RO; bitpos: [23:0]; default: 0;
+ *  Need add description
+ */
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1    0x00FFFFFFU
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_M  (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_S)
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_V  0x00FFFFFFU
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_S  0
+/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1 : RO; bitpos: [24]; default: 0;
+ *  Need add description
+ */
 #define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1    (BIT(24))
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_M  (BIT(24))
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_V  0x1
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_M  (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_S)
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_V  0x00000001U
 #define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_S  24
-/* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1 : RO ;bitpos:[23:0] ;default: 24'b0 ; */
-/*description: Need add description.*/
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1    0x00FFFFFF
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_M  ((ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_V)<<(ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_S))
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_V  0xFFFFFF
-#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_S  0
+/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1 : RO; bitpos: [25]; default: 0;
+ *  Need add description
+ */
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1    (BIT(25))
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_M  (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_S)
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_S  25
 
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x58)
-/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0 : RO ;bitpos:[28:25] ;default: 4'b0 ; */
-/*description: Need add description.*/
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0    0x0000000F
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_M  ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_V)<<(ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_S))
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_V  0xF
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_S  25
-/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0 : RO ;bitpos:[24] ;default: 1'b0 ; */
-/*description: Need add description.*/
+/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG register
+ *  register description
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x58)
+/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0 : RO; bitpos: [23:0]; default: 0;
+ *  Need add description
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0    0x00FFFFFFU
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_S)
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_V  0x00FFFFFFU
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_S  0
+/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0 : RO; bitpos: [24]; default: 0;
+ *  Need add description
+ */
 #define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0    (BIT(24))
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_M  (BIT(24))
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_V  0x1
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_S)
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_V  0x00000001U
 #define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_S  24
-/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0 : RO ;bitpos:[23:0] ;default: 24'b0 ; */
-/*description: Need add description.*/
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0    0x00FFFFFF
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_M  ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_V)<<(ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_S))
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_V  0xFFFFFF
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_S  0
+/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0 : RO; bitpos: [28:25]; default: 0;
+ *  Need add description
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0    0x0000000FU
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_S)
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_V  0x0000000FU
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_S  25
 
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x5C)
-/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: Need add description.*/
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0    0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_M  ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_V)<<(ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_S))
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_V  0xFFFFFFFF
+/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG register
+ *  register description
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x5c)
+/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0 : RO; bitpos: [31:0]; default: 0;
+ *  Need add description
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_S)
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_V  0xFFFFFFFFU
 #define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_S  0
 
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x60)
-/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1 : RO ;bitpos:[28:25] ;default: 4'b0 ; */
-/*description: Need add description.*/
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1    0x0000000F
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_M  ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_V)<<(ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_S))
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_V  0xF
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_S  25
-/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1 : RO ;bitpos:[24] ;default: 1'b0 ; */
-/*description: Need add description.*/
+/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_REG register
+ *  register description
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_REG (DR_REG_ASSIST_DEBUG_BASE + 0x60)
+/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1 : RO; bitpos: [23:0]; default: 0;
+ *  Need add description
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1    0x00FFFFFFU
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_S)
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_V  0x00FFFFFFU
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_S  0
+/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1 : RO; bitpos: [24]; default: 0;
+ *  Need add description
+ */
 #define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1    (BIT(24))
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_M  (BIT(24))
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_V  0x1
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_S)
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_V  0x00000001U
 #define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_S  24
-/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1 : RO ;bitpos:[23:0] ;default: 24'b0 ; */
-/*description: Need add description.*/
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1    0x00FFFFFF
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_M  ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_V)<<(ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_S))
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_V  0xFFFFFF
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_S  0
+/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1 : RO; bitpos: [28:25]; default: 0;
+ *  Need add description
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1    0x0000000FU
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_S)
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_V  0x0000000FU
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_S  25
 
-#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x64)
-/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: Need add description.*/
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1    0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_M  ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_V)<<(ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_S))
-#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_V  0xFFFFFFFF
+/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG register
+ *  register description
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG (DR_REG_ASSIST_DEBUG_BASE + 0x64)
+/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1 : RO; bitpos: [31:0]; default: 0;
+ *  Need add description
+ */
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_M  (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_S)
+#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_V  0xFFFFFFFFU
 #define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_S  0
 
-#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x68)
-/* ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 : R/W ;bitpos:[19:0] ;default: 20'b0 ; */
-/*description: Need add description.*/
-#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0    0x000FFFFF
-#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_M  ((ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V)<<(ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_S))
-#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V  0xFFFFF
+/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG register
+ *  register description
+ */
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x68)
+/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 : R/W; bitpos: [19:0]; default: 0;
+ *  Need add description
+ */
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0    0x000FFFFFU
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_M  (ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V << ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_S)
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V  0x000FFFFFU
 #define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_S  0
 
-#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x6C)
-/* ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 : R/W ;bitpos:[19:0] ;default: 20'b0 ; */
-/*description: Need add description.*/
-#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1    0x000FFFFF
-#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_M  ((ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_V)<<(ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_S))
-#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_V  0xFFFFF
+/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG register
+ *  register description
+ */
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x6c)
+/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 : R/W; bitpos: [19:0]; default: 0;
+ *  Need add description
+ */
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1    0x000FFFFFU
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_M  (ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_V << ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_S)
+#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_V  0x000FFFFFU
 #define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_S  0
 
-#define ASSIST_DEBUG_LOG_SETTING_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x70)
-/* ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE : R/W ;bitpos:[7] ;default: 1'b1 ; */
-/*description: Need add description.*/
+/** ASSIST_DEBUG_LOG_SETTING_REG register
+ *  register description
+ */
+#define ASSIST_DEBUG_LOG_SETTING_REG (DR_REG_ASSIST_DEBUG_BASE + 0x70)
+/** ASSIST_DEBUG_LOG_ENA : R/W; bitpos: [2:0]; default: 0;
+ *  Need add description
+ */
+#define ASSIST_DEBUG_LOG_ENA    0x00000007U
+#define ASSIST_DEBUG_LOG_ENA_M  (ASSIST_DEBUG_LOG_ENA_V << ASSIST_DEBUG_LOG_ENA_S)
+#define ASSIST_DEBUG_LOG_ENA_V  0x00000007U
+#define ASSIST_DEBUG_LOG_ENA_S  0
+/** ASSIST_DEBUG_LOG_MODE : R/W; bitpos: [6:3]; default: 0;
+ *  Need add description
+ */
+#define ASSIST_DEBUG_LOG_MODE    0x0000000FU
+#define ASSIST_DEBUG_LOG_MODE_M  (ASSIST_DEBUG_LOG_MODE_V << ASSIST_DEBUG_LOG_MODE_S)
+#define ASSIST_DEBUG_LOG_MODE_V  0x0000000FU
+#define ASSIST_DEBUG_LOG_MODE_S  3
+/** ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE : R/W; bitpos: [7]; default: 1;
+ *  Need add description
+ */
 #define ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE    (BIT(7))
-#define ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE_M  (BIT(7))
-#define ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE_V  0x1
+#define ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE_M  (ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE_V << ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE_S)
+#define ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE_V  0x00000001U
 #define ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE_S  7
-/* ASSIST_DEBUG_LOG_MODE : R/W ;bitpos:[6:3] ;default: 4'b0 ; */
-/*description: Need add description.*/
-#define ASSIST_DEBUG_LOG_MODE    0x0000000F
-#define ASSIST_DEBUG_LOG_MODE_M  ((ASSIST_DEBUG_LOG_MODE_V)<<(ASSIST_DEBUG_LOG_MODE_S))
-#define ASSIST_DEBUG_LOG_MODE_V  0xF
-#define ASSIST_DEBUG_LOG_MODE_S  3
-/* ASSIST_DEBUG_LOG_ENA : R/W ;bitpos:[2:0] ;default: 3'b0 ; */
-/*description: Need add description.*/
-#define ASSIST_DEBUG_LOG_ENA    0x00000007
-#define ASSIST_DEBUG_LOG_ENA_M  ((ASSIST_DEBUG_LOG_ENA_V)<<(ASSIST_DEBUG_LOG_ENA_S))
-#define ASSIST_DEBUG_LOG_ENA_V  0x7
-#define ASSIST_DEBUG_LOG_ENA_S  0
 
-#define ASSIST_DEBUG_LOG_DATA_0_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x74)
-/* ASSIST_DEBUG_LOG_DATA_0 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: Need add description.*/
-#define ASSIST_DEBUG_LOG_DATA_0    0xFFFFFFFF
-#define ASSIST_DEBUG_LOG_DATA_0_M  ((ASSIST_DEBUG_LOG_DATA_0_V)<<(ASSIST_DEBUG_LOG_DATA_0_S))
-#define ASSIST_DEBUG_LOG_DATA_0_V  0xFFFFFFFF
+/** ASSIST_DEBUG_LOG_DATA_0_REG register
+ *  register description
+ */
+#define ASSIST_DEBUG_LOG_DATA_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x74)
+/** ASSIST_DEBUG_LOG_DATA_0 : R/W; bitpos: [31:0]; default: 0;
+ *  Need add description
+ */
+#define ASSIST_DEBUG_LOG_DATA_0    0xFFFFFFFFU
+#define ASSIST_DEBUG_LOG_DATA_0_M  (ASSIST_DEBUG_LOG_DATA_0_V << ASSIST_DEBUG_LOG_DATA_0_S)
+#define ASSIST_DEBUG_LOG_DATA_0_V  0xFFFFFFFFU
 #define ASSIST_DEBUG_LOG_DATA_0_S  0
 
-#define ASSIST_DEBUG_LOG_DATA_MASK_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x78)
-/* ASSIST_DEBUG_LOG_DATA_SIZE : R/W ;bitpos:[15:0] ;default: 16'b0 ; */
-/*description: Need add description.*/
-#define ASSIST_DEBUG_LOG_DATA_SIZE    0x0000FFFF
-#define ASSIST_DEBUG_LOG_DATA_SIZE_M  ((ASSIST_DEBUG_LOG_DATA_SIZE_V)<<(ASSIST_DEBUG_LOG_DATA_SIZE_S))
-#define ASSIST_DEBUG_LOG_DATA_SIZE_V  0xFFFF
+/** ASSIST_DEBUG_LOG_DATA_MASK_REG register
+ *  register description
+ */
+#define ASSIST_DEBUG_LOG_DATA_MASK_REG (DR_REG_ASSIST_DEBUG_BASE + 0x78)
+/** ASSIST_DEBUG_LOG_DATA_SIZE : R/W; bitpos: [15:0]; default: 0;
+ *  Need add description
+ */
+#define ASSIST_DEBUG_LOG_DATA_SIZE    0x0000FFFFU
+#define ASSIST_DEBUG_LOG_DATA_SIZE_M  (ASSIST_DEBUG_LOG_DATA_SIZE_V << ASSIST_DEBUG_LOG_DATA_SIZE_S)
+#define ASSIST_DEBUG_LOG_DATA_SIZE_V  0x0000FFFFU
 #define ASSIST_DEBUG_LOG_DATA_SIZE_S  0
 
-#define ASSIST_DEBUG_LOG_MIN_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x7C)
-/* ASSIST_DEBUG_LOG_MIN : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: Need add description.*/
-#define ASSIST_DEBUG_LOG_MIN    0xFFFFFFFF
-#define ASSIST_DEBUG_LOG_MIN_M  ((ASSIST_DEBUG_LOG_MIN_V)<<(ASSIST_DEBUG_LOG_MIN_S))
-#define ASSIST_DEBUG_LOG_MIN_V  0xFFFFFFFF
+/** ASSIST_DEBUG_LOG_MIN_REG register
+ *  register description
+ */
+#define ASSIST_DEBUG_LOG_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x7c)
+/** ASSIST_DEBUG_LOG_MIN : R/W; bitpos: [31:0]; default: 0;
+ *  Need add description
+ */
+#define ASSIST_DEBUG_LOG_MIN    0xFFFFFFFFU
+#define ASSIST_DEBUG_LOG_MIN_M  (ASSIST_DEBUG_LOG_MIN_V << ASSIST_DEBUG_LOG_MIN_S)
+#define ASSIST_DEBUG_LOG_MIN_V  0xFFFFFFFFU
 #define ASSIST_DEBUG_LOG_MIN_S  0
 
-#define ASSIST_DEBUG_LOG_MAX_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x80)
-/* ASSIST_DEBUG_LOG_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: Need add description.*/
-#define ASSIST_DEBUG_LOG_MAX    0xFFFFFFFF
-#define ASSIST_DEBUG_LOG_MAX_M  ((ASSIST_DEBUG_LOG_MAX_V)<<(ASSIST_DEBUG_LOG_MAX_S))
-#define ASSIST_DEBUG_LOG_MAX_V  0xFFFFFFFF
+/** ASSIST_DEBUG_LOG_MAX_REG register
+ *  register description
+ */
+#define ASSIST_DEBUG_LOG_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x80)
+/** ASSIST_DEBUG_LOG_MAX : R/W; bitpos: [31:0]; default: 0;
+ *  Need add description
+ */
+#define ASSIST_DEBUG_LOG_MAX    0xFFFFFFFFU
+#define ASSIST_DEBUG_LOG_MAX_M  (ASSIST_DEBUG_LOG_MAX_V << ASSIST_DEBUG_LOG_MAX_S)
+#define ASSIST_DEBUG_LOG_MAX_V  0xFFFFFFFFU
 #define ASSIST_DEBUG_LOG_MAX_S  0
 
-#define ASSIST_DEBUG_LOG_MEM_START_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x84)
-/* ASSIST_DEBUG_LOG_MEM_START : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: Need add description.*/
-#define ASSIST_DEBUG_LOG_MEM_START    0xFFFFFFFF
-#define ASSIST_DEBUG_LOG_MEM_START_M  ((ASSIST_DEBUG_LOG_MEM_START_V)<<(ASSIST_DEBUG_LOG_MEM_START_S))
-#define ASSIST_DEBUG_LOG_MEM_START_V  0xFFFFFFFF
+/** ASSIST_DEBUG_LOG_MEM_START_REG register
+ *  register description
+ */
+#define ASSIST_DEBUG_LOG_MEM_START_REG (DR_REG_ASSIST_DEBUG_BASE + 0x84)
+/** ASSIST_DEBUG_LOG_MEM_START : R/W; bitpos: [31:0]; default: 0;
+ *  Need add description
+ */
+#define ASSIST_DEBUG_LOG_MEM_START    0xFFFFFFFFU
+#define ASSIST_DEBUG_LOG_MEM_START_M  (ASSIST_DEBUG_LOG_MEM_START_V << ASSIST_DEBUG_LOG_MEM_START_S)
+#define ASSIST_DEBUG_LOG_MEM_START_V  0xFFFFFFFFU
 #define ASSIST_DEBUG_LOG_MEM_START_S  0
 
-#define ASSIST_DEBUG_LOG_MEM_END_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x88)
-/* ASSIST_DEBUG_LOG_MEM_END : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: Need add description.*/
-#define ASSIST_DEBUG_LOG_MEM_END    0xFFFFFFFF
-#define ASSIST_DEBUG_LOG_MEM_END_M  ((ASSIST_DEBUG_LOG_MEM_END_V)<<(ASSIST_DEBUG_LOG_MEM_END_S))
-#define ASSIST_DEBUG_LOG_MEM_END_V  0xFFFFFFFF
+/** ASSIST_DEBUG_LOG_MEM_END_REG register
+ *  register description
+ */
+#define ASSIST_DEBUG_LOG_MEM_END_REG (DR_REG_ASSIST_DEBUG_BASE + 0x88)
+/** ASSIST_DEBUG_LOG_MEM_END : R/W; bitpos: [31:0]; default: 0;
+ *  Need add description
+ */
+#define ASSIST_DEBUG_LOG_MEM_END    0xFFFFFFFFU
+#define ASSIST_DEBUG_LOG_MEM_END_M  (ASSIST_DEBUG_LOG_MEM_END_V << ASSIST_DEBUG_LOG_MEM_END_S)
+#define ASSIST_DEBUG_LOG_MEM_END_V  0xFFFFFFFFU
 #define ASSIST_DEBUG_LOG_MEM_END_S  0
 
-#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x8C)
-/* ASSIST_DEBUG_LOG_MEM_WRITING_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: Need add description.*/
-#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR    0xFFFFFFFF
-#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_M  ((ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_V)<<(ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_S))
-#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_V  0xFFFFFFFF
+/** ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_REG register
+ *  register description
+ */
+#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_REG (DR_REG_ASSIST_DEBUG_BASE + 0x8c)
+/** ASSIST_DEBUG_LOG_MEM_WRITING_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  Need add description
+ */
+#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR    0xFFFFFFFFU
+#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_M  (ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_V << ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_S)
+#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_V  0xFFFFFFFFU
 #define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_S  0
 
-#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x90)
-/* ASSIST_DEBUG_CLR_LOG_MEM_FULL_FLAG : R/W ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Need add description.*/
-#define ASSIST_DEBUG_CLR_LOG_MEM_FULL_FLAG    (BIT(1))
-#define ASSIST_DEBUG_CLR_LOG_MEM_FULL_FLAG_M  (BIT(1))
-#define ASSIST_DEBUG_CLR_LOG_MEM_FULL_FLAG_V  0x1
-#define ASSIST_DEBUG_CLR_LOG_MEM_FULL_FLAG_S  1
-/* ASSIST_DEBUG_LOG_MEM_FULL_FLAG : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Need add description.*/
+/** ASSIST_DEBUG_LOG_MEM_FULL_FLAG_REG register
+ *  register description
+ */
+#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG_REG (DR_REG_ASSIST_DEBUG_BASE + 0x90)
+/** ASSIST_DEBUG_LOG_MEM_FULL_FLAG : RO; bitpos: [0]; default: 0;
+ *  Need add description
+ */
 #define ASSIST_DEBUG_LOG_MEM_FULL_FLAG    (BIT(0))
-#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG_M  (BIT(0))
-#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG_V  0x1
+#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG_M  (ASSIST_DEBUG_LOG_MEM_FULL_FLAG_V << ASSIST_DEBUG_LOG_MEM_FULL_FLAG_S)
+#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG_V  0x00000001U
 #define ASSIST_DEBUG_LOG_MEM_FULL_FLAG_S  0
+/** ASSIST_DEBUG_CLR_LOG_MEM_FULL_FLAG : R/W; bitpos: [1]; default: 0;
+ *  Need add description
+ */
+#define ASSIST_DEBUG_CLR_LOG_MEM_FULL_FLAG    (BIT(1))
+#define ASSIST_DEBUG_CLR_LOG_MEM_FULL_FLAG_M  (ASSIST_DEBUG_CLR_LOG_MEM_FULL_FLAG_V << ASSIST_DEBUG_CLR_LOG_MEM_FULL_FLAG_S)
+#define ASSIST_DEBUG_CLR_LOG_MEM_FULL_FLAG_V  0x00000001U
+#define ASSIST_DEBUG_CLR_LOG_MEM_FULL_FLAG_S  1
 
-#define ASSIST_DEBUG_C0RE_0_LASTPC_BEFORE_EXCEPTION_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x94)
-/* ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: Need add description.*/
-#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC    0xFFFFFFFF
-#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_M  ((ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V)<<(ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S))
-#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V  0xFFFFFFFF
+/** ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXCEPTION_REG register
+ *  register description
+ */
+#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXCEPTION_REG (DR_REG_ASSIST_DEBUG_BASE + 0x94)
+/** ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC : RO; bitpos: [31:0]; default: 0;
+ *  Need add description
+ */
+#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC    0xFFFFFFFFU
+#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_M  (ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V << ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S)
+#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V  0xFFFFFFFFU
 #define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S  0
 
-#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x98)
-/* ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Need add description.*/
-#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE    (BIT(1))
-#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_M  (BIT(1))
-#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_V  0x1
-#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_S  1
-/* ASSIST_DEBUG_CORE_0_DEBUG_MODE : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Need add description.*/
+/** ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG register
+ *  register description
+ */
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x98)
+/** ASSIST_DEBUG_CORE_0_DEBUG_MODE : RO; bitpos: [0]; default: 0;
+ *  Need add description
+ */
 #define ASSIST_DEBUG_CORE_0_DEBUG_MODE    (BIT(0))
-#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_M  (BIT(0))
-#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_V  0x1
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_M  (ASSIST_DEBUG_CORE_0_DEBUG_MODE_V << ASSIST_DEBUG_CORE_0_DEBUG_MODE_S)
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_V  0x00000001U
 #define ASSIST_DEBUG_CORE_0_DEBUG_MODE_S  0
+/** ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE : RO; bitpos: [1]; default: 0;
+ *  Need add description
+ */
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE    (BIT(1))
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_M  (ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_V << ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_S)
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_V  0x00000001U
+#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_S  1
 
-#define ASSIST_DEBUG_DATE_REG          (DR_REG_ASSIST_DEBUG_BASE + 0x1FC)
-/* ASSIST_DEBUG_DATE : R/W ;bitpos:[27:0] ;default: 28'h2008010 ; */
-/*description: Need add description.*/
-#define ASSIST_DEBUG_DATE    0x0FFFFFFF
-#define ASSIST_DEBUG_DATE_M  ((ASSIST_DEBUG_DATE_V)<<(ASSIST_DEBUG_DATE_S))
-#define ASSIST_DEBUG_DATE_V  0xFFFFFFF
-#define ASSIST_DEBUG_DATE_S  0
-
+/** ASSIST_DEBUG_DATE_REG register
+ *  register description
+ */
+#define ASSIST_DEBUG_DATE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x1fc)
+/** ASSIST_DEBUG_ASSIST_DEBUG_DATE : R/W; bitpos: [27:0]; default: 33587216;
+ *  Need add description
+ */
+#define ASSIST_DEBUG_ASSIST_DEBUG_DATE    0x0FFFFFFFU
+#define ASSIST_DEBUG_ASSIST_DEBUG_DATE_M  (ASSIST_DEBUG_ASSIST_DEBUG_DATE_V << ASSIST_DEBUG_ASSIST_DEBUG_DATE_S)
+#define ASSIST_DEBUG_ASSIST_DEBUG_DATE_V  0x0FFFFFFFU
+#define ASSIST_DEBUG_ASSIST_DEBUG_DATE_S  0
 
 #ifdef __cplusplus
 }
 #endif
-
-
-
-#endif /*_SOC_ASSIST_DEBUG_REG_H_ */

components/soc/esp32h2/include/rev2/soc/clkrst_reg.h

@@ -0,0 +1,1274 @@
+/**
+ * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** SYSTEM_SYSCLK_CONF_REG register
+ *  register description
+ */
+#define SYSTEM_SYSCLK_CONF_REG (DR_REG_SYSTEM_BASE + 0x0)
+/** SYSTEM_CLK_XTAL_FREQ : RO; bitpos: [7:0]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_CLK_XTAL_FREQ    0x000000FFU
+#define SYSTEM_CLK_XTAL_FREQ_M  (SYSTEM_CLK_XTAL_FREQ_V << SYSTEM_CLK_XTAL_FREQ_S)
+#define SYSTEM_CLK_XTAL_FREQ_V  0x000000FFU
+#define SYSTEM_CLK_XTAL_FREQ_S  0
+/** SYSTEM_SPLL_FREQ : RO; bitpos: [15:8]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_SPLL_FREQ    0x000000FFU
+#define SYSTEM_SPLL_FREQ_M  (SYSTEM_SPLL_FREQ_V << SYSTEM_SPLL_FREQ_S)
+#define SYSTEM_SPLL_FREQ_V  0x000000FFU
+#define SYSTEM_SPLL_FREQ_S  8
+/** SYSTEM_SOC_CLK_SEL : R/W; bitpos: [17:16]; default: 3;
+ *  Need add description
+ */
+#define SYSTEM_SOC_CLK_SEL    0x00000003U
+#define SYSTEM_SOC_CLK_SEL_M  (SYSTEM_SOC_CLK_SEL_V << SYSTEM_SOC_CLK_SEL_S)
+#define SYSTEM_SOC_CLK_SEL_V  0x00000003U
+#define SYSTEM_SOC_CLK_SEL_S  16
+
+/** SYSTEM_CPUCLK_CONF_REG register
+ *  register description
+ */
+#define SYSTEM_CPUCLK_CONF_REG (DR_REG_SYSTEM_BASE + 0x4)
+/** SYSTEM_CPU_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_CPU_DIV_NUM    0x000000FFU
+#define SYSTEM_CPU_DIV_NUM_M  (SYSTEM_CPU_DIV_NUM_V << SYSTEM_CPU_DIV_NUM_S)
+#define SYSTEM_CPU_DIV_NUM_V  0x000000FFU
+#define SYSTEM_CPU_DIV_NUM_S  0
+/** SYSTEM_PRE_DIV_CNT : R/W; bitpos: [13:8]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_PRE_DIV_CNT    0x0000003FU
+#define SYSTEM_PRE_DIV_CNT_M  (SYSTEM_PRE_DIV_CNT_V << SYSTEM_PRE_DIV_CNT_S)
+#define SYSTEM_PRE_DIV_CNT_V  0x0000003FU
+#define SYSTEM_PRE_DIV_CNT_S  8
+/** SYSTEM_CPU_DIV_DENOMINATOR : R/W; bitpos: [21:16]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_CPU_DIV_DENOMINATOR    0x0000003FU
+#define SYSTEM_CPU_DIV_DENOMINATOR_M  (SYSTEM_CPU_DIV_DENOMINATOR_V << SYSTEM_CPU_DIV_DENOMINATOR_S)
+#define SYSTEM_CPU_DIV_DENOMINATOR_V  0x0000003FU
+#define SYSTEM_CPU_DIV_DENOMINATOR_S  16
+
+/** SYSTEM_BUSCLK_CONF_REG register
+ *  register description
+ */
+#define SYSTEM_BUSCLK_CONF_REG (DR_REG_SYSTEM_BASE + 0x8)
+/** SYSTEM_APB_DIV_NUM : R/W; bitpos: [7:0]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_APB_DIV_NUM    0x000000FFU
+#define SYSTEM_APB_DIV_NUM_M  (SYSTEM_APB_DIV_NUM_V << SYSTEM_APB_DIV_NUM_S)
+#define SYSTEM_APB_DIV_NUM_V  0x000000FFU
+#define SYSTEM_APB_DIV_NUM_S  0
+/** SYSTEM_AHB_DIV_NUM : R/W; bitpos: [15:8]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_AHB_DIV_NUM    0x000000FFU
+#define SYSTEM_AHB_DIV_NUM_M  (SYSTEM_AHB_DIV_NUM_V << SYSTEM_AHB_DIV_NUM_S)
+#define SYSTEM_AHB_DIV_NUM_V  0x000000FFU
+#define SYSTEM_AHB_DIV_NUM_S  8
+
+/** SYSTEM_MODCLK_CONF_REG register
+ *  register description
+ */
+#define SYSTEM_MODCLK_CONF_REG (DR_REG_SYSTEM_BASE + 0xc)
+/** SYSTEM_MODEM_CLK_SEL : R/W; bitpos: [1:0]; default: 1;
+ *  Need add description
+ */
+#define SYSTEM_MODEM_CLK_SEL    0x00000003U
+#define SYSTEM_MODEM_CLK_SEL_M  (SYSTEM_MODEM_CLK_SEL_V << SYSTEM_MODEM_CLK_SEL_S)
+#define SYSTEM_MODEM_CLK_SEL_V  0x00000003U
+#define SYSTEM_MODEM_CLK_SEL_S  0
+/** SYSTEM_ETM_CLK_SEL : R/W; bitpos: [2]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_ETM_CLK_SEL    (BIT(2))
+#define SYSTEM_ETM_CLK_SEL_M  (SYSTEM_ETM_CLK_SEL_V << SYSTEM_ETM_CLK_SEL_S)
+#define SYSTEM_ETM_CLK_SEL_V  0x00000001U
+#define SYSTEM_ETM_CLK_SEL_S  2
+/** SYSTEM_ETM_CLK_ACTIVE : R/W; bitpos: [3]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_ETM_CLK_ACTIVE    (BIT(3))
+#define SYSTEM_ETM_CLK_ACTIVE_M  (SYSTEM_ETM_CLK_ACTIVE_V << SYSTEM_ETM_CLK_ACTIVE_S)
+#define SYSTEM_ETM_CLK_ACTIVE_V  0x00000001U
+#define SYSTEM_ETM_CLK_ACTIVE_S  3
+/** SYSTEM_COEX_LPCLK_SEL : R/W; bitpos: [5:4]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_COEX_LPCLK_SEL    0x00000003U
+#define SYSTEM_COEX_LPCLK_SEL_M  (SYSTEM_COEX_LPCLK_SEL_V << SYSTEM_COEX_LPCLK_SEL_S)
+#define SYSTEM_COEX_LPCLK_SEL_V  0x00000003U
+#define SYSTEM_COEX_LPCLK_SEL_S  4
+/** SYSTEM_COEX_LPCLK_DIV : R/W; bitpos: [15:6]; default: 999;
+ *  Need add description
+ */
+#define SYSTEM_COEX_LPCLK_DIV    0x000003FFU
+#define SYSTEM_COEX_LPCLK_DIV_M  (SYSTEM_COEX_LPCLK_DIV_V << SYSTEM_COEX_LPCLK_DIV_S)
+#define SYSTEM_COEX_LPCLK_DIV_V  0x000003FFU
+#define SYSTEM_COEX_LPCLK_DIV_S  6
+
+/** SYSTEM_CLK_OUT_EN_REG register
+ *  register description
+ */
+#define SYSTEM_CLK_OUT_EN_REG (DR_REG_SYSTEM_BASE + 0x10)
+/** SYSTEM_CLK_8M_BT_OEN : R/W; bitpos: [3]; default: 1;
+ *  Need add description
+ */
+#define SYSTEM_CLK_8M_BT_OEN    (BIT(3))
+#define SYSTEM_CLK_8M_BT_OEN_M  (SYSTEM_CLK_8M_BT_OEN_V << SYSTEM_CLK_8M_BT_OEN_S)
+#define SYSTEM_CLK_8M_BT_OEN_V  0x00000001U
+#define SYSTEM_CLK_8M_BT_OEN_S  3
+/** SYSTEM_CLK_16M_BT_OEN : R/W; bitpos: [4]; default: 1;
+ *  Need add description
+ */
+#define SYSTEM_CLK_16M_BT_OEN    (BIT(4))
+#define SYSTEM_CLK_16M_BT_OEN_M  (SYSTEM_CLK_16M_BT_OEN_V << SYSTEM_CLK_16M_BT_OEN_S)
+#define SYSTEM_CLK_16M_BT_OEN_V  0x00000001U
+#define SYSTEM_CLK_16M_BT_OEN_S  4
+/** SYSTEM_CLK_32M_BT_OEN : R/W; bitpos: [5]; default: 1;
+ *  Need add description
+ */
+#define SYSTEM_CLK_32M_BT_OEN    (BIT(5))
+#define SYSTEM_CLK_32M_BT_OEN_M  (SYSTEM_CLK_32M_BT_OEN_V << SYSTEM_CLK_32M_BT_OEN_S)
+#define SYSTEM_CLK_32M_BT_OEN_V  0x00000001U
+#define SYSTEM_CLK_32M_BT_OEN_S  5
+/** SYSTEM_CLK_APB_OEN : R/W; bitpos: [6]; default: 1;
+ *  Need add description
+ */
+#define SYSTEM_CLK_APB_OEN    (BIT(6))
+#define SYSTEM_CLK_APB_OEN_M  (SYSTEM_CLK_APB_OEN_V << SYSTEM_CLK_APB_OEN_S)
+#define SYSTEM_CLK_APB_OEN_V  0x00000001U
+#define SYSTEM_CLK_APB_OEN_S  6
+/** SYSTEM_CLK_AHB_OEN : R/W; bitpos: [7]; default: 1;
+ *  Need add description
+ */
+#define SYSTEM_CLK_AHB_OEN    (BIT(7))
+#define SYSTEM_CLK_AHB_OEN_M  (SYSTEM_CLK_AHB_OEN_V << SYSTEM_CLK_AHB_OEN_S)
+#define SYSTEM_CLK_AHB_OEN_V  0x00000001U
+#define SYSTEM_CLK_AHB_OEN_S  7
+/** SYSTEM_CLK_CPU_OEN : R/W; bitpos: [8]; default: 1;
+ *  Need add description
+ */
+#define SYSTEM_CLK_CPU_OEN    (BIT(8))
+#define SYSTEM_CLK_CPU_OEN_M  (SYSTEM_CLK_CPU_OEN_V << SYSTEM_CLK_CPU_OEN_S)
+#define SYSTEM_CLK_CPU_OEN_V  0x00000001U
+#define SYSTEM_CLK_CPU_OEN_S  8
+/** SYSTEM_CLK_SPLL_OEN : R/W; bitpos: [9]; default: 1;
+ *  Need add description
+ */
+#define SYSTEM_CLK_SPLL_OEN    (BIT(9))
+#define SYSTEM_CLK_SPLL_OEN_M  (SYSTEM_CLK_SPLL_OEN_V << SYSTEM_CLK_SPLL_OEN_S)
+#define SYSTEM_CLK_SPLL_OEN_V  0x00000001U
+#define SYSTEM_CLK_SPLL_OEN_S  9
+/** SYSTEM_CLK_XTAL_OEN : R/W; bitpos: [10]; default: 1;
+ *  Need add description
+ */
+#define SYSTEM_CLK_XTAL_OEN    (BIT(10))
+#define SYSTEM_CLK_XTAL_OEN_M  (SYSTEM_CLK_XTAL_OEN_V << SYSTEM_CLK_XTAL_OEN_S)
+#define SYSTEM_CLK_XTAL_OEN_V  0x00000001U
+#define SYSTEM_CLK_XTAL_OEN_S  10
+/** SYSTEM_CLK_RFDAC_OEN : R/W; bitpos: [11]; default: 1;
+ *  Need add description
+ */
+#define SYSTEM_CLK_RFDAC_OEN    (BIT(11))
+#define SYSTEM_CLK_RFDAC_OEN_M  (SYSTEM_CLK_RFDAC_OEN_V << SYSTEM_CLK_RFDAC_OEN_S)
+#define SYSTEM_CLK_RFDAC_OEN_V  0x00000001U
+#define SYSTEM_CLK_RFDAC_OEN_S  11
+/** SYSTEM_CLK_RFADC_OEN : R/W; bitpos: [12]; default: 1;
+ *  Need add description
+ */
+#define SYSTEM_CLK_RFADC_OEN    (BIT(12))
+#define SYSTEM_CLK_RFADC_OEN_M  (SYSTEM_CLK_RFADC_OEN_V << SYSTEM_CLK_RFADC_OEN_S)
+#define SYSTEM_CLK_RFADC_OEN_V  0x00000001U
+#define SYSTEM_CLK_RFADC_OEN_S  12
+
+/** SYSTEM_MODEM_CLK_EN_REG register
+ *  register description
+ */
+#define SYSTEM_MODEM_CLK_EN_REG (DR_REG_SYSTEM_BASE + 0x14)
+/** SYSTEM_FE_CAL_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_FE_CAL_CLK_EN    (BIT(0))
+#define SYSTEM_FE_CAL_CLK_EN_M  (SYSTEM_FE_CAL_CLK_EN_V << SYSTEM_FE_CAL_CLK_EN_S)
+#define SYSTEM_FE_CAL_CLK_EN_V  0x00000001U
+#define SYSTEM_FE_CAL_CLK_EN_S  0
+/** SYSTEM_FE_CLK_EN : R/W; bitpos: [1]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_FE_CLK_EN    (BIT(1))
+#define SYSTEM_FE_CLK_EN_M  (SYSTEM_FE_CLK_EN_V << SYSTEM_FE_CLK_EN_S)
+#define SYSTEM_FE_CLK_EN_V  0x00000001U
+#define SYSTEM_FE_CLK_EN_S  1
+/** SYSTEM_MAC_CLK_EN : R/W; bitpos: [2]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_MAC_CLK_EN    (BIT(2))
+#define SYSTEM_MAC_CLK_EN_M  (SYSTEM_MAC_CLK_EN_V << SYSTEM_MAC_CLK_EN_S)
+#define SYSTEM_MAC_CLK_EN_V  0x00000001U
+#define SYSTEM_MAC_CLK_EN_S  2
+/** SYSTEM_BT_CLK_EN : R/W; bitpos: [3]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_BT_CLK_EN    (BIT(3))
+#define SYSTEM_BT_CLK_EN_M  (SYSTEM_BT_CLK_EN_V << SYSTEM_BT_CLK_EN_S)
+#define SYSTEM_BT_CLK_EN_V  0x00000001U
+#define SYSTEM_BT_CLK_EN_S  3
+/** SYSTEM_BTMAC_CLK_EN : R/W; bitpos: [4]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_BTMAC_CLK_EN    (BIT(4))
+#define SYSTEM_BTMAC_CLK_EN_M  (SYSTEM_BTMAC_CLK_EN_V << SYSTEM_BTMAC_CLK_EN_S)
+#define SYSTEM_BTMAC_CLK_EN_V  0x00000001U
+#define SYSTEM_BTMAC_CLK_EN_S  4
+/** SYSTEM_SDIO_CLK_EN : R/W; bitpos: [5]; default: 1;
+ *  Need add description
+ */
+#define SYSTEM_SDIO_CLK_EN    (BIT(5))
+#define SYSTEM_SDIO_CLK_EN_M  (SYSTEM_SDIO_CLK_EN_V << SYSTEM_SDIO_CLK_EN_S)
+#define SYSTEM_SDIO_CLK_EN_V  0x00000001U
+#define SYSTEM_SDIO_CLK_EN_S  5
+/** SYSTEM_EMAC_CLK_EN : R/W; bitpos: [6]; default: 1;
+ *  Need add description
+ */
+#define SYSTEM_EMAC_CLK_EN    (BIT(6))
+#define SYSTEM_EMAC_CLK_EN_M  (SYSTEM_EMAC_CLK_EN_V << SYSTEM_EMAC_CLK_EN_S)
+#define SYSTEM_EMAC_CLK_EN_V  0x00000001U
+#define SYSTEM_EMAC_CLK_EN_S  6
+/** SYSTEM_MACPWR_CLK_EN : R/W; bitpos: [7]; default: 1;
+ *  Need add description
+ */
+#define SYSTEM_MACPWR_CLK_EN    (BIT(7))
+#define SYSTEM_MACPWR_CLK_EN_M  (SYSTEM_MACPWR_CLK_EN_V << SYSTEM_MACPWR_CLK_EN_S)
+#define SYSTEM_MACPWR_CLK_EN_V  0x00000001U
+#define SYSTEM_MACPWR_CLK_EN_S  7
+/** SYSTEM_RW_BTMAC_CLK_EN : R/W; bitpos: [8]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_RW_BTMAC_CLK_EN    (BIT(8))
+#define SYSTEM_RW_BTMAC_CLK_EN_M  (SYSTEM_RW_BTMAC_CLK_EN_V << SYSTEM_RW_BTMAC_CLK_EN_S)
+#define SYSTEM_RW_BTMAC_CLK_EN_V  0x00000001U
+#define SYSTEM_RW_BTMAC_CLK_EN_S  8
+/** SYSTEM_I2C_CLK_EN : R/W; bitpos: [9]; default: 1;
+ *  Need add description
+ */
+#define SYSTEM_I2C_CLK_EN    (BIT(9))
+#define SYSTEM_I2C_CLK_EN_M  (SYSTEM_I2C_CLK_EN_V << SYSTEM_I2C_CLK_EN_S)
+#define SYSTEM_I2C_CLK_EN_V  0x00000001U
+#define SYSTEM_I2C_CLK_EN_S  9
+/** SYSTEM_I2CMST_CLK_EN : R/W; bitpos: [10]; default: 1;
+ *  Need add description
+ */
+#define SYSTEM_I2CMST_CLK_EN    (BIT(10))
+#define SYSTEM_I2CMST_CLK_EN_M  (SYSTEM_I2CMST_CLK_EN_V << SYSTEM_I2CMST_CLK_EN_S)
+#define SYSTEM_I2CMST_CLK_EN_V  0x00000001U
+#define SYSTEM_I2CMST_CLK_EN_S  10
+/** SYSTEM_COEX_CLK_EN : R/W; bitpos: [11]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_COEX_CLK_EN    (BIT(11))
+#define SYSTEM_COEX_CLK_EN_M  (SYSTEM_COEX_CLK_EN_V << SYSTEM_COEX_CLK_EN_S)
+#define SYSTEM_COEX_CLK_EN_V  0x00000001U
+#define SYSTEM_COEX_CLK_EN_S  11
+/** SYSTEM_IEEE802154BB_CLK_EN : R/W; bitpos: [12]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_IEEE802154BB_CLK_EN    (BIT(12))
+#define SYSTEM_IEEE802154BB_CLK_EN_M  (SYSTEM_IEEE802154BB_CLK_EN_V << SYSTEM_IEEE802154BB_CLK_EN_S)
+#define SYSTEM_IEEE802154BB_CLK_EN_V  0x00000001U
+#define SYSTEM_IEEE802154BB_CLK_EN_S  12
+/** SYSTEM_IEEE802154MAC_CLK_EN : R/W; bitpos: [13]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_IEEE802154MAC_CLK_EN    (BIT(13))
+#define SYSTEM_IEEE802154MAC_CLK_EN_M  (SYSTEM_IEEE802154MAC_CLK_EN_V << SYSTEM_IEEE802154MAC_CLK_EN_S)
+#define SYSTEM_IEEE802154MAC_CLK_EN_V  0x00000001U
+#define SYSTEM_IEEE802154MAC_CLK_EN_S  13
+/** SYSTEM_BLE_SEC_ECB_CLK_EN : R/W; bitpos: [14]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_BLE_SEC_ECB_CLK_EN    (BIT(14))
+#define SYSTEM_BLE_SEC_ECB_CLK_EN_M  (SYSTEM_BLE_SEC_ECB_CLK_EN_V << SYSTEM_BLE_SEC_ECB_CLK_EN_S)
+#define SYSTEM_BLE_SEC_ECB_CLK_EN_V  0x00000001U
+#define SYSTEM_BLE_SEC_ECB_CLK_EN_S  14
+/** SYSTEM_BLE_SEC_CCM_CLK_EN : R/W; bitpos: [15]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_BLE_SEC_CCM_CLK_EN    (BIT(15))
+#define SYSTEM_BLE_SEC_CCM_CLK_EN_M  (SYSTEM_BLE_SEC_CCM_CLK_EN_V << SYSTEM_BLE_SEC_CCM_CLK_EN_S)
+#define SYSTEM_BLE_SEC_CCM_CLK_EN_V  0x00000001U
+#define SYSTEM_BLE_SEC_CCM_CLK_EN_S  15
+/** SYSTEM_BLE_SEC_AAR_CLK_EN : R/W; bitpos: [16]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_BLE_SEC_AAR_CLK_EN    (BIT(16))
+#define SYSTEM_BLE_SEC_AAR_CLK_EN_M  (SYSTEM_BLE_SEC_AAR_CLK_EN_V << SYSTEM_BLE_SEC_AAR_CLK_EN_S)
+#define SYSTEM_BLE_SEC_AAR_CLK_EN_V  0x00000001U
+#define SYSTEM_BLE_SEC_AAR_CLK_EN_S  16
+/** SYSTEM_BLE_SEC_CLK_EN : R/W; bitpos: [17]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_BLE_SEC_CLK_EN    (BIT(17))
+#define SYSTEM_BLE_SEC_CLK_EN_M  (SYSTEM_BLE_SEC_CLK_EN_V << SYSTEM_BLE_SEC_CLK_EN_S)
+#define SYSTEM_BLE_SEC_CLK_EN_V  0x00000001U
+#define SYSTEM_BLE_SEC_CLK_EN_S  17
+/** SYSTEM_BTLC_CLK_EN : R/W; bitpos: [18]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_BTLC_CLK_EN    (BIT(18))
+#define SYSTEM_BTLC_CLK_EN_M  (SYSTEM_BTLC_CLK_EN_V << SYSTEM_BTLC_CLK_EN_S)
+#define SYSTEM_BTLC_CLK_EN_V  0x00000001U
+#define SYSTEM_BTLC_CLK_EN_S  18
+/** SYSTEM_RFDAC_CLK_EN : R/W; bitpos: [19]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_RFDAC_CLK_EN    (BIT(19))
+#define SYSTEM_RFDAC_CLK_EN_M  (SYSTEM_RFDAC_CLK_EN_V << SYSTEM_RFDAC_CLK_EN_S)
+#define SYSTEM_RFDAC_CLK_EN_V  0x00000001U
+#define SYSTEM_RFDAC_CLK_EN_S  19
+/** SYSTEM_RFADC_CLK_EN : R/W; bitpos: [20]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_RFADC_CLK_EN    (BIT(20))
+#define SYSTEM_RFADC_CLK_EN_M  (SYSTEM_RFADC_CLK_EN_V << SYSTEM_RFADC_CLK_EN_S)
+#define SYSTEM_RFADC_CLK_EN_V  0x00000001U
+#define SYSTEM_RFADC_CLK_EN_S  20
+/** SYSTEM_DATA_DUMP_CLK_EN : R/W; bitpos: [21]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_DATA_DUMP_CLK_EN    (BIT(21))
+#define SYSTEM_DATA_DUMP_CLK_EN_M  (SYSTEM_DATA_DUMP_CLK_EN_V << SYSTEM_DATA_DUMP_CLK_EN_S)
+#define SYSTEM_DATA_DUMP_CLK_EN_V  0x00000001U
+#define SYSTEM_DATA_DUMP_CLK_EN_S  21
+
+/** SYSTEM_MODEM_RST_EN_REG register
+ *  register description
+ */
+#define SYSTEM_MODEM_RST_EN_REG (DR_REG_SYSTEM_BASE + 0x18)
+/** SYSTEM_FE_RST : R/W; bitpos: [0]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_FE_RST    (BIT(0))
+#define SYSTEM_FE_RST_M  (SYSTEM_FE_RST_V << SYSTEM_FE_RST_S)
+#define SYSTEM_FE_RST_V  0x00000001U
+#define SYSTEM_FE_RST_S  0
+/** SYSTEM_MAC_RST : R/W; bitpos: [1]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_MAC_RST    (BIT(1))
+#define SYSTEM_MAC_RST_M  (SYSTEM_MAC_RST_V << SYSTEM_MAC_RST_S)
+#define SYSTEM_MAC_RST_V  0x00000001U
+#define SYSTEM_MAC_RST_S  1
+/** SYSTEM_BT_RST : R/W; bitpos: [2]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_BT_RST    (BIT(2))
+#define SYSTEM_BT_RST_M  (SYSTEM_BT_RST_V << SYSTEM_BT_RST_S)
+#define SYSTEM_BT_RST_V  0x00000001U
+#define SYSTEM_BT_RST_S  2
+/** SYSTEM_BTMAC_RST : R/W; bitpos: [3]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_BTMAC_RST    (BIT(3))
+#define SYSTEM_BTMAC_RST_M  (SYSTEM_BTMAC_RST_V << SYSTEM_BTMAC_RST_S)
+#define SYSTEM_BTMAC_RST_V  0x00000001U
+#define SYSTEM_BTMAC_RST_S  3
+/** SYSTEM_SDIO_RST : R/W; bitpos: [4]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_SDIO_RST    (BIT(4))
+#define SYSTEM_SDIO_RST_M  (SYSTEM_SDIO_RST_V << SYSTEM_SDIO_RST_S)
+#define SYSTEM_SDIO_RST_V  0x00000001U
+#define SYSTEM_SDIO_RST_S  4
+/** SYSTEM_EMAC_RST : R/W; bitpos: [5]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_EMAC_RST    (BIT(5))
+#define SYSTEM_EMAC_RST_M  (SYSTEM_EMAC_RST_V << SYSTEM_EMAC_RST_S)
+#define SYSTEM_EMAC_RST_V  0x00000001U
+#define SYSTEM_EMAC_RST_S  5
+/** SYSTEM_MACPWR_RST : R/W; bitpos: [6]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_MACPWR_RST    (BIT(6))
+#define SYSTEM_MACPWR_RST_M  (SYSTEM_MACPWR_RST_V << SYSTEM_MACPWR_RST_S)
+#define SYSTEM_MACPWR_RST_V  0x00000001U
+#define SYSTEM_MACPWR_RST_S  6
+/** SYSTEM_RW_BTMAC_RST : R/W; bitpos: [7]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_RW_BTMAC_RST    (BIT(7))
+#define SYSTEM_RW_BTMAC_RST_M  (SYSTEM_RW_BTMAC_RST_V << SYSTEM_RW_BTMAC_RST_S)
+#define SYSTEM_RW_BTMAC_RST_V  0x00000001U
+#define SYSTEM_RW_BTMAC_RST_S  7
+/** SYSTEM_RW_BTLP_RST : R/W; bitpos: [8]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_RW_BTLP_RST    (BIT(8))
+#define SYSTEM_RW_BTLP_RST_M  (SYSTEM_RW_BTLP_RST_V << SYSTEM_RW_BTLP_RST_S)
+#define SYSTEM_RW_BTLP_RST_V  0x00000001U
+#define SYSTEM_RW_BTLP_RST_S  8
+/** SYSTEM_RW_BTREG_RST : R/W; bitpos: [9]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_RW_BTREG_RST    (BIT(9))
+#define SYSTEM_RW_BTREG_RST_M  (SYSTEM_RW_BTREG_RST_V << SYSTEM_RW_BTREG_RST_S)
+#define SYSTEM_RW_BTREG_RST_V  0x00000001U
+#define SYSTEM_RW_BTREG_RST_S  9
+/** SYSTEM_RW_BTLPREG_RST : R/W; bitpos: [10]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_RW_BTLPREG_RST    (BIT(10))
+#define SYSTEM_RW_BTLPREG_RST_M  (SYSTEM_RW_BTLPREG_RST_V << SYSTEM_RW_BTLPREG_RST_S)
+#define SYSTEM_RW_BTLPREG_RST_V  0x00000001U
+#define SYSTEM_RW_BTLPREG_RST_S  10
+/** SYSTEM_BT_REG_RST : R/W; bitpos: [11]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_BT_REG_RST    (BIT(11))
+#define SYSTEM_BT_REG_RST_M  (SYSTEM_BT_REG_RST_V << SYSTEM_BT_REG_RST_S)
+#define SYSTEM_BT_REG_RST_V  0x00000001U
+#define SYSTEM_BT_REG_RST_S  11
+/** SYSTEM_COEX_RST : R/W; bitpos: [12]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_COEX_RST    (BIT(12))
+#define SYSTEM_COEX_RST_M  (SYSTEM_COEX_RST_V << SYSTEM_COEX_RST_S)
+#define SYSTEM_COEX_RST_V  0x00000001U
+#define SYSTEM_COEX_RST_S  12
+/** SYSTEM_IEEE802154BB_RST : R/W; bitpos: [13]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_IEEE802154BB_RST    (BIT(13))
+#define SYSTEM_IEEE802154BB_RST_M  (SYSTEM_IEEE802154BB_RST_V << SYSTEM_IEEE802154BB_RST_S)
+#define SYSTEM_IEEE802154BB_RST_V  0x00000001U
+#define SYSTEM_IEEE802154BB_RST_S  13
+/** SYSTEM_IEEE802154MAC_RST : R/W; bitpos: [14]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_IEEE802154MAC_RST    (BIT(14))
+#define SYSTEM_IEEE802154MAC_RST_M  (SYSTEM_IEEE802154MAC_RST_V << SYSTEM_IEEE802154MAC_RST_S)
+#define SYSTEM_IEEE802154MAC_RST_V  0x00000001U
+#define SYSTEM_IEEE802154MAC_RST_S  14
+/** SYSTEM_BLE_SEC_ECB_RST : R/W; bitpos: [15]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_BLE_SEC_ECB_RST    (BIT(15))
+#define SYSTEM_BLE_SEC_ECB_RST_M  (SYSTEM_BLE_SEC_ECB_RST_V << SYSTEM_BLE_SEC_ECB_RST_S)
+#define SYSTEM_BLE_SEC_ECB_RST_V  0x00000001U
+#define SYSTEM_BLE_SEC_ECB_RST_S  15
+/** SYSTEM_BLE_SEC_CCM_RST : R/W; bitpos: [16]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_BLE_SEC_CCM_RST    (BIT(16))
+#define SYSTEM_BLE_SEC_CCM_RST_M  (SYSTEM_BLE_SEC_CCM_RST_V << SYSTEM_BLE_SEC_CCM_RST_S)
+#define SYSTEM_BLE_SEC_CCM_RST_V  0x00000001U
+#define SYSTEM_BLE_SEC_CCM_RST_S  16
+/** SYSTEM_BLE_SEC_AAR_RST : R/W; bitpos: [17]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_BLE_SEC_AAR_RST    (BIT(17))
+#define SYSTEM_BLE_SEC_AAR_RST_M  (SYSTEM_BLE_SEC_AAR_RST_V << SYSTEM_BLE_SEC_AAR_RST_S)
+#define SYSTEM_BLE_SEC_AAR_RST_V  0x00000001U
+#define SYSTEM_BLE_SEC_AAR_RST_S  17
+/** SYSTEM_BLE_SEC_RST : R/W; bitpos: [18]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_BLE_SEC_RST    (BIT(18))
+#define SYSTEM_BLE_SEC_RST_M  (SYSTEM_BLE_SEC_RST_V << SYSTEM_BLE_SEC_RST_S)
+#define SYSTEM_BLE_SEC_RST_V  0x00000001U
+#define SYSTEM_BLE_SEC_RST_S  18
+/** SYSTEM_APB_RET_RST : R/W; bitpos: [19]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_APB_RET_RST    (BIT(19))
+#define SYSTEM_APB_RET_RST_M  (SYSTEM_APB_RET_RST_V << SYSTEM_APB_RET_RST_S)
+#define SYSTEM_APB_RET_RST_V  0x00000001U
+#define SYSTEM_APB_RET_RST_S  19
+/** SYSTEM_DATA_DUMP_RST : R/W; bitpos: [20]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_DATA_DUMP_RST    (BIT(20))
+#define SYSTEM_DATA_DUMP_RST_M  (SYSTEM_DATA_DUMP_RST_V << SYSTEM_DATA_DUMP_RST_S)
+#define SYSTEM_DATA_DUMP_RST_V  0x00000001U
+#define SYSTEM_DATA_DUMP_RST_S  20
+
+/** SYSTEM_PERIP_CLK_CONF_REG register
+ *  register description
+ */
+#define SYSTEM_PERIP_CLK_CONF_REG (DR_REG_SYSTEM_BASE + 0x1c)
+/** SYSTEM_SEC_DIV_NUM : R/W; bitpos: [7:0]; default: 1;
+ *  Need add description
+ */
+#define SYSTEM_SEC_DIV_NUM    0x000000FFU
+#define SYSTEM_SEC_DIV_NUM_M  (SYSTEM_SEC_DIV_NUM_V << SYSTEM_SEC_DIV_NUM_S)
+#define SYSTEM_SEC_DIV_NUM_V  0x000000FFU
+#define SYSTEM_SEC_DIV_NUM_S  0
+/** SYSTEM_USB_DEVICE_DIV_NUM : R/W; bitpos: [15:8]; default: 1;
+ *  Need add description
+ */
+#define SYSTEM_USB_DEVICE_DIV_NUM    0x000000FFU
+#define SYSTEM_USB_DEVICE_DIV_NUM_M  (SYSTEM_USB_DEVICE_DIV_NUM_V << SYSTEM_USB_DEVICE_DIV_NUM_S)
+#define SYSTEM_USB_DEVICE_DIV_NUM_V  0x000000FFU
+#define SYSTEM_USB_DEVICE_DIV_NUM_S  8
+/** SYSTEM_TWAI_DIV_NUM : R/W; bitpos: [23:16]; default: 1;
+ *  Need add description
+ */
+#define SYSTEM_TWAI_DIV_NUM    0x000000FFU
+#define SYSTEM_TWAI_DIV_NUM_M  (SYSTEM_TWAI_DIV_NUM_V << SYSTEM_TWAI_DIV_NUM_S)
+#define SYSTEM_TWAI_DIV_NUM_V  0x000000FFU
+#define SYSTEM_TWAI_DIV_NUM_S  16
+/** SYSTEM_MSPI_DIV_NUM : R/W; bitpos: [31:24]; default: 1;
+ *  Need add description
+ */
+#define SYSTEM_MSPI_DIV_NUM    0x000000FFU
+#define SYSTEM_MSPI_DIV_NUM_M  (SYSTEM_MSPI_DIV_NUM_V << SYSTEM_MSPI_DIV_NUM_S)
+#define SYSTEM_MSPI_DIV_NUM_V  0x000000FFU
+#define SYSTEM_MSPI_DIV_NUM_S  24
+
+/** SYSTEM_PERIP_CLK_EN0_REG register
+ *  register description
+ */
+#define SYSTEM_PERIP_CLK_EN0_REG (DR_REG_SYSTEM_BASE + 0x20)
+/** SYSTEM_TIMERS_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Need add description
+ */
+#define SYSTEM_TIMERS_CLK_EN    (BIT(0))
+#define SYSTEM_TIMERS_CLK_EN_M  (SYSTEM_TIMERS_CLK_EN_V << SYSTEM_TIMERS_CLK_EN_S)
+#define SYSTEM_TIMERS_CLK_EN_V  0x00000001U
+#define SYSTEM_TIMERS_CLK_EN_S  0
+/** SYSTEM_SPI01_CLK_EN : R/W; bitpos: [1]; default: 1;
+ *  Need add description
+ */
+#define SYSTEM_SPI01_CLK_EN    (BIT(1))
+#define SYSTEM_SPI01_CLK_EN_M  (SYSTEM_SPI01_CLK_EN_V << SYSTEM_SPI01_CLK_EN_S)
+#define SYSTEM_SPI01_CLK_EN_V  0x00000001U
+#define SYSTEM_SPI01_CLK_EN_S  1
+/** SYSTEM_UART_CLK_EN : R/W; bitpos: [2]; default: 1;
+ *  Need add description
+ */
+#define SYSTEM_UART_CLK_EN    (BIT(2))
+#define SYSTEM_UART_CLK_EN_M  (SYSTEM_UART_CLK_EN_V << SYSTEM_UART_CLK_EN_S)
+#define SYSTEM_UART_CLK_EN_V  0x00000001U
+#define SYSTEM_UART_CLK_EN_S  2
+/** SYSTEM_WDG_CLK_EN : R/W; bitpos: [3]; default: 1;
+ *  Need add description
+ */
+#define SYSTEM_WDG_CLK_EN    (BIT(3))
+#define SYSTEM_WDG_CLK_EN_M  (SYSTEM_WDG_CLK_EN_V << SYSTEM_WDG_CLK_EN_S)
+#define SYSTEM_WDG_CLK_EN_V  0x00000001U
+#define SYSTEM_WDG_CLK_EN_S  3
+/** SYSTEM_I2S0_CLK_EN : R/W; bitpos: [4]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_I2S0_CLK_EN    (BIT(4))
+#define SYSTEM_I2S0_CLK_EN_M  (SYSTEM_I2S0_CLK_EN_V << SYSTEM_I2S0_CLK_EN_S)
+#define SYSTEM_I2S0_CLK_EN_V  0x00000001U
+#define SYSTEM_I2S0_CLK_EN_S  4
+/** SYSTEM_UART1_CLK_EN : R/W; bitpos: [5]; default: 1;
+ *  Need add description
+ */
+#define SYSTEM_UART1_CLK_EN    (BIT(5))
+#define SYSTEM_UART1_CLK_EN_M  (SYSTEM_UART1_CLK_EN_V << SYSTEM_UART1_CLK_EN_S)
+#define SYSTEM_UART1_CLK_EN_V  0x00000001U
+#define SYSTEM_UART1_CLK_EN_S  5
+/** SYSTEM_SPI2_CLK_EN : R/W; bitpos: [6]; default: 1;
+ *  Need add description
+ */
+#define SYSTEM_SPI2_CLK_EN    (BIT(6))
+#define SYSTEM_SPI2_CLK_EN_M  (SYSTEM_SPI2_CLK_EN_V << SYSTEM_SPI2_CLK_EN_S)
+#define SYSTEM_SPI2_CLK_EN_V  0x00000001U
+#define SYSTEM_SPI2_CLK_EN_S  6
+/** SYSTEM_I2C_EXT0_CLK_EN : R/W; bitpos: [7]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_I2C_EXT0_CLK_EN    (BIT(7))
+#define SYSTEM_I2C_EXT0_CLK_EN_M  (SYSTEM_I2C_EXT0_CLK_EN_V << SYSTEM_I2C_EXT0_CLK_EN_S)
+#define SYSTEM_I2C_EXT0_CLK_EN_V  0x00000001U
+#define SYSTEM_I2C_EXT0_CLK_EN_S  7
+/** SYSTEM_UHCI0_CLK_EN : R/W; bitpos: [8]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_UHCI0_CLK_EN    (BIT(8))
+#define SYSTEM_UHCI0_CLK_EN_M  (SYSTEM_UHCI0_CLK_EN_V << SYSTEM_UHCI0_CLK_EN_S)
+#define SYSTEM_UHCI0_CLK_EN_V  0x00000001U
+#define SYSTEM_UHCI0_CLK_EN_S  8
+/** SYSTEM_RMT_CLK_EN : R/W; bitpos: [9]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_RMT_CLK_EN    (BIT(9))
+#define SYSTEM_RMT_CLK_EN_M  (SYSTEM_RMT_CLK_EN_V << SYSTEM_RMT_CLK_EN_S)
+#define SYSTEM_RMT_CLK_EN_V  0x00000001U
+#define SYSTEM_RMT_CLK_EN_S  9
+/** SYSTEM_PCNT_CLK_EN : R/W; bitpos: [10]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_PCNT_CLK_EN    (BIT(10))
+#define SYSTEM_PCNT_CLK_EN_M  (SYSTEM_PCNT_CLK_EN_V << SYSTEM_PCNT_CLK_EN_S)
+#define SYSTEM_PCNT_CLK_EN_V  0x00000001U
+#define SYSTEM_PCNT_CLK_EN_S  10
+/** SYSTEM_LEDC_CLK_EN : R/W; bitpos: [11]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_LEDC_CLK_EN    (BIT(11))
+#define SYSTEM_LEDC_CLK_EN_M  (SYSTEM_LEDC_CLK_EN_V << SYSTEM_LEDC_CLK_EN_S)
+#define SYSTEM_LEDC_CLK_EN_V  0x00000001U
+#define SYSTEM_LEDC_CLK_EN_S  11
+/** SYSTEM_UHCI1_CLK_EN : R/W; bitpos: [12]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_UHCI1_CLK_EN    (BIT(12))
+#define SYSTEM_UHCI1_CLK_EN_M  (SYSTEM_UHCI1_CLK_EN_V << SYSTEM_UHCI1_CLK_EN_S)
+#define SYSTEM_UHCI1_CLK_EN_V  0x00000001U
+#define SYSTEM_UHCI1_CLK_EN_S  12
+/** SYSTEM_TIMERGROUP_CLK_EN : R/W; bitpos: [13]; default: 1;
+ *  Need add description
+ */
+#define SYSTEM_TIMERGROUP_CLK_EN    (BIT(13))
+#define SYSTEM_TIMERGROUP_CLK_EN_M  (SYSTEM_TIMERGROUP_CLK_EN_V << SYSTEM_TIMERGROUP_CLK_EN_S)
+#define SYSTEM_TIMERGROUP_CLK_EN_V  0x00000001U
+#define SYSTEM_TIMERGROUP_CLK_EN_S  13
+/** SYSTEM_EFUSE_CLK_EN : R/W; bitpos: [14]; default: 1;
+ *  Need add description
+ */
+#define SYSTEM_EFUSE_CLK_EN    (BIT(14))
+#define SYSTEM_EFUSE_CLK_EN_M  (SYSTEM_EFUSE_CLK_EN_V << SYSTEM_EFUSE_CLK_EN_S)
+#define SYSTEM_EFUSE_CLK_EN_V  0x00000001U
+#define SYSTEM_EFUSE_CLK_EN_S  14
+/** SYSTEM_TIMERGROUP1_CLK_EN : R/W; bitpos: [15]; default: 1;
+ *  Need add description
+ */
+#define SYSTEM_TIMERGROUP1_CLK_EN    (BIT(15))
+#define SYSTEM_TIMERGROUP1_CLK_EN_M  (SYSTEM_TIMERGROUP1_CLK_EN_V << SYSTEM_TIMERGROUP1_CLK_EN_S)
+#define SYSTEM_TIMERGROUP1_CLK_EN_V  0x00000001U
+#define SYSTEM_TIMERGROUP1_CLK_EN_S  15
+/** SYSTEM_SPI3_CLK_EN : R/W; bitpos: [16]; default: 1;
+ *  Need add description
+ */
+#define SYSTEM_SPI3_CLK_EN    (BIT(16))
+#define SYSTEM_SPI3_CLK_EN_M  (SYSTEM_SPI3_CLK_EN_V << SYSTEM_SPI3_CLK_EN_S)
+#define SYSTEM_SPI3_CLK_EN_V  0x00000001U
+#define SYSTEM_SPI3_CLK_EN_S  16
+/** SYSTEM_PWM0_CLK_EN : R/W; bitpos: [17]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_PWM0_CLK_EN    (BIT(17))
+#define SYSTEM_PWM0_CLK_EN_M  (SYSTEM_PWM0_CLK_EN_V << SYSTEM_PWM0_CLK_EN_S)
+#define SYSTEM_PWM0_CLK_EN_V  0x00000001U
+#define SYSTEM_PWM0_CLK_EN_S  17
+/** SYSTEM_I2C_EXT1_CLK_EN : R/W; bitpos: [18]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_I2C_EXT1_CLK_EN    (BIT(18))
+#define SYSTEM_I2C_EXT1_CLK_EN_M  (SYSTEM_I2C_EXT1_CLK_EN_V << SYSTEM_I2C_EXT1_CLK_EN_S)
+#define SYSTEM_I2C_EXT1_CLK_EN_V  0x00000001U
+#define SYSTEM_I2C_EXT1_CLK_EN_S  18
+/** SYSTEM_TWAI_CLK_EN : R/W; bitpos: [19]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_TWAI_CLK_EN    (BIT(19))
+#define SYSTEM_TWAI_CLK_EN_M  (SYSTEM_TWAI_CLK_EN_V << SYSTEM_TWAI_CLK_EN_S)
+#define SYSTEM_TWAI_CLK_EN_V  0x00000001U
+#define SYSTEM_TWAI_CLK_EN_S  19
+/** SYSTEM_PWM1_CLK_EN : R/W; bitpos: [20]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_PWM1_CLK_EN    (BIT(20))
+#define SYSTEM_PWM1_CLK_EN_M  (SYSTEM_PWM1_CLK_EN_V << SYSTEM_PWM1_CLK_EN_S)
+#define SYSTEM_PWM1_CLK_EN_V  0x00000001U
+#define SYSTEM_PWM1_CLK_EN_S  20
+/** SYSTEM_I2S1_CLK_EN : R/W; bitpos: [21]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_I2S1_CLK_EN    (BIT(21))
+#define SYSTEM_I2S1_CLK_EN_M  (SYSTEM_I2S1_CLK_EN_V << SYSTEM_I2S1_CLK_EN_S)
+#define SYSTEM_I2S1_CLK_EN_V  0x00000001U
+#define SYSTEM_I2S1_CLK_EN_S  21
+/** SYSTEM_SPI2_DMA_CLK_EN : R/W; bitpos: [22]; default: 1;
+ *  Need add description
+ */
+#define SYSTEM_SPI2_DMA_CLK_EN    (BIT(22))
+#define SYSTEM_SPI2_DMA_CLK_EN_M  (SYSTEM_SPI2_DMA_CLK_EN_V << SYSTEM_SPI2_DMA_CLK_EN_S)
+#define SYSTEM_SPI2_DMA_CLK_EN_V  0x00000001U
+#define SYSTEM_SPI2_DMA_CLK_EN_S  22
+/** SYSTEM_USB_DEVICE_CLK_EN : R/W; bitpos: [23]; default: 1;
+ *  Need add description
+ */
+#define SYSTEM_USB_DEVICE_CLK_EN    (BIT(23))
+#define SYSTEM_USB_DEVICE_CLK_EN_M  (SYSTEM_USB_DEVICE_CLK_EN_V << SYSTEM_USB_DEVICE_CLK_EN_S)
+#define SYSTEM_USB_DEVICE_CLK_EN_V  0x00000001U
+#define SYSTEM_USB_DEVICE_CLK_EN_S  23
+/** SYSTEM_UART_MEM_CLK_EN : R/W; bitpos: [24]; default: 1;
+ *  Need add description
+ */
+#define SYSTEM_UART_MEM_CLK_EN    (BIT(24))
+#define SYSTEM_UART_MEM_CLK_EN_M  (SYSTEM_UART_MEM_CLK_EN_V << SYSTEM_UART_MEM_CLK_EN_S)
+#define SYSTEM_UART_MEM_CLK_EN_V  0x00000001U
+#define SYSTEM_UART_MEM_CLK_EN_S  24
+/** SYSTEM_PWM2_CLK_EN : R/W; bitpos: [25]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_PWM2_CLK_EN    (BIT(25))
+#define SYSTEM_PWM2_CLK_EN_M  (SYSTEM_PWM2_CLK_EN_V << SYSTEM_PWM2_CLK_EN_S)
+#define SYSTEM_PWM2_CLK_EN_V  0x00000001U
+#define SYSTEM_PWM2_CLK_EN_S  25
+/** SYSTEM_PWM3_CLK_EN : R/W; bitpos: [26]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_PWM3_CLK_EN    (BIT(26))
+#define SYSTEM_PWM3_CLK_EN_M  (SYSTEM_PWM3_CLK_EN_V << SYSTEM_PWM3_CLK_EN_S)
+#define SYSTEM_PWM3_CLK_EN_V  0x00000001U
+#define SYSTEM_PWM3_CLK_EN_S  26
+/** SYSTEM_SPI3_DMA_CLK_EN : R/W; bitpos: [27]; default: 1;
+ *  Need add description
+ */
+#define SYSTEM_SPI3_DMA_CLK_EN    (BIT(27))
+#define SYSTEM_SPI3_DMA_CLK_EN_M  (SYSTEM_SPI3_DMA_CLK_EN_V << SYSTEM_SPI3_DMA_CLK_EN_S)
+#define SYSTEM_SPI3_DMA_CLK_EN_V  0x00000001U
+#define SYSTEM_SPI3_DMA_CLK_EN_S  27
+/** SYSTEM_APB_SARADC_CLK_EN : R/W; bitpos: [28]; default: 1;
+ *  Need add description
+ */
+#define SYSTEM_APB_SARADC_CLK_EN    (BIT(28))
+#define SYSTEM_APB_SARADC_CLK_EN_M  (SYSTEM_APB_SARADC_CLK_EN_V << SYSTEM_APB_SARADC_CLK_EN_S)
+#define SYSTEM_APB_SARADC_CLK_EN_V  0x00000001U
+#define SYSTEM_APB_SARADC_CLK_EN_S  28
+/** SYSTEM_SYSTIMER_CLK_EN : R/W; bitpos: [29]; default: 1;
+ *  Need add description
+ */
+#define SYSTEM_SYSTIMER_CLK_EN    (BIT(29))
+#define SYSTEM_SYSTIMER_CLK_EN_M  (SYSTEM_SYSTIMER_CLK_EN_V << SYSTEM_SYSTIMER_CLK_EN_S)
+#define SYSTEM_SYSTIMER_CLK_EN_V  0x00000001U
+#define SYSTEM_SYSTIMER_CLK_EN_S  29
+/** SYSTEM_ADC2_ARB_CLK_EN : R/W; bitpos: [30]; default: 1;
+ *  Need add description
+ */
+#define SYSTEM_ADC2_ARB_CLK_EN    (BIT(30))
+#define SYSTEM_ADC2_ARB_CLK_EN_M  (SYSTEM_ADC2_ARB_CLK_EN_V << SYSTEM_ADC2_ARB_CLK_EN_S)
+#define SYSTEM_ADC2_ARB_CLK_EN_V  0x00000001U
+#define SYSTEM_ADC2_ARB_CLK_EN_S  30
+/** SYSTEM_SPI4_CLK_EN : R/W; bitpos: [31]; default: 1;
+ *  Need add description
+ */
+#define SYSTEM_SPI4_CLK_EN    (BIT(31))
+#define SYSTEM_SPI4_CLK_EN_M  (SYSTEM_SPI4_CLK_EN_V << SYSTEM_SPI4_CLK_EN_S)
+#define SYSTEM_SPI4_CLK_EN_V  0x00000001U
+#define SYSTEM_SPI4_CLK_EN_S  31
+
+/** SYSTEM_PERIP_CLK_EN1_REG register
+ *  register description
+ */
+#define SYSTEM_PERIP_CLK_EN1_REG (DR_REG_SYSTEM_BASE + 0x24)
+/** SYSTEM_RETENTION_TOP_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Need add description
+ */
+#define SYSTEM_RETENTION_TOP_CLK_EN    (BIT(0))
+#define SYSTEM_RETENTION_TOP_CLK_EN_M  (SYSTEM_RETENTION_TOP_CLK_EN_V << SYSTEM_RETENTION_TOP_CLK_EN_S)
+#define SYSTEM_RETENTION_TOP_CLK_EN_V  0x00000001U
+#define SYSTEM_RETENTION_TOP_CLK_EN_S  0
+/** SYSTEM_CRYPTO_AES_CLK_EN : R/W; bitpos: [1]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_CRYPTO_AES_CLK_EN    (BIT(1))
+#define SYSTEM_CRYPTO_AES_CLK_EN_M  (SYSTEM_CRYPTO_AES_CLK_EN_V << SYSTEM_CRYPTO_AES_CLK_EN_S)
+#define SYSTEM_CRYPTO_AES_CLK_EN_V  0x00000001U
+#define SYSTEM_CRYPTO_AES_CLK_EN_S  1
+/** SYSTEM_CRYPTO_SHA_CLK_EN : R/W; bitpos: [2]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_CRYPTO_SHA_CLK_EN    (BIT(2))
+#define SYSTEM_CRYPTO_SHA_CLK_EN_M  (SYSTEM_CRYPTO_SHA_CLK_EN_V << SYSTEM_CRYPTO_SHA_CLK_EN_S)
+#define SYSTEM_CRYPTO_SHA_CLK_EN_V  0x00000001U
+#define SYSTEM_CRYPTO_SHA_CLK_EN_S  2
+/** SYSTEM_CRYPTO_RSA_CLK_EN : R/W; bitpos: [3]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_CRYPTO_RSA_CLK_EN    (BIT(3))
+#define SYSTEM_CRYPTO_RSA_CLK_EN_M  (SYSTEM_CRYPTO_RSA_CLK_EN_V << SYSTEM_CRYPTO_RSA_CLK_EN_S)
+#define SYSTEM_CRYPTO_RSA_CLK_EN_V  0x00000001U
+#define SYSTEM_CRYPTO_RSA_CLK_EN_S  3
+/** SYSTEM_CRYPTO_DS_CLK_EN : R/W; bitpos: [4]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_CRYPTO_DS_CLK_EN    (BIT(4))
+#define SYSTEM_CRYPTO_DS_CLK_EN_M  (SYSTEM_CRYPTO_DS_CLK_EN_V << SYSTEM_CRYPTO_DS_CLK_EN_S)
+#define SYSTEM_CRYPTO_DS_CLK_EN_V  0x00000001U
+#define SYSTEM_CRYPTO_DS_CLK_EN_S  4
+/** SYSTEM_CRYPTO_HMAC_CLK_EN : R/W; bitpos: [5]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_CRYPTO_HMAC_CLK_EN    (BIT(5))
+#define SYSTEM_CRYPTO_HMAC_CLK_EN_M  (SYSTEM_CRYPTO_HMAC_CLK_EN_V << SYSTEM_CRYPTO_HMAC_CLK_EN_S)
+#define SYSTEM_CRYPTO_HMAC_CLK_EN_V  0x00000001U
+#define SYSTEM_CRYPTO_HMAC_CLK_EN_S  5
+/** SYSTEM_CRYPTO_ECC_CLK_EN : R/W; bitpos: [6]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_CRYPTO_ECC_CLK_EN    (BIT(6))
+#define SYSTEM_CRYPTO_ECC_CLK_EN_M  (SYSTEM_CRYPTO_ECC_CLK_EN_V << SYSTEM_CRYPTO_ECC_CLK_EN_S)
+#define SYSTEM_CRYPTO_ECC_CLK_EN_V  0x00000001U
+#define SYSTEM_CRYPTO_ECC_CLK_EN_S  6
+/** SYSTEM_DMA_CLK_EN : R/W; bitpos: [7]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_DMA_CLK_EN    (BIT(7))
+#define SYSTEM_DMA_CLK_EN_M  (SYSTEM_DMA_CLK_EN_V << SYSTEM_DMA_CLK_EN_S)
+#define SYSTEM_DMA_CLK_EN_V  0x00000001U
+#define SYSTEM_DMA_CLK_EN_S  7
+/** SYSTEM_SDIO_HOST_CLK_EN : R/W; bitpos: [8]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_SDIO_HOST_CLK_EN    (BIT(8))
+#define SYSTEM_SDIO_HOST_CLK_EN_M  (SYSTEM_SDIO_HOST_CLK_EN_V << SYSTEM_SDIO_HOST_CLK_EN_S)
+#define SYSTEM_SDIO_HOST_CLK_EN_V  0x00000001U
+#define SYSTEM_SDIO_HOST_CLK_EN_S  8
+/** SYSTEM_LCD_CAM_CLK_EN : R/W; bitpos: [9]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_LCD_CAM_CLK_EN    (BIT(9))
+#define SYSTEM_LCD_CAM_CLK_EN_M  (SYSTEM_LCD_CAM_CLK_EN_V << SYSTEM_LCD_CAM_CLK_EN_S)
+#define SYSTEM_LCD_CAM_CLK_EN_V  0x00000001U
+#define SYSTEM_LCD_CAM_CLK_EN_S  9
+/** SYSTEM_UART2_CLK_EN : R/W; bitpos: [10]; default: 1;
+ *  Need add description
+ */
+#define SYSTEM_UART2_CLK_EN    (BIT(10))
+#define SYSTEM_UART2_CLK_EN_M  (SYSTEM_UART2_CLK_EN_V << SYSTEM_UART2_CLK_EN_S)
+#define SYSTEM_UART2_CLK_EN_V  0x00000001U
+#define SYSTEM_UART2_CLK_EN_S  10
+/** SYSTEM_TSENS_CLK_EN : R/W; bitpos: [11]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_TSENS_CLK_EN    (BIT(11))
+#define SYSTEM_TSENS_CLK_EN_M  (SYSTEM_TSENS_CLK_EN_V << SYSTEM_TSENS_CLK_EN_S)
+#define SYSTEM_TSENS_CLK_EN_V  0x00000001U
+#define SYSTEM_TSENS_CLK_EN_S  11
+/** SYSTEM_ETM_CLK_EN : R/W; bitpos: [12]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_ETM_CLK_EN    (BIT(12))
+#define SYSTEM_ETM_CLK_EN_M  (SYSTEM_ETM_CLK_EN_V << SYSTEM_ETM_CLK_EN_S)
+#define SYSTEM_ETM_CLK_EN_V  0x00000001U
+#define SYSTEM_ETM_CLK_EN_S  12
+/** SYSTEM_TIMERGROUP3_CLK_EN : R/W; bitpos: [13]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_TIMERGROUP3_CLK_EN    (BIT(13))
+#define SYSTEM_TIMERGROUP3_CLK_EN_M  (SYSTEM_TIMERGROUP3_CLK_EN_V << SYSTEM_TIMERGROUP3_CLK_EN_S)
+#define SYSTEM_TIMERGROUP3_CLK_EN_V  0x00000001U
+#define SYSTEM_TIMERGROUP3_CLK_EN_S  13
+/** SYSTEM_REGRET_CLK_EN : R/W; bitpos: [14]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_REGRET_CLK_EN    (BIT(14))
+#define SYSTEM_REGRET_CLK_EN_M  (SYSTEM_REGRET_CLK_EN_V << SYSTEM_REGRET_CLK_EN_S)
+#define SYSTEM_REGRET_CLK_EN_V  0x00000001U
+#define SYSTEM_REGRET_CLK_EN_S  14
+/** SYSTEM_PVT_CLK_EN : R/W; bitpos: [15]; default: 1;
+ *  Need add description
+ */
+#define SYSTEM_PVT_CLK_EN    (BIT(15))
+#define SYSTEM_PVT_CLK_EN_M  (SYSTEM_PVT_CLK_EN_V << SYSTEM_PVT_CLK_EN_S)
+#define SYSTEM_PVT_CLK_EN_V  0x00000001U
+#define SYSTEM_PVT_CLK_EN_S  15
+
+/** SYSTEM_PERIP_RST_EN0_REG register
+ *  register description
+ */
+#define SYSTEM_PERIP_RST_EN0_REG (DR_REG_SYSTEM_BASE + 0x28)
+/** SYSTEM_TIMERS_RST : R/W; bitpos: [0]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_TIMERS_RST    (BIT(0))
+#define SYSTEM_TIMERS_RST_M  (SYSTEM_TIMERS_RST_V << SYSTEM_TIMERS_RST_S)
+#define SYSTEM_TIMERS_RST_V  0x00000001U
+#define SYSTEM_TIMERS_RST_S  0
+/** SYSTEM_SPI01_RST : R/W; bitpos: [1]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_SPI01_RST    (BIT(1))
+#define SYSTEM_SPI01_RST_M  (SYSTEM_SPI01_RST_V << SYSTEM_SPI01_RST_S)
+#define SYSTEM_SPI01_RST_V  0x00000001U
+#define SYSTEM_SPI01_RST_S  1
+/** SYSTEM_UART_RST : R/W; bitpos: [2]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_UART_RST    (BIT(2))
+#define SYSTEM_UART_RST_M  (SYSTEM_UART_RST_V << SYSTEM_UART_RST_S)
+#define SYSTEM_UART_RST_V  0x00000001U
+#define SYSTEM_UART_RST_S  2
+/** SYSTEM_WDG_RST : R/W; bitpos: [3]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_WDG_RST    (BIT(3))
+#define SYSTEM_WDG_RST_M  (SYSTEM_WDG_RST_V << SYSTEM_WDG_RST_S)
+#define SYSTEM_WDG_RST_V  0x00000001U
+#define SYSTEM_WDG_RST_S  3
+/** SYSTEM_I2S0_RST : R/W; bitpos: [4]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_I2S0_RST    (BIT(4))
+#define SYSTEM_I2S0_RST_M  (SYSTEM_I2S0_RST_V << SYSTEM_I2S0_RST_S)
+#define SYSTEM_I2S0_RST_V  0x00000001U
+#define SYSTEM_I2S0_RST_S  4
+/** SYSTEM_UART1_RST : R/W; bitpos: [5]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_UART1_RST    (BIT(5))
+#define SYSTEM_UART1_RST_M  (SYSTEM_UART1_RST_V << SYSTEM_UART1_RST_S)
+#define SYSTEM_UART1_RST_V  0x00000001U
+#define SYSTEM_UART1_RST_S  5
+/** SYSTEM_SPI2_RST : R/W; bitpos: [6]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_SPI2_RST    (BIT(6))
+#define SYSTEM_SPI2_RST_M  (SYSTEM_SPI2_RST_V << SYSTEM_SPI2_RST_S)
+#define SYSTEM_SPI2_RST_V  0x00000001U
+#define SYSTEM_SPI2_RST_S  6
+/** SYSTEM_I2C_EXT0_RST : R/W; bitpos: [7]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_I2C_EXT0_RST    (BIT(7))
+#define SYSTEM_I2C_EXT0_RST_M  (SYSTEM_I2C_EXT0_RST_V << SYSTEM_I2C_EXT0_RST_S)
+#define SYSTEM_I2C_EXT0_RST_V  0x00000001U
+#define SYSTEM_I2C_EXT0_RST_S  7
+/** SYSTEM_UHCI0_RST : R/W; bitpos: [8]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_UHCI0_RST    (BIT(8))
+#define SYSTEM_UHCI0_RST_M  (SYSTEM_UHCI0_RST_V << SYSTEM_UHCI0_RST_S)
+#define SYSTEM_UHCI0_RST_V  0x00000001U
+#define SYSTEM_UHCI0_RST_S  8
+/** SYSTEM_RMT_RST : R/W; bitpos: [9]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_RMT_RST    (BIT(9))
+#define SYSTEM_RMT_RST_M  (SYSTEM_RMT_RST_V << SYSTEM_RMT_RST_S)
+#define SYSTEM_RMT_RST_V  0x00000001U
+#define SYSTEM_RMT_RST_S  9
+/** SYSTEM_PCNT_RST : R/W; bitpos: [10]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_PCNT_RST    (BIT(10))
+#define SYSTEM_PCNT_RST_M  (SYSTEM_PCNT_RST_V << SYSTEM_PCNT_RST_S)
+#define SYSTEM_PCNT_RST_V  0x00000001U
+#define SYSTEM_PCNT_RST_S  10
+/** SYSTEM_LEDC_RST : R/W; bitpos: [11]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_LEDC_RST    (BIT(11))
+#define SYSTEM_LEDC_RST_M  (SYSTEM_LEDC_RST_V << SYSTEM_LEDC_RST_S)
+#define SYSTEM_LEDC_RST_V  0x00000001U
+#define SYSTEM_LEDC_RST_S  11
+/** SYSTEM_UHCI1_RST : R/W; bitpos: [12]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_UHCI1_RST    (BIT(12))
+#define SYSTEM_UHCI1_RST_M  (SYSTEM_UHCI1_RST_V << SYSTEM_UHCI1_RST_S)
+#define SYSTEM_UHCI1_RST_V  0x00000001U
+#define SYSTEM_UHCI1_RST_S  12
+/** SYSTEM_TIMERGROUP_RST : R/W; bitpos: [13]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_TIMERGROUP_RST    (BIT(13))
+#define SYSTEM_TIMERGROUP_RST_M  (SYSTEM_TIMERGROUP_RST_V << SYSTEM_TIMERGROUP_RST_S)
+#define SYSTEM_TIMERGROUP_RST_V  0x00000001U
+#define SYSTEM_TIMERGROUP_RST_S  13
+/** SYSTEM_EFUSE_RST : R/W; bitpos: [14]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_EFUSE_RST    (BIT(14))
+#define SYSTEM_EFUSE_RST_M  (SYSTEM_EFUSE_RST_V << SYSTEM_EFUSE_RST_S)
+#define SYSTEM_EFUSE_RST_V  0x00000001U
+#define SYSTEM_EFUSE_RST_S  14
+/** SYSTEM_TIMERGROUP1_RST : R/W; bitpos: [15]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_TIMERGROUP1_RST    (BIT(15))
+#define SYSTEM_TIMERGROUP1_RST_M  (SYSTEM_TIMERGROUP1_RST_V << SYSTEM_TIMERGROUP1_RST_S)
+#define SYSTEM_TIMERGROUP1_RST_V  0x00000001U
+#define SYSTEM_TIMERGROUP1_RST_S  15
+/** SYSTEM_SPI3_RST : R/W; bitpos: [16]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_SPI3_RST    (BIT(16))
+#define SYSTEM_SPI3_RST_M  (SYSTEM_SPI3_RST_V << SYSTEM_SPI3_RST_S)
+#define SYSTEM_SPI3_RST_V  0x00000001U
+#define SYSTEM_SPI3_RST_S  16
+/** SYSTEM_PWM0_RST : R/W; bitpos: [17]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_PWM0_RST    (BIT(17))
+#define SYSTEM_PWM0_RST_M  (SYSTEM_PWM0_RST_V << SYSTEM_PWM0_RST_S)
+#define SYSTEM_PWM0_RST_V  0x00000001U
+#define SYSTEM_PWM0_RST_S  17
+/** SYSTEM_I2C_EXT1_RST : R/W; bitpos: [18]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_I2C_EXT1_RST    (BIT(18))
+#define SYSTEM_I2C_EXT1_RST_M  (SYSTEM_I2C_EXT1_RST_V << SYSTEM_I2C_EXT1_RST_S)
+#define SYSTEM_I2C_EXT1_RST_V  0x00000001U
+#define SYSTEM_I2C_EXT1_RST_S  18
+/** SYSTEM_TWAI_RST : R/W; bitpos: [19]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_TWAI_RST    (BIT(19))
+#define SYSTEM_TWAI_RST_M  (SYSTEM_TWAI_RST_V << SYSTEM_TWAI_RST_S)
+#define SYSTEM_TWAI_RST_V  0x00000001U
+#define SYSTEM_TWAI_RST_S  19
+/** SYSTEM_PWM1_RST : R/W; bitpos: [20]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_PWM1_RST    (BIT(20))
+#define SYSTEM_PWM1_RST_M  (SYSTEM_PWM1_RST_V << SYSTEM_PWM1_RST_S)
+#define SYSTEM_PWM1_RST_V  0x00000001U
+#define SYSTEM_PWM1_RST_S  20
+/** SYSTEM_I2S1_RST : R/W; bitpos: [21]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_I2S1_RST    (BIT(21))
+#define SYSTEM_I2S1_RST_M  (SYSTEM_I2S1_RST_V << SYSTEM_I2S1_RST_S)
+#define SYSTEM_I2S1_RST_V  0x00000001U
+#define SYSTEM_I2S1_RST_S  21
+/** SYSTEM_SPI2_DMA_RST : R/W; bitpos: [22]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_SPI2_DMA_RST    (BIT(22))
+#define SYSTEM_SPI2_DMA_RST_M  (SYSTEM_SPI2_DMA_RST_V << SYSTEM_SPI2_DMA_RST_S)
+#define SYSTEM_SPI2_DMA_RST_V  0x00000001U
+#define SYSTEM_SPI2_DMA_RST_S  22
+/** SYSTEM_USB_DEVICE_RST : R/W; bitpos: [23]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_USB_DEVICE_RST    (BIT(23))
+#define SYSTEM_USB_DEVICE_RST_M  (SYSTEM_USB_DEVICE_RST_V << SYSTEM_USB_DEVICE_RST_S)
+#define SYSTEM_USB_DEVICE_RST_V  0x00000001U
+#define SYSTEM_USB_DEVICE_RST_S  23
+/** SYSTEM_UART_MEM_RST : R/W; bitpos: [24]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_UART_MEM_RST    (BIT(24))
+#define SYSTEM_UART_MEM_RST_M  (SYSTEM_UART_MEM_RST_V << SYSTEM_UART_MEM_RST_S)
+#define SYSTEM_UART_MEM_RST_V  0x00000001U
+#define SYSTEM_UART_MEM_RST_S  24
+/** SYSTEM_PWM2_RST : R/W; bitpos: [25]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_PWM2_RST    (BIT(25))
+#define SYSTEM_PWM2_RST_M  (SYSTEM_PWM2_RST_V << SYSTEM_PWM2_RST_S)
+#define SYSTEM_PWM2_RST_V  0x00000001U
+#define SYSTEM_PWM2_RST_S  25
+/** SYSTEM_PWM3_RST : R/W; bitpos: [26]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_PWM3_RST    (BIT(26))
+#define SYSTEM_PWM3_RST_M  (SYSTEM_PWM3_RST_V << SYSTEM_PWM3_RST_S)
+#define SYSTEM_PWM3_RST_V  0x00000001U
+#define SYSTEM_PWM3_RST_S  26
+/** SYSTEM_SPI3_DMA_RST : R/W; bitpos: [27]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_SPI3_DMA_RST    (BIT(27))
+#define SYSTEM_SPI3_DMA_RST_M  (SYSTEM_SPI3_DMA_RST_V << SYSTEM_SPI3_DMA_RST_S)
+#define SYSTEM_SPI3_DMA_RST_V  0x00000001U
+#define SYSTEM_SPI3_DMA_RST_S  27
+/** SYSTEM_APB_SARADC_RST : R/W; bitpos: [28]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_APB_SARADC_RST    (BIT(28))
+#define SYSTEM_APB_SARADC_RST_M  (SYSTEM_APB_SARADC_RST_V << SYSTEM_APB_SARADC_RST_S)
+#define SYSTEM_APB_SARADC_RST_V  0x00000001U
+#define SYSTEM_APB_SARADC_RST_S  28
+/** SYSTEM_SYSTIMER_RST : R/W; bitpos: [29]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_SYSTIMER_RST    (BIT(29))
+#define SYSTEM_SYSTIMER_RST_M  (SYSTEM_SYSTIMER_RST_V << SYSTEM_SYSTIMER_RST_S)
+#define SYSTEM_SYSTIMER_RST_V  0x00000001U
+#define SYSTEM_SYSTIMER_RST_S  29
+/** SYSTEM_ADC2_ARB_RST : R/W; bitpos: [30]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_ADC2_ARB_RST    (BIT(30))
+#define SYSTEM_ADC2_ARB_RST_M  (SYSTEM_ADC2_ARB_RST_V << SYSTEM_ADC2_ARB_RST_S)
+#define SYSTEM_ADC2_ARB_RST_V  0x00000001U
+#define SYSTEM_ADC2_ARB_RST_S  30
+/** SYSTEM_SPI4_RST : R/W; bitpos: [31]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_SPI4_RST    (BIT(31))
+#define SYSTEM_SPI4_RST_M  (SYSTEM_SPI4_RST_V << SYSTEM_SPI4_RST_S)
+#define SYSTEM_SPI4_RST_V  0x00000001U
+#define SYSTEM_SPI4_RST_S  31
+
+/** SYSTEM_PERIP_RST_EN1_REG register
+ *  register description
+ */
+#define SYSTEM_PERIP_RST_EN1_REG (DR_REG_SYSTEM_BASE + 0x2c)
+/** SYSTEM_RETENTION_TOP_RST : R/W; bitpos: [0]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_RETENTION_TOP_RST    (BIT(0))
+#define SYSTEM_RETENTION_TOP_RST_M  (SYSTEM_RETENTION_TOP_RST_V << SYSTEM_RETENTION_TOP_RST_S)
+#define SYSTEM_RETENTION_TOP_RST_V  0x00000001U
+#define SYSTEM_RETENTION_TOP_RST_S  0
+/** SYSTEM_CRYPTO_AES_RST : R/W; bitpos: [1]; default: 1;
+ *  Need add description
+ */
+#define SYSTEM_CRYPTO_AES_RST    (BIT(1))
+#define SYSTEM_CRYPTO_AES_RST_M  (SYSTEM_CRYPTO_AES_RST_V << SYSTEM_CRYPTO_AES_RST_S)
+#define SYSTEM_CRYPTO_AES_RST_V  0x00000001U
+#define SYSTEM_CRYPTO_AES_RST_S  1
+/** SYSTEM_CRYPTO_SHA_RST : R/W; bitpos: [2]; default: 1;
+ *  Need add description
+ */
+#define SYSTEM_CRYPTO_SHA_RST    (BIT(2))
+#define SYSTEM_CRYPTO_SHA_RST_M  (SYSTEM_CRYPTO_SHA_RST_V << SYSTEM_CRYPTO_SHA_RST_S)
+#define SYSTEM_CRYPTO_SHA_RST_V  0x00000001U
+#define SYSTEM_CRYPTO_SHA_RST_S  2
+/** SYSTEM_CRYPTO_RSA_RST : R/W; bitpos: [3]; default: 1;
+ *  Need add description
+ */
+#define SYSTEM_CRYPTO_RSA_RST    (BIT(3))
+#define SYSTEM_CRYPTO_RSA_RST_M  (SYSTEM_CRYPTO_RSA_RST_V << SYSTEM_CRYPTO_RSA_RST_S)
+#define SYSTEM_CRYPTO_RSA_RST_V  0x00000001U
+#define SYSTEM_CRYPTO_RSA_RST_S  3
+/** SYSTEM_CRYPTO_DS_RST : R/W; bitpos: [4]; default: 1;
+ *  Need add description
+ */
+#define SYSTEM_CRYPTO_DS_RST    (BIT(4))
+#define SYSTEM_CRYPTO_DS_RST_M  (SYSTEM_CRYPTO_DS_RST_V << SYSTEM_CRYPTO_DS_RST_S)
+#define SYSTEM_CRYPTO_DS_RST_V  0x00000001U
+#define SYSTEM_CRYPTO_DS_RST_S  4
+/** SYSTEM_CRYPTO_HMAC_RST : R/W; bitpos: [5]; default: 1;
+ *  Need add description
+ */
+#define SYSTEM_CRYPTO_HMAC_RST    (BIT(5))
+#define SYSTEM_CRYPTO_HMAC_RST_M  (SYSTEM_CRYPTO_HMAC_RST_V << SYSTEM_CRYPTO_HMAC_RST_S)
+#define SYSTEM_CRYPTO_HMAC_RST_V  0x00000001U
+#define SYSTEM_CRYPTO_HMAC_RST_S  5
+/** SYSTEM_CRYPTO_ECC_RST : R/W; bitpos: [6]; default: 1;
+ *  Need add description
+ */
+#define SYSTEM_CRYPTO_ECC_RST    (BIT(6))
+#define SYSTEM_CRYPTO_ECC_RST_M  (SYSTEM_CRYPTO_ECC_RST_V << SYSTEM_CRYPTO_ECC_RST_S)
+#define SYSTEM_CRYPTO_ECC_RST_V  0x00000001U
+#define SYSTEM_CRYPTO_ECC_RST_S  6
+/** SYSTEM_DMA_RST : R/W; bitpos: [7]; default: 1;
+ *  Need add description
+ */
+#define SYSTEM_DMA_RST    (BIT(7))
+#define SYSTEM_DMA_RST_M  (SYSTEM_DMA_RST_V << SYSTEM_DMA_RST_S)
+#define SYSTEM_DMA_RST_V  0x00000001U
+#define SYSTEM_DMA_RST_S  7
+/** SYSTEM_SDIO_HOST_RST : R/W; bitpos: [8]; default: 1;
+ *  Need add description
+ */
+#define SYSTEM_SDIO_HOST_RST    (BIT(8))
+#define SYSTEM_SDIO_HOST_RST_M  (SYSTEM_SDIO_HOST_RST_V << SYSTEM_SDIO_HOST_RST_S)
+#define SYSTEM_SDIO_HOST_RST_V  0x00000001U
+#define SYSTEM_SDIO_HOST_RST_S  8
+/** SYSTEM_LCD_CAM_RST : R/W; bitpos: [9]; default: 1;
+ *  Need add description
+ */
+#define SYSTEM_LCD_CAM_RST    (BIT(9))
+#define SYSTEM_LCD_CAM_RST_M  (SYSTEM_LCD_CAM_RST_V << SYSTEM_LCD_CAM_RST_S)
+#define SYSTEM_LCD_CAM_RST_V  0x00000001U
+#define SYSTEM_LCD_CAM_RST_S  9
+/** SYSTEM_UART2_RST : R/W; bitpos: [10]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_UART2_RST    (BIT(10))
+#define SYSTEM_UART2_RST_M  (SYSTEM_UART2_RST_V << SYSTEM_UART2_RST_S)
+#define SYSTEM_UART2_RST_V  0x00000001U
+#define SYSTEM_UART2_RST_S  10
+/** SYSTEM_TSENS_RST : R/W; bitpos: [11]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_TSENS_RST    (BIT(11))
+#define SYSTEM_TSENS_RST_M  (SYSTEM_TSENS_RST_V << SYSTEM_TSENS_RST_S)
+#define SYSTEM_TSENS_RST_V  0x00000001U
+#define SYSTEM_TSENS_RST_S  11
+/** SYSTEM_ETM_RST : R/W; bitpos: [12]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_ETM_RST    (BIT(12))
+#define SYSTEM_ETM_RST_M  (SYSTEM_ETM_RST_V << SYSTEM_ETM_RST_S)
+#define SYSTEM_ETM_RST_V  0x00000001U
+#define SYSTEM_ETM_RST_S  12
+/** SYSTEM_TIMERGROUP3_RST : R/W; bitpos: [13]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_TIMERGROUP3_RST    (BIT(13))
+#define SYSTEM_TIMERGROUP3_RST_M  (SYSTEM_TIMERGROUP3_RST_V << SYSTEM_TIMERGROUP3_RST_S)
+#define SYSTEM_TIMERGROUP3_RST_V  0x00000001U
+#define SYSTEM_TIMERGROUP3_RST_S  13
+/** SYSTEM_REGRET_RST : R/W; bitpos: [14]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_REGRET_RST    (BIT(14))
+#define SYSTEM_REGRET_RST_M  (SYSTEM_REGRET_RST_V << SYSTEM_REGRET_RST_S)
+#define SYSTEM_REGRET_RST_V  0x00000001U
+#define SYSTEM_REGRET_RST_S  14
+/** SYSTEM_PVT_RST : R/W; bitpos: [15]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_PVT_RST    (BIT(15))
+#define SYSTEM_PVT_RST_M  (SYSTEM_PVT_RST_V << SYSTEM_PVT_RST_S)
+#define SYSTEM_PVT_RST_V  0x00000001U
+#define SYSTEM_PVT_RST_S  15
+
+/** SYSTEM_FPGA_DBG_REG register
+ *  register description
+ */
+#define SYSTEM_FPGA_DBG_REG (DR_REG_SYSTEM_BASE + 0x30)
+/** SYSTEM_FPGA_DEBUG : R/W; bitpos: [31:0]; default: 4294967295;
+ *  Need add description
+ */
+#define SYSTEM_FPGA_DEBUG    0xFFFFFFFFU
+#define SYSTEM_FPGA_DEBUG_M  (SYSTEM_FPGA_DEBUG_V << SYSTEM_FPGA_DEBUG_S)
+#define SYSTEM_FPGA_DEBUG_V  0xFFFFFFFFU
+#define SYSTEM_FPGA_DEBUG_S  0
+
+/** SYSTEM_REGCLK_CONF_REG register
+ *  register description
+ */
+#define SYSTEM_REGCLK_CONF_REG (DR_REG_SYSTEM_BASE + 0x34)
+/** SYSTEM_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_CLK_EN    (BIT(0))
+#define SYSTEM_CLK_EN_M  (SYSTEM_CLK_EN_V << SYSTEM_CLK_EN_S)
+#define SYSTEM_CLK_EN_V  0x00000001U
+#define SYSTEM_CLK_EN_S  0
+
+/** SYSTEM_DATE_REG register
+ *  register description
+ */
+#define SYSTEM_DATE_REG (DR_REG_SYSTEM_BASE + 0x38)
+/** SYSTEM_DATE : R/W; bitpos: [27:0]; default: 34640435;
+ *  Need add description
+ */
+#define SYSTEM_DATE    0x0FFFFFFFU
+#define SYSTEM_DATE_M  (SYSTEM_DATE_V << SYSTEM_DATE_S)
+#define SYSTEM_DATE_V  0x0FFFFFFFU
+#define SYSTEM_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32h2/include/rev2/soc/ecc_mult_reg.h

@@ -0,0 +1,130 @@
+/**
+ * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** ECC_MULT_INT_RAW_REG register
+ *  Add later.
+ */
+#define ECC_MULT_INT_RAW_REG (DR_REG_ECC_MULT_BASE + 0xc)
+/** ECC_MULT_CALC_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
+ *  Add later.
+ */
+#define ECC_MULT_CALC_DONE_INT_RAW    (BIT(0))
+#define ECC_MULT_CALC_DONE_INT_RAW_M  (ECC_MULT_CALC_DONE_INT_RAW_V << ECC_MULT_CALC_DONE_INT_RAW_S)
+#define ECC_MULT_CALC_DONE_INT_RAW_V  0x00000001U
+#define ECC_MULT_CALC_DONE_INT_RAW_S  0
+
+/** ECC_MULT_INT_ST_REG register
+ *  Add later.
+ */
+#define ECC_MULT_INT_ST_REG (DR_REG_ECC_MULT_BASE + 0x10)
+/** ECC_MULT_CALC_DONE_INT_ST : RO; bitpos: [0]; default: 0;
+ *  Add later.
+ */
+#define ECC_MULT_CALC_DONE_INT_ST    (BIT(0))
+#define ECC_MULT_CALC_DONE_INT_ST_M  (ECC_MULT_CALC_DONE_INT_ST_V << ECC_MULT_CALC_DONE_INT_ST_S)
+#define ECC_MULT_CALC_DONE_INT_ST_V  0x00000001U
+#define ECC_MULT_CALC_DONE_INT_ST_S  0
+
+/** ECC_MULT_INT_ENA_REG register
+ *  Add later.
+ */
+#define ECC_MULT_INT_ENA_REG (DR_REG_ECC_MULT_BASE + 0x14)
+/** ECC_MULT_CALC_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Add later.
+ */
+#define ECC_MULT_CALC_DONE_INT_ENA    (BIT(0))
+#define ECC_MULT_CALC_DONE_INT_ENA_M  (ECC_MULT_CALC_DONE_INT_ENA_V << ECC_MULT_CALC_DONE_INT_ENA_S)
+#define ECC_MULT_CALC_DONE_INT_ENA_V  0x00000001U
+#define ECC_MULT_CALC_DONE_INT_ENA_S  0
+
+/** ECC_MULT_INT_CLR_REG register
+ *  Add later.
+ */
+#define ECC_MULT_INT_CLR_REG (DR_REG_ECC_MULT_BASE + 0x18)
+/** ECC_MULT_CALC_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Add later.
+ */
+#define ECC_MULT_CALC_DONE_INT_CLR    (BIT(0))
+#define ECC_MULT_CALC_DONE_INT_CLR_M  (ECC_MULT_CALC_DONE_INT_CLR_V << ECC_MULT_CALC_DONE_INT_CLR_S)
+#define ECC_MULT_CALC_DONE_INT_CLR_V  0x00000001U
+#define ECC_MULT_CALC_DONE_INT_CLR_S  0
+
+/** ECC_MULT_CONF_REG register
+ *  Add later.
+ */
+#define ECC_MULT_CONF_REG (DR_REG_ECC_MULT_BASE + 0x1c)
+/** ECC_MULT_START : R/W/SC; bitpos: [0]; default: 0;
+ *  Add later.
+ */
+#define ECC_MULT_START    (BIT(0))
+#define ECC_MULT_START_M  (ECC_MULT_START_V << ECC_MULT_START_S)
+#define ECC_MULT_START_V  0x00000001U
+#define ECC_MULT_START_S  0
+/** ECC_MULT_RESET : WT; bitpos: [1]; default: 0;
+ *  Add later.
+ */
+#define ECC_MULT_RESET    (BIT(1))
+#define ECC_MULT_RESET_M  (ECC_MULT_RESET_V << ECC_MULT_RESET_S)
+#define ECC_MULT_RESET_V  0x00000001U
+#define ECC_MULT_RESET_S  1
+/** ECC_MULT_KEY_LENGTH : R/W; bitpos: [2]; default: 0;
+ *  Add later.
+ */
+#define ECC_MULT_KEY_LENGTH    (BIT(2))
+#define ECC_MULT_KEY_LENGTH_M  (ECC_MULT_KEY_LENGTH_V << ECC_MULT_KEY_LENGTH_S)
+#define ECC_MULT_KEY_LENGTH_V  0x00000001U
+#define ECC_MULT_KEY_LENGTH_S  2
+/** ECC_MULT_SECURITY_MODE : R/W; bitpos: [3]; default: 0;
+ *  Add later.
+ */
+#define ECC_MULT_SECURITY_MODE    (BIT(3))
+#define ECC_MULT_SECURITY_MODE_M  (ECC_MULT_SECURITY_MODE_V << ECC_MULT_SECURITY_MODE_S)
+#define ECC_MULT_SECURITY_MODE_V  0x00000001U
+#define ECC_MULT_SECURITY_MODE_S  3
+/** ECC_MULT_CLK_EN : R/W; bitpos: [4]; default: 0;
+ *  Add later.
+ */
+#define ECC_MULT_CLK_EN    (BIT(4))
+#define ECC_MULT_CLK_EN_M  (ECC_MULT_CLK_EN_V << ECC_MULT_CLK_EN_S)
+#define ECC_MULT_CLK_EN_V  0x00000001U
+#define ECC_MULT_CLK_EN_S  4
+/** ECC_MULT_WORK_MODE : R/W; bitpos: [6:5]; default: 0;
+ *  Add later.
+ */
+#define ECC_MULT_WORK_MODE    0x00000003U
+#define ECC_MULT_WORK_MODE_M  (ECC_MULT_WORK_MODE_V << ECC_MULT_WORK_MODE_S)
+#define ECC_MULT_WORK_MODE_V  0x00000003U
+#define ECC_MULT_WORK_MODE_S  5
+/** ECC_MULT_VERIFICATION_RESULT : RO/SS; bitpos: [7]; default: 0;
+ *  Add later.
+ */
+#define ECC_MULT_VERIFICATION_RESULT    (BIT(7))
+#define ECC_MULT_VERIFICATION_RESULT_M  (ECC_MULT_VERIFICATION_RESULT_V << ECC_MULT_VERIFICATION_RESULT_S)
+#define ECC_MULT_VERIFICATION_RESULT_V  0x00000001U
+#define ECC_MULT_VERIFICATION_RESULT_S  7
+
+/** ECC_MULT_DATE_REG register
+ *  Add later.
+ */
+#define ECC_MULT_DATE_REG (DR_REG_ECC_MULT_BASE + 0xfc)
+/** ECC_MULT_DATE : R/W; bitpos: [27:0]; default: 33628720;
+ *  ECC mult version control register
+ */
+#define ECC_MULT_DATE    0x0FFFFFFFU
+#define ECC_MULT_DATE_M  (ECC_MULT_DATE_V << ECC_MULT_DATE_S)
+#define ECC_MULT_DATE_V  0x0FFFFFFFU
+#define ECC_MULT_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32h2/include/rev2/soc/ecc_mult_struct.h

@@ -0,0 +1,145 @@
+/**
+ * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Interrupt registers */
+/** Type of int_raw register
+ *  Add later.
+ */
+typedef union {
+    struct {
+        /** calc_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
+         *  Add later.
+         */
+        uint32_t calc_done_int_raw:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ecc_mult_int_raw_reg_t;
+
+/** Type of int_st register
+ *  Add later.
+ */
+typedef union {
+    struct {
+        /** calc_done_int_st : RO; bitpos: [0]; default: 0;
+         *  Add later.
+         */
+        uint32_t calc_done_int_st:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ecc_mult_int_st_reg_t;
+
+/** Type of int_ena register
+ *  Add later.
+ */
+typedef union {
+    struct {
+        /** calc_done_int_ena : R/W; bitpos: [0]; default: 0;
+         *  Add later.
+         */
+        uint32_t calc_done_int_ena:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ecc_mult_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  Add later.
+ */
+typedef union {
+    struct {
+        /** calc_done_int_clr : WT; bitpos: [0]; default: 0;
+         *  Add later.
+         */
+        uint32_t calc_done_int_clr:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} ecc_mult_int_clr_reg_t;
+
+
+/** Group: RX Control and configuration registers */
+/** Type of conf register
+ *  Add later.
+ */
+typedef union {
+    struct {
+        /** start : R/W/SC; bitpos: [0]; default: 0;
+         *  Add later.
+         */
+        uint32_t start:1;
+        /** reset : WT; bitpos: [1]; default: 0;
+         *  Add later.
+         */
+        uint32_t reset:1;
+        /** key_length : R/W; bitpos: [2]; default: 0;
+         *  Add later.
+         */
+        uint32_t key_length:1;
+        /** security_mode : R/W; bitpos: [3]; default: 0;
+         *  Add later.
+         */
+        uint32_t security_mode:1;
+        /** clk_en : R/W; bitpos: [4]; default: 0;
+         *  Add later.
+         */
+        uint32_t clk_en:1;
+        /** work_mode : R/W; bitpos: [6:5]; default: 0;
+         *  Add later.
+         */
+        uint32_t work_mode:2;
+        /** verification_result : RO/SS; bitpos: [7]; default: 0;
+         *  Add later.
+         */
+        uint32_t verification_result:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} ecc_mult_conf_reg_t;
+
+
+/** Group: Version register */
+/** Type of date register
+ *  Add later.
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 33628720;
+         *  ECC mult version control register
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} ecc_mult_date_reg_t;
+
+
+typedef struct {
+    uint32_t reserved_000[3];
+    volatile ecc_mult_int_raw_reg_t int_raw;
+    volatile ecc_mult_int_st_reg_t int_st;
+    volatile ecc_mult_int_ena_reg_t int_ena;
+    volatile ecc_mult_int_clr_reg_t int_clr;
+    volatile ecc_mult_conf_reg_t conf;
+    uint32_t reserved_020[55];
+    volatile ecc_mult_date_reg_t date;
+} ecc_mult_dev_t;
+
+
+#ifndef __cplusplus
+_Static_assert(sizeof(ecc_mult_dev_t) == 0x100, "Invalid size of ecc_mult_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32h2/include/rev2/soc/efuse_reg.h

@@ -0,0 +1,2338 @@
+/**
+ * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** EFUSE_PGM_DATA0_REG register
+ *  Register 0 that stores data to be programmed.
+ */
+#define EFUSE_PGM_DATA0_REG (DR_REG_EFUSE_BASE + 0x0)
+/** EFUSE_PGM_DATA_0 : R/W; bitpos: [31:0]; default: 0;
+ *  The content of the 0th 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_0    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_0_M  (EFUSE_PGM_DATA_0_V << EFUSE_PGM_DATA_0_S)
+#define EFUSE_PGM_DATA_0_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_0_S  0
+
+/** EFUSE_PGM_DATA1_REG register
+ *  Register 1 that stores data to be programmed.
+ */
+#define EFUSE_PGM_DATA1_REG (DR_REG_EFUSE_BASE + 0x4)
+/** EFUSE_PGM_DATA_1 : R/W; bitpos: [31:0]; default: 0;
+ *  The content of the 1st 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_1    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_1_M  (EFUSE_PGM_DATA_1_V << EFUSE_PGM_DATA_1_S)
+#define EFUSE_PGM_DATA_1_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_1_S  0
+
+/** EFUSE_PGM_DATA2_REG register
+ *  Register 2 that stores data to be programmed.
+ */
+#define EFUSE_PGM_DATA2_REG (DR_REG_EFUSE_BASE + 0x8)
+/** EFUSE_PGM_DATA_2 : R/W; bitpos: [31:0]; default: 0;
+ *  The content of the 2nd 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_2    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_2_M  (EFUSE_PGM_DATA_2_V << EFUSE_PGM_DATA_2_S)
+#define EFUSE_PGM_DATA_2_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_2_S  0
+
+/** EFUSE_PGM_DATA3_REG register
+ *  Register 3 that stores data to be programmed.
+ */
+#define EFUSE_PGM_DATA3_REG (DR_REG_EFUSE_BASE + 0xc)
+/** EFUSE_PGM_DATA_3 : R/W; bitpos: [31:0]; default: 0;
+ *  The content of the 3rd 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_3    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_3_M  (EFUSE_PGM_DATA_3_V << EFUSE_PGM_DATA_3_S)
+#define EFUSE_PGM_DATA_3_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_3_S  0
+
+/** EFUSE_PGM_DATA4_REG register
+ *  Register 4 that stores data to be programmed.
+ */
+#define EFUSE_PGM_DATA4_REG (DR_REG_EFUSE_BASE + 0x10)
+/** EFUSE_PGM_DATA_4 : R/W; bitpos: [31:0]; default: 0;
+ *  The content of the 4th 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_4    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_4_M  (EFUSE_PGM_DATA_4_V << EFUSE_PGM_DATA_4_S)
+#define EFUSE_PGM_DATA_4_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_4_S  0
+
+/** EFUSE_PGM_DATA5_REG register
+ *  Register 5 that stores data to be programmed.
+ */
+#define EFUSE_PGM_DATA5_REG (DR_REG_EFUSE_BASE + 0x14)
+/** EFUSE_PGM_DATA_5 : R/W; bitpos: [31:0]; default: 0;
+ *  The content of the 5th 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_5    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_5_M  (EFUSE_PGM_DATA_5_V << EFUSE_PGM_DATA_5_S)
+#define EFUSE_PGM_DATA_5_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_5_S  0
+
+/** EFUSE_PGM_DATA6_REG register
+ *  Register 6 that stores data to be programmed.
+ */
+#define EFUSE_PGM_DATA6_REG (DR_REG_EFUSE_BASE + 0x18)
+/** EFUSE_PGM_DATA_6 : R/W; bitpos: [31:0]; default: 0;
+ *  The content of the 6th 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_6    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_6_M  (EFUSE_PGM_DATA_6_V << EFUSE_PGM_DATA_6_S)
+#define EFUSE_PGM_DATA_6_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_6_S  0
+
+/** EFUSE_PGM_DATA7_REG register
+ *  Register 7 that stores data to be programmed.
+ */
+#define EFUSE_PGM_DATA7_REG (DR_REG_EFUSE_BASE + 0x1c)
+/** EFUSE_PGM_DATA_7 : R/W; bitpos: [31:0]; default: 0;
+ *  The content of the 7th 32-bit data to be programmed.
+ */
+#define EFUSE_PGM_DATA_7    0xFFFFFFFFU
+#define EFUSE_PGM_DATA_7_M  (EFUSE_PGM_DATA_7_V << EFUSE_PGM_DATA_7_S)
+#define EFUSE_PGM_DATA_7_V  0xFFFFFFFFU
+#define EFUSE_PGM_DATA_7_S  0
+
+/** EFUSE_PGM_CHECK_VALUE0_REG register
+ *  Register 0 that stores the RS code to be programmed.
+ */
+#define EFUSE_PGM_CHECK_VALUE0_REG (DR_REG_EFUSE_BASE + 0x20)
+/** EFUSE_PGM_RS_DATA_0 : R/W; bitpos: [31:0]; default: 0;
+ *  The content of the 0th 32-bit RS code to be programmed.
+ */
+#define EFUSE_PGM_RS_DATA_0    0xFFFFFFFFU
+#define EFUSE_PGM_RS_DATA_0_M  (EFUSE_PGM_RS_DATA_0_V << EFUSE_PGM_RS_DATA_0_S)
+#define EFUSE_PGM_RS_DATA_0_V  0xFFFFFFFFU
+#define EFUSE_PGM_RS_DATA_0_S  0
+
+/** EFUSE_PGM_CHECK_VALUE1_REG register
+ *  Register 1 that stores the RS code to be programmed.
+ */
+#define EFUSE_PGM_CHECK_VALUE1_REG (DR_REG_EFUSE_BASE + 0x24)
+/** EFUSE_PGM_RS_DATA_1 : R/W; bitpos: [31:0]; default: 0;
+ *  The content of the 1st 32-bit RS code to be programmed.
+ */
+#define EFUSE_PGM_RS_DATA_1    0xFFFFFFFFU
+#define EFUSE_PGM_RS_DATA_1_M  (EFUSE_PGM_RS_DATA_1_V << EFUSE_PGM_RS_DATA_1_S)
+#define EFUSE_PGM_RS_DATA_1_V  0xFFFFFFFFU
+#define EFUSE_PGM_RS_DATA_1_S  0
+
+/** EFUSE_PGM_CHECK_VALUE2_REG register
+ *  Register 2 that stores the RS code to be programmed.
+ */
+#define EFUSE_PGM_CHECK_VALUE2_REG (DR_REG_EFUSE_BASE + 0x28)
+/** EFUSE_PGM_RS_DATA_2 : R/W; bitpos: [31:0]; default: 0;
+ *  The content of the 2nd 32-bit RS code to be programmed.
+ */
+#define EFUSE_PGM_RS_DATA_2    0xFFFFFFFFU
+#define EFUSE_PGM_RS_DATA_2_M  (EFUSE_PGM_RS_DATA_2_V << EFUSE_PGM_RS_DATA_2_S)
+#define EFUSE_PGM_RS_DATA_2_V  0xFFFFFFFFU
+#define EFUSE_PGM_RS_DATA_2_S  0
+
+/** EFUSE_RD_WR_DIS_REG register
+ *  BLOCK0 data register $n.
+ */
+#define EFUSE_RD_WR_DIS_REG (DR_REG_EFUSE_BASE + 0x2c)
+/** EFUSE_WR_DIS : RO; bitpos: [31:0]; default: 0;
+ *  The value of WR_DIS.
+ */
+#define EFUSE_WR_DIS    0xFFFFFFFFU
+#define EFUSE_WR_DIS_M  (EFUSE_WR_DIS_V << EFUSE_WR_DIS_S)
+#define EFUSE_WR_DIS_V  0xFFFFFFFFU
+#define EFUSE_WR_DIS_S  0
+
+/** EFUSE_RD_REPEAT_DATA0_REG register
+ *  BLOCK0 data register $n.
+ */
+#define EFUSE_RD_REPEAT_DATA0_REG (DR_REG_EFUSE_BASE + 0x30)
+/** EFUSE_RD_DIS : RO; bitpos: [6:0]; default: 0;
+ *  The value of RD_DIS.
+ */
+#define EFUSE_RD_DIS    0x0000007FU
+#define EFUSE_RD_DIS_M  (EFUSE_RD_DIS_V << EFUSE_RD_DIS_S)
+#define EFUSE_RD_DIS_V  0x0000007FU
+#define EFUSE_RD_DIS_S  0
+/** EFUSE_DIS_RTC_RAM_BOOT : RO; bitpos: [7]; default: 0;
+ *  The value of DIS_RTC_RAM_BOOT.
+ */
+#define EFUSE_DIS_RTC_RAM_BOOT    (BIT(7))
+#define EFUSE_DIS_RTC_RAM_BOOT_M  (EFUSE_DIS_RTC_RAM_BOOT_V << EFUSE_DIS_RTC_RAM_BOOT_S)
+#define EFUSE_DIS_RTC_RAM_BOOT_V  0x00000001U
+#define EFUSE_DIS_RTC_RAM_BOOT_S  7
+/** EFUSE_DIS_ICACHE : RO; bitpos: [8]; default: 0;
+ *  The value of DIS_ICACHE.
+ */
+#define EFUSE_DIS_ICACHE    (BIT(8))
+#define EFUSE_DIS_ICACHE_M  (EFUSE_DIS_ICACHE_V << EFUSE_DIS_ICACHE_S)
+#define EFUSE_DIS_ICACHE_V  0x00000001U
+#define EFUSE_DIS_ICACHE_S  8
+/** EFUSE_DIS_USB_JTAG : RO; bitpos: [9]; default: 0;
+ *  The value of DIS_USB_JTAG.
+ */
+#define EFUSE_DIS_USB_JTAG    (BIT(9))
+#define EFUSE_DIS_USB_JTAG_M  (EFUSE_DIS_USB_JTAG_V << EFUSE_DIS_USB_JTAG_S)
+#define EFUSE_DIS_USB_JTAG_V  0x00000001U
+#define EFUSE_DIS_USB_JTAG_S  9
+/** EFUSE_DIS_DOWNLOAD_ICACHE : RO; bitpos: [10]; default: 0;
+ *  The value of DIS_DOWNLOAD_ICACHE.
+ */
+#define EFUSE_DIS_DOWNLOAD_ICACHE    (BIT(10))
+#define EFUSE_DIS_DOWNLOAD_ICACHE_M  (EFUSE_DIS_DOWNLOAD_ICACHE_V << EFUSE_DIS_DOWNLOAD_ICACHE_S)
+#define EFUSE_DIS_DOWNLOAD_ICACHE_V  0x00000001U
+#define EFUSE_DIS_DOWNLOAD_ICACHE_S  10
+/** EFUSE_DIS_USB_DEVICE : RO; bitpos: [11]; default: 0;
+ *  The value of DIS_USB_DEVICE.
+ */
+#define EFUSE_DIS_USB_DEVICE    (BIT(11))
+#define EFUSE_DIS_USB_DEVICE_M  (EFUSE_DIS_USB_DEVICE_V << EFUSE_DIS_USB_DEVICE_S)
+#define EFUSE_DIS_USB_DEVICE_V  0x00000001U
+#define EFUSE_DIS_USB_DEVICE_S  11
+/** EFUSE_DIS_FORCE_DOWNLOAD : RO; bitpos: [12]; default: 0;
+ *  The value of DIS_FORCE_DOWNLOAD.
+ */
+#define EFUSE_DIS_FORCE_DOWNLOAD    (BIT(12))
+#define EFUSE_DIS_FORCE_DOWNLOAD_M  (EFUSE_DIS_FORCE_DOWNLOAD_V << EFUSE_DIS_FORCE_DOWNLOAD_S)
+#define EFUSE_DIS_FORCE_DOWNLOAD_V  0x00000001U
+#define EFUSE_DIS_FORCE_DOWNLOAD_S  12
+/** EFUSE_DIS_USB : RO; bitpos: [13]; default: 0;
+ *  The value of DIS_USB.
+ */
+#define EFUSE_DIS_USB    (BIT(13))
+#define EFUSE_DIS_USB_M  (EFUSE_DIS_USB_V << EFUSE_DIS_USB_S)
+#define EFUSE_DIS_USB_V  0x00000001U
+#define EFUSE_DIS_USB_S  13
+/** EFUSE_DIS_TWAI : RO; bitpos: [14]; default: 0;
+ *  The value of DIS_TWAI.
+ */
+#define EFUSE_DIS_TWAI    (BIT(14))
+#define EFUSE_DIS_TWAI_M  (EFUSE_DIS_TWAI_V << EFUSE_DIS_TWAI_S)
+#define EFUSE_DIS_TWAI_V  0x00000001U
+#define EFUSE_DIS_TWAI_S  14
+/** EFUSE_JTAG_SEL_ENABLE : RO; bitpos: [15]; default: 0;
+ *  The value of JTAG_SEL_ENABLE.
+ */
+#define EFUSE_JTAG_SEL_ENABLE    (BIT(15))
+#define EFUSE_JTAG_SEL_ENABLE_M  (EFUSE_JTAG_SEL_ENABLE_V << EFUSE_JTAG_SEL_ENABLE_S)
+#define EFUSE_JTAG_SEL_ENABLE_V  0x00000001U
+#define EFUSE_JTAG_SEL_ENABLE_S  15
+/** EFUSE_SOFT_DIS_JTAG : RO; bitpos: [18:16]; default: 0;
+ *  The value of SOFT_DIS_JTAG.
+ */
+#define EFUSE_SOFT_DIS_JTAG    0x00000007U
+#define EFUSE_SOFT_DIS_JTAG_M  (EFUSE_SOFT_DIS_JTAG_V << EFUSE_SOFT_DIS_JTAG_S)
+#define EFUSE_SOFT_DIS_JTAG_V  0x00000007U
+#define EFUSE_SOFT_DIS_JTAG_S  16
+/** EFUSE_DIS_PAD_JTAG : RO; bitpos: [19]; default: 0;
+ *  The value of DIS_PAD_JTAG.
+ */
+#define EFUSE_DIS_PAD_JTAG    (BIT(19))
+#define EFUSE_DIS_PAD_JTAG_M  (EFUSE_DIS_PAD_JTAG_V << EFUSE_DIS_PAD_JTAG_S)
+#define EFUSE_DIS_PAD_JTAG_V  0x00000001U
+#define EFUSE_DIS_PAD_JTAG_S  19
+/** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : RO; bitpos: [20]; default: 0;
+ *  The value of DIS_DOWNLOAD_MANUAL_ENCRYPT.
+ */
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT    (BIT(20))
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M  (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S)
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V  0x00000001U
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S  20
+/** EFUSE_USB_DREFH : RO; bitpos: [22:21]; default: 0;
+ *  The value of USB_DREFH.
+ */
+#define EFUSE_USB_DREFH    0x00000003U
+#define EFUSE_USB_DREFH_M  (EFUSE_USB_DREFH_V << EFUSE_USB_DREFH_S)
+#define EFUSE_USB_DREFH_V  0x00000003U
+#define EFUSE_USB_DREFH_S  21
+/** EFUSE_USB_DREFL : RO; bitpos: [24:23]; default: 0;
+ *  The value of USB_DREFL.
+ */
+#define EFUSE_USB_DREFL    0x00000003U
+#define EFUSE_USB_DREFL_M  (EFUSE_USB_DREFL_V << EFUSE_USB_DREFL_S)
+#define EFUSE_USB_DREFL_V  0x00000003U
+#define EFUSE_USB_DREFL_S  23
+/** EFUSE_USB_EXCHG_PINS : RO; bitpos: [25]; default: 0;
+ *  The value of USB_EXCHG_PINS.
+ */
+#define EFUSE_USB_EXCHG_PINS    (BIT(25))
+#define EFUSE_USB_EXCHG_PINS_M  (EFUSE_USB_EXCHG_PINS_V << EFUSE_USB_EXCHG_PINS_S)
+#define EFUSE_USB_EXCHG_PINS_V  0x00000001U
+#define EFUSE_USB_EXCHG_PINS_S  25
+/** EFUSE_VDD_SPI_AS_GPIO : RO; bitpos: [26]; default: 0;
+ *  The value of VDD_SPI_AS_GPIO.
+ */
+#define EFUSE_VDD_SPI_AS_GPIO    (BIT(26))
+#define EFUSE_VDD_SPI_AS_GPIO_M  (EFUSE_VDD_SPI_AS_GPIO_V << EFUSE_VDD_SPI_AS_GPIO_S)
+#define EFUSE_VDD_SPI_AS_GPIO_V  0x00000001U
+#define EFUSE_VDD_SPI_AS_GPIO_S  26
+/** EFUSE_BTLC_GPIO_ENABLE : RO; bitpos: [28:27]; default: 0;
+ *  The value of BTLC_GPIO_ENABLE.
+ */
+#define EFUSE_BTLC_GPIO_ENABLE    0x00000003U
+#define EFUSE_BTLC_GPIO_ENABLE_M  (EFUSE_BTLC_GPIO_ENABLE_V << EFUSE_BTLC_GPIO_ENABLE_S)
+#define EFUSE_BTLC_GPIO_ENABLE_V  0x00000003U
+#define EFUSE_BTLC_GPIO_ENABLE_S  27
+/** EFUSE_POWERGLITCH_EN : RO; bitpos: [29]; default: 0;
+ *  The value of POWERGLITCH_EN.
+ */
+#define EFUSE_POWERGLITCH_EN    (BIT(29))
+#define EFUSE_POWERGLITCH_EN_M  (EFUSE_POWERGLITCH_EN_V << EFUSE_POWERGLITCH_EN_S)
+#define EFUSE_POWERGLITCH_EN_V  0x00000001U
+#define EFUSE_POWERGLITCH_EN_S  29
+/** EFUSE_POWER_GLITCH_DSENSE : RO; bitpos: [31:30]; default: 0;
+ *  The value of POWER_GLITCH_DSENSE.
+ */
+#define EFUSE_POWER_GLITCH_DSENSE    0x00000003U
+#define EFUSE_POWER_GLITCH_DSENSE_M  (EFUSE_POWER_GLITCH_DSENSE_V << EFUSE_POWER_GLITCH_DSENSE_S)
+#define EFUSE_POWER_GLITCH_DSENSE_V  0x00000003U
+#define EFUSE_POWER_GLITCH_DSENSE_S  30
+
+/** EFUSE_RD_REPEAT_DATA1_REG register
+ *  BLOCK0 data register $n.
+ */
+#define EFUSE_RD_REPEAT_DATA1_REG (DR_REG_EFUSE_BASE + 0x34)
+/** EFUSE_RPT4_RESERVED2 : RO; bitpos: [15:0]; default: 0;
+ *  Reserved.
+ */
+#define EFUSE_RPT4_RESERVED2    0x0000FFFFU
+#define EFUSE_RPT4_RESERVED2_M  (EFUSE_RPT4_RESERVED2_V << EFUSE_RPT4_RESERVED2_S)
+#define EFUSE_RPT4_RESERVED2_V  0x0000FFFFU
+#define EFUSE_RPT4_RESERVED2_S  0
+/** EFUSE_WDT_DELAY_SEL : RO; bitpos: [17:16]; default: 0;
+ *  The value of WDT_DELAY_SEL.
+ */
+#define EFUSE_WDT_DELAY_SEL    0x00000003U
+#define EFUSE_WDT_DELAY_SEL_M  (EFUSE_WDT_DELAY_SEL_V << EFUSE_WDT_DELAY_SEL_S)
+#define EFUSE_WDT_DELAY_SEL_V  0x00000003U
+#define EFUSE_WDT_DELAY_SEL_S  16
+/** EFUSE_SPI_BOOT_CRYPT_CNT : RO; bitpos: [20:18]; default: 0;
+ *  The value of SPI_BOOT_CRYPT_CNT.
+ */
+#define EFUSE_SPI_BOOT_CRYPT_CNT    0x00000007U
+#define EFUSE_SPI_BOOT_CRYPT_CNT_M  (EFUSE_SPI_BOOT_CRYPT_CNT_V << EFUSE_SPI_BOOT_CRYPT_CNT_S)
+#define EFUSE_SPI_BOOT_CRYPT_CNT_V  0x00000007U
+#define EFUSE_SPI_BOOT_CRYPT_CNT_S  18
+/** EFUSE_SECURE_BOOT_KEY_REVOKE0 : RO; bitpos: [21]; default: 0;
+ *  The value of SECURE_BOOT_KEY_REVOKE0.
+ */
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0    (BIT(21))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_M  (EFUSE_SECURE_BOOT_KEY_REVOKE0_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_S)
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_V  0x00000001U
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_S  21
+/** EFUSE_SECURE_BOOT_KEY_REVOKE1 : RO; bitpos: [22]; default: 0;
+ *  The value of SECURE_BOOT_KEY_REVOKE1.
+ */
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1    (BIT(22))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_M  (EFUSE_SECURE_BOOT_KEY_REVOKE1_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_S)
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_V  0x00000001U
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_S  22
+/** EFUSE_SECURE_BOOT_KEY_REVOKE2 : RO; bitpos: [23]; default: 0;
+ *  The value of SECURE_BOOT_KEY_REVOKE2.
+ */
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2    (BIT(23))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_M  (EFUSE_SECURE_BOOT_KEY_REVOKE2_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_S)
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_V  0x00000001U
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_S  23
+/** EFUSE_KEY_PURPOSE_0 : RO; bitpos: [27:24]; default: 0;
+ *  The value of KEY_PURPOSE_0.
+ */
+#define EFUSE_KEY_PURPOSE_0    0x0000000FU
+#define EFUSE_KEY_PURPOSE_0_M  (EFUSE_KEY_PURPOSE_0_V << EFUSE_KEY_PURPOSE_0_S)
+#define EFUSE_KEY_PURPOSE_0_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_0_S  24
+/** EFUSE_KEY_PURPOSE_1 : RO; bitpos: [31:28]; default: 0;
+ *  The value of KEY_PURPOSE_1.
+ */
+#define EFUSE_KEY_PURPOSE_1    0x0000000FU
+#define EFUSE_KEY_PURPOSE_1_M  (EFUSE_KEY_PURPOSE_1_V << EFUSE_KEY_PURPOSE_1_S)
+#define EFUSE_KEY_PURPOSE_1_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_1_S  28
+
+/** EFUSE_RD_REPEAT_DATA2_REG register
+ *  BLOCK0 data register $n.
+ */
+#define EFUSE_RD_REPEAT_DATA2_REG (DR_REG_EFUSE_BASE + 0x38)
+/** EFUSE_KEY_PURPOSE_2 : RO; bitpos: [3:0]; default: 0;
+ *  The value of KEY_PURPOSE_2.
+ */
+#define EFUSE_KEY_PURPOSE_2    0x0000000FU
+#define EFUSE_KEY_PURPOSE_2_M  (EFUSE_KEY_PURPOSE_2_V << EFUSE_KEY_PURPOSE_2_S)
+#define EFUSE_KEY_PURPOSE_2_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_2_S  0
+/** EFUSE_KEY_PURPOSE_3 : RO; bitpos: [7:4]; default: 0;
+ *  The value of KEY_PURPOSE_3.
+ */
+#define EFUSE_KEY_PURPOSE_3    0x0000000FU
+#define EFUSE_KEY_PURPOSE_3_M  (EFUSE_KEY_PURPOSE_3_V << EFUSE_KEY_PURPOSE_3_S)
+#define EFUSE_KEY_PURPOSE_3_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_3_S  4
+/** EFUSE_KEY_PURPOSE_4 : RO; bitpos: [11:8]; default: 0;
+ *  The value of KEY_PURPOSE_4.
+ */
+#define EFUSE_KEY_PURPOSE_4    0x0000000FU
+#define EFUSE_KEY_PURPOSE_4_M  (EFUSE_KEY_PURPOSE_4_V << EFUSE_KEY_PURPOSE_4_S)
+#define EFUSE_KEY_PURPOSE_4_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_4_S  8
+/** EFUSE_KEY_PURPOSE_5 : RO; bitpos: [15:12]; default: 0;
+ *  The value of KEY_PURPOSE_5.
+ */
+#define EFUSE_KEY_PURPOSE_5    0x0000000FU
+#define EFUSE_KEY_PURPOSE_5_M  (EFUSE_KEY_PURPOSE_5_V << EFUSE_KEY_PURPOSE_5_S)
+#define EFUSE_KEY_PURPOSE_5_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_5_S  12
+/** EFUSE_RPT4_RESERVED3 : RO; bitpos: [19:16]; default: 0;
+ *  Reserved.
+ */
+#define EFUSE_RPT4_RESERVED3    0x0000000FU
+#define EFUSE_RPT4_RESERVED3_M  (EFUSE_RPT4_RESERVED3_V << EFUSE_RPT4_RESERVED3_S)
+#define EFUSE_RPT4_RESERVED3_V  0x0000000FU
+#define EFUSE_RPT4_RESERVED3_S  16
+/** EFUSE_SECURE_BOOT_EN : RO; bitpos: [20]; default: 0;
+ *  The value of SECURE_BOOT_EN.
+ */
+#define EFUSE_SECURE_BOOT_EN    (BIT(20))
+#define EFUSE_SECURE_BOOT_EN_M  (EFUSE_SECURE_BOOT_EN_V << EFUSE_SECURE_BOOT_EN_S)
+#define EFUSE_SECURE_BOOT_EN_V  0x00000001U
+#define EFUSE_SECURE_BOOT_EN_S  20
+/** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : RO; bitpos: [21]; default: 0;
+ *  The value of SECURE_BOOT_AGGRESSIVE_REVOKE.
+ */
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE    (BIT(21))
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M  (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S)
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V  0x00000001U
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S  21
+/** EFUSE_RPT4_RESERVED0 : RO; bitpos: [27:22]; default: 0;
+ *  Reserved.
+ */
+#define EFUSE_RPT4_RESERVED0    0x0000003FU
+#define EFUSE_RPT4_RESERVED0_M  (EFUSE_RPT4_RESERVED0_V << EFUSE_RPT4_RESERVED0_S)
+#define EFUSE_RPT4_RESERVED0_V  0x0000003FU
+#define EFUSE_RPT4_RESERVED0_S  22
+/** EFUSE_FLASH_TPUW : RO; bitpos: [31:28]; default: 0;
+ *  The value of FLASH_TPUW.
+ */
+#define EFUSE_FLASH_TPUW    0x0000000FU
+#define EFUSE_FLASH_TPUW_M  (EFUSE_FLASH_TPUW_V << EFUSE_FLASH_TPUW_S)
+#define EFUSE_FLASH_TPUW_V  0x0000000FU
+#define EFUSE_FLASH_TPUW_S  28
+
+/** EFUSE_RD_REPEAT_DATA3_REG register
+ *  BLOCK0 data register $n.
+ */
+#define EFUSE_RD_REPEAT_DATA3_REG (DR_REG_EFUSE_BASE + 0x3c)
+/** EFUSE_DIS_DOWNLOAD_MODE : RO; bitpos: [0]; default: 0;
+ *  The value of DIS_DOWNLOAD_MODE.
+ */
+#define EFUSE_DIS_DOWNLOAD_MODE    (BIT(0))
+#define EFUSE_DIS_DOWNLOAD_MODE_M  (EFUSE_DIS_DOWNLOAD_MODE_V << EFUSE_DIS_DOWNLOAD_MODE_S)
+#define EFUSE_DIS_DOWNLOAD_MODE_V  0x00000001U
+#define EFUSE_DIS_DOWNLOAD_MODE_S  0
+/** EFUSE_DIS_LEGACY_SPI_BOOT : RO; bitpos: [1]; default: 0;
+ *  The value of DIS_LEGACY_SPI_BOOT.
+ */
+#define EFUSE_DIS_LEGACY_SPI_BOOT    (BIT(1))
+#define EFUSE_DIS_LEGACY_SPI_BOOT_M  (EFUSE_DIS_LEGACY_SPI_BOOT_V << EFUSE_DIS_LEGACY_SPI_BOOT_S)
+#define EFUSE_DIS_LEGACY_SPI_BOOT_V  0x00000001U
+#define EFUSE_DIS_LEGACY_SPI_BOOT_S  1
+/** EFUSE_UART_PRINT_CHANNEL : RO; bitpos: [2]; default: 0;
+ *  The value of UART_PRINT_CHANNEL.
+ */
+#define EFUSE_UART_PRINT_CHANNEL    (BIT(2))
+#define EFUSE_UART_PRINT_CHANNEL_M  (EFUSE_UART_PRINT_CHANNEL_V << EFUSE_UART_PRINT_CHANNEL_S)
+#define EFUSE_UART_PRINT_CHANNEL_V  0x00000001U
+#define EFUSE_UART_PRINT_CHANNEL_S  2
+/** EFUSE_FLASH_ECC_MODE : RO; bitpos: [3]; default: 0;
+ *  The value of FLASH_ECC_MODE.
+ */
+#define EFUSE_FLASH_ECC_MODE    (BIT(3))
+#define EFUSE_FLASH_ECC_MODE_M  (EFUSE_FLASH_ECC_MODE_V << EFUSE_FLASH_ECC_MODE_S)
+#define EFUSE_FLASH_ECC_MODE_V  0x00000001U
+#define EFUSE_FLASH_ECC_MODE_S  3
+/** EFUSE_DIS_USB_DOWNLOAD_MODE : RO; bitpos: [4]; default: 0;
+ *  The value of DIS_USB_DOWNLOAD_MODE.
+ */
+#define EFUSE_DIS_USB_DOWNLOAD_MODE    (BIT(4))
+#define EFUSE_DIS_USB_DOWNLOAD_MODE_M  (EFUSE_DIS_USB_DOWNLOAD_MODE_V << EFUSE_DIS_USB_DOWNLOAD_MODE_S)
+#define EFUSE_DIS_USB_DOWNLOAD_MODE_V  0x00000001U
+#define EFUSE_DIS_USB_DOWNLOAD_MODE_S  4
+/** EFUSE_ENABLE_SECURITY_DOWNLOAD : RO; bitpos: [5]; default: 0;
+ *  The value of ENABLE_SECURITY_DOWNLOAD.
+ */
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD    (BIT(5))
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_M  (EFUSE_ENABLE_SECURITY_DOWNLOAD_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_S)
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_V  0x00000001U
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_S  5
+/** EFUSE_UART_PRINT_CONTROL : RO; bitpos: [7:6]; default: 0;
+ *  The value of UART_PRINT_CONTROL.
+ */
+#define EFUSE_UART_PRINT_CONTROL    0x00000003U
+#define EFUSE_UART_PRINT_CONTROL_M  (EFUSE_UART_PRINT_CONTROL_V << EFUSE_UART_PRINT_CONTROL_S)
+#define EFUSE_UART_PRINT_CONTROL_V  0x00000003U
+#define EFUSE_UART_PRINT_CONTROL_S  6
+/** EFUSE_PIN_POWER_SELECTION : RO; bitpos: [8]; default: 0;
+ *  The value of PIN_POWER_SELECTION.
+ */
+#define EFUSE_PIN_POWER_SELECTION    (BIT(8))
+#define EFUSE_PIN_POWER_SELECTION_M  (EFUSE_PIN_POWER_SELECTION_V << EFUSE_PIN_POWER_SELECTION_S)
+#define EFUSE_PIN_POWER_SELECTION_V  0x00000001U
+#define EFUSE_PIN_POWER_SELECTION_S  8
+/** EFUSE_FLASH_TYPE : RO; bitpos: [9]; default: 0;
+ *  The value of FLASH_TYPE.
+ */
+#define EFUSE_FLASH_TYPE    (BIT(9))
+#define EFUSE_FLASH_TYPE_M  (EFUSE_FLASH_TYPE_V << EFUSE_FLASH_TYPE_S)
+#define EFUSE_FLASH_TYPE_V  0x00000001U
+#define EFUSE_FLASH_TYPE_S  9
+/** EFUSE_FLASH_PAGE_SIZE : RO; bitpos: [11:10]; default: 0;
+ *  The value of FLASH_PAGE_SIZE.
+ */
+#define EFUSE_FLASH_PAGE_SIZE    0x00000003U
+#define EFUSE_FLASH_PAGE_SIZE_M  (EFUSE_FLASH_PAGE_SIZE_V << EFUSE_FLASH_PAGE_SIZE_S)
+#define EFUSE_FLASH_PAGE_SIZE_V  0x00000003U
+#define EFUSE_FLASH_PAGE_SIZE_S  10
+/** EFUSE_FLASH_ECC_EN : RO; bitpos: [12]; default: 0;
+ *  The value of FLASH_ECC_EN.
+ */
+#define EFUSE_FLASH_ECC_EN    (BIT(12))
+#define EFUSE_FLASH_ECC_EN_M  (EFUSE_FLASH_ECC_EN_V << EFUSE_FLASH_ECC_EN_S)
+#define EFUSE_FLASH_ECC_EN_V  0x00000001U
+#define EFUSE_FLASH_ECC_EN_S  12
+/** EFUSE_FORCE_SEND_RESUME : RO; bitpos: [13]; default: 0;
+ *  The value of FORCE_SEND_RESUME.
+ */
+#define EFUSE_FORCE_SEND_RESUME    (BIT(13))
+#define EFUSE_FORCE_SEND_RESUME_M  (EFUSE_FORCE_SEND_RESUME_V << EFUSE_FORCE_SEND_RESUME_S)
+#define EFUSE_FORCE_SEND_RESUME_V  0x00000001U
+#define EFUSE_FORCE_SEND_RESUME_S  13
+/** EFUSE_SECURE_VERSION : RO; bitpos: [29:14]; default: 0;
+ *  The value of SECURE_VERSION.
+ */
+#define EFUSE_SECURE_VERSION    0x0000FFFFU
+#define EFUSE_SECURE_VERSION_M  (EFUSE_SECURE_VERSION_V << EFUSE_SECURE_VERSION_S)
+#define EFUSE_SECURE_VERSION_V  0x0000FFFFU
+#define EFUSE_SECURE_VERSION_S  14
+/** EFUSE_RPT4_RESERVED1 : RO; bitpos: [31:30]; default: 0;
+ *  Reserved.
+ */
+#define EFUSE_RPT4_RESERVED1    0x00000003U
+#define EFUSE_RPT4_RESERVED1_M  (EFUSE_RPT4_RESERVED1_V << EFUSE_RPT4_RESERVED1_S)
+#define EFUSE_RPT4_RESERVED1_V  0x00000003U
+#define EFUSE_RPT4_RESERVED1_S  30
+
+/** EFUSE_RD_REPEAT_DATA4_REG register
+ *  BLOCK0 data register $n.
+ */
+#define EFUSE_RD_REPEAT_DATA4_REG (DR_REG_EFUSE_BASE + 0x40)
+/** EFUSE_RPT4_RESERVED4 : RO; bitpos: [23:0]; default: 0;
+ *  Reserved.
+ */
+#define EFUSE_RPT4_RESERVED4    0x00FFFFFFU
+#define EFUSE_RPT4_RESERVED4_M  (EFUSE_RPT4_RESERVED4_V << EFUSE_RPT4_RESERVED4_S)
+#define EFUSE_RPT4_RESERVED4_V  0x00FFFFFFU
+#define EFUSE_RPT4_RESERVED4_S  0
+
+/** EFUSE_RD_MAC_SPI_SYS_0_REG register
+ *  BLOCK1 data register $n.
+ */
+#define EFUSE_RD_MAC_SPI_SYS_0_REG (DR_REG_EFUSE_BASE + 0x44)
+/** EFUSE_MAC_0 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the low 32 bits of MAC address.
+ */
+#define EFUSE_MAC_0    0xFFFFFFFFU
+#define EFUSE_MAC_0_M  (EFUSE_MAC_0_V << EFUSE_MAC_0_S)
+#define EFUSE_MAC_0_V  0xFFFFFFFFU
+#define EFUSE_MAC_0_S  0
+
+/** EFUSE_RD_MAC_SPI_SYS_1_REG register
+ *  BLOCK1 data register $n.
+ */
+#define EFUSE_RD_MAC_SPI_SYS_1_REG (DR_REG_EFUSE_BASE + 0x48)
+/** EFUSE_MAC_1 : RO; bitpos: [15:0]; default: 0;
+ *  Stores the high 16 bits of MAC address.
+ */
+#define EFUSE_MAC_1    0x0000FFFFU
+#define EFUSE_MAC_1_M  (EFUSE_MAC_1_V << EFUSE_MAC_1_S)
+#define EFUSE_MAC_1_V  0x0000FFFFU
+#define EFUSE_MAC_1_S  0
+/** EFUSE_SPI_PAD_CONF_0 : RO; bitpos: [31:16]; default: 0;
+ *  Stores the zeroth part of SPI_PAD_CONF.
+ */
+#define EFUSE_SPI_PAD_CONF_0    0x0000FFFFU
+#define EFUSE_SPI_PAD_CONF_0_M  (EFUSE_SPI_PAD_CONF_0_V << EFUSE_SPI_PAD_CONF_0_S)
+#define EFUSE_SPI_PAD_CONF_0_V  0x0000FFFFU
+#define EFUSE_SPI_PAD_CONF_0_S  16
+
+/** EFUSE_RD_MAC_SPI_SYS_2_REG register
+ *  BLOCK1 data register $n.
+ */
+#define EFUSE_RD_MAC_SPI_SYS_2_REG (DR_REG_EFUSE_BASE + 0x4c)
+/** EFUSE_SPI_PAD_CONF_1 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the first part of SPI_PAD_CONF.
+ */
+#define EFUSE_SPI_PAD_CONF_1    0xFFFFFFFFU
+#define EFUSE_SPI_PAD_CONF_1_M  (EFUSE_SPI_PAD_CONF_1_V << EFUSE_SPI_PAD_CONF_1_S)
+#define EFUSE_SPI_PAD_CONF_1_V  0xFFFFFFFFU
+#define EFUSE_SPI_PAD_CONF_1_S  0
+
+/** EFUSE_RD_MAC_SPI_SYS_3_REG register
+ *  BLOCK1 data register $n.
+ */
+#define EFUSE_RD_MAC_SPI_SYS_3_REG (DR_REG_EFUSE_BASE + 0x50)
+/** EFUSE_SPI_PAD_CONF_2 : RO; bitpos: [17:0]; default: 0;
+ *  Stores the second part of SPI_PAD_CONF.
+ */
+#define EFUSE_SPI_PAD_CONF_2    0x0003FFFFU
+#define EFUSE_SPI_PAD_CONF_2_M  (EFUSE_SPI_PAD_CONF_2_V << EFUSE_SPI_PAD_CONF_2_S)
+#define EFUSE_SPI_PAD_CONF_2_V  0x0003FFFFU
+#define EFUSE_SPI_PAD_CONF_2_S  0
+/** EFUSE_SYS_DATA_PART0_0 : RO; bitpos: [31:18]; default: 0;
+ *  Stores the fist 14 bits of the zeroth part of system data.
+ */
+#define EFUSE_SYS_DATA_PART0_0    0x00003FFFU
+#define EFUSE_SYS_DATA_PART0_0_M  (EFUSE_SYS_DATA_PART0_0_V << EFUSE_SYS_DATA_PART0_0_S)
+#define EFUSE_SYS_DATA_PART0_0_V  0x00003FFFU
+#define EFUSE_SYS_DATA_PART0_0_S  18
+
+/** EFUSE_RD_MAC_SPI_SYS_4_REG register
+ *  BLOCK1 data register $n.
+ */
+#define EFUSE_RD_MAC_SPI_SYS_4_REG (DR_REG_EFUSE_BASE + 0x54)
+/** EFUSE_SYS_DATA_PART0_1 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fist 32 bits of the zeroth part of system data.
+ */
+#define EFUSE_SYS_DATA_PART0_1    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART0_1_M  (EFUSE_SYS_DATA_PART0_1_V << EFUSE_SYS_DATA_PART0_1_S)
+#define EFUSE_SYS_DATA_PART0_1_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART0_1_S  0
+
+/** EFUSE_RD_MAC_SPI_SYS_5_REG register
+ *  BLOCK1 data register $n.
+ */
+#define EFUSE_RD_MAC_SPI_SYS_5_REG (DR_REG_EFUSE_BASE + 0x58)
+/** EFUSE_SYS_DATA_PART0_2 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the second 32 bits of the zeroth part of system data.
+ */
+#define EFUSE_SYS_DATA_PART0_2    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART0_2_M  (EFUSE_SYS_DATA_PART0_2_V << EFUSE_SYS_DATA_PART0_2_S)
+#define EFUSE_SYS_DATA_PART0_2_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART0_2_S  0
+
+/** EFUSE_RD_SYS_PART1_DATA0_REG register
+ *  Register $n of BLOCK2 (system).
+ */
+#define EFUSE_RD_SYS_PART1_DATA0_REG (DR_REG_EFUSE_BASE + 0x5c)
+/** EFUSE_SYS_DATA_PART1_0 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the zeroth 32 bits of the first part of system data.
+ */
+#define EFUSE_SYS_DATA_PART1_0    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART1_0_M  (EFUSE_SYS_DATA_PART1_0_V << EFUSE_SYS_DATA_PART1_0_S)
+#define EFUSE_SYS_DATA_PART1_0_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART1_0_S  0
+
+/** EFUSE_RD_SYS_PART1_DATA1_REG register
+ *  Register $n of BLOCK2 (system).
+ */
+#define EFUSE_RD_SYS_PART1_DATA1_REG (DR_REG_EFUSE_BASE + 0x60)
+/** EFUSE_SYS_DATA_PART1_1 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the first 32 bits of the first part of system data.
+ */
+#define EFUSE_SYS_DATA_PART1_1    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART1_1_M  (EFUSE_SYS_DATA_PART1_1_V << EFUSE_SYS_DATA_PART1_1_S)
+#define EFUSE_SYS_DATA_PART1_1_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART1_1_S  0
+
+/** EFUSE_RD_SYS_PART1_DATA2_REG register
+ *  Register $n of BLOCK2 (system).
+ */
+#define EFUSE_RD_SYS_PART1_DATA2_REG (DR_REG_EFUSE_BASE + 0x64)
+/** EFUSE_SYS_DATA_PART1_2 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the second 32 bits of the first part of system data.
+ */
+#define EFUSE_SYS_DATA_PART1_2    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART1_2_M  (EFUSE_SYS_DATA_PART1_2_V << EFUSE_SYS_DATA_PART1_2_S)
+#define EFUSE_SYS_DATA_PART1_2_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART1_2_S  0
+
+/** EFUSE_RD_SYS_PART1_DATA3_REG register
+ *  Register $n of BLOCK2 (system).
+ */
+#define EFUSE_RD_SYS_PART1_DATA3_REG (DR_REG_EFUSE_BASE + 0x68)
+/** EFUSE_SYS_DATA_PART1_3 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the third 32 bits of the first part of system data.
+ */
+#define EFUSE_SYS_DATA_PART1_3    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART1_3_M  (EFUSE_SYS_DATA_PART1_3_V << EFUSE_SYS_DATA_PART1_3_S)
+#define EFUSE_SYS_DATA_PART1_3_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART1_3_S  0
+
+/** EFUSE_RD_SYS_PART1_DATA4_REG register
+ *  Register $n of BLOCK2 (system).
+ */
+#define EFUSE_RD_SYS_PART1_DATA4_REG (DR_REG_EFUSE_BASE + 0x6c)
+/** EFUSE_SYS_DATA_PART1_4 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fourth 32 bits of the first part of system data.
+ */
+#define EFUSE_SYS_DATA_PART1_4    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART1_4_M  (EFUSE_SYS_DATA_PART1_4_V << EFUSE_SYS_DATA_PART1_4_S)
+#define EFUSE_SYS_DATA_PART1_4_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART1_4_S  0
+
+/** EFUSE_RD_SYS_PART1_DATA5_REG register
+ *  Register $n of BLOCK2 (system).
+ */
+#define EFUSE_RD_SYS_PART1_DATA5_REG (DR_REG_EFUSE_BASE + 0x70)
+/** EFUSE_SYS_DATA_PART1_5 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fifth 32 bits of the first part of system data.
+ */
+#define EFUSE_SYS_DATA_PART1_5    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART1_5_M  (EFUSE_SYS_DATA_PART1_5_V << EFUSE_SYS_DATA_PART1_5_S)
+#define EFUSE_SYS_DATA_PART1_5_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART1_5_S  0
+
+/** EFUSE_RD_SYS_PART1_DATA6_REG register
+ *  Register $n of BLOCK2 (system).
+ */
+#define EFUSE_RD_SYS_PART1_DATA6_REG (DR_REG_EFUSE_BASE + 0x74)
+/** EFUSE_SYS_DATA_PART1_6 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the sixth 32 bits of the first part of system data.
+ */
+#define EFUSE_SYS_DATA_PART1_6    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART1_6_M  (EFUSE_SYS_DATA_PART1_6_V << EFUSE_SYS_DATA_PART1_6_S)
+#define EFUSE_SYS_DATA_PART1_6_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART1_6_S  0
+
+/** EFUSE_RD_SYS_PART1_DATA7_REG register
+ *  Register $n of BLOCK2 (system).
+ */
+#define EFUSE_RD_SYS_PART1_DATA7_REG (DR_REG_EFUSE_BASE + 0x78)
+/** EFUSE_SYS_DATA_PART1_7 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the seventh 32 bits of the first part of system data.
+ */
+#define EFUSE_SYS_DATA_PART1_7    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART1_7_M  (EFUSE_SYS_DATA_PART1_7_V << EFUSE_SYS_DATA_PART1_7_S)
+#define EFUSE_SYS_DATA_PART1_7_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART1_7_S  0
+
+/** EFUSE_RD_USR_DATA0_REG register
+ *  Register $n of BLOCK3 (user).
+ */
+#define EFUSE_RD_USR_DATA0_REG (DR_REG_EFUSE_BASE + 0x7c)
+/** EFUSE_USR_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the zeroth 32 bits of BLOCK3 (user).
+ */
+#define EFUSE_USR_DATA0    0xFFFFFFFFU
+#define EFUSE_USR_DATA0_M  (EFUSE_USR_DATA0_V << EFUSE_USR_DATA0_S)
+#define EFUSE_USR_DATA0_V  0xFFFFFFFFU
+#define EFUSE_USR_DATA0_S  0
+
+/** EFUSE_RD_USR_DATA1_REG register
+ *  Register $n of BLOCK3 (user).
+ */
+#define EFUSE_RD_USR_DATA1_REG (DR_REG_EFUSE_BASE + 0x80)
+/** EFUSE_USR_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the first 32 bits of BLOCK3 (user).
+ */
+#define EFUSE_USR_DATA1    0xFFFFFFFFU
+#define EFUSE_USR_DATA1_M  (EFUSE_USR_DATA1_V << EFUSE_USR_DATA1_S)
+#define EFUSE_USR_DATA1_V  0xFFFFFFFFU
+#define EFUSE_USR_DATA1_S  0
+
+/** EFUSE_RD_USR_DATA2_REG register
+ *  Register $n of BLOCK3 (user).
+ */
+#define EFUSE_RD_USR_DATA2_REG (DR_REG_EFUSE_BASE + 0x84)
+/** EFUSE_USR_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the second 32 bits of BLOCK3 (user).
+ */
+#define EFUSE_USR_DATA2    0xFFFFFFFFU
+#define EFUSE_USR_DATA2_M  (EFUSE_USR_DATA2_V << EFUSE_USR_DATA2_S)
+#define EFUSE_USR_DATA2_V  0xFFFFFFFFU
+#define EFUSE_USR_DATA2_S  0
+
+/** EFUSE_RD_USR_DATA3_REG register
+ *  Register $n of BLOCK3 (user).
+ */
+#define EFUSE_RD_USR_DATA3_REG (DR_REG_EFUSE_BASE + 0x88)
+/** EFUSE_USR_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the third 32 bits of BLOCK3 (user).
+ */
+#define EFUSE_USR_DATA3    0xFFFFFFFFU
+#define EFUSE_USR_DATA3_M  (EFUSE_USR_DATA3_V << EFUSE_USR_DATA3_S)
+#define EFUSE_USR_DATA3_V  0xFFFFFFFFU
+#define EFUSE_USR_DATA3_S  0
+
+/** EFUSE_RD_USR_DATA4_REG register
+ *  Register $n of BLOCK3 (user).
+ */
+#define EFUSE_RD_USR_DATA4_REG (DR_REG_EFUSE_BASE + 0x8c)
+/** EFUSE_USR_DATA4 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fourth 32 bits of BLOCK3 (user).
+ */
+#define EFUSE_USR_DATA4    0xFFFFFFFFU
+#define EFUSE_USR_DATA4_M  (EFUSE_USR_DATA4_V << EFUSE_USR_DATA4_S)
+#define EFUSE_USR_DATA4_V  0xFFFFFFFFU
+#define EFUSE_USR_DATA4_S  0
+
+/** EFUSE_RD_USR_DATA5_REG register
+ *  Register $n of BLOCK3 (user).
+ */
+#define EFUSE_RD_USR_DATA5_REG (DR_REG_EFUSE_BASE + 0x90)
+/** EFUSE_USR_DATA5 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fifth 32 bits of BLOCK3 (user).
+ */
+#define EFUSE_USR_DATA5    0xFFFFFFFFU
+#define EFUSE_USR_DATA5_M  (EFUSE_USR_DATA5_V << EFUSE_USR_DATA5_S)
+#define EFUSE_USR_DATA5_V  0xFFFFFFFFU
+#define EFUSE_USR_DATA5_S  0
+
+/** EFUSE_RD_USR_DATA6_REG register
+ *  Register $n of BLOCK3 (user).
+ */
+#define EFUSE_RD_USR_DATA6_REG (DR_REG_EFUSE_BASE + 0x94)
+/** EFUSE_USR_DATA6 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the sixth 32 bits of BLOCK3 (user).
+ */
+#define EFUSE_USR_DATA6    0xFFFFFFFFU
+#define EFUSE_USR_DATA6_M  (EFUSE_USR_DATA6_V << EFUSE_USR_DATA6_S)
+#define EFUSE_USR_DATA6_V  0xFFFFFFFFU
+#define EFUSE_USR_DATA6_S  0
+
+/** EFUSE_RD_USR_DATA7_REG register
+ *  Register $n of BLOCK3 (user).
+ */
+#define EFUSE_RD_USR_DATA7_REG (DR_REG_EFUSE_BASE + 0x98)
+/** EFUSE_USR_DATA7 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the seventh 32 bits of BLOCK3 (user).
+ */
+#define EFUSE_USR_DATA7    0xFFFFFFFFU
+#define EFUSE_USR_DATA7_M  (EFUSE_USR_DATA7_V << EFUSE_USR_DATA7_S)
+#define EFUSE_USR_DATA7_V  0xFFFFFFFFU
+#define EFUSE_USR_DATA7_S  0
+
+/** EFUSE_RD_KEY0_DATA0_REG register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+#define EFUSE_RD_KEY0_DATA0_REG (DR_REG_EFUSE_BASE + 0x9c)
+/** EFUSE_KEY0_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the zeroth 32 bits of KEY0.
+ */
+#define EFUSE_KEY0_DATA0    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA0_M  (EFUSE_KEY0_DATA0_V << EFUSE_KEY0_DATA0_S)
+#define EFUSE_KEY0_DATA0_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA0_S  0
+
+/** EFUSE_RD_KEY0_DATA1_REG register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+#define EFUSE_RD_KEY0_DATA1_REG (DR_REG_EFUSE_BASE + 0xa0)
+/** EFUSE_KEY0_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the first 32 bits of KEY0.
+ */
+#define EFUSE_KEY0_DATA1    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA1_M  (EFUSE_KEY0_DATA1_V << EFUSE_KEY0_DATA1_S)
+#define EFUSE_KEY0_DATA1_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA1_S  0
+
+/** EFUSE_RD_KEY0_DATA2_REG register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+#define EFUSE_RD_KEY0_DATA2_REG (DR_REG_EFUSE_BASE + 0xa4)
+/** EFUSE_KEY0_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the second 32 bits of KEY0.
+ */
+#define EFUSE_KEY0_DATA2    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA2_M  (EFUSE_KEY0_DATA2_V << EFUSE_KEY0_DATA2_S)
+#define EFUSE_KEY0_DATA2_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA2_S  0
+
+/** EFUSE_RD_KEY0_DATA3_REG register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+#define EFUSE_RD_KEY0_DATA3_REG (DR_REG_EFUSE_BASE + 0xa8)
+/** EFUSE_KEY0_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the third 32 bits of KEY0.
+ */
+#define EFUSE_KEY0_DATA3    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA3_M  (EFUSE_KEY0_DATA3_V << EFUSE_KEY0_DATA3_S)
+#define EFUSE_KEY0_DATA3_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA3_S  0
+
+/** EFUSE_RD_KEY0_DATA4_REG register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+#define EFUSE_RD_KEY0_DATA4_REG (DR_REG_EFUSE_BASE + 0xac)
+/** EFUSE_KEY0_DATA4 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fourth 32 bits of KEY0.
+ */
+#define EFUSE_KEY0_DATA4    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA4_M  (EFUSE_KEY0_DATA4_V << EFUSE_KEY0_DATA4_S)
+#define EFUSE_KEY0_DATA4_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA4_S  0
+
+/** EFUSE_RD_KEY0_DATA5_REG register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+#define EFUSE_RD_KEY0_DATA5_REG (DR_REG_EFUSE_BASE + 0xb0)
+/** EFUSE_KEY0_DATA5 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fifth 32 bits of KEY0.
+ */
+#define EFUSE_KEY0_DATA5    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA5_M  (EFUSE_KEY0_DATA5_V << EFUSE_KEY0_DATA5_S)
+#define EFUSE_KEY0_DATA5_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA5_S  0
+
+/** EFUSE_RD_KEY0_DATA6_REG register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+#define EFUSE_RD_KEY0_DATA6_REG (DR_REG_EFUSE_BASE + 0xb4)
+/** EFUSE_KEY0_DATA6 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the sixth 32 bits of KEY0.
+ */
+#define EFUSE_KEY0_DATA6    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA6_M  (EFUSE_KEY0_DATA6_V << EFUSE_KEY0_DATA6_S)
+#define EFUSE_KEY0_DATA6_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA6_S  0
+
+/** EFUSE_RD_KEY0_DATA7_REG register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+#define EFUSE_RD_KEY0_DATA7_REG (DR_REG_EFUSE_BASE + 0xb8)
+/** EFUSE_KEY0_DATA7 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the seventh 32 bits of KEY0.
+ */
+#define EFUSE_KEY0_DATA7    0xFFFFFFFFU
+#define EFUSE_KEY0_DATA7_M  (EFUSE_KEY0_DATA7_V << EFUSE_KEY0_DATA7_S)
+#define EFUSE_KEY0_DATA7_V  0xFFFFFFFFU
+#define EFUSE_KEY0_DATA7_S  0
+
+/** EFUSE_RD_KEY1_DATA0_REG register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+#define EFUSE_RD_KEY1_DATA0_REG (DR_REG_EFUSE_BASE + 0xbc)
+/** EFUSE_KEY1_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the zeroth 32 bits of KEY1.
+ */
+#define EFUSE_KEY1_DATA0    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA0_M  (EFUSE_KEY1_DATA0_V << EFUSE_KEY1_DATA0_S)
+#define EFUSE_KEY1_DATA0_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA0_S  0
+
+/** EFUSE_RD_KEY1_DATA1_REG register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+#define EFUSE_RD_KEY1_DATA1_REG (DR_REG_EFUSE_BASE + 0xc0)
+/** EFUSE_KEY1_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the first 32 bits of KEY1.
+ */
+#define EFUSE_KEY1_DATA1    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA1_M  (EFUSE_KEY1_DATA1_V << EFUSE_KEY1_DATA1_S)
+#define EFUSE_KEY1_DATA1_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA1_S  0
+
+/** EFUSE_RD_KEY1_DATA2_REG register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+#define EFUSE_RD_KEY1_DATA2_REG (DR_REG_EFUSE_BASE + 0xc4)
+/** EFUSE_KEY1_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the second 32 bits of KEY1.
+ */
+#define EFUSE_KEY1_DATA2    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA2_M  (EFUSE_KEY1_DATA2_V << EFUSE_KEY1_DATA2_S)
+#define EFUSE_KEY1_DATA2_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA2_S  0
+
+/** EFUSE_RD_KEY1_DATA3_REG register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+#define EFUSE_RD_KEY1_DATA3_REG (DR_REG_EFUSE_BASE + 0xc8)
+/** EFUSE_KEY1_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the third 32 bits of KEY1.
+ */
+#define EFUSE_KEY1_DATA3    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA3_M  (EFUSE_KEY1_DATA3_V << EFUSE_KEY1_DATA3_S)
+#define EFUSE_KEY1_DATA3_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA3_S  0
+
+/** EFUSE_RD_KEY1_DATA4_REG register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+#define EFUSE_RD_KEY1_DATA4_REG (DR_REG_EFUSE_BASE + 0xcc)
+/** EFUSE_KEY1_DATA4 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fourth 32 bits of KEY1.
+ */
+#define EFUSE_KEY1_DATA4    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA4_M  (EFUSE_KEY1_DATA4_V << EFUSE_KEY1_DATA4_S)
+#define EFUSE_KEY1_DATA4_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA4_S  0
+
+/** EFUSE_RD_KEY1_DATA5_REG register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+#define EFUSE_RD_KEY1_DATA5_REG (DR_REG_EFUSE_BASE + 0xd0)
+/** EFUSE_KEY1_DATA5 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fifth 32 bits of KEY1.
+ */
+#define EFUSE_KEY1_DATA5    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA5_M  (EFUSE_KEY1_DATA5_V << EFUSE_KEY1_DATA5_S)
+#define EFUSE_KEY1_DATA5_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA5_S  0
+
+/** EFUSE_RD_KEY1_DATA6_REG register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+#define EFUSE_RD_KEY1_DATA6_REG (DR_REG_EFUSE_BASE + 0xd4)
+/** EFUSE_KEY1_DATA6 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the sixth 32 bits of KEY1.
+ */
+#define EFUSE_KEY1_DATA6    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA6_M  (EFUSE_KEY1_DATA6_V << EFUSE_KEY1_DATA6_S)
+#define EFUSE_KEY1_DATA6_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA6_S  0
+
+/** EFUSE_RD_KEY1_DATA7_REG register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+#define EFUSE_RD_KEY1_DATA7_REG (DR_REG_EFUSE_BASE + 0xd8)
+/** EFUSE_KEY1_DATA7 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the seventh 32 bits of KEY1.
+ */
+#define EFUSE_KEY1_DATA7    0xFFFFFFFFU
+#define EFUSE_KEY1_DATA7_M  (EFUSE_KEY1_DATA7_V << EFUSE_KEY1_DATA7_S)
+#define EFUSE_KEY1_DATA7_V  0xFFFFFFFFU
+#define EFUSE_KEY1_DATA7_S  0
+
+/** EFUSE_RD_KEY2_DATA0_REG register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+#define EFUSE_RD_KEY2_DATA0_REG (DR_REG_EFUSE_BASE + 0xdc)
+/** EFUSE_KEY2_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the zeroth 32 bits of KEY2.
+ */
+#define EFUSE_KEY2_DATA0    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA0_M  (EFUSE_KEY2_DATA0_V << EFUSE_KEY2_DATA0_S)
+#define EFUSE_KEY2_DATA0_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA0_S  0
+
+/** EFUSE_RD_KEY2_DATA1_REG register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+#define EFUSE_RD_KEY2_DATA1_REG (DR_REG_EFUSE_BASE + 0xe0)
+/** EFUSE_KEY2_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the first 32 bits of KEY2.
+ */
+#define EFUSE_KEY2_DATA1    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA1_M  (EFUSE_KEY2_DATA1_V << EFUSE_KEY2_DATA1_S)
+#define EFUSE_KEY2_DATA1_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA1_S  0
+
+/** EFUSE_RD_KEY2_DATA2_REG register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+#define EFUSE_RD_KEY2_DATA2_REG (DR_REG_EFUSE_BASE + 0xe4)
+/** EFUSE_KEY2_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the second 32 bits of KEY2.
+ */
+#define EFUSE_KEY2_DATA2    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA2_M  (EFUSE_KEY2_DATA2_V << EFUSE_KEY2_DATA2_S)
+#define EFUSE_KEY2_DATA2_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA2_S  0
+
+/** EFUSE_RD_KEY2_DATA3_REG register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+#define EFUSE_RD_KEY2_DATA3_REG (DR_REG_EFUSE_BASE + 0xe8)
+/** EFUSE_KEY2_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the third 32 bits of KEY2.
+ */
+#define EFUSE_KEY2_DATA3    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA3_M  (EFUSE_KEY2_DATA3_V << EFUSE_KEY2_DATA3_S)
+#define EFUSE_KEY2_DATA3_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA3_S  0
+
+/** EFUSE_RD_KEY2_DATA4_REG register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+#define EFUSE_RD_KEY2_DATA4_REG (DR_REG_EFUSE_BASE + 0xec)
+/** EFUSE_KEY2_DATA4 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fourth 32 bits of KEY2.
+ */
+#define EFUSE_KEY2_DATA4    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA4_M  (EFUSE_KEY2_DATA4_V << EFUSE_KEY2_DATA4_S)
+#define EFUSE_KEY2_DATA4_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA4_S  0
+
+/** EFUSE_RD_KEY2_DATA5_REG register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+#define EFUSE_RD_KEY2_DATA5_REG (DR_REG_EFUSE_BASE + 0xf0)
+/** EFUSE_KEY2_DATA5 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fifth 32 bits of KEY2.
+ */
+#define EFUSE_KEY2_DATA5    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA5_M  (EFUSE_KEY2_DATA5_V << EFUSE_KEY2_DATA5_S)
+#define EFUSE_KEY2_DATA5_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA5_S  0
+
+/** EFUSE_RD_KEY2_DATA6_REG register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+#define EFUSE_RD_KEY2_DATA6_REG (DR_REG_EFUSE_BASE + 0xf4)
+/** EFUSE_KEY2_DATA6 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the sixth 32 bits of KEY2.
+ */
+#define EFUSE_KEY2_DATA6    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA6_M  (EFUSE_KEY2_DATA6_V << EFUSE_KEY2_DATA6_S)
+#define EFUSE_KEY2_DATA6_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA6_S  0
+
+/** EFUSE_RD_KEY2_DATA7_REG register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+#define EFUSE_RD_KEY2_DATA7_REG (DR_REG_EFUSE_BASE + 0xf8)
+/** EFUSE_KEY2_DATA7 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the seventh 32 bits of KEY2.
+ */
+#define EFUSE_KEY2_DATA7    0xFFFFFFFFU
+#define EFUSE_KEY2_DATA7_M  (EFUSE_KEY2_DATA7_V << EFUSE_KEY2_DATA7_S)
+#define EFUSE_KEY2_DATA7_V  0xFFFFFFFFU
+#define EFUSE_KEY2_DATA7_S  0
+
+/** EFUSE_RD_KEY3_DATA0_REG register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+#define EFUSE_RD_KEY3_DATA0_REG (DR_REG_EFUSE_BASE + 0xfc)
+/** EFUSE_KEY3_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the zeroth 32 bits of KEY3.
+ */
+#define EFUSE_KEY3_DATA0    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA0_M  (EFUSE_KEY3_DATA0_V << EFUSE_KEY3_DATA0_S)
+#define EFUSE_KEY3_DATA0_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA0_S  0
+
+/** EFUSE_RD_KEY3_DATA1_REG register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+#define EFUSE_RD_KEY3_DATA1_REG (DR_REG_EFUSE_BASE + 0x100)
+/** EFUSE_KEY3_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the first 32 bits of KEY3.
+ */
+#define EFUSE_KEY3_DATA1    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA1_M  (EFUSE_KEY3_DATA1_V << EFUSE_KEY3_DATA1_S)
+#define EFUSE_KEY3_DATA1_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA1_S  0
+
+/** EFUSE_RD_KEY3_DATA2_REG register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+#define EFUSE_RD_KEY3_DATA2_REG (DR_REG_EFUSE_BASE + 0x104)
+/** EFUSE_KEY3_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the second 32 bits of KEY3.
+ */
+#define EFUSE_KEY3_DATA2    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA2_M  (EFUSE_KEY3_DATA2_V << EFUSE_KEY3_DATA2_S)
+#define EFUSE_KEY3_DATA2_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA2_S  0
+
+/** EFUSE_RD_KEY3_DATA3_REG register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+#define EFUSE_RD_KEY3_DATA3_REG (DR_REG_EFUSE_BASE + 0x108)
+/** EFUSE_KEY3_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the third 32 bits of KEY3.
+ */
+#define EFUSE_KEY3_DATA3    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA3_M  (EFUSE_KEY3_DATA3_V << EFUSE_KEY3_DATA3_S)
+#define EFUSE_KEY3_DATA3_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA3_S  0
+
+/** EFUSE_RD_KEY3_DATA4_REG register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+#define EFUSE_RD_KEY3_DATA4_REG (DR_REG_EFUSE_BASE + 0x10c)
+/** EFUSE_KEY3_DATA4 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fourth 32 bits of KEY3.
+ */
+#define EFUSE_KEY3_DATA4    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA4_M  (EFUSE_KEY3_DATA4_V << EFUSE_KEY3_DATA4_S)
+#define EFUSE_KEY3_DATA4_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA4_S  0
+
+/** EFUSE_RD_KEY3_DATA5_REG register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+#define EFUSE_RD_KEY3_DATA5_REG (DR_REG_EFUSE_BASE + 0x110)
+/** EFUSE_KEY3_DATA5 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fifth 32 bits of KEY3.
+ */
+#define EFUSE_KEY3_DATA5    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA5_M  (EFUSE_KEY3_DATA5_V << EFUSE_KEY3_DATA5_S)
+#define EFUSE_KEY3_DATA5_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA5_S  0
+
+/** EFUSE_RD_KEY3_DATA6_REG register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+#define EFUSE_RD_KEY3_DATA6_REG (DR_REG_EFUSE_BASE + 0x114)
+/** EFUSE_KEY3_DATA6 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the sixth 32 bits of KEY3.
+ */
+#define EFUSE_KEY3_DATA6    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA6_M  (EFUSE_KEY3_DATA6_V << EFUSE_KEY3_DATA6_S)
+#define EFUSE_KEY3_DATA6_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA6_S  0
+
+/** EFUSE_RD_KEY3_DATA7_REG register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+#define EFUSE_RD_KEY3_DATA7_REG (DR_REG_EFUSE_BASE + 0x118)
+/** EFUSE_KEY3_DATA7 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the seventh 32 bits of KEY3.
+ */
+#define EFUSE_KEY3_DATA7    0xFFFFFFFFU
+#define EFUSE_KEY3_DATA7_M  (EFUSE_KEY3_DATA7_V << EFUSE_KEY3_DATA7_S)
+#define EFUSE_KEY3_DATA7_V  0xFFFFFFFFU
+#define EFUSE_KEY3_DATA7_S  0
+
+/** EFUSE_RD_KEY4_DATA0_REG register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+#define EFUSE_RD_KEY4_DATA0_REG (DR_REG_EFUSE_BASE + 0x11c)
+/** EFUSE_KEY4_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the zeroth 32 bits of KEY4.
+ */
+#define EFUSE_KEY4_DATA0    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA0_M  (EFUSE_KEY4_DATA0_V << EFUSE_KEY4_DATA0_S)
+#define EFUSE_KEY4_DATA0_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA0_S  0
+
+/** EFUSE_RD_KEY4_DATA1_REG register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+#define EFUSE_RD_KEY4_DATA1_REG (DR_REG_EFUSE_BASE + 0x120)
+/** EFUSE_KEY4_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the first 32 bits of KEY4.
+ */
+#define EFUSE_KEY4_DATA1    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA1_M  (EFUSE_KEY4_DATA1_V << EFUSE_KEY4_DATA1_S)
+#define EFUSE_KEY4_DATA1_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA1_S  0
+
+/** EFUSE_RD_KEY4_DATA2_REG register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+#define EFUSE_RD_KEY4_DATA2_REG (DR_REG_EFUSE_BASE + 0x124)
+/** EFUSE_KEY4_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the second 32 bits of KEY4.
+ */
+#define EFUSE_KEY4_DATA2    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA2_M  (EFUSE_KEY4_DATA2_V << EFUSE_KEY4_DATA2_S)
+#define EFUSE_KEY4_DATA2_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA2_S  0
+
+/** EFUSE_RD_KEY4_DATA3_REG register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+#define EFUSE_RD_KEY4_DATA3_REG (DR_REG_EFUSE_BASE + 0x128)
+/** EFUSE_KEY4_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the third 32 bits of KEY4.
+ */
+#define EFUSE_KEY4_DATA3    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA3_M  (EFUSE_KEY4_DATA3_V << EFUSE_KEY4_DATA3_S)
+#define EFUSE_KEY4_DATA3_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA3_S  0
+
+/** EFUSE_RD_KEY4_DATA4_REG register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+#define EFUSE_RD_KEY4_DATA4_REG (DR_REG_EFUSE_BASE + 0x12c)
+/** EFUSE_KEY4_DATA4 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fourth 32 bits of KEY4.
+ */
+#define EFUSE_KEY4_DATA4    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA4_M  (EFUSE_KEY4_DATA4_V << EFUSE_KEY4_DATA4_S)
+#define EFUSE_KEY4_DATA4_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA4_S  0
+
+/** EFUSE_RD_KEY4_DATA5_REG register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+#define EFUSE_RD_KEY4_DATA5_REG (DR_REG_EFUSE_BASE + 0x130)
+/** EFUSE_KEY4_DATA5 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fifth 32 bits of KEY4.
+ */
+#define EFUSE_KEY4_DATA5    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA5_M  (EFUSE_KEY4_DATA5_V << EFUSE_KEY4_DATA5_S)
+#define EFUSE_KEY4_DATA5_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA5_S  0
+
+/** EFUSE_RD_KEY4_DATA6_REG register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+#define EFUSE_RD_KEY4_DATA6_REG (DR_REG_EFUSE_BASE + 0x134)
+/** EFUSE_KEY4_DATA6 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the sixth 32 bits of KEY4.
+ */
+#define EFUSE_KEY4_DATA6    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA6_M  (EFUSE_KEY4_DATA6_V << EFUSE_KEY4_DATA6_S)
+#define EFUSE_KEY4_DATA6_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA6_S  0
+
+/** EFUSE_RD_KEY4_DATA7_REG register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+#define EFUSE_RD_KEY4_DATA7_REG (DR_REG_EFUSE_BASE + 0x138)
+/** EFUSE_KEY4_DATA7 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the seventh 32 bits of KEY4.
+ */
+#define EFUSE_KEY4_DATA7    0xFFFFFFFFU
+#define EFUSE_KEY4_DATA7_M  (EFUSE_KEY4_DATA7_V << EFUSE_KEY4_DATA7_S)
+#define EFUSE_KEY4_DATA7_V  0xFFFFFFFFU
+#define EFUSE_KEY4_DATA7_S  0
+
+/** EFUSE_RD_KEY5_DATA0_REG register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+#define EFUSE_RD_KEY5_DATA0_REG (DR_REG_EFUSE_BASE + 0x13c)
+/** EFUSE_KEY5_DATA0 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the zeroth 32 bits of KEY5.
+ */
+#define EFUSE_KEY5_DATA0    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA0_M  (EFUSE_KEY5_DATA0_V << EFUSE_KEY5_DATA0_S)
+#define EFUSE_KEY5_DATA0_V  0xFFFFFFFFU
+#define EFUSE_KEY5_DATA0_S  0
+
+/** EFUSE_RD_KEY5_DATA1_REG register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+#define EFUSE_RD_KEY5_DATA1_REG (DR_REG_EFUSE_BASE + 0x140)
+/** EFUSE_KEY5_DATA1 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the first 32 bits of KEY5.
+ */
+#define EFUSE_KEY5_DATA1    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA1_M  (EFUSE_KEY5_DATA1_V << EFUSE_KEY5_DATA1_S)
+#define EFUSE_KEY5_DATA1_V  0xFFFFFFFFU
+#define EFUSE_KEY5_DATA1_S  0
+
+/** EFUSE_RD_KEY5_DATA2_REG register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+#define EFUSE_RD_KEY5_DATA2_REG (DR_REG_EFUSE_BASE + 0x144)
+/** EFUSE_KEY5_DATA2 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the second 32 bits of KEY5.
+ */
+#define EFUSE_KEY5_DATA2    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA2_M  (EFUSE_KEY5_DATA2_V << EFUSE_KEY5_DATA2_S)
+#define EFUSE_KEY5_DATA2_V  0xFFFFFFFFU
+#define EFUSE_KEY5_DATA2_S  0
+
+/** EFUSE_RD_KEY5_DATA3_REG register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+#define EFUSE_RD_KEY5_DATA3_REG (DR_REG_EFUSE_BASE + 0x148)
+/** EFUSE_KEY5_DATA3 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the third 32 bits of KEY5.
+ */
+#define EFUSE_KEY5_DATA3    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA3_M  (EFUSE_KEY5_DATA3_V << EFUSE_KEY5_DATA3_S)
+#define EFUSE_KEY5_DATA3_V  0xFFFFFFFFU
+#define EFUSE_KEY5_DATA3_S  0
+
+/** EFUSE_RD_KEY5_DATA4_REG register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+#define EFUSE_RD_KEY5_DATA4_REG (DR_REG_EFUSE_BASE + 0x14c)
+/** EFUSE_KEY5_DATA4 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fourth 32 bits of KEY5.
+ */
+#define EFUSE_KEY5_DATA4    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA4_M  (EFUSE_KEY5_DATA4_V << EFUSE_KEY5_DATA4_S)
+#define EFUSE_KEY5_DATA4_V  0xFFFFFFFFU
+#define EFUSE_KEY5_DATA4_S  0
+
+/** EFUSE_RD_KEY5_DATA5_REG register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+#define EFUSE_RD_KEY5_DATA5_REG (DR_REG_EFUSE_BASE + 0x150)
+/** EFUSE_KEY5_DATA5 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the fifth 32 bits of KEY5.
+ */
+#define EFUSE_KEY5_DATA5    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA5_M  (EFUSE_KEY5_DATA5_V << EFUSE_KEY5_DATA5_S)
+#define EFUSE_KEY5_DATA5_V  0xFFFFFFFFU
+#define EFUSE_KEY5_DATA5_S  0
+
+/** EFUSE_RD_KEY5_DATA6_REG register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+#define EFUSE_RD_KEY5_DATA6_REG (DR_REG_EFUSE_BASE + 0x154)
+/** EFUSE_KEY5_DATA6 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the sixth 32 bits of KEY5.
+ */
+#define EFUSE_KEY5_DATA6    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA6_M  (EFUSE_KEY5_DATA6_V << EFUSE_KEY5_DATA6_S)
+#define EFUSE_KEY5_DATA6_V  0xFFFFFFFFU
+#define EFUSE_KEY5_DATA6_S  0
+
+/** EFUSE_RD_KEY5_DATA7_REG register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+#define EFUSE_RD_KEY5_DATA7_REG (DR_REG_EFUSE_BASE + 0x158)
+/** EFUSE_KEY5_DATA7 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the seventh 32 bits of KEY5.
+ */
+#define EFUSE_KEY5_DATA7    0xFFFFFFFFU
+#define EFUSE_KEY5_DATA7_M  (EFUSE_KEY5_DATA7_V << EFUSE_KEY5_DATA7_S)
+#define EFUSE_KEY5_DATA7_V  0xFFFFFFFFU
+#define EFUSE_KEY5_DATA7_S  0
+
+/** EFUSE_RD_SYS_PART2_DATA0_REG register
+ *  Register $n of BLOCK10 (system).
+ */
+#define EFUSE_RD_SYS_PART2_DATA0_REG (DR_REG_EFUSE_BASE + 0x15c)
+/** EFUSE_SYS_DATA_PART2_0 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the $nth 32 bits of the 2nd part of system data.
+ */
+#define EFUSE_SYS_DATA_PART2_0    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_0_M  (EFUSE_SYS_DATA_PART2_0_V << EFUSE_SYS_DATA_PART2_0_S)
+#define EFUSE_SYS_DATA_PART2_0_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_0_S  0
+
+/** EFUSE_RD_SYS_PART2_DATA1_REG register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+#define EFUSE_RD_SYS_PART2_DATA1_REG (DR_REG_EFUSE_BASE + 0x160)
+/** EFUSE_SYS_DATA_PART2_1 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the $nth 32 bits of the 2nd part of system data.
+ */
+#define EFUSE_SYS_DATA_PART2_1    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_1_M  (EFUSE_SYS_DATA_PART2_1_V << EFUSE_SYS_DATA_PART2_1_S)
+#define EFUSE_SYS_DATA_PART2_1_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_1_S  0
+
+/** EFUSE_RD_SYS_PART2_DATA2_REG register
+ *  Register $n of BLOCK10 (system).
+ */
+#define EFUSE_RD_SYS_PART2_DATA2_REG (DR_REG_EFUSE_BASE + 0x164)
+/** EFUSE_SYS_DATA_PART2_2 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the $nth 32 bits of the 2nd part of system data.
+ */
+#define EFUSE_SYS_DATA_PART2_2    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_2_M  (EFUSE_SYS_DATA_PART2_2_V << EFUSE_SYS_DATA_PART2_2_S)
+#define EFUSE_SYS_DATA_PART2_2_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_2_S  0
+
+/** EFUSE_RD_SYS_PART2_DATA3_REG register
+ *  Register $n of BLOCK10 (system).
+ */
+#define EFUSE_RD_SYS_PART2_DATA3_REG (DR_REG_EFUSE_BASE + 0x168)
+/** EFUSE_SYS_DATA_PART2_3 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the $nth 32 bits of the 2nd part of system data.
+ */
+#define EFUSE_SYS_DATA_PART2_3    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_3_M  (EFUSE_SYS_DATA_PART2_3_V << EFUSE_SYS_DATA_PART2_3_S)
+#define EFUSE_SYS_DATA_PART2_3_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_3_S  0
+
+/** EFUSE_RD_SYS_PART2_DATA4_REG register
+ *  Register $n of BLOCK10 (system).
+ */
+#define EFUSE_RD_SYS_PART2_DATA4_REG (DR_REG_EFUSE_BASE + 0x16c)
+/** EFUSE_SYS_DATA_PART2_4 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the $nth 32 bits of the 2nd part of system data.
+ */
+#define EFUSE_SYS_DATA_PART2_4    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_4_M  (EFUSE_SYS_DATA_PART2_4_V << EFUSE_SYS_DATA_PART2_4_S)
+#define EFUSE_SYS_DATA_PART2_4_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_4_S  0
+
+/** EFUSE_RD_SYS_PART2_DATA5_REG register
+ *  Register $n of BLOCK10 (system).
+ */
+#define EFUSE_RD_SYS_PART2_DATA5_REG (DR_REG_EFUSE_BASE + 0x170)
+/** EFUSE_SYS_DATA_PART2_5 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the $nth 32 bits of the 2nd part of system data.
+ */
+#define EFUSE_SYS_DATA_PART2_5    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_5_M  (EFUSE_SYS_DATA_PART2_5_V << EFUSE_SYS_DATA_PART2_5_S)
+#define EFUSE_SYS_DATA_PART2_5_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_5_S  0
+
+/** EFUSE_RD_SYS_PART2_DATA6_REG register
+ *  Register $n of BLOCK10 (system).
+ */
+#define EFUSE_RD_SYS_PART2_DATA6_REG (DR_REG_EFUSE_BASE + 0x174)
+/** EFUSE_SYS_DATA_PART2_6 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the $nth 32 bits of the 2nd part of system data.
+ */
+#define EFUSE_SYS_DATA_PART2_6    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_6_M  (EFUSE_SYS_DATA_PART2_6_V << EFUSE_SYS_DATA_PART2_6_S)
+#define EFUSE_SYS_DATA_PART2_6_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_6_S  0
+
+/** EFUSE_RD_SYS_PART2_DATA7_REG register
+ *  Register $n of BLOCK10 (system).
+ */
+#define EFUSE_RD_SYS_PART2_DATA7_REG (DR_REG_EFUSE_BASE + 0x178)
+/** EFUSE_SYS_DATA_PART2_7 : RO; bitpos: [31:0]; default: 0;
+ *  Stores the $nth 32 bits of the 2nd part of system data.
+ */
+#define EFUSE_SYS_DATA_PART2_7    0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_7_M  (EFUSE_SYS_DATA_PART2_7_V << EFUSE_SYS_DATA_PART2_7_S)
+#define EFUSE_SYS_DATA_PART2_7_V  0xFFFFFFFFU
+#define EFUSE_SYS_DATA_PART2_7_S  0
+
+/** EFUSE_RD_REPEAT_ERR0_REG register
+ *  Programming error record register 0 of BLOCK0.
+ */
+#define EFUSE_RD_REPEAT_ERR0_REG (DR_REG_EFUSE_BASE + 0x17c)
+/** EFUSE_RD_DIS_ERR : RO; bitpos: [6:0]; default: 0;
+ *  If any bit in RD_DIS is 1, then it indicates a programming error.
+ */
+#define EFUSE_RD_DIS_ERR    0x0000007FU
+#define EFUSE_RD_DIS_ERR_M  (EFUSE_RD_DIS_ERR_V << EFUSE_RD_DIS_ERR_S)
+#define EFUSE_RD_DIS_ERR_V  0x0000007FU
+#define EFUSE_RD_DIS_ERR_S  0
+/** EFUSE_DIS_RTC_RAM_BOOT_ERR : RO; bitpos: [7]; default: 0;
+ *  If DIS_RTC_RAM_BOOT is 1, then it indicates a programming error.
+ */
+#define EFUSE_DIS_RTC_RAM_BOOT_ERR    (BIT(7))
+#define EFUSE_DIS_RTC_RAM_BOOT_ERR_M  (EFUSE_DIS_RTC_RAM_BOOT_ERR_V << EFUSE_DIS_RTC_RAM_BOOT_ERR_S)
+#define EFUSE_DIS_RTC_RAM_BOOT_ERR_V  0x00000001U
+#define EFUSE_DIS_RTC_RAM_BOOT_ERR_S  7
+/** EFUSE_DIS_ICACHE_ERR : RO; bitpos: [8]; default: 0;
+ *  If DIS_ICACHE is 1, then it indicates a programming error.
+ */
+#define EFUSE_DIS_ICACHE_ERR    (BIT(8))
+#define EFUSE_DIS_ICACHE_ERR_M  (EFUSE_DIS_ICACHE_ERR_V << EFUSE_DIS_ICACHE_ERR_S)
+#define EFUSE_DIS_ICACHE_ERR_V  0x00000001U
+#define EFUSE_DIS_ICACHE_ERR_S  8
+/** EFUSE_DIS_USB_JTAG_ERR : RO; bitpos: [9]; default: 0;
+ *  If DIS_USB_JTAG is 1, then it indicates a programming error.
+ */
+#define EFUSE_DIS_USB_JTAG_ERR    (BIT(9))
+#define EFUSE_DIS_USB_JTAG_ERR_M  (EFUSE_DIS_USB_JTAG_ERR_V << EFUSE_DIS_USB_JTAG_ERR_S)
+#define EFUSE_DIS_USB_JTAG_ERR_V  0x00000001U
+#define EFUSE_DIS_USB_JTAG_ERR_S  9
+/** EFUSE_DIS_DOWNLOAD_ICACHE_ERR : RO; bitpos: [10]; default: 0;
+ *  If DIS_DOWNLOAD_ICACHE is 1, then it indicates a programming error.
+ */
+#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR    (BIT(10))
+#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_M  (EFUSE_DIS_DOWNLOAD_ICACHE_ERR_V << EFUSE_DIS_DOWNLOAD_ICACHE_ERR_S)
+#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_V  0x00000001U
+#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_S  10
+/** EFUSE_DIS_USB_DEVICE_ERR : RO; bitpos: [11]; default: 0;
+ *  If DIS_USB_DEVICE is 1, then it indicates a programming error.
+ */
+#define EFUSE_DIS_USB_DEVICE_ERR    (BIT(11))
+#define EFUSE_DIS_USB_DEVICE_ERR_M  (EFUSE_DIS_USB_DEVICE_ERR_V << EFUSE_DIS_USB_DEVICE_ERR_S)
+#define EFUSE_DIS_USB_DEVICE_ERR_V  0x00000001U
+#define EFUSE_DIS_USB_DEVICE_ERR_S  11
+/** EFUSE_DIS_FORCE_DOWNLOAD_ERR : RO; bitpos: [12]; default: 0;
+ *  If DIS_FORCE_DOWNLOAD is 1, then it indicates a programming error.
+ */
+#define EFUSE_DIS_FORCE_DOWNLOAD_ERR    (BIT(12))
+#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_M  (EFUSE_DIS_FORCE_DOWNLOAD_ERR_V << EFUSE_DIS_FORCE_DOWNLOAD_ERR_S)
+#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_V  0x00000001U
+#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_S  12
+/** EFUSE_DIS_USB_ERR : RO; bitpos: [13]; default: 0;
+ *  If DIS_USB is 1, then it indicates a programming error.
+ */
+#define EFUSE_DIS_USB_ERR    (BIT(13))
+#define EFUSE_DIS_USB_ERR_M  (EFUSE_DIS_USB_ERR_V << EFUSE_DIS_USB_ERR_S)
+#define EFUSE_DIS_USB_ERR_V  0x00000001U
+#define EFUSE_DIS_USB_ERR_S  13
+/** EFUSE_DIS_TWAI_ERR : RO; bitpos: [14]; default: 0;
+ *  If DIS_TWAI is 1, then it indicates a programming error.
+ */
+#define EFUSE_DIS_TWAI_ERR    (BIT(14))
+#define EFUSE_DIS_TWAI_ERR_M  (EFUSE_DIS_TWAI_ERR_V << EFUSE_DIS_TWAI_ERR_S)
+#define EFUSE_DIS_TWAI_ERR_V  0x00000001U
+#define EFUSE_DIS_TWAI_ERR_S  14
+/** EFUSE_JTAG_SEL_ENABLE_ERR : RO; bitpos: [15]; default: 0;
+ *  If JTAG_SEL_ENABLE is 1, then it indicates a programming error.
+ */
+#define EFUSE_JTAG_SEL_ENABLE_ERR    (BIT(15))
+#define EFUSE_JTAG_SEL_ENABLE_ERR_M  (EFUSE_JTAG_SEL_ENABLE_ERR_V << EFUSE_JTAG_SEL_ENABLE_ERR_S)
+#define EFUSE_JTAG_SEL_ENABLE_ERR_V  0x00000001U
+#define EFUSE_JTAG_SEL_ENABLE_ERR_S  15
+/** EFUSE_SOFT_DIS_JTAG_ERR : RO; bitpos: [18:16]; default: 0;
+ *  If SOFT_DIS_JTAG is 1, then it indicates a programming error.
+ */
+#define EFUSE_SOFT_DIS_JTAG_ERR    0x00000007U
+#define EFUSE_SOFT_DIS_JTAG_ERR_M  (EFUSE_SOFT_DIS_JTAG_ERR_V << EFUSE_SOFT_DIS_JTAG_ERR_S)
+#define EFUSE_SOFT_DIS_JTAG_ERR_V  0x00000007U
+#define EFUSE_SOFT_DIS_JTAG_ERR_S  16
+/** EFUSE_DIS_PAD_JTAG_ERR : RO; bitpos: [19]; default: 0;
+ *  If DIS_PAD_JTAG is 1, then it indicates a programming error.
+ */
+#define EFUSE_DIS_PAD_JTAG_ERR    (BIT(19))
+#define EFUSE_DIS_PAD_JTAG_ERR_M  (EFUSE_DIS_PAD_JTAG_ERR_V << EFUSE_DIS_PAD_JTAG_ERR_S)
+#define EFUSE_DIS_PAD_JTAG_ERR_V  0x00000001U
+#define EFUSE_DIS_PAD_JTAG_ERR_S  19
+/** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR : RO; bitpos: [20]; default: 0;
+ *  If DIS_DOWNLOAD_MANUAL_ENCRYPT is 1, then it indicates a programming error.
+ */
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR    (BIT(20))
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_M  (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S)
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V  0x00000001U
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S  20
+/** EFUSE_USB_DREFH_ERR : RO; bitpos: [22:21]; default: 0;
+ *  If any bit in USB_DREFH is 1, then it indicates a programming error.
+ */
+#define EFUSE_USB_DREFH_ERR    0x00000003U
+#define EFUSE_USB_DREFH_ERR_M  (EFUSE_USB_DREFH_ERR_V << EFUSE_USB_DREFH_ERR_S)
+#define EFUSE_USB_DREFH_ERR_V  0x00000003U
+#define EFUSE_USB_DREFH_ERR_S  21
+/** EFUSE_USB_DREFL_ERR : RO; bitpos: [24:23]; default: 0;
+ *  If any bit in USB_DREFL is 1, then it indicates a programming error.
+ */
+#define EFUSE_USB_DREFL_ERR    0x00000003U
+#define EFUSE_USB_DREFL_ERR_M  (EFUSE_USB_DREFL_ERR_V << EFUSE_USB_DREFL_ERR_S)
+#define EFUSE_USB_DREFL_ERR_V  0x00000003U
+#define EFUSE_USB_DREFL_ERR_S  23
+/** EFUSE_USB_EXCHG_PINS_ERR : RO; bitpos: [25]; default: 0;
+ *  If USB_EXCHG_PINS is 1, then it indicates a programming error.
+ */
+#define EFUSE_USB_EXCHG_PINS_ERR    (BIT(25))
+#define EFUSE_USB_EXCHG_PINS_ERR_M  (EFUSE_USB_EXCHG_PINS_ERR_V << EFUSE_USB_EXCHG_PINS_ERR_S)
+#define EFUSE_USB_EXCHG_PINS_ERR_V  0x00000001U
+#define EFUSE_USB_EXCHG_PINS_ERR_S  25
+/** EFUSE_VDD_SPI_AS_GPIO_ERR : RO; bitpos: [26]; default: 0;
+ *  If VDD_SPI_AS_GPIO is 1, then it indicates a programming error.
+ */
+#define EFUSE_VDD_SPI_AS_GPIO_ERR    (BIT(26))
+#define EFUSE_VDD_SPI_AS_GPIO_ERR_M  (EFUSE_VDD_SPI_AS_GPIO_ERR_V << EFUSE_VDD_SPI_AS_GPIO_ERR_S)
+#define EFUSE_VDD_SPI_AS_GPIO_ERR_V  0x00000001U
+#define EFUSE_VDD_SPI_AS_GPIO_ERR_S  26
+/** EFUSE_BTLC_GPIO_ENABLE_ERR : RO; bitpos: [28:27]; default: 0;
+ *  If any bit in BTLC_GPIO_ENABLE is 1, then it indicates a programming error.
+ */
+#define EFUSE_BTLC_GPIO_ENABLE_ERR    0x00000003U
+#define EFUSE_BTLC_GPIO_ENABLE_ERR_M  (EFUSE_BTLC_GPIO_ENABLE_ERR_V << EFUSE_BTLC_GPIO_ENABLE_ERR_S)
+#define EFUSE_BTLC_GPIO_ENABLE_ERR_V  0x00000003U
+#define EFUSE_BTLC_GPIO_ENABLE_ERR_S  27
+/** EFUSE_POWERGLITCH_EN_ERR : RO; bitpos: [29]; default: 0;
+ *  If POWERGLITCH_EN is 1, then it indicates a programming error.
+ */
+#define EFUSE_POWERGLITCH_EN_ERR    (BIT(29))
+#define EFUSE_POWERGLITCH_EN_ERR_M  (EFUSE_POWERGLITCH_EN_ERR_V << EFUSE_POWERGLITCH_EN_ERR_S)
+#define EFUSE_POWERGLITCH_EN_ERR_V  0x00000001U
+#define EFUSE_POWERGLITCH_EN_ERR_S  29
+/** EFUSE_POWER_GLITCH_DSENSE_ERR : RO; bitpos: [31:30]; default: 0;
+ *  If any bit in POWER_GLITCH_DSENSE is 1, then it indicates a programming error.
+ */
+#define EFUSE_POWER_GLITCH_DSENSE_ERR    0x00000003U
+#define EFUSE_POWER_GLITCH_DSENSE_ERR_M  (EFUSE_POWER_GLITCH_DSENSE_ERR_V << EFUSE_POWER_GLITCH_DSENSE_ERR_S)
+#define EFUSE_POWER_GLITCH_DSENSE_ERR_V  0x00000003U
+#define EFUSE_POWER_GLITCH_DSENSE_ERR_S  30
+
+/** EFUSE_RD_REPEAT_ERR1_REG register
+ *  Programming error record register 1 of BLOCK0.
+ */
+#define EFUSE_RD_REPEAT_ERR1_REG (DR_REG_EFUSE_BASE + 0x180)
+/** EFUSE_RPT4_RESERVED2_ERR : RO; bitpos: [15:0]; default: 0;
+ *  Reserved.
+ */
+#define EFUSE_RPT4_RESERVED2_ERR    0x0000FFFFU
+#define EFUSE_RPT4_RESERVED2_ERR_M  (EFUSE_RPT4_RESERVED2_ERR_V << EFUSE_RPT4_RESERVED2_ERR_S)
+#define EFUSE_RPT4_RESERVED2_ERR_V  0x0000FFFFU
+#define EFUSE_RPT4_RESERVED2_ERR_S  0
+/** EFUSE_WDT_DELAY_SEL_ERR : RO; bitpos: [17:16]; default: 0;
+ *  If any bit in WDT_DELAY_SEL is 1, then it indicates a programming error.
+ */
+#define EFUSE_WDT_DELAY_SEL_ERR    0x00000003U
+#define EFUSE_WDT_DELAY_SEL_ERR_M  (EFUSE_WDT_DELAY_SEL_ERR_V << EFUSE_WDT_DELAY_SEL_ERR_S)
+#define EFUSE_WDT_DELAY_SEL_ERR_V  0x00000003U
+#define EFUSE_WDT_DELAY_SEL_ERR_S  16
+/** EFUSE_SPI_BOOT_CRYPT_CNT_ERR : RO; bitpos: [20:18]; default: 0;
+ *  If any bit in SPI_BOOT_CRYPT_CNT is 1, then it indicates a programming error.
+ */
+#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR    0x00000007U
+#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_M  (EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V << EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S)
+#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V  0x00000007U
+#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S  18
+/** EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR : RO; bitpos: [21]; default: 0;
+ *  If SECURE_BOOT_KEY_REVOKE0 is 1, then it indicates a programming error.
+ */
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR    (BIT(21))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_M  (EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S)
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V  0x00000001U
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S  21
+/** EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR : RO; bitpos: [22]; default: 0;
+ *  If SECURE_BOOT_KEY_REVOKE1 is 1, then it indicates a programming error.
+ */
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR    (BIT(22))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_M  (EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S)
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V  0x00000001U
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S  22
+/** EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR : RO; bitpos: [23]; default: 0;
+ *  If SECURE_BOOT_KEY_REVOKE2 is 1, then it indicates a programming error.
+ */
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR    (BIT(23))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_M  (EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S)
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V  0x00000001U
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S  23
+/** EFUSE_KEY_PURPOSE_0_ERR : RO; bitpos: [27:24]; default: 0;
+ *  If any bit in KEY_PURPOSE_0 is 1, then it indicates a programming error.
+ */
+#define EFUSE_KEY_PURPOSE_0_ERR    0x0000000FU
+#define EFUSE_KEY_PURPOSE_0_ERR_M  (EFUSE_KEY_PURPOSE_0_ERR_V << EFUSE_KEY_PURPOSE_0_ERR_S)
+#define EFUSE_KEY_PURPOSE_0_ERR_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_0_ERR_S  24
+/** EFUSE_KEY_PURPOSE_1_ERR : RO; bitpos: [31:28]; default: 0;
+ *  If any bit in KEY_PURPOSE_1 is 1, then it indicates a programming error.
+ */
+#define EFUSE_KEY_PURPOSE_1_ERR    0x0000000FU
+#define EFUSE_KEY_PURPOSE_1_ERR_M  (EFUSE_KEY_PURPOSE_1_ERR_V << EFUSE_KEY_PURPOSE_1_ERR_S)
+#define EFUSE_KEY_PURPOSE_1_ERR_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_1_ERR_S  28
+
+/** EFUSE_RD_REPEAT_ERR2_REG register
+ *  Programming error record register 2 of BLOCK0.
+ */
+#define EFUSE_RD_REPEAT_ERR2_REG (DR_REG_EFUSE_BASE + 0x184)
+/** EFUSE_KEY_PURPOSE_2_ERR : RO; bitpos: [3:0]; default: 0;
+ *  If any bit in KEY_PURPOSE_2 is 1, then it indicates a programming error.
+ */
+#define EFUSE_KEY_PURPOSE_2_ERR    0x0000000FU
+#define EFUSE_KEY_PURPOSE_2_ERR_M  (EFUSE_KEY_PURPOSE_2_ERR_V << EFUSE_KEY_PURPOSE_2_ERR_S)
+#define EFUSE_KEY_PURPOSE_2_ERR_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_2_ERR_S  0
+/** EFUSE_KEY_PURPOSE_3_ERR : RO; bitpos: [7:4]; default: 0;
+ *  If any bit in KEY_PURPOSE_3 is 1, then it indicates a programming error.
+ */
+#define EFUSE_KEY_PURPOSE_3_ERR    0x0000000FU
+#define EFUSE_KEY_PURPOSE_3_ERR_M  (EFUSE_KEY_PURPOSE_3_ERR_V << EFUSE_KEY_PURPOSE_3_ERR_S)
+#define EFUSE_KEY_PURPOSE_3_ERR_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_3_ERR_S  4
+/** EFUSE_KEY_PURPOSE_4_ERR : RO; bitpos: [11:8]; default: 0;
+ *  If any bit in KEY_PURPOSE_4 is 1, then it indicates a programming error.
+ */
+#define EFUSE_KEY_PURPOSE_4_ERR    0x0000000FU
+#define EFUSE_KEY_PURPOSE_4_ERR_M  (EFUSE_KEY_PURPOSE_4_ERR_V << EFUSE_KEY_PURPOSE_4_ERR_S)
+#define EFUSE_KEY_PURPOSE_4_ERR_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_4_ERR_S  8
+/** EFUSE_KEY_PURPOSE_5_ERR : RO; bitpos: [15:12]; default: 0;
+ *  If any bit in KEY_PURPOSE_5 is 1, then it indicates a programming error.
+ */
+#define EFUSE_KEY_PURPOSE_5_ERR    0x0000000FU
+#define EFUSE_KEY_PURPOSE_5_ERR_M  (EFUSE_KEY_PURPOSE_5_ERR_V << EFUSE_KEY_PURPOSE_5_ERR_S)
+#define EFUSE_KEY_PURPOSE_5_ERR_V  0x0000000FU
+#define EFUSE_KEY_PURPOSE_5_ERR_S  12
+/** EFUSE_RPT4_RESERVED3_ERR : RO; bitpos: [19:16]; default: 0;
+ *  Reserved.
+ */
+#define EFUSE_RPT4_RESERVED3_ERR    0x0000000FU
+#define EFUSE_RPT4_RESERVED3_ERR_M  (EFUSE_RPT4_RESERVED3_ERR_V << EFUSE_RPT4_RESERVED3_ERR_S)
+#define EFUSE_RPT4_RESERVED3_ERR_V  0x0000000FU
+#define EFUSE_RPT4_RESERVED3_ERR_S  16
+/** EFUSE_SECURE_BOOT_EN_ERR : RO; bitpos: [20]; default: 0;
+ *  If SECURE_BOOT_EN is 1, then it indicates a programming error.
+ */
+#define EFUSE_SECURE_BOOT_EN_ERR    (BIT(20))
+#define EFUSE_SECURE_BOOT_EN_ERR_M  (EFUSE_SECURE_BOOT_EN_ERR_V << EFUSE_SECURE_BOOT_EN_ERR_S)
+#define EFUSE_SECURE_BOOT_EN_ERR_V  0x00000001U
+#define EFUSE_SECURE_BOOT_EN_ERR_S  20
+/** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR : RO; bitpos: [21]; default: 0;
+ *  If SECURE_BOOT_AGGRESSIVE_REVOKE is 1, then it indicates a programming error.
+ */
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR    (BIT(21))
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_M  (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S)
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V  0x00000001U
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S  21
+/** EFUSE_RPT4_RESERVED0_ERR : RO; bitpos: [27:22]; default: 0;
+ *  Reserved.
+ */
+#define EFUSE_RPT4_RESERVED0_ERR    0x0000003FU
+#define EFUSE_RPT4_RESERVED0_ERR_M  (EFUSE_RPT4_RESERVED0_ERR_V << EFUSE_RPT4_RESERVED0_ERR_S)
+#define EFUSE_RPT4_RESERVED0_ERR_V  0x0000003FU
+#define EFUSE_RPT4_RESERVED0_ERR_S  22
+/** EFUSE_FLASH_TPUW_ERR : RO; bitpos: [31:28]; default: 0;
+ *  If any bit in FLASH_TPUM is 1, then it indicates a programming error.
+ */
+#define EFUSE_FLASH_TPUW_ERR    0x0000000FU
+#define EFUSE_FLASH_TPUW_ERR_M  (EFUSE_FLASH_TPUW_ERR_V << EFUSE_FLASH_TPUW_ERR_S)
+#define EFUSE_FLASH_TPUW_ERR_V  0x0000000FU
+#define EFUSE_FLASH_TPUW_ERR_S  28
+
+/** EFUSE_RD_REPEAT_ERR3_REG register
+ *  Programming error record register 3 of BLOCK0.
+ */
+#define EFUSE_RD_REPEAT_ERR3_REG (DR_REG_EFUSE_BASE + 0x188)
+/** EFUSE_DIS_DOWNLOAD_MODE_ERR : RO; bitpos: [0]; default: 0;
+ *  If DIS_DOWNLOAD_MODE is 1, then it indicates a programming error.
+ */
+#define EFUSE_DIS_DOWNLOAD_MODE_ERR    (BIT(0))
+#define EFUSE_DIS_DOWNLOAD_MODE_ERR_M  (EFUSE_DIS_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_DOWNLOAD_MODE_ERR_S)
+#define EFUSE_DIS_DOWNLOAD_MODE_ERR_V  0x00000001U
+#define EFUSE_DIS_DOWNLOAD_MODE_ERR_S  0
+/** EFUSE_DIS_LEGACY_SPI_BOOT_ERR : RO; bitpos: [1]; default: 0;
+ *  If DIS_LEGACY_SPI_BOOT is 1, then it indicates a programming error.
+ */
+#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR    (BIT(1))
+#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR_M  (EFUSE_DIS_LEGACY_SPI_BOOT_ERR_V << EFUSE_DIS_LEGACY_SPI_BOOT_ERR_S)
+#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR_V  0x00000001U
+#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR_S  1
+/** EFUSE_UART_PRINT_CHANNEL_ERR : RO; bitpos: [2]; default: 0;
+ *  If UART_PRINT_CHANNEL is 1, then it indicates a programming error.
+ */
+#define EFUSE_UART_PRINT_CHANNEL_ERR    (BIT(2))
+#define EFUSE_UART_PRINT_CHANNEL_ERR_M  (EFUSE_UART_PRINT_CHANNEL_ERR_V << EFUSE_UART_PRINT_CHANNEL_ERR_S)
+#define EFUSE_UART_PRINT_CHANNEL_ERR_V  0x00000001U
+#define EFUSE_UART_PRINT_CHANNEL_ERR_S  2
+/** EFUSE_FLASH_ECC_MODE_ERR : RO; bitpos: [3]; default: 0;
+ *  If FLASH_ECC_MODE is 1, then it indicates a programming error.
+ */
+#define EFUSE_FLASH_ECC_MODE_ERR    (BIT(3))
+#define EFUSE_FLASH_ECC_MODE_ERR_M  (EFUSE_FLASH_ECC_MODE_ERR_V << EFUSE_FLASH_ECC_MODE_ERR_S)
+#define EFUSE_FLASH_ECC_MODE_ERR_V  0x00000001U
+#define EFUSE_FLASH_ECC_MODE_ERR_S  3
+/** EFUSE_DIS_USB_DOWNLOAD_MODE_ERR : RO; bitpos: [4]; default: 0;
+ *  If DIS_USB_DOWNLOAD_MODE is 1, then it indicates a programming error.
+ */
+#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR    (BIT(4))
+#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_M  (EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_S)
+#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_V  0x00000001U
+#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_S  4
+/** EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR : RO; bitpos: [5]; default: 0;
+ *  If ENABLE_SECURITY_DOWNLOAD is 1, then it indicates a programming error.
+ */
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR    (BIT(5))
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_M  (EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S)
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V  0x00000001U
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S  5
+/** EFUSE_UART_PRINT_CONTROL_ERR : RO; bitpos: [7:6]; default: 0;
+ *  If any bit in UART_PRINT_CONTROL is 1, then it indicates a programming error.
+ */
+#define EFUSE_UART_PRINT_CONTROL_ERR    0x00000003U
+#define EFUSE_UART_PRINT_CONTROL_ERR_M  (EFUSE_UART_PRINT_CONTROL_ERR_V << EFUSE_UART_PRINT_CONTROL_ERR_S)
+#define EFUSE_UART_PRINT_CONTROL_ERR_V  0x00000003U
+#define EFUSE_UART_PRINT_CONTROL_ERR_S  6
+/** EFUSE_PIN_POWER_SELECTION_ERR : RO; bitpos: [8]; default: 0;
+ *  If PIN_POWER_SELECTION is 1, then it indicates a programming error.
+ */
+#define EFUSE_PIN_POWER_SELECTION_ERR    (BIT(8))
+#define EFUSE_PIN_POWER_SELECTION_ERR_M  (EFUSE_PIN_POWER_SELECTION_ERR_V << EFUSE_PIN_POWER_SELECTION_ERR_S)
+#define EFUSE_PIN_POWER_SELECTION_ERR_V  0x00000001U
+#define EFUSE_PIN_POWER_SELECTION_ERR_S  8
+/** EFUSE_FLASH_TYPE_ERR : RO; bitpos: [9]; default: 0;
+ *  If FLASH_TYPE is 1, then it indicates a programming error.
+ */
+#define EFUSE_FLASH_TYPE_ERR    (BIT(9))
+#define EFUSE_FLASH_TYPE_ERR_M  (EFUSE_FLASH_TYPE_ERR_V << EFUSE_FLASH_TYPE_ERR_S)
+#define EFUSE_FLASH_TYPE_ERR_V  0x00000001U
+#define EFUSE_FLASH_TYPE_ERR_S  9
+/** EFUSE_FLASH_PAGE_SIZE_ERR : RO; bitpos: [11:10]; default: 0;
+ *  If any bits in FLASH_PAGE_SIZE is 1, then it indicates a programming error.
+ */
+#define EFUSE_FLASH_PAGE_SIZE_ERR    0x00000003U
+#define EFUSE_FLASH_PAGE_SIZE_ERR_M  (EFUSE_FLASH_PAGE_SIZE_ERR_V << EFUSE_FLASH_PAGE_SIZE_ERR_S)
+#define EFUSE_FLASH_PAGE_SIZE_ERR_V  0x00000003U
+#define EFUSE_FLASH_PAGE_SIZE_ERR_S  10
+/** EFUSE_FLASH_ECC_EN_ERR : RO; bitpos: [12]; default: 0;
+ *  If FLASH_ECC_EN_ERR is 1, then it indicates a programming error.
+ */
+#define EFUSE_FLASH_ECC_EN_ERR    (BIT(12))
+#define EFUSE_FLASH_ECC_EN_ERR_M  (EFUSE_FLASH_ECC_EN_ERR_V << EFUSE_FLASH_ECC_EN_ERR_S)
+#define EFUSE_FLASH_ECC_EN_ERR_V  0x00000001U
+#define EFUSE_FLASH_ECC_EN_ERR_S  12
+/** EFUSE_FORCE_SEND_RESUME_ERR : RO; bitpos: [13]; default: 0;
+ *  If FORCE_SEND_RESUME is 1, then it indicates a programming error.
+ */
+#define EFUSE_FORCE_SEND_RESUME_ERR    (BIT(13))
+#define EFUSE_FORCE_SEND_RESUME_ERR_M  (EFUSE_FORCE_SEND_RESUME_ERR_V << EFUSE_FORCE_SEND_RESUME_ERR_S)
+#define EFUSE_FORCE_SEND_RESUME_ERR_V  0x00000001U
+#define EFUSE_FORCE_SEND_RESUME_ERR_S  13
+/** EFUSE_SECURE_VERSION_ERR : RO; bitpos: [29:14]; default: 0;
+ *  If any bit in SECURE_VERSION is 1, then it indicates a programming error.
+ */
+#define EFUSE_SECURE_VERSION_ERR    0x0000FFFFU
+#define EFUSE_SECURE_VERSION_ERR_M  (EFUSE_SECURE_VERSION_ERR_V << EFUSE_SECURE_VERSION_ERR_S)
+#define EFUSE_SECURE_VERSION_ERR_V  0x0000FFFFU
+#define EFUSE_SECURE_VERSION_ERR_S  14
+/** EFUSE_RPT4_RESERVED1_ERR : RO; bitpos: [31:30]; default: 0;
+ *  Reserved.
+ */
+#define EFUSE_RPT4_RESERVED1_ERR    0x00000003U
+#define EFUSE_RPT4_RESERVED1_ERR_M  (EFUSE_RPT4_RESERVED1_ERR_V << EFUSE_RPT4_RESERVED1_ERR_S)
+#define EFUSE_RPT4_RESERVED1_ERR_V  0x00000003U
+#define EFUSE_RPT4_RESERVED1_ERR_S  30
+
+/** EFUSE_RD_REPEAT_ERR4_REG register
+ *  Programming error record register 4 of BLOCK0.
+ */
+#define EFUSE_RD_REPEAT_ERR4_REG (DR_REG_EFUSE_BASE + 0x190)
+/** EFUSE_RPT4_RESERVED4_ERR : RO; bitpos: [23:0]; default: 0;
+ *  Reserved.
+ */
+#define EFUSE_RPT4_RESERVED4_ERR    0x00FFFFFFU
+#define EFUSE_RPT4_RESERVED4_ERR_M  (EFUSE_RPT4_RESERVED4_ERR_V << EFUSE_RPT4_RESERVED4_ERR_S)
+#define EFUSE_RPT4_RESERVED4_ERR_V  0x00FFFFFFU
+#define EFUSE_RPT4_RESERVED4_ERR_S  0
+
+/** EFUSE_RD_RS_ERR0_REG register
+ *  Programming error record register 0 of BLOCK1-10.
+ */
+#define EFUSE_RD_RS_ERR0_REG (DR_REG_EFUSE_BASE + 0x1c0)
+/** EFUSE_MAC_SPI_8M_ERR_NUM : RO; bitpos: [2:0]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_MAC_SPI_8M_ERR_NUM    0x00000007U
+#define EFUSE_MAC_SPI_8M_ERR_NUM_M  (EFUSE_MAC_SPI_8M_ERR_NUM_V << EFUSE_MAC_SPI_8M_ERR_NUM_S)
+#define EFUSE_MAC_SPI_8M_ERR_NUM_V  0x00000007U
+#define EFUSE_MAC_SPI_8M_ERR_NUM_S  0
+/** EFUSE_MAC_SPI_8M_FAIL : RO; bitpos: [3]; default: 0;
+ *  0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that
+ *  programming user data failed and the number of error bytes is over 6.
+ */
+#define EFUSE_MAC_SPI_8M_FAIL    (BIT(3))
+#define EFUSE_MAC_SPI_8M_FAIL_M  (EFUSE_MAC_SPI_8M_FAIL_V << EFUSE_MAC_SPI_8M_FAIL_S)
+#define EFUSE_MAC_SPI_8M_FAIL_V  0x00000001U
+#define EFUSE_MAC_SPI_8M_FAIL_S  3
+/** EFUSE_SYS_PART1_NUM : RO; bitpos: [6:4]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_SYS_PART1_NUM    0x00000007U
+#define EFUSE_SYS_PART1_NUM_M  (EFUSE_SYS_PART1_NUM_V << EFUSE_SYS_PART1_NUM_S)
+#define EFUSE_SYS_PART1_NUM_V  0x00000007U
+#define EFUSE_SYS_PART1_NUM_S  4
+/** EFUSE_SYS_PART1_FAIL : RO; bitpos: [7]; default: 0;
+ *  0: Means no failure and that the data of system part1 is reliable 1: Means that
+ *  programming user data failed and the number of error bytes is over 6.
+ */
+#define EFUSE_SYS_PART1_FAIL    (BIT(7))
+#define EFUSE_SYS_PART1_FAIL_M  (EFUSE_SYS_PART1_FAIL_V << EFUSE_SYS_PART1_FAIL_S)
+#define EFUSE_SYS_PART1_FAIL_V  0x00000001U
+#define EFUSE_SYS_PART1_FAIL_S  7
+/** EFUSE_USR_DATA_ERR_NUM : RO; bitpos: [10:8]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_USR_DATA_ERR_NUM    0x00000007U
+#define EFUSE_USR_DATA_ERR_NUM_M  (EFUSE_USR_DATA_ERR_NUM_V << EFUSE_USR_DATA_ERR_NUM_S)
+#define EFUSE_USR_DATA_ERR_NUM_V  0x00000007U
+#define EFUSE_USR_DATA_ERR_NUM_S  8
+/** EFUSE_USR_DATA_FAIL : RO; bitpos: [11]; default: 0;
+ *  0: Means no failure and that the user data is reliable 1: Means that programming
+ *  user data failed and the number of error bytes is over 6.
+ */
+#define EFUSE_USR_DATA_FAIL    (BIT(11))
+#define EFUSE_USR_DATA_FAIL_M  (EFUSE_USR_DATA_FAIL_V << EFUSE_USR_DATA_FAIL_S)
+#define EFUSE_USR_DATA_FAIL_V  0x00000001U
+#define EFUSE_USR_DATA_FAIL_S  11
+/** EFUSE_KEY0_ERR_NUM : RO; bitpos: [14:12]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_KEY0_ERR_NUM    0x00000007U
+#define EFUSE_KEY0_ERR_NUM_M  (EFUSE_KEY0_ERR_NUM_V << EFUSE_KEY0_ERR_NUM_S)
+#define EFUSE_KEY0_ERR_NUM_V  0x00000007U
+#define EFUSE_KEY0_ERR_NUM_S  12
+/** EFUSE_KEY0_FAIL : RO; bitpos: [15]; default: 0;
+ *  0: Means no failure and that the data of key$n is reliable 1: Means that
+ *  programming key$n failed and the number of error bytes is over 6.
+ */
+#define EFUSE_KEY0_FAIL    (BIT(15))
+#define EFUSE_KEY0_FAIL_M  (EFUSE_KEY0_FAIL_V << EFUSE_KEY0_FAIL_S)
+#define EFUSE_KEY0_FAIL_V  0x00000001U
+#define EFUSE_KEY0_FAIL_S  15
+/** EFUSE_KEY1_ERR_NUM : RO; bitpos: [18:16]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_KEY1_ERR_NUM    0x00000007U
+#define EFUSE_KEY1_ERR_NUM_M  (EFUSE_KEY1_ERR_NUM_V << EFUSE_KEY1_ERR_NUM_S)
+#define EFUSE_KEY1_ERR_NUM_V  0x00000007U
+#define EFUSE_KEY1_ERR_NUM_S  16
+/** EFUSE_KEY1_FAIL : RO; bitpos: [19]; default: 0;
+ *  0: Means no failure and that the data of key$n is reliable 1: Means that
+ *  programming key$n failed and the number of error bytes is over 6.
+ */
+#define EFUSE_KEY1_FAIL    (BIT(19))
+#define EFUSE_KEY1_FAIL_M  (EFUSE_KEY1_FAIL_V << EFUSE_KEY1_FAIL_S)
+#define EFUSE_KEY1_FAIL_V  0x00000001U
+#define EFUSE_KEY1_FAIL_S  19
+/** EFUSE_KEY2_ERR_NUM : RO; bitpos: [22:20]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_KEY2_ERR_NUM    0x00000007U
+#define EFUSE_KEY2_ERR_NUM_M  (EFUSE_KEY2_ERR_NUM_V << EFUSE_KEY2_ERR_NUM_S)
+#define EFUSE_KEY2_ERR_NUM_V  0x00000007U
+#define EFUSE_KEY2_ERR_NUM_S  20
+/** EFUSE_KEY2_FAIL : RO; bitpos: [23]; default: 0;
+ *  0: Means no failure and that the data of key$n is reliable 1: Means that
+ *  programming key$n failed and the number of error bytes is over 6.
+ */
+#define EFUSE_KEY2_FAIL    (BIT(23))
+#define EFUSE_KEY2_FAIL_M  (EFUSE_KEY2_FAIL_V << EFUSE_KEY2_FAIL_S)
+#define EFUSE_KEY2_FAIL_V  0x00000001U
+#define EFUSE_KEY2_FAIL_S  23
+/** EFUSE_KEY3_ERR_NUM : RO; bitpos: [26:24]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_KEY3_ERR_NUM    0x00000007U
+#define EFUSE_KEY3_ERR_NUM_M  (EFUSE_KEY3_ERR_NUM_V << EFUSE_KEY3_ERR_NUM_S)
+#define EFUSE_KEY3_ERR_NUM_V  0x00000007U
+#define EFUSE_KEY3_ERR_NUM_S  24
+/** EFUSE_KEY3_FAIL : RO; bitpos: [27]; default: 0;
+ *  0: Means no failure and that the data of key$n is reliable 1: Means that
+ *  programming key$n failed and the number of error bytes is over 6.
+ */
+#define EFUSE_KEY3_FAIL    (BIT(27))
+#define EFUSE_KEY3_FAIL_M  (EFUSE_KEY3_FAIL_V << EFUSE_KEY3_FAIL_S)
+#define EFUSE_KEY3_FAIL_V  0x00000001U
+#define EFUSE_KEY3_FAIL_S  27
+/** EFUSE_KEY4_ERR_NUM : RO; bitpos: [30:28]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_KEY4_ERR_NUM    0x00000007U
+#define EFUSE_KEY4_ERR_NUM_M  (EFUSE_KEY4_ERR_NUM_V << EFUSE_KEY4_ERR_NUM_S)
+#define EFUSE_KEY4_ERR_NUM_V  0x00000007U
+#define EFUSE_KEY4_ERR_NUM_S  28
+/** EFUSE_KEY4_FAIL : RO; bitpos: [31]; default: 0;
+ *  0: Means no failure and that the data of key$n is reliable 1: Means that
+ *  programming key$n failed and the number of error bytes is over 6.
+ */
+#define EFUSE_KEY4_FAIL    (BIT(31))
+#define EFUSE_KEY4_FAIL_M  (EFUSE_KEY4_FAIL_V << EFUSE_KEY4_FAIL_S)
+#define EFUSE_KEY4_FAIL_V  0x00000001U
+#define EFUSE_KEY4_FAIL_S  31
+
+/** EFUSE_RD_RS_ERR1_REG register
+ *  Programming error record register 1 of BLOCK1-10.
+ */
+#define EFUSE_RD_RS_ERR1_REG (DR_REG_EFUSE_BASE + 0x1c4)
+/** EFUSE_KEY5_ERR_NUM : RO; bitpos: [2:0]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_KEY5_ERR_NUM    0x00000007U
+#define EFUSE_KEY5_ERR_NUM_M  (EFUSE_KEY5_ERR_NUM_V << EFUSE_KEY5_ERR_NUM_S)
+#define EFUSE_KEY5_ERR_NUM_V  0x00000007U
+#define EFUSE_KEY5_ERR_NUM_S  0
+/** EFUSE_KEY5_FAIL : RO; bitpos: [3]; default: 0;
+ *  0: Means no failure and that the data of KEY5 is reliable 1: Means that programming
+ *  user data failed and the number of error bytes is over 6.
+ */
+#define EFUSE_KEY5_FAIL    (BIT(3))
+#define EFUSE_KEY5_FAIL_M  (EFUSE_KEY5_FAIL_V << EFUSE_KEY5_FAIL_S)
+#define EFUSE_KEY5_FAIL_V  0x00000001U
+#define EFUSE_KEY5_FAIL_S  3
+/** EFUSE_SYS_PART2_ERR_NUM : RO; bitpos: [6:4]; default: 0;
+ *  The value of this signal means the number of error bytes.
+ */
+#define EFUSE_SYS_PART2_ERR_NUM    0x00000007U
+#define EFUSE_SYS_PART2_ERR_NUM_M  (EFUSE_SYS_PART2_ERR_NUM_V << EFUSE_SYS_PART2_ERR_NUM_S)
+#define EFUSE_SYS_PART2_ERR_NUM_V  0x00000007U
+#define EFUSE_SYS_PART2_ERR_NUM_S  4
+/** EFUSE_SYS_PART2_FAIL : RO; bitpos: [7]; default: 0;
+ *  0: Means no failure and that the data of system part2 is reliable 1: Means that
+ *  programming user data failed and the number of error bytes is over 6.
+ */
+#define EFUSE_SYS_PART2_FAIL    (BIT(7))
+#define EFUSE_SYS_PART2_FAIL_M  (EFUSE_SYS_PART2_FAIL_V << EFUSE_SYS_PART2_FAIL_S)
+#define EFUSE_SYS_PART2_FAIL_V  0x00000001U
+#define EFUSE_SYS_PART2_FAIL_S  7
+
+/** EFUSE_CLK_REG register
+ *  eFuse clcok configuration register.
+ */
+#define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x1c8)
+/** EFUSE_MEM_FORCE_PD : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to force eFuse SRAM into power-saving mode.
+ */
+#define EFUSE_MEM_FORCE_PD    (BIT(0))
+#define EFUSE_MEM_FORCE_PD_M  (EFUSE_MEM_FORCE_PD_V << EFUSE_MEM_FORCE_PD_S)
+#define EFUSE_MEM_FORCE_PD_V  0x00000001U
+#define EFUSE_MEM_FORCE_PD_S  0
+/** EFUSE_MEM_CLK_FORCE_ON : R/W; bitpos: [1]; default: 1;
+ *  Set this bit and force to activate clock signal of eFuse SRAM.
+ */
+#define EFUSE_MEM_CLK_FORCE_ON    (BIT(1))
+#define EFUSE_MEM_CLK_FORCE_ON_M  (EFUSE_MEM_CLK_FORCE_ON_V << EFUSE_MEM_CLK_FORCE_ON_S)
+#define EFUSE_MEM_CLK_FORCE_ON_V  0x00000001U
+#define EFUSE_MEM_CLK_FORCE_ON_S  1
+/** EFUSE_MEM_FORCE_PU : R/W; bitpos: [2]; default: 0;
+ *  Set this bit to force eFuse SRAM into working mode.
+ */
+#define EFUSE_MEM_FORCE_PU    (BIT(2))
+#define EFUSE_MEM_FORCE_PU_M  (EFUSE_MEM_FORCE_PU_V << EFUSE_MEM_FORCE_PU_S)
+#define EFUSE_MEM_FORCE_PU_V  0x00000001U
+#define EFUSE_MEM_FORCE_PU_S  2
+/** EFUSE_CLK_EN : R/W; bitpos: [16]; default: 0;
+ *  Set this bit and force to enable clock signal of eFuse memory.
+ */
+#define EFUSE_CLK_EN    (BIT(16))
+#define EFUSE_CLK_EN_M  (EFUSE_CLK_EN_V << EFUSE_CLK_EN_S)
+#define EFUSE_CLK_EN_V  0x00000001U
+#define EFUSE_CLK_EN_S  16
+
+/** EFUSE_CONF_REG register
+ *  eFuse operation mode configuraiton register
+ */
+#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1cc)
+/** EFUSE_OP_CODE : R/W; bitpos: [15:0]; default: 0;
+ *  0x5A5A: Operate programming command 0x5AA5: Operate read command.
+ */
+#define EFUSE_OP_CODE    0x0000FFFFU
+#define EFUSE_OP_CODE_M  (EFUSE_OP_CODE_V << EFUSE_OP_CODE_S)
+#define EFUSE_OP_CODE_V  0x0000FFFFU
+#define EFUSE_OP_CODE_S  0
+
+/** EFUSE_STATUS_REG register
+ *  eFuse status register.
+ */
+#define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x1d0)
+/** EFUSE_STATE : RO; bitpos: [3:0]; default: 0;
+ *  Indicates the state of the eFuse state machine.
+ */
+#define EFUSE_STATE    0x0000000FU
+#define EFUSE_STATE_M  (EFUSE_STATE_V << EFUSE_STATE_S)
+#define EFUSE_STATE_V  0x0000000FU
+#define EFUSE_STATE_S  0
+/** EFUSE_OTP_LOAD_SW : RO; bitpos: [4]; default: 0;
+ *  The value of OTP_LOAD_SW.
+ */
+#define EFUSE_OTP_LOAD_SW    (BIT(4))
+#define EFUSE_OTP_LOAD_SW_M  (EFUSE_OTP_LOAD_SW_V << EFUSE_OTP_LOAD_SW_S)
+#define EFUSE_OTP_LOAD_SW_V  0x00000001U
+#define EFUSE_OTP_LOAD_SW_S  4
+/** EFUSE_OTP_VDDQ_C_SYNC2 : RO; bitpos: [5]; default: 0;
+ *  The value of OTP_VDDQ_C_SYNC2.
+ */
+#define EFUSE_OTP_VDDQ_C_SYNC2    (BIT(5))
+#define EFUSE_OTP_VDDQ_C_SYNC2_M  (EFUSE_OTP_VDDQ_C_SYNC2_V << EFUSE_OTP_VDDQ_C_SYNC2_S)
+#define EFUSE_OTP_VDDQ_C_SYNC2_V  0x00000001U
+#define EFUSE_OTP_VDDQ_C_SYNC2_S  5
+/** EFUSE_OTP_STROBE_SW : RO; bitpos: [6]; default: 0;
+ *  The value of OTP_STROBE_SW.
+ */
+#define EFUSE_OTP_STROBE_SW    (BIT(6))
+#define EFUSE_OTP_STROBE_SW_M  (EFUSE_OTP_STROBE_SW_V << EFUSE_OTP_STROBE_SW_S)
+#define EFUSE_OTP_STROBE_SW_V  0x00000001U
+#define EFUSE_OTP_STROBE_SW_S  6
+/** EFUSE_OTP_CSB_SW : RO; bitpos: [7]; default: 0;
+ *  The value of OTP_CSB_SW.
+ */
+#define EFUSE_OTP_CSB_SW    (BIT(7))
+#define EFUSE_OTP_CSB_SW_M  (EFUSE_OTP_CSB_SW_V << EFUSE_OTP_CSB_SW_S)
+#define EFUSE_OTP_CSB_SW_V  0x00000001U
+#define EFUSE_OTP_CSB_SW_S  7
+/** EFUSE_OTP_PGENB_SW : RO; bitpos: [8]; default: 0;
+ *  The value of OTP_PGENB_SW.
+ */
+#define EFUSE_OTP_PGENB_SW    (BIT(8))
+#define EFUSE_OTP_PGENB_SW_M  (EFUSE_OTP_PGENB_SW_V << EFUSE_OTP_PGENB_SW_S)
+#define EFUSE_OTP_PGENB_SW_V  0x00000001U
+#define EFUSE_OTP_PGENB_SW_S  8
+/** EFUSE_OTP_VDDQ_IS_SW : RO; bitpos: [9]; default: 0;
+ *  The value of OTP_VDDQ_IS_SW.
+ */
+#define EFUSE_OTP_VDDQ_IS_SW    (BIT(9))
+#define EFUSE_OTP_VDDQ_IS_SW_M  (EFUSE_OTP_VDDQ_IS_SW_V << EFUSE_OTP_VDDQ_IS_SW_S)
+#define EFUSE_OTP_VDDQ_IS_SW_V  0x00000001U
+#define EFUSE_OTP_VDDQ_IS_SW_S  9
+/** EFUSE_REPEAT_ERR_CNT : RO; bitpos: [17:10]; default: 0;
+ *  Indicates the number of error bits during programming BLOCK0.
+ */
+#define EFUSE_REPEAT_ERR_CNT    0x000000FFU
+#define EFUSE_REPEAT_ERR_CNT_M  (EFUSE_REPEAT_ERR_CNT_V << EFUSE_REPEAT_ERR_CNT_S)
+#define EFUSE_REPEAT_ERR_CNT_V  0x000000FFU
+#define EFUSE_REPEAT_ERR_CNT_S  10
+
+/** EFUSE_CMD_REG register
+ *  eFuse command register.
+ */
+#define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x1d4)
+/** EFUSE_READ_CMD : R/W; bitpos: [0]; default: 0;
+ *  Set this bit to send read command.
+ */
+#define EFUSE_READ_CMD    (BIT(0))
+#define EFUSE_READ_CMD_M  (EFUSE_READ_CMD_V << EFUSE_READ_CMD_S)
+#define EFUSE_READ_CMD_V  0x00000001U
+#define EFUSE_READ_CMD_S  0
+/** EFUSE_PGM_CMD : R/W; bitpos: [1]; default: 0;
+ *  Set this bit to send programming command.
+ */
+#define EFUSE_PGM_CMD    (BIT(1))
+#define EFUSE_PGM_CMD_M  (EFUSE_PGM_CMD_V << EFUSE_PGM_CMD_S)
+#define EFUSE_PGM_CMD_V  0x00000001U
+#define EFUSE_PGM_CMD_S  1
+/** EFUSE_BLK_NUM : R/W; bitpos: [5:2]; default: 0;
+ *  The serial number of the block to be programmed. Value 0-10 corresponds to block
+ *  number 0-10, respectively.
+ */
+#define EFUSE_BLK_NUM    0x0000000FU
+#define EFUSE_BLK_NUM_M  (EFUSE_BLK_NUM_V << EFUSE_BLK_NUM_S)
+#define EFUSE_BLK_NUM_V  0x0000000FU
+#define EFUSE_BLK_NUM_S  2
+
+/** EFUSE_INT_RAW_REG register
+ *  eFuse raw interrupt register.
+ */
+#define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x1d8)
+/** EFUSE_READ_DONE_INT_RAW : RO; bitpos: [0]; default: 0;
+ *  The raw bit signal for read_done interrupt.
+ */
+#define EFUSE_READ_DONE_INT_RAW    (BIT(0))
+#define EFUSE_READ_DONE_INT_RAW_M  (EFUSE_READ_DONE_INT_RAW_V << EFUSE_READ_DONE_INT_RAW_S)
+#define EFUSE_READ_DONE_INT_RAW_V  0x00000001U
+#define EFUSE_READ_DONE_INT_RAW_S  0
+/** EFUSE_PGM_DONE_INT_RAW : RO; bitpos: [1]; default: 0;
+ *  The raw bit signal for pgm_done interrupt.
+ */
+#define EFUSE_PGM_DONE_INT_RAW    (BIT(1))
+#define EFUSE_PGM_DONE_INT_RAW_M  (EFUSE_PGM_DONE_INT_RAW_V << EFUSE_PGM_DONE_INT_RAW_S)
+#define EFUSE_PGM_DONE_INT_RAW_V  0x00000001U
+#define EFUSE_PGM_DONE_INT_RAW_S  1
+
+/** EFUSE_INT_ST_REG register
+ *  eFuse interrupt status register.
+ */
+#define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x1dc)
+/** EFUSE_READ_DONE_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The status signal for read_done interrupt.
+ */
+#define EFUSE_READ_DONE_INT_ST    (BIT(0))
+#define EFUSE_READ_DONE_INT_ST_M  (EFUSE_READ_DONE_INT_ST_V << EFUSE_READ_DONE_INT_ST_S)
+#define EFUSE_READ_DONE_INT_ST_V  0x00000001U
+#define EFUSE_READ_DONE_INT_ST_S  0
+/** EFUSE_PGM_DONE_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The status signal for pgm_done interrupt.
+ */
+#define EFUSE_PGM_DONE_INT_ST    (BIT(1))
+#define EFUSE_PGM_DONE_INT_ST_M  (EFUSE_PGM_DONE_INT_ST_V << EFUSE_PGM_DONE_INT_ST_S)
+#define EFUSE_PGM_DONE_INT_ST_V  0x00000001U
+#define EFUSE_PGM_DONE_INT_ST_S  1
+
+/** EFUSE_INT_ENA_REG register
+ *  eFuse interrupt enable register.
+ */
+#define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x1e0)
+/** EFUSE_READ_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The enable signal for read_done interrupt.
+ */
+#define EFUSE_READ_DONE_INT_ENA    (BIT(0))
+#define EFUSE_READ_DONE_INT_ENA_M  (EFUSE_READ_DONE_INT_ENA_V << EFUSE_READ_DONE_INT_ENA_S)
+#define EFUSE_READ_DONE_INT_ENA_V  0x00000001U
+#define EFUSE_READ_DONE_INT_ENA_S  0
+/** EFUSE_PGM_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The enable signal for pgm_done interrupt.
+ */
+#define EFUSE_PGM_DONE_INT_ENA    (BIT(1))
+#define EFUSE_PGM_DONE_INT_ENA_M  (EFUSE_PGM_DONE_INT_ENA_V << EFUSE_PGM_DONE_INT_ENA_S)
+#define EFUSE_PGM_DONE_INT_ENA_V  0x00000001U
+#define EFUSE_PGM_DONE_INT_ENA_S  1
+
+/** EFUSE_INT_CLR_REG register
+ *  eFuse interrupt clear register.
+ */
+#define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x1e4)
+/** EFUSE_READ_DONE_INT_CLR : WO; bitpos: [0]; default: 0;
+ *  The clear signal for read_done interrupt.
+ */
+#define EFUSE_READ_DONE_INT_CLR    (BIT(0))
+#define EFUSE_READ_DONE_INT_CLR_M  (EFUSE_READ_DONE_INT_CLR_V << EFUSE_READ_DONE_INT_CLR_S)
+#define EFUSE_READ_DONE_INT_CLR_V  0x00000001U
+#define EFUSE_READ_DONE_INT_CLR_S  0
+/** EFUSE_PGM_DONE_INT_CLR : WO; bitpos: [1]; default: 0;
+ *  The clear signal for pgm_done interrupt.
+ */
+#define EFUSE_PGM_DONE_INT_CLR    (BIT(1))
+#define EFUSE_PGM_DONE_INT_CLR_M  (EFUSE_PGM_DONE_INT_CLR_V << EFUSE_PGM_DONE_INT_CLR_S)
+#define EFUSE_PGM_DONE_INT_CLR_V  0x00000001U
+#define EFUSE_PGM_DONE_INT_CLR_S  1
+
+/** EFUSE_DAC_CONF_REG register
+ *  Controls the eFuse programming voltage.
+ */
+#define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x1e8)
+/** EFUSE_DAC_CLK_DIV : R/W; bitpos: [7:0]; default: 28;
+ *  Controls the division factor of the rising clock of the programming voltage.
+ */
+#define EFUSE_DAC_CLK_DIV    0x000000FFU
+#define EFUSE_DAC_CLK_DIV_M  (EFUSE_DAC_CLK_DIV_V << EFUSE_DAC_CLK_DIV_S)
+#define EFUSE_DAC_CLK_DIV_V  0x000000FFU
+#define EFUSE_DAC_CLK_DIV_S  0
+/** EFUSE_DAC_CLK_PAD_SEL : R/W; bitpos: [8]; default: 0;
+ *  Don't care.
+ */
+#define EFUSE_DAC_CLK_PAD_SEL    (BIT(8))
+#define EFUSE_DAC_CLK_PAD_SEL_M  (EFUSE_DAC_CLK_PAD_SEL_V << EFUSE_DAC_CLK_PAD_SEL_S)
+#define EFUSE_DAC_CLK_PAD_SEL_V  0x00000001U
+#define EFUSE_DAC_CLK_PAD_SEL_S  8
+/** EFUSE_DAC_NUM : R/W; bitpos: [16:9]; default: 255;
+ *  Controls the rising period of the programming voltage.
+ */
+#define EFUSE_DAC_NUM    0x000000FFU
+#define EFUSE_DAC_NUM_M  (EFUSE_DAC_NUM_V << EFUSE_DAC_NUM_S)
+#define EFUSE_DAC_NUM_V  0x000000FFU
+#define EFUSE_DAC_NUM_S  9
+/** EFUSE_OE_CLR : R/W; bitpos: [17]; default: 0;
+ *  Reduces the power supply of the programming voltage.
+ */
+#define EFUSE_OE_CLR    (BIT(17))
+#define EFUSE_OE_CLR_M  (EFUSE_OE_CLR_V << EFUSE_OE_CLR_S)
+#define EFUSE_OE_CLR_V  0x00000001U
+#define EFUSE_OE_CLR_S  17
+
+/** EFUSE_RD_TIM_CONF_REG register
+ *  Configures read timing parameters.
+ */
+#define EFUSE_RD_TIM_CONF_REG (DR_REG_EFUSE_BASE + 0x1ec)
+/** EFUSE_READ_INIT_NUM : R/W; bitpos: [31:24]; default: 18;
+ *  Configures the initial read time of eFuse.
+ */
+#define EFUSE_READ_INIT_NUM    0x000000FFU
+#define EFUSE_READ_INIT_NUM_M  (EFUSE_READ_INIT_NUM_V << EFUSE_READ_INIT_NUM_S)
+#define EFUSE_READ_INIT_NUM_V  0x000000FFU
+#define EFUSE_READ_INIT_NUM_S  24
+
+/** EFUSE_WR_TIM_CONF1_REG register
+ *  Configurarion register 1 of eFuse programming timing parameters.
+ */
+#define EFUSE_WR_TIM_CONF1_REG (DR_REG_EFUSE_BASE + 0x1f0)
+/** EFUSE_PWR_ON_NUM : R/W; bitpos: [23:8]; default: 10368;
+ *  Configures the power up time for VDDQ.
+ */
+#define EFUSE_PWR_ON_NUM    0x0000FFFFU
+#define EFUSE_PWR_ON_NUM_M  (EFUSE_PWR_ON_NUM_V << EFUSE_PWR_ON_NUM_S)
+#define EFUSE_PWR_ON_NUM_V  0x0000FFFFU
+#define EFUSE_PWR_ON_NUM_S  8
+
+/** EFUSE_WR_TIM_CONF2_REG register
+ *  Configurarion register 2 of eFuse programming timing parameters.
+ */
+#define EFUSE_WR_TIM_CONF2_REG (DR_REG_EFUSE_BASE + 0x1f4)
+/** EFUSE_PWR_OFF_NUM : R/W; bitpos: [15:0]; default: 400;
+ *  Configures the power outage time for VDDQ.
+ */
+#define EFUSE_PWR_OFF_NUM    0x0000FFFFU
+#define EFUSE_PWR_OFF_NUM_M  (EFUSE_PWR_OFF_NUM_V << EFUSE_PWR_OFF_NUM_S)
+#define EFUSE_PWR_OFF_NUM_V  0x0000FFFFU
+#define EFUSE_PWR_OFF_NUM_S  0
+
+/** EFUSE_DATE_REG register
+ *  eFuse version register.
+ */
+#define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x1fc)
+/** EFUSE_DATE : R/W; bitpos: [27:0]; default: 33583616;
+ *  Stores eFuse version.
+ */
+#define EFUSE_DATE    0x0FFFFFFFU
+#define EFUSE_DATE_M  (EFUSE_DATE_V << EFUSE_DATE_S)
+#define EFUSE_DATE_V  0x0FFFFFFFU
+#define EFUSE_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32h2/include/rev2/soc/efuse_struct.h

@@ -0,0 +1,2201 @@
+/**
+ * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: PGM Data Register */
+/** Type of pgm_data0 register
+ *  Register 0 that stores data to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_data_0 : R/W; bitpos: [31:0]; default: 0;
+         *  The content of the 0th 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_0:32;
+    };
+    uint32_t val;
+} efuse_pgm_data0_reg_t;
+
+/** Type of pgm_data1 register
+ *  Register 1 that stores data to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_data_1 : R/W; bitpos: [31:0]; default: 0;
+         *  The content of the 1st 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_1:32;
+    };
+    uint32_t val;
+} efuse_pgm_data1_reg_t;
+
+/** Type of pgm_data2 register
+ *  Register 2 that stores data to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_data_2 : R/W; bitpos: [31:0]; default: 0;
+         *  The content of the 2nd 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_2:32;
+    };
+    uint32_t val;
+} efuse_pgm_data2_reg_t;
+
+/** Type of pgm_data3 register
+ *  Register 3 that stores data to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_data_3 : R/W; bitpos: [31:0]; default: 0;
+         *  The content of the 3rd 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_3:32;
+    };
+    uint32_t val;
+} efuse_pgm_data3_reg_t;
+
+/** Type of pgm_data4 register
+ *  Register 4 that stores data to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_data_4 : R/W; bitpos: [31:0]; default: 0;
+         *  The content of the 4th 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_4:32;
+    };
+    uint32_t val;
+} efuse_pgm_data4_reg_t;
+
+/** Type of pgm_data5 register
+ *  Register 5 that stores data to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_data_5 : R/W; bitpos: [31:0]; default: 0;
+         *  The content of the 5th 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_5:32;
+    };
+    uint32_t val;
+} efuse_pgm_data5_reg_t;
+
+/** Type of pgm_data6 register
+ *  Register 6 that stores data to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_data_6 : R/W; bitpos: [31:0]; default: 0;
+         *  The content of the 6th 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_6:32;
+    };
+    uint32_t val;
+} efuse_pgm_data6_reg_t;
+
+/** Type of pgm_data7 register
+ *  Register 7 that stores data to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_data_7 : R/W; bitpos: [31:0]; default: 0;
+         *  The content of the 7th 32-bit data to be programmed.
+         */
+        uint32_t pgm_data_7:32;
+    };
+    uint32_t val;
+} efuse_pgm_data7_reg_t;
+
+/** Type of pgm_check_value0 register
+ *  Register 0 that stores the RS code to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_rs_data_0 : R/W; bitpos: [31:0]; default: 0;
+         *  The content of the 0th 32-bit RS code to be programmed.
+         */
+        uint32_t pgm_rs_data_0:32;
+    };
+    uint32_t val;
+} efuse_pgm_check_value0_reg_t;
+
+/** Type of pgm_check_value1 register
+ *  Register 1 that stores the RS code to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_rs_data_1 : R/W; bitpos: [31:0]; default: 0;
+         *  The content of the 1st 32-bit RS code to be programmed.
+         */
+        uint32_t pgm_rs_data_1:32;
+    };
+    uint32_t val;
+} efuse_pgm_check_value1_reg_t;
+
+/** Type of pgm_check_value2 register
+ *  Register 2 that stores the RS code to be programmed.
+ */
+typedef union {
+    struct {
+        /** pgm_rs_data_2 : R/W; bitpos: [31:0]; default: 0;
+         *  The content of the 2nd 32-bit RS code to be programmed.
+         */
+        uint32_t pgm_rs_data_2:32;
+    };
+    uint32_t val;
+} efuse_pgm_check_value2_reg_t;
+
+
+/** Group: ******** Registers */
+/** Type of rd_wr_dis register
+ *  BLOCK0 data register $n.
+ */
+typedef union {
+    struct {
+        /** wr_dis : RO; bitpos: [31:0]; default: 0;
+         *  The value of WR_DIS.
+         */
+        uint32_t wr_dis:32;
+    };
+    uint32_t val;
+} efuse_rd_wr_dis_reg_t;
+
+/** Type of rd_repeat_data0 register
+ *  BLOCK0 data register $n.
+ */
+typedef union {
+    struct {
+        /** rd_dis : RO; bitpos: [6:0]; default: 0;
+         *  The value of RD_DIS.
+         */
+        uint32_t rd_dis:7;
+        /** dis_rtc_ram_boot : RO; bitpos: [7]; default: 0;
+         *  The value of DIS_RTC_RAM_BOOT.
+         */
+        uint32_t dis_rtc_ram_boot:1;
+        /** dis_icache : RO; bitpos: [8]; default: 0;
+         *  The value of DIS_ICACHE.
+         */
+        uint32_t dis_icache:1;
+        /** dis_usb_jtag : RO; bitpos: [9]; default: 0;
+         *  The value of DIS_USB_JTAG.
+         */
+        uint32_t dis_usb_jtag:1;
+        /** dis_download_icache : RO; bitpos: [10]; default: 0;
+         *  The value of DIS_DOWNLOAD_ICACHE.
+         */
+        uint32_t dis_download_icache:1;
+        /** dis_usb_device : RO; bitpos: [11]; default: 0;
+         *  The value of DIS_USB_DEVICE.
+         */
+        uint32_t dis_usb_device:1;
+        /** dis_force_download : RO; bitpos: [12]; default: 0;
+         *  The value of DIS_FORCE_DOWNLOAD.
+         */
+        uint32_t dis_force_download:1;
+        /** dis_usb : RO; bitpos: [13]; default: 0;
+         *  The value of DIS_USB.
+         */
+        uint32_t dis_usb:1;
+        /** dis_twai : RO; bitpos: [14]; default: 0;
+         *  The value of DIS_TWAI.
+         */
+        uint32_t dis_twai:1;
+        /** jtag_sel_enable : RO; bitpos: [15]; default: 0;
+         *  The value of JTAG_SEL_ENABLE.
+         */
+        uint32_t jtag_sel_enable:1;
+        /** soft_dis_jtag : RO; bitpos: [18:16]; default: 0;
+         *  The value of SOFT_DIS_JTAG.
+         */
+        uint32_t soft_dis_jtag:3;
+        /** dis_pad_jtag : RO; bitpos: [19]; default: 0;
+         *  The value of DIS_PAD_JTAG.
+         */
+        uint32_t dis_pad_jtag:1;
+        /** dis_download_manual_encrypt : RO; bitpos: [20]; default: 0;
+         *  The value of DIS_DOWNLOAD_MANUAL_ENCRYPT.
+         */
+        uint32_t dis_download_manual_encrypt:1;
+        /** usb_drefh : RO; bitpos: [22:21]; default: 0;
+         *  The value of USB_DREFH.
+         */
+        uint32_t usb_drefh:2;
+        /** usb_drefl : RO; bitpos: [24:23]; default: 0;
+         *  The value of USB_DREFL.
+         */
+        uint32_t usb_drefl:2;
+        /** usb_exchg_pins : RO; bitpos: [25]; default: 0;
+         *  The value of USB_EXCHG_PINS.
+         */
+        uint32_t usb_exchg_pins:1;
+        /** vdd_spi_as_gpio : RO; bitpos: [26]; default: 0;
+         *  The value of VDD_SPI_AS_GPIO.
+         */
+        uint32_t vdd_spi_as_gpio:1;
+        /** btlc_gpio_enable : RO; bitpos: [28:27]; default: 0;
+         *  The value of BTLC_GPIO_ENABLE.
+         */
+        uint32_t btlc_gpio_enable:2;
+        /** powerglitch_en : RO; bitpos: [29]; default: 0;
+         *  The value of POWERGLITCH_EN.
+         */
+        uint32_t powerglitch_en:1;
+        /** power_glitch_dsense : RO; bitpos: [31:30]; default: 0;
+         *  The value of POWER_GLITCH_DSENSE.
+         */
+        uint32_t power_glitch_dsense:2;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data0_reg_t;
+
+/** Type of rd_repeat_data1 register
+ *  BLOCK0 data register $n.
+ */
+typedef union {
+    struct {
+        /** rpt4_reserved2 : RO; bitpos: [15:0]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rpt4_reserved2:16;
+        /** wdt_delay_sel : RO; bitpos: [17:16]; default: 0;
+         *  The value of WDT_DELAY_SEL.
+         */
+        uint32_t wdt_delay_sel:2;
+        /** spi_boot_crypt_cnt : RO; bitpos: [20:18]; default: 0;
+         *  The value of SPI_BOOT_CRYPT_CNT.
+         */
+        uint32_t spi_boot_crypt_cnt:3;
+        /** secure_boot_key_revoke0 : RO; bitpos: [21]; default: 0;
+         *  The value of SECURE_BOOT_KEY_REVOKE0.
+         */
+        uint32_t secure_boot_key_revoke0:1;
+        /** secure_boot_key_revoke1 : RO; bitpos: [22]; default: 0;
+         *  The value of SECURE_BOOT_KEY_REVOKE1.
+         */
+        uint32_t secure_boot_key_revoke1:1;
+        /** secure_boot_key_revoke2 : RO; bitpos: [23]; default: 0;
+         *  The value of SECURE_BOOT_KEY_REVOKE2.
+         */
+        uint32_t secure_boot_key_revoke2:1;
+        /** key_purpose_0 : RO; bitpos: [27:24]; default: 0;
+         *  The value of KEY_PURPOSE_0.
+         */
+        uint32_t key_purpose_0:4;
+        /** key_purpose_1 : RO; bitpos: [31:28]; default: 0;
+         *  The value of KEY_PURPOSE_1.
+         */
+        uint32_t key_purpose_1:4;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data1_reg_t;
+
+/** Type of rd_repeat_data2 register
+ *  BLOCK0 data register $n.
+ */
+typedef union {
+    struct {
+        /** key_purpose_2 : RO; bitpos: [3:0]; default: 0;
+         *  The value of KEY_PURPOSE_2.
+         */
+        uint32_t key_purpose_2:4;
+        /** key_purpose_3 : RO; bitpos: [7:4]; default: 0;
+         *  The value of KEY_PURPOSE_3.
+         */
+        uint32_t key_purpose_3:4;
+        /** key_purpose_4 : RO; bitpos: [11:8]; default: 0;
+         *  The value of KEY_PURPOSE_4.
+         */
+        uint32_t key_purpose_4:4;
+        /** key_purpose_5 : RO; bitpos: [15:12]; default: 0;
+         *  The value of KEY_PURPOSE_5.
+         */
+        uint32_t key_purpose_5:4;
+        /** rpt4_reserved3 : RO; bitpos: [19:16]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rpt4_reserved3:4;
+        /** secure_boot_en : RO; bitpos: [20]; default: 0;
+         *  The value of SECURE_BOOT_EN.
+         */
+        uint32_t secure_boot_en:1;
+        /** secure_boot_aggressive_revoke : RO; bitpos: [21]; default: 0;
+         *  The value of SECURE_BOOT_AGGRESSIVE_REVOKE.
+         */
+        uint32_t secure_boot_aggressive_revoke:1;
+        /** rpt4_reserved0 : RO; bitpos: [27:22]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rpt4_reserved0:6;
+        /** flash_tpuw : RO; bitpos: [31:28]; default: 0;
+         *  The value of FLASH_TPUW.
+         */
+        uint32_t flash_tpuw:4;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data2_reg_t;
+
+/** Type of rd_repeat_data3 register
+ *  BLOCK0 data register $n.
+ */
+typedef union {
+    struct {
+        /** dis_download_mode : RO; bitpos: [0]; default: 0;
+         *  The value of DIS_DOWNLOAD_MODE.
+         */
+        uint32_t dis_download_mode:1;
+        /** dis_legacy_spi_boot : RO; bitpos: [1]; default: 0;
+         *  The value of DIS_LEGACY_SPI_BOOT.
+         */
+        uint32_t dis_legacy_spi_boot:1;
+        /** uart_print_channel : RO; bitpos: [2]; default: 0;
+         *  The value of UART_PRINT_CHANNEL.
+         */
+        uint32_t uart_print_channel:1;
+        /** flash_ecc_mode : RO; bitpos: [3]; default: 0;
+         *  The value of FLASH_ECC_MODE.
+         */
+        uint32_t flash_ecc_mode:1;
+        /** dis_usb_download_mode : RO; bitpos: [4]; default: 0;
+         *  The value of DIS_USB_DOWNLOAD_MODE.
+         */
+        uint32_t dis_usb_download_mode:1;
+        /** enable_security_download : RO; bitpos: [5]; default: 0;
+         *  The value of ENABLE_SECURITY_DOWNLOAD.
+         */
+        uint32_t enable_security_download:1;
+        /** uart_print_control : RO; bitpos: [7:6]; default: 0;
+         *  The value of UART_PRINT_CONTROL.
+         */
+        uint32_t uart_print_control:2;
+        /** pin_power_selection : RO; bitpos: [8]; default: 0;
+         *  The value of PIN_POWER_SELECTION.
+         */
+        uint32_t pin_power_selection:1;
+        /** flash_type : RO; bitpos: [9]; default: 0;
+         *  The value of FLASH_TYPE.
+         */
+        uint32_t flash_type:1;
+        /** flash_page_size : RO; bitpos: [11:10]; default: 0;
+         *  The value of FLASH_PAGE_SIZE.
+         */
+        uint32_t flash_page_size:2;
+        /** flash_ecc_en : RO; bitpos: [12]; default: 0;
+         *  The value of FLASH_ECC_EN.
+         */
+        uint32_t flash_ecc_en:1;
+        /** force_send_resume : RO; bitpos: [13]; default: 0;
+         *  The value of FORCE_SEND_RESUME.
+         */
+        uint32_t force_send_resume:1;
+        /** secure_version : RO; bitpos: [29:14]; default: 0;
+         *  The value of SECURE_VERSION.
+         */
+        uint32_t secure_version:16;
+        /** rpt4_reserved1 : RO; bitpos: [31:30]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rpt4_reserved1:2;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data3_reg_t;
+
+/** Type of rd_repeat_data4 register
+ *  BLOCK0 data register $n.
+ */
+typedef union {
+    struct {
+        /** rpt4_reserved4 : RO; bitpos: [23:0]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rpt4_reserved4:24;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} efuse_rd_repeat_data4_reg_t;
+
+/** Type of rd_mac_spi_sys_0 register
+ *  BLOCK1 data register $n.
+ */
+typedef union {
+    struct {
+        /** mac_0 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the low 32 bits of MAC address.
+         */
+        uint32_t mac_0:32;
+    };
+    uint32_t val;
+} efuse_rd_mac_spi_sys_0_reg_t;
+
+/** Type of rd_mac_spi_sys_1 register
+ *  BLOCK1 data register $n.
+ */
+typedef union {
+    struct {
+        /** mac_1 : RO; bitpos: [15:0]; default: 0;
+         *  Stores the high 16 bits of MAC address.
+         */
+        uint32_t mac_1:16;
+        /** spi_pad_conf_0 : RO; bitpos: [31:16]; default: 0;
+         *  Stores the zeroth part of SPI_PAD_CONF.
+         */
+        uint32_t spi_pad_conf_0:16;
+    };
+    uint32_t val;
+} efuse_rd_mac_spi_sys_1_reg_t;
+
+/** Type of rd_mac_spi_sys_2 register
+ *  BLOCK1 data register $n.
+ */
+typedef union {
+    struct {
+        /** spi_pad_conf_1 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the first part of SPI_PAD_CONF.
+         */
+        uint32_t spi_pad_conf_1:32;
+    };
+    uint32_t val;
+} efuse_rd_mac_spi_sys_2_reg_t;
+
+/** Type of rd_mac_spi_sys_3 register
+ *  BLOCK1 data register $n.
+ */
+typedef union {
+    struct {
+        /** spi_pad_conf_2 : RO; bitpos: [17:0]; default: 0;
+         *  Stores the second part of SPI_PAD_CONF.
+         */
+        uint32_t spi_pad_conf_2:18;
+        /** sys_data_part0_0 : RO; bitpos: [31:18]; default: 0;
+         *  Stores the fist 14 bits of the zeroth part of system data.
+         */
+        uint32_t sys_data_part0_0:14;
+    };
+    uint32_t val;
+} efuse_rd_mac_spi_sys_3_reg_t;
+
+/** Type of rd_mac_spi_sys_4 register
+ *  BLOCK1 data register $n.
+ */
+typedef union {
+    struct {
+        /** sys_data_part0_1 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fist 32 bits of the zeroth part of system data.
+         */
+        uint32_t sys_data_part0_1:32;
+    };
+    uint32_t val;
+} efuse_rd_mac_spi_sys_4_reg_t;
+
+/** Type of rd_mac_spi_sys_5 register
+ *  BLOCK1 data register $n.
+ */
+typedef union {
+    struct {
+        /** sys_data_part0_2 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the second 32 bits of the zeroth part of system data.
+         */
+        uint32_t sys_data_part0_2:32;
+    };
+    uint32_t val;
+} efuse_rd_mac_spi_sys_5_reg_t;
+
+/** Type of rd_sys_part1_data0 register
+ *  Register $n of BLOCK2 (system).
+ */
+typedef union {
+    struct {
+        /** sys_data_part1_0 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the zeroth 32 bits of the first part of system data.
+         */
+        uint32_t sys_data_part1_0:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data0_reg_t;
+
+/** Type of rd_sys_part1_data1 register
+ *  Register $n of BLOCK2 (system).
+ */
+typedef union {
+    struct {
+        /** sys_data_part1_1 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the first 32 bits of the first part of system data.
+         */
+        uint32_t sys_data_part1_1:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data1_reg_t;
+
+/** Type of rd_sys_part1_data2 register
+ *  Register $n of BLOCK2 (system).
+ */
+typedef union {
+    struct {
+        /** sys_data_part1_2 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the second 32 bits of the first part of system data.
+         */
+        uint32_t sys_data_part1_2:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data2_reg_t;
+
+/** Type of rd_sys_part1_data3 register
+ *  Register $n of BLOCK2 (system).
+ */
+typedef union {
+    struct {
+        /** sys_data_part1_3 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the third 32 bits of the first part of system data.
+         */
+        uint32_t sys_data_part1_3:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data3_reg_t;
+
+/** Type of rd_sys_part1_data4 register
+ *  Register $n of BLOCK2 (system).
+ */
+typedef union {
+    struct {
+        /** sys_data_part1_4 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fourth 32 bits of the first part of system data.
+         */
+        uint32_t sys_data_part1_4:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data4_reg_t;
+
+/** Type of rd_sys_part1_data5 register
+ *  Register $n of BLOCK2 (system).
+ */
+typedef union {
+    struct {
+        /** sys_data_part1_5 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fifth 32 bits of the first part of system data.
+         */
+        uint32_t sys_data_part1_5:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data5_reg_t;
+
+/** Type of rd_sys_part1_data6 register
+ *  Register $n of BLOCK2 (system).
+ */
+typedef union {
+    struct {
+        /** sys_data_part1_6 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the sixth 32 bits of the first part of system data.
+         */
+        uint32_t sys_data_part1_6:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data6_reg_t;
+
+/** Type of rd_sys_part1_data7 register
+ *  Register $n of BLOCK2 (system).
+ */
+typedef union {
+    struct {
+        /** sys_data_part1_7 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the seventh 32 bits of the first part of system data.
+         */
+        uint32_t sys_data_part1_7:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part1_data7_reg_t;
+
+/** Type of rd_usr_data0 register
+ *  Register $n of BLOCK3 (user).
+ */
+typedef union {
+    struct {
+        /** usr_data0 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the zeroth 32 bits of BLOCK3 (user).
+         */
+        uint32_t usr_data0:32;
+    };
+    uint32_t val;
+} efuse_rd_usr_data0_reg_t;
+
+/** Type of rd_usr_data1 register
+ *  Register $n of BLOCK3 (user).
+ */
+typedef union {
+    struct {
+        /** usr_data1 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the first 32 bits of BLOCK3 (user).
+         */
+        uint32_t usr_data1:32;
+    };
+    uint32_t val;
+} efuse_rd_usr_data1_reg_t;
+
+/** Type of rd_usr_data2 register
+ *  Register $n of BLOCK3 (user).
+ */
+typedef union {
+    struct {
+        /** usr_data2 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the second 32 bits of BLOCK3 (user).
+         */
+        uint32_t usr_data2:32;
+    };
+    uint32_t val;
+} efuse_rd_usr_data2_reg_t;
+
+/** Type of rd_usr_data3 register
+ *  Register $n of BLOCK3 (user).
+ */
+typedef union {
+    struct {
+        /** usr_data3 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the third 32 bits of BLOCK3 (user).
+         */
+        uint32_t usr_data3:32;
+    };
+    uint32_t val;
+} efuse_rd_usr_data3_reg_t;
+
+/** Type of rd_usr_data4 register
+ *  Register $n of BLOCK3 (user).
+ */
+typedef union {
+    struct {
+        /** usr_data4 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fourth 32 bits of BLOCK3 (user).
+         */
+        uint32_t usr_data4:32;
+    };
+    uint32_t val;
+} efuse_rd_usr_data4_reg_t;
+
+/** Type of rd_usr_data5 register
+ *  Register $n of BLOCK3 (user).
+ */
+typedef union {
+    struct {
+        /** usr_data5 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fifth 32 bits of BLOCK3 (user).
+         */
+        uint32_t usr_data5:32;
+    };
+    uint32_t val;
+} efuse_rd_usr_data5_reg_t;
+
+/** Type of rd_usr_data6 register
+ *  Register $n of BLOCK3 (user).
+ */
+typedef union {
+    struct {
+        /** usr_data6 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the sixth 32 bits of BLOCK3 (user).
+         */
+        uint32_t usr_data6:32;
+    };
+    uint32_t val;
+} efuse_rd_usr_data6_reg_t;
+
+/** Type of rd_usr_data7 register
+ *  Register $n of BLOCK3 (user).
+ */
+typedef union {
+    struct {
+        /** usr_data7 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the seventh 32 bits of BLOCK3 (user).
+         */
+        uint32_t usr_data7:32;
+    };
+    uint32_t val;
+} efuse_rd_usr_data7_reg_t;
+
+/** Type of rd_key0_data0 register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+typedef union {
+    struct {
+        /** key0_data0 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the zeroth 32 bits of KEY0.
+         */
+        uint32_t key0_data0:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data0_reg_t;
+
+/** Type of rd_key0_data1 register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+typedef union {
+    struct {
+        /** key0_data1 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the first 32 bits of KEY0.
+         */
+        uint32_t key0_data1:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data1_reg_t;
+
+/** Type of rd_key0_data2 register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+typedef union {
+    struct {
+        /** key0_data2 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the second 32 bits of KEY0.
+         */
+        uint32_t key0_data2:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data2_reg_t;
+
+/** Type of rd_key0_data3 register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+typedef union {
+    struct {
+        /** key0_data3 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the third 32 bits of KEY0.
+         */
+        uint32_t key0_data3:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data3_reg_t;
+
+/** Type of rd_key0_data4 register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+typedef union {
+    struct {
+        /** key0_data4 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fourth 32 bits of KEY0.
+         */
+        uint32_t key0_data4:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data4_reg_t;
+
+/** Type of rd_key0_data5 register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+typedef union {
+    struct {
+        /** key0_data5 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fifth 32 bits of KEY0.
+         */
+        uint32_t key0_data5:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data5_reg_t;
+
+/** Type of rd_key0_data6 register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+typedef union {
+    struct {
+        /** key0_data6 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the sixth 32 bits of KEY0.
+         */
+        uint32_t key0_data6:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data6_reg_t;
+
+/** Type of rd_key0_data7 register
+ *  Register $n of BLOCK4 (KEY0).
+ */
+typedef union {
+    struct {
+        /** key0_data7 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the seventh 32 bits of KEY0.
+         */
+        uint32_t key0_data7:32;
+    };
+    uint32_t val;
+} efuse_rd_key0_data7_reg_t;
+
+/** Type of rd_key1_data0 register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+typedef union {
+    struct {
+        /** key1_data0 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the zeroth 32 bits of KEY1.
+         */
+        uint32_t key1_data0:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data0_reg_t;
+
+/** Type of rd_key1_data1 register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+typedef union {
+    struct {
+        /** key1_data1 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the first 32 bits of KEY1.
+         */
+        uint32_t key1_data1:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data1_reg_t;
+
+/** Type of rd_key1_data2 register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+typedef union {
+    struct {
+        /** key1_data2 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the second 32 bits of KEY1.
+         */
+        uint32_t key1_data2:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data2_reg_t;
+
+/** Type of rd_key1_data3 register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+typedef union {
+    struct {
+        /** key1_data3 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the third 32 bits of KEY1.
+         */
+        uint32_t key1_data3:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data3_reg_t;
+
+/** Type of rd_key1_data4 register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+typedef union {
+    struct {
+        /** key1_data4 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fourth 32 bits of KEY1.
+         */
+        uint32_t key1_data4:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data4_reg_t;
+
+/** Type of rd_key1_data5 register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+typedef union {
+    struct {
+        /** key1_data5 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fifth 32 bits of KEY1.
+         */
+        uint32_t key1_data5:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data5_reg_t;
+
+/** Type of rd_key1_data6 register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+typedef union {
+    struct {
+        /** key1_data6 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the sixth 32 bits of KEY1.
+         */
+        uint32_t key1_data6:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data6_reg_t;
+
+/** Type of rd_key1_data7 register
+ *  Register $n of BLOCK5 (KEY1).
+ */
+typedef union {
+    struct {
+        /** key1_data7 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the seventh 32 bits of KEY1.
+         */
+        uint32_t key1_data7:32;
+    };
+    uint32_t val;
+} efuse_rd_key1_data7_reg_t;
+
+/** Type of rd_key2_data0 register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+typedef union {
+    struct {
+        /** key2_data0 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the zeroth 32 bits of KEY2.
+         */
+        uint32_t key2_data0:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data0_reg_t;
+
+/** Type of rd_key2_data1 register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+typedef union {
+    struct {
+        /** key2_data1 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the first 32 bits of KEY2.
+         */
+        uint32_t key2_data1:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data1_reg_t;
+
+/** Type of rd_key2_data2 register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+typedef union {
+    struct {
+        /** key2_data2 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the second 32 bits of KEY2.
+         */
+        uint32_t key2_data2:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data2_reg_t;
+
+/** Type of rd_key2_data3 register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+typedef union {
+    struct {
+        /** key2_data3 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the third 32 bits of KEY2.
+         */
+        uint32_t key2_data3:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data3_reg_t;
+
+/** Type of rd_key2_data4 register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+typedef union {
+    struct {
+        /** key2_data4 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fourth 32 bits of KEY2.
+         */
+        uint32_t key2_data4:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data4_reg_t;
+
+/** Type of rd_key2_data5 register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+typedef union {
+    struct {
+        /** key2_data5 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fifth 32 bits of KEY2.
+         */
+        uint32_t key2_data5:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data5_reg_t;
+
+/** Type of rd_key2_data6 register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+typedef union {
+    struct {
+        /** key2_data6 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the sixth 32 bits of KEY2.
+         */
+        uint32_t key2_data6:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data6_reg_t;
+
+/** Type of rd_key2_data7 register
+ *  Register $n of BLOCK6 (KEY2).
+ */
+typedef union {
+    struct {
+        /** key2_data7 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the seventh 32 bits of KEY2.
+         */
+        uint32_t key2_data7:32;
+    };
+    uint32_t val;
+} efuse_rd_key2_data7_reg_t;
+
+/** Type of rd_key3_data0 register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+typedef union {
+    struct {
+        /** key3_data0 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the zeroth 32 bits of KEY3.
+         */
+        uint32_t key3_data0:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data0_reg_t;
+
+/** Type of rd_key3_data1 register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+typedef union {
+    struct {
+        /** key3_data1 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the first 32 bits of KEY3.
+         */
+        uint32_t key3_data1:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data1_reg_t;
+
+/** Type of rd_key3_data2 register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+typedef union {
+    struct {
+        /** key3_data2 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the second 32 bits of KEY3.
+         */
+        uint32_t key3_data2:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data2_reg_t;
+
+/** Type of rd_key3_data3 register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+typedef union {
+    struct {
+        /** key3_data3 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the third 32 bits of KEY3.
+         */
+        uint32_t key3_data3:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data3_reg_t;
+
+/** Type of rd_key3_data4 register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+typedef union {
+    struct {
+        /** key3_data4 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fourth 32 bits of KEY3.
+         */
+        uint32_t key3_data4:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data4_reg_t;
+
+/** Type of rd_key3_data5 register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+typedef union {
+    struct {
+        /** key3_data5 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fifth 32 bits of KEY3.
+         */
+        uint32_t key3_data5:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data5_reg_t;
+
+/** Type of rd_key3_data6 register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+typedef union {
+    struct {
+        /** key3_data6 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the sixth 32 bits of KEY3.
+         */
+        uint32_t key3_data6:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data6_reg_t;
+
+/** Type of rd_key3_data7 register
+ *  Register $n of BLOCK7 (KEY3).
+ */
+typedef union {
+    struct {
+        /** key3_data7 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the seventh 32 bits of KEY3.
+         */
+        uint32_t key3_data7:32;
+    };
+    uint32_t val;
+} efuse_rd_key3_data7_reg_t;
+
+/** Type of rd_key4_data0 register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+typedef union {
+    struct {
+        /** key4_data0 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the zeroth 32 bits of KEY4.
+         */
+        uint32_t key4_data0:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data0_reg_t;
+
+/** Type of rd_key4_data1 register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+typedef union {
+    struct {
+        /** key4_data1 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the first 32 bits of KEY4.
+         */
+        uint32_t key4_data1:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data1_reg_t;
+
+/** Type of rd_key4_data2 register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+typedef union {
+    struct {
+        /** key4_data2 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the second 32 bits of KEY4.
+         */
+        uint32_t key4_data2:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data2_reg_t;
+
+/** Type of rd_key4_data3 register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+typedef union {
+    struct {
+        /** key4_data3 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the third 32 bits of KEY4.
+         */
+        uint32_t key4_data3:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data3_reg_t;
+
+/** Type of rd_key4_data4 register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+typedef union {
+    struct {
+        /** key4_data4 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fourth 32 bits of KEY4.
+         */
+        uint32_t key4_data4:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data4_reg_t;
+
+/** Type of rd_key4_data5 register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+typedef union {
+    struct {
+        /** key4_data5 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fifth 32 bits of KEY4.
+         */
+        uint32_t key4_data5:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data5_reg_t;
+
+/** Type of rd_key4_data6 register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+typedef union {
+    struct {
+        /** key4_data6 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the sixth 32 bits of KEY4.
+         */
+        uint32_t key4_data6:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data6_reg_t;
+
+/** Type of rd_key4_data7 register
+ *  Register $n of BLOCK8 (KEY4).
+ */
+typedef union {
+    struct {
+        /** key4_data7 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the seventh 32 bits of KEY4.
+         */
+        uint32_t key4_data7:32;
+    };
+    uint32_t val;
+} efuse_rd_key4_data7_reg_t;
+
+/** Type of rd_key5_data0 register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+typedef union {
+    struct {
+        /** key5_data0 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the zeroth 32 bits of KEY5.
+         */
+        uint32_t key5_data0:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data0_reg_t;
+
+/** Type of rd_key5_data1 register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+typedef union {
+    struct {
+        /** key5_data1 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the first 32 bits of KEY5.
+         */
+        uint32_t key5_data1:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data1_reg_t;
+
+/** Type of rd_key5_data2 register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+typedef union {
+    struct {
+        /** key5_data2 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the second 32 bits of KEY5.
+         */
+        uint32_t key5_data2:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data2_reg_t;
+
+/** Type of rd_key5_data3 register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+typedef union {
+    struct {
+        /** key5_data3 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the third 32 bits of KEY5.
+         */
+        uint32_t key5_data3:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data3_reg_t;
+
+/** Type of rd_key5_data4 register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+typedef union {
+    struct {
+        /** key5_data4 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fourth 32 bits of KEY5.
+         */
+        uint32_t key5_data4:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data4_reg_t;
+
+/** Type of rd_key5_data5 register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+typedef union {
+    struct {
+        /** key5_data5 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the fifth 32 bits of KEY5.
+         */
+        uint32_t key5_data5:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data5_reg_t;
+
+/** Type of rd_key5_data6 register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+typedef union {
+    struct {
+        /** key5_data6 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the sixth 32 bits of KEY5.
+         */
+        uint32_t key5_data6:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data6_reg_t;
+
+/** Type of rd_key5_data7 register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+typedef union {
+    struct {
+        /** key5_data7 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the seventh 32 bits of KEY5.
+         */
+        uint32_t key5_data7:32;
+    };
+    uint32_t val;
+} efuse_rd_key5_data7_reg_t;
+
+/** Type of rd_sys_part2_data0 register
+ *  Register $n of BLOCK10 (system).
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_0 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the $nth 32 bits of the 2nd part of system data.
+         */
+        uint32_t sys_data_part2_0:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data0_reg_t;
+
+/** Type of rd_sys_part2_data1 register
+ *  Register $n of BLOCK9 (KEY5).
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_1 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the $nth 32 bits of the 2nd part of system data.
+         */
+        uint32_t sys_data_part2_1:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data1_reg_t;
+
+/** Type of rd_sys_part2_data2 register
+ *  Register $n of BLOCK10 (system).
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_2 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the $nth 32 bits of the 2nd part of system data.
+         */
+        uint32_t sys_data_part2_2:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data2_reg_t;
+
+/** Type of rd_sys_part2_data3 register
+ *  Register $n of BLOCK10 (system).
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_3 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the $nth 32 bits of the 2nd part of system data.
+         */
+        uint32_t sys_data_part2_3:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data3_reg_t;
+
+/** Type of rd_sys_part2_data4 register
+ *  Register $n of BLOCK10 (system).
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_4 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the $nth 32 bits of the 2nd part of system data.
+         */
+        uint32_t sys_data_part2_4:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data4_reg_t;
+
+/** Type of rd_sys_part2_data5 register
+ *  Register $n of BLOCK10 (system).
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_5 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the $nth 32 bits of the 2nd part of system data.
+         */
+        uint32_t sys_data_part2_5:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data5_reg_t;
+
+/** Type of rd_sys_part2_data6 register
+ *  Register $n of BLOCK10 (system).
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_6 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the $nth 32 bits of the 2nd part of system data.
+         */
+        uint32_t sys_data_part2_6:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data6_reg_t;
+
+/** Type of rd_sys_part2_data7 register
+ *  Register $n of BLOCK10 (system).
+ */
+typedef union {
+    struct {
+        /** sys_data_part2_7 : RO; bitpos: [31:0]; default: 0;
+         *  Stores the $nth 32 bits of the 2nd part of system data.
+         */
+        uint32_t sys_data_part2_7:32;
+    };
+    uint32_t val;
+} efuse_rd_sys_part2_data7_reg_t;
+
+/** Type of rd_repeat_err0 register
+ *  Programming error record register 0 of BLOCK0.
+ */
+typedef union {
+    struct {
+        /** rd_dis_err : RO; bitpos: [6:0]; default: 0;
+         *  If any bit in RD_DIS is 1, then it indicates a programming error.
+         */
+        uint32_t rd_dis_err:7;
+        /** dis_rtc_ram_boot_err : RO; bitpos: [7]; default: 0;
+         *  If DIS_RTC_RAM_BOOT is 1, then it indicates a programming error.
+         */
+        uint32_t dis_rtc_ram_boot_err:1;
+        /** dis_icache_err : RO; bitpos: [8]; default: 0;
+         *  If DIS_ICACHE is 1, then it indicates a programming error.
+         */
+        uint32_t dis_icache_err:1;
+        /** dis_usb_jtag_err : RO; bitpos: [9]; default: 0;
+         *  If DIS_USB_JTAG is 1, then it indicates a programming error.
+         */
+        uint32_t dis_usb_jtag_err:1;
+        /** dis_download_icache_err : RO; bitpos: [10]; default: 0;
+         *  If DIS_DOWNLOAD_ICACHE is 1, then it indicates a programming error.
+         */
+        uint32_t dis_download_icache_err:1;
+        /** dis_usb_device_err : RO; bitpos: [11]; default: 0;
+         *  If DIS_USB_DEVICE is 1, then it indicates a programming error.
+         */
+        uint32_t dis_usb_device_err:1;
+        /** dis_force_download_err : RO; bitpos: [12]; default: 0;
+         *  If DIS_FORCE_DOWNLOAD is 1, then it indicates a programming error.
+         */
+        uint32_t dis_force_download_err:1;
+        /** dis_usb_err : RO; bitpos: [13]; default: 0;
+         *  If DIS_USB is 1, then it indicates a programming error.
+         */
+        uint32_t dis_usb_err:1;
+        /** dis_twai_err : RO; bitpos: [14]; default: 0;
+         *  If DIS_TWAI is 1, then it indicates a programming error.
+         */
+        uint32_t dis_twai_err:1;
+        /** jtag_sel_enable_err : RO; bitpos: [15]; default: 0;
+         *  If JTAG_SEL_ENABLE is 1, then it indicates a programming error.
+         */
+        uint32_t jtag_sel_enable_err:1;
+        /** soft_dis_jtag_err : RO; bitpos: [18:16]; default: 0;
+         *  If SOFT_DIS_JTAG is 1, then it indicates a programming error.
+         */
+        uint32_t soft_dis_jtag_err:3;
+        /** dis_pad_jtag_err : RO; bitpos: [19]; default: 0;
+         *  If DIS_PAD_JTAG is 1, then it indicates a programming error.
+         */
+        uint32_t dis_pad_jtag_err:1;
+        /** dis_download_manual_encrypt_err : RO; bitpos: [20]; default: 0;
+         *  If DIS_DOWNLOAD_MANUAL_ENCRYPT is 1, then it indicates a programming error.
+         */
+        uint32_t dis_download_manual_encrypt_err:1;
+        /** usb_drefh_err : RO; bitpos: [22:21]; default: 0;
+         *  If any bit in USB_DREFH is 1, then it indicates a programming error.
+         */
+        uint32_t usb_drefh_err:2;
+        /** usb_drefl_err : RO; bitpos: [24:23]; default: 0;
+         *  If any bit in USB_DREFL is 1, then it indicates a programming error.
+         */
+        uint32_t usb_drefl_err:2;
+        /** usb_exchg_pins_err : RO; bitpos: [25]; default: 0;
+         *  If USB_EXCHG_PINS is 1, then it indicates a programming error.
+         */
+        uint32_t usb_exchg_pins_err:1;
+        /** vdd_spi_as_gpio_err : RO; bitpos: [26]; default: 0;
+         *  If VDD_SPI_AS_GPIO is 1, then it indicates a programming error.
+         */
+        uint32_t vdd_spi_as_gpio_err:1;
+        /** btlc_gpio_enable_err : RO; bitpos: [28:27]; default: 0;
+         *  If any bit in BTLC_GPIO_ENABLE is 1, then it indicates a programming error.
+         */
+        uint32_t btlc_gpio_enable_err:2;
+        /** powerglitch_en_err : RO; bitpos: [29]; default: 0;
+         *  If POWERGLITCH_EN is 1, then it indicates a programming error.
+         */
+        uint32_t powerglitch_en_err:1;
+        /** power_glitch_dsense_err : RO; bitpos: [31:30]; default: 0;
+         *  If any bit in POWER_GLITCH_DSENSE is 1, then it indicates a programming error.
+         */
+        uint32_t power_glitch_dsense_err:2;
+    };
+    uint32_t val;
+} efuse_rd_repeat_err0_reg_t;
+
+/** Type of rd_repeat_err1 register
+ *  Programming error record register 1 of BLOCK0.
+ */
+typedef union {
+    struct {
+        /** rpt4_reserved2_err : RO; bitpos: [15:0]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rpt4_reserved2_err:16;
+        /** wdt_delay_sel_err : RO; bitpos: [17:16]; default: 0;
+         *  If any bit in WDT_DELAY_SEL is 1, then it indicates a programming error.
+         */
+        uint32_t wdt_delay_sel_err:2;
+        /** spi_boot_crypt_cnt_err : RO; bitpos: [20:18]; default: 0;
+         *  If any bit in SPI_BOOT_CRYPT_CNT is 1, then it indicates a programming error.
+         */
+        uint32_t spi_boot_crypt_cnt_err:3;
+        /** secure_boot_key_revoke0_err : RO; bitpos: [21]; default: 0;
+         *  If SECURE_BOOT_KEY_REVOKE0 is 1, then it indicates a programming error.
+         */
+        uint32_t secure_boot_key_revoke0_err:1;
+        /** secure_boot_key_revoke1_err : RO; bitpos: [22]; default: 0;
+         *  If SECURE_BOOT_KEY_REVOKE1 is 1, then it indicates a programming error.
+         */
+        uint32_t secure_boot_key_revoke1_err:1;
+        /** secure_boot_key_revoke2_err : RO; bitpos: [23]; default: 0;
+         *  If SECURE_BOOT_KEY_REVOKE2 is 1, then it indicates a programming error.
+         */
+        uint32_t secure_boot_key_revoke2_err:1;
+        /** key_purpose_0_err : RO; bitpos: [27:24]; default: 0;
+         *  If any bit in KEY_PURPOSE_0 is 1, then it indicates a programming error.
+         */
+        uint32_t key_purpose_0_err:4;
+        /** key_purpose_1_err : RO; bitpos: [31:28]; default: 0;
+         *  If any bit in KEY_PURPOSE_1 is 1, then it indicates a programming error.
+         */
+        uint32_t key_purpose_1_err:4;
+    };
+    uint32_t val;
+} efuse_rd_repeat_err1_reg_t;
+
+/** Type of rd_repeat_err2 register
+ *  Programming error record register 2 of BLOCK0.
+ */
+typedef union {
+    struct {
+        /** key_purpose_2_err : RO; bitpos: [3:0]; default: 0;
+         *  If any bit in KEY_PURPOSE_2 is 1, then it indicates a programming error.
+         */
+        uint32_t key_purpose_2_err:4;
+        /** key_purpose_3_err : RO; bitpos: [7:4]; default: 0;
+         *  If any bit in KEY_PURPOSE_3 is 1, then it indicates a programming error.
+         */
+        uint32_t key_purpose_3_err:4;
+        /** key_purpose_4_err : RO; bitpos: [11:8]; default: 0;
+         *  If any bit in KEY_PURPOSE_4 is 1, then it indicates a programming error.
+         */
+        uint32_t key_purpose_4_err:4;
+        /** key_purpose_5_err : RO; bitpos: [15:12]; default: 0;
+         *  If any bit in KEY_PURPOSE_5 is 1, then it indicates a programming error.
+         */
+        uint32_t key_purpose_5_err:4;
+        /** rpt4_reserved3_err : RO; bitpos: [19:16]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rpt4_reserved3_err:4;
+        /** secure_boot_en_err : RO; bitpos: [20]; default: 0;
+         *  If SECURE_BOOT_EN is 1, then it indicates a programming error.
+         */
+        uint32_t secure_boot_en_err:1;
+        /** secure_boot_aggressive_revoke_err : RO; bitpos: [21]; default: 0;
+         *  If SECURE_BOOT_AGGRESSIVE_REVOKE is 1, then it indicates a programming error.
+         */
+        uint32_t secure_boot_aggressive_revoke_err:1;
+        /** rpt4_reserved0_err : RO; bitpos: [27:22]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rpt4_reserved0_err:6;
+        /** flash_tpuw_err : RO; bitpos: [31:28]; default: 0;
+         *  If any bit in FLASH_TPUM is 1, then it indicates a programming error.
+         */
+        uint32_t flash_tpuw_err:4;
+    };
+    uint32_t val;
+} efuse_rd_repeat_err2_reg_t;
+
+/** Type of rd_repeat_err3 register
+ *  Programming error record register 3 of BLOCK0.
+ */
+typedef union {
+    struct {
+        /** dis_download_mode_err : RO; bitpos: [0]; default: 0;
+         *  If DIS_DOWNLOAD_MODE is 1, then it indicates a programming error.
+         */
+        uint32_t dis_download_mode_err:1;
+        /** dis_legacy_spi_boot_err : RO; bitpos: [1]; default: 0;
+         *  If DIS_LEGACY_SPI_BOOT is 1, then it indicates a programming error.
+         */
+        uint32_t dis_legacy_spi_boot_err:1;
+        /** uart_print_channel_err : RO; bitpos: [2]; default: 0;
+         *  If UART_PRINT_CHANNEL is 1, then it indicates a programming error.
+         */
+        uint32_t uart_print_channel_err:1;
+        /** flash_ecc_mode_err : RO; bitpos: [3]; default: 0;
+         *  If FLASH_ECC_MODE is 1, then it indicates a programming error.
+         */
+        uint32_t flash_ecc_mode_err:1;
+        /** dis_usb_download_mode_err : RO; bitpos: [4]; default: 0;
+         *  If DIS_USB_DOWNLOAD_MODE is 1, then it indicates a programming error.
+         */
+        uint32_t dis_usb_download_mode_err:1;
+        /** enable_security_download_err : RO; bitpos: [5]; default: 0;
+         *  If ENABLE_SECURITY_DOWNLOAD is 1, then it indicates a programming error.
+         */
+        uint32_t enable_security_download_err:1;
+        /** uart_print_control_err : RO; bitpos: [7:6]; default: 0;
+         *  If any bit in UART_PRINT_CONTROL is 1, then it indicates a programming error.
+         */
+        uint32_t uart_print_control_err:2;
+        /** pin_power_selection_err : RO; bitpos: [8]; default: 0;
+         *  If PIN_POWER_SELECTION is 1, then it indicates a programming error.
+         */
+        uint32_t pin_power_selection_err:1;
+        /** flash_type_err : RO; bitpos: [9]; default: 0;
+         *  If FLASH_TYPE is 1, then it indicates a programming error.
+         */
+        uint32_t flash_type_err:1;
+        /** flash_page_size_err : RO; bitpos: [11:10]; default: 0;
+         *  If any bits in FLASH_PAGE_SIZE is 1, then it indicates a programming error.
+         */
+        uint32_t flash_page_size_err:2;
+        /** flash_ecc_en_err : RO; bitpos: [12]; default: 0;
+         *  If FLASH_ECC_EN_ERR is 1, then it indicates a programming error.
+         */
+        uint32_t flash_ecc_en_err:1;
+        /** force_send_resume_err : RO; bitpos: [13]; default: 0;
+         *  If FORCE_SEND_RESUME is 1, then it indicates a programming error.
+         */
+        uint32_t force_send_resume_err:1;
+        /** secure_version_err : RO; bitpos: [29:14]; default: 0;
+         *  If any bit in SECURE_VERSION is 1, then it indicates a programming error.
+         */
+        uint32_t secure_version_err:16;
+        /** rpt4_reserved1_err : RO; bitpos: [31:30]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rpt4_reserved1_err:2;
+    };
+    uint32_t val;
+} efuse_rd_repeat_err3_reg_t;
+
+/** Type of rd_repeat_err4 register
+ *  Programming error record register 4 of BLOCK0.
+ */
+typedef union {
+    struct {
+        /** rpt4_reserved4_err : RO; bitpos: [23:0]; default: 0;
+         *  Reserved.
+         */
+        uint32_t rpt4_reserved4_err:24;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} efuse_rd_repeat_err4_reg_t;
+
+/** Type of rd_rs_err0 register
+ *  Programming error record register 0 of BLOCK1-10.
+ */
+typedef union {
+    struct {
+        /** mac_spi_8m_err_num : RO; bitpos: [2:0]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t mac_spi_8m_err_num:3;
+        /** mac_spi_8m_fail : RO; bitpos: [3]; default: 0;
+         *  0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that
+         *  programming user data failed and the number of error bytes is over 6.
+         */
+        uint32_t mac_spi_8m_fail:1;
+        /** sys_part1_num : RO; bitpos: [6:4]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t sys_part1_num:3;
+        /** sys_part1_fail : RO; bitpos: [7]; default: 0;
+         *  0: Means no failure and that the data of system part1 is reliable 1: Means that
+         *  programming user data failed and the number of error bytes is over 6.
+         */
+        uint32_t sys_part1_fail:1;
+        /** usr_data_err_num : RO; bitpos: [10:8]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t usr_data_err_num:3;
+        /** usr_data_fail : RO; bitpos: [11]; default: 0;
+         *  0: Means no failure and that the user data is reliable 1: Means that programming
+         *  user data failed and the number of error bytes is over 6.
+         */
+        uint32_t usr_data_fail:1;
+        /** key0_err_num : RO; bitpos: [14:12]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t key0_err_num:3;
+        /** key0_fail : RO; bitpos: [15]; default: 0;
+         *  0: Means no failure and that the data of key$n is reliable 1: Means that
+         *  programming key$n failed and the number of error bytes is over 6.
+         */
+        uint32_t key0_fail:1;
+        /** key1_err_num : RO; bitpos: [18:16]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t key1_err_num:3;
+        /** key1_fail : RO; bitpos: [19]; default: 0;
+         *  0: Means no failure and that the data of key$n is reliable 1: Means that
+         *  programming key$n failed and the number of error bytes is over 6.
+         */
+        uint32_t key1_fail:1;
+        /** key2_err_num : RO; bitpos: [22:20]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t key2_err_num:3;
+        /** key2_fail : RO; bitpos: [23]; default: 0;
+         *  0: Means no failure and that the data of key$n is reliable 1: Means that
+         *  programming key$n failed and the number of error bytes is over 6.
+         */
+        uint32_t key2_fail:1;
+        /** key3_err_num : RO; bitpos: [26:24]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t key3_err_num:3;
+        /** key3_fail : RO; bitpos: [27]; default: 0;
+         *  0: Means no failure and that the data of key$n is reliable 1: Means that
+         *  programming key$n failed and the number of error bytes is over 6.
+         */
+        uint32_t key3_fail:1;
+        /** key4_err_num : RO; bitpos: [30:28]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t key4_err_num:3;
+        /** key4_fail : RO; bitpos: [31]; default: 0;
+         *  0: Means no failure and that the data of key$n is reliable 1: Means that
+         *  programming key$n failed and the number of error bytes is over 6.
+         */
+        uint32_t key4_fail:1;
+    };
+    uint32_t val;
+} efuse_rd_rs_err0_reg_t;
+
+/** Type of rd_rs_err1 register
+ *  Programming error record register 1 of BLOCK1-10.
+ */
+typedef union {
+    struct {
+        /** key5_err_num : RO; bitpos: [2:0]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t key5_err_num:3;
+        /** key5_fail : RO; bitpos: [3]; default: 0;
+         *  0: Means no failure and that the data of KEY5 is reliable 1: Means that programming
+         *  user data failed and the number of error bytes is over 6.
+         */
+        uint32_t key5_fail:1;
+        /** sys_part2_err_num : RO; bitpos: [6:4]; default: 0;
+         *  The value of this signal means the number of error bytes.
+         */
+        uint32_t sys_part2_err_num:3;
+        /** sys_part2_fail : RO; bitpos: [7]; default: 0;
+         *  0: Means no failure and that the data of system part2 is reliable 1: Means that
+         *  programming user data failed and the number of error bytes is over 6.
+         */
+        uint32_t sys_part2_fail:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} efuse_rd_rs_err1_reg_t;
+
+/** Type of clk register
+ *  eFuse clcok configuration register.
+ */
+typedef union {
+    struct {
+        /** mem_force_pd : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to force eFuse SRAM into power-saving mode.
+         */
+        uint32_t mem_force_pd:1;
+        /** mem_clk_force_on : R/W; bitpos: [1]; default: 1;
+         *  Set this bit and force to activate clock signal of eFuse SRAM.
+         */
+        uint32_t mem_clk_force_on:1;
+        /** mem_force_pu : R/W; bitpos: [2]; default: 0;
+         *  Set this bit to force eFuse SRAM into working mode.
+         */
+        uint32_t mem_force_pu:1;
+        uint32_t reserved_3:13;
+        /** clk_en : R/W; bitpos: [16]; default: 0;
+         *  Set this bit and force to enable clock signal of eFuse memory.
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} efuse_clk_reg_t;
+
+/** Type of conf register
+ *  eFuse operation mode configuraiton register
+ */
+typedef union {
+    struct {
+        /** op_code : R/W; bitpos: [15:0]; default: 0;
+         *  0x5A5A: Operate programming command 0x5AA5: Operate read command.
+         */
+        uint32_t op_code:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} efuse_conf_reg_t;
+
+/** Type of status register
+ *  eFuse status register.
+ */
+typedef union {
+    struct {
+        /** state : RO; bitpos: [3:0]; default: 0;
+         *  Indicates the state of the eFuse state machine.
+         */
+        uint32_t state:4;
+        /** otp_load_sw : RO; bitpos: [4]; default: 0;
+         *  The value of OTP_LOAD_SW.
+         */
+        uint32_t otp_load_sw:1;
+        /** otp_vddq_c_sync2 : RO; bitpos: [5]; default: 0;
+         *  The value of OTP_VDDQ_C_SYNC2.
+         */
+        uint32_t otp_vddq_c_sync2:1;
+        /** otp_strobe_sw : RO; bitpos: [6]; default: 0;
+         *  The value of OTP_STROBE_SW.
+         */
+        uint32_t otp_strobe_sw:1;
+        /** otp_csb_sw : RO; bitpos: [7]; default: 0;
+         *  The value of OTP_CSB_SW.
+         */
+        uint32_t otp_csb_sw:1;
+        /** otp_pgenb_sw : RO; bitpos: [8]; default: 0;
+         *  The value of OTP_PGENB_SW.
+         */
+        uint32_t otp_pgenb_sw:1;
+        /** otp_vddq_is_sw : RO; bitpos: [9]; default: 0;
+         *  The value of OTP_VDDQ_IS_SW.
+         */
+        uint32_t otp_vddq_is_sw:1;
+        /** repeat_err_cnt : RO; bitpos: [17:10]; default: 0;
+         *  Indicates the number of error bits during programming BLOCK0.
+         */
+        uint32_t repeat_err_cnt:8;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} efuse_status_reg_t;
+
+/** Type of cmd register
+ *  eFuse command register.
+ */
+typedef union {
+    struct {
+        /** read_cmd : R/W; bitpos: [0]; default: 0;
+         *  Set this bit to send read command.
+         */
+        uint32_t read_cmd:1;
+        /** pgm_cmd : R/W; bitpos: [1]; default: 0;
+         *  Set this bit to send programming command.
+         */
+        uint32_t pgm_cmd:1;
+        /** blk_num : R/W; bitpos: [5:2]; default: 0;
+         *  The serial number of the block to be programmed. Value 0-10 corresponds to block
+         *  number 0-10, respectively.
+         */
+        uint32_t blk_num:4;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} efuse_cmd_reg_t;
+
+/** Type of int_raw register
+ *  eFuse raw interrupt register.
+ */
+typedef union {
+    struct {
+        /** read_done_int_raw : RO; bitpos: [0]; default: 0;
+         *  The raw bit signal for read_done interrupt.
+         */
+        uint32_t read_done_int_raw:1;
+        /** pgm_done_int_raw : RO; bitpos: [1]; default: 0;
+         *  The raw bit signal for pgm_done interrupt.
+         */
+        uint32_t pgm_done_int_raw:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} efuse_int_raw_reg_t;
+
+/** Type of int_st register
+ *  eFuse interrupt status register.
+ */
+typedef union {
+    struct {
+        /** read_done_int_st : RO; bitpos: [0]; default: 0;
+         *  The status signal for read_done interrupt.
+         */
+        uint32_t read_done_int_st:1;
+        /** pgm_done_int_st : RO; bitpos: [1]; default: 0;
+         *  The status signal for pgm_done interrupt.
+         */
+        uint32_t pgm_done_int_st:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} efuse_int_st_reg_t;
+
+/** Type of int_ena register
+ *  eFuse interrupt enable register.
+ */
+typedef union {
+    struct {
+        /** read_done_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The enable signal for read_done interrupt.
+         */
+        uint32_t read_done_int_ena:1;
+        /** pgm_done_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The enable signal for pgm_done interrupt.
+         */
+        uint32_t pgm_done_int_ena:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} efuse_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  eFuse interrupt clear register.
+ */
+typedef union {
+    struct {
+        /** read_done_int_clr : WO; bitpos: [0]; default: 0;
+         *  The clear signal for read_done interrupt.
+         */
+        uint32_t read_done_int_clr:1;
+        /** pgm_done_int_clr : WO; bitpos: [1]; default: 0;
+         *  The clear signal for pgm_done interrupt.
+         */
+        uint32_t pgm_done_int_clr:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} efuse_int_clr_reg_t;
+
+/** Type of dac_conf register
+ *  Controls the eFuse programming voltage.
+ */
+typedef union {
+    struct {
+        /** dac_clk_div : R/W; bitpos: [7:0]; default: 28;
+         *  Controls the division factor of the rising clock of the programming voltage.
+         */
+        uint32_t dac_clk_div:8;
+        /** dac_clk_pad_sel : R/W; bitpos: [8]; default: 0;
+         *  Don't care.
+         */
+        uint32_t dac_clk_pad_sel:1;
+        /** dac_num : R/W; bitpos: [16:9]; default: 255;
+         *  Controls the rising period of the programming voltage.
+         */
+        uint32_t dac_num:8;
+        /** oe_clr : R/W; bitpos: [17]; default: 0;
+         *  Reduces the power supply of the programming voltage.
+         */
+        uint32_t oe_clr:1;
+        uint32_t reserved_18:14;
+    };
+    uint32_t val;
+} efuse_dac_conf_reg_t;
+
+/** Type of rd_tim_conf register
+ *  Configures read timing parameters.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:24;
+        /** read_init_num : R/W; bitpos: [31:24]; default: 18;
+         *  Configures the initial read time of eFuse.
+         */
+        uint32_t read_init_num:8;
+    };
+    uint32_t val;
+} efuse_rd_tim_conf_reg_t;
+
+/** Type of wr_tim_conf1 register
+ *  Configurarion register 1 of eFuse programming timing parameters.
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:8;
+        /** pwr_on_num : R/W; bitpos: [23:8]; default: 10368;
+         *  Configures the power up time for VDDQ.
+         */
+        uint32_t pwr_on_num:16;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} efuse_wr_tim_conf1_reg_t;
+
+/** Type of wr_tim_conf2 register
+ *  Configurarion register 2 of eFuse programming timing parameters.
+ */
+typedef union {
+    struct {
+        /** pwr_off_num : R/W; bitpos: [15:0]; default: 400;
+         *  Configures the power outage time for VDDQ.
+         */
+        uint32_t pwr_off_num:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} efuse_wr_tim_conf2_reg_t;
+
+/** Type of date register
+ *  eFuse version register.
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [27:0]; default: 33583616;
+         *  Stores eFuse version.
+         */
+        uint32_t date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} efuse_date_reg_t;
+
+
+typedef struct {
+    volatile efuse_pgm_data0_reg_t pgm_data0;
+    volatile efuse_pgm_data1_reg_t pgm_data1;
+    volatile efuse_pgm_data2_reg_t pgm_data2;
+    volatile efuse_pgm_data3_reg_t pgm_data3;
+    volatile efuse_pgm_data4_reg_t pgm_data4;
+    volatile efuse_pgm_data5_reg_t pgm_data5;
+    volatile efuse_pgm_data6_reg_t pgm_data6;
+    volatile efuse_pgm_data7_reg_t pgm_data7;
+    volatile efuse_pgm_check_value0_reg_t pgm_check_value0;
+    volatile efuse_pgm_check_value1_reg_t pgm_check_value1;
+    volatile efuse_pgm_check_value2_reg_t pgm_check_value2;
+    volatile efuse_rd_wr_dis_reg_t rd_wr_dis;
+    volatile efuse_rd_repeat_data0_reg_t rd_repeat_data0;
+    volatile efuse_rd_repeat_data1_reg_t rd_repeat_data1;
+    volatile efuse_rd_repeat_data2_reg_t rd_repeat_data2;
+    volatile efuse_rd_repeat_data3_reg_t rd_repeat_data3;
+    volatile efuse_rd_repeat_data4_reg_t rd_repeat_data4;
+    volatile efuse_rd_mac_spi_sys_0_reg_t rd_mac_spi_sys_0;
+    volatile efuse_rd_mac_spi_sys_1_reg_t rd_mac_spi_sys_1;
+    volatile efuse_rd_mac_spi_sys_2_reg_t rd_mac_spi_sys_2;
+    volatile efuse_rd_mac_spi_sys_3_reg_t rd_mac_spi_sys_3;
+    volatile efuse_rd_mac_spi_sys_4_reg_t rd_mac_spi_sys_4;
+    volatile efuse_rd_mac_spi_sys_5_reg_t rd_mac_spi_sys_5;
+    volatile efuse_rd_sys_part1_data0_reg_t rd_sys_part1_data0;
+    volatile efuse_rd_sys_part1_data1_reg_t rd_sys_part1_data1;
+    volatile efuse_rd_sys_part1_data2_reg_t rd_sys_part1_data2;
+    volatile efuse_rd_sys_part1_data3_reg_t rd_sys_part1_data3;
+    volatile efuse_rd_sys_part1_data4_reg_t rd_sys_part1_data4;
+    volatile efuse_rd_sys_part1_data5_reg_t rd_sys_part1_data5;
+    volatile efuse_rd_sys_part1_data6_reg_t rd_sys_part1_data6;
+    volatile efuse_rd_sys_part1_data7_reg_t rd_sys_part1_data7;
+    volatile efuse_rd_usr_data0_reg_t rd_usr_data0;
+    volatile efuse_rd_usr_data1_reg_t rd_usr_data1;
+    volatile efuse_rd_usr_data2_reg_t rd_usr_data2;
+    volatile efuse_rd_usr_data3_reg_t rd_usr_data3;
+    volatile efuse_rd_usr_data4_reg_t rd_usr_data4;
+    volatile efuse_rd_usr_data5_reg_t rd_usr_data5;
+    volatile efuse_rd_usr_data6_reg_t rd_usr_data6;
+    volatile efuse_rd_usr_data7_reg_t rd_usr_data7;
+    volatile efuse_rd_key0_data0_reg_t rd_key0_data0;
+    volatile efuse_rd_key0_data1_reg_t rd_key0_data1;
+    volatile efuse_rd_key0_data2_reg_t rd_key0_data2;
+    volatile efuse_rd_key0_data3_reg_t rd_key0_data3;
+    volatile efuse_rd_key0_data4_reg_t rd_key0_data4;
+    volatile efuse_rd_key0_data5_reg_t rd_key0_data5;
+    volatile efuse_rd_key0_data6_reg_t rd_key0_data6;
+    volatile efuse_rd_key0_data7_reg_t rd_key0_data7;
+    volatile efuse_rd_key1_data0_reg_t rd_key1_data0;
+    volatile efuse_rd_key1_data1_reg_t rd_key1_data1;
+    volatile efuse_rd_key1_data2_reg_t rd_key1_data2;
+    volatile efuse_rd_key1_data3_reg_t rd_key1_data3;
+    volatile efuse_rd_key1_data4_reg_t rd_key1_data4;
+    volatile efuse_rd_key1_data5_reg_t rd_key1_data5;
+    volatile efuse_rd_key1_data6_reg_t rd_key1_data6;
+    volatile efuse_rd_key1_data7_reg_t rd_key1_data7;
+    volatile efuse_rd_key2_data0_reg_t rd_key2_data0;
+    volatile efuse_rd_key2_data1_reg_t rd_key2_data1;
+    volatile efuse_rd_key2_data2_reg_t rd_key2_data2;
+    volatile efuse_rd_key2_data3_reg_t rd_key2_data3;
+    volatile efuse_rd_key2_data4_reg_t rd_key2_data4;
+    volatile efuse_rd_key2_data5_reg_t rd_key2_data5;
+    volatile efuse_rd_key2_data6_reg_t rd_key2_data6;
+    volatile efuse_rd_key2_data7_reg_t rd_key2_data7;
+    volatile efuse_rd_key3_data0_reg_t rd_key3_data0;
+    volatile efuse_rd_key3_data1_reg_t rd_key3_data1;
+    volatile efuse_rd_key3_data2_reg_t rd_key3_data2;
+    volatile efuse_rd_key3_data3_reg_t rd_key3_data3;
+    volatile efuse_rd_key3_data4_reg_t rd_key3_data4;
+    volatile efuse_rd_key3_data5_reg_t rd_key3_data5;
+    volatile efuse_rd_key3_data6_reg_t rd_key3_data6;
+    volatile efuse_rd_key3_data7_reg_t rd_key3_data7;
+    volatile efuse_rd_key4_data0_reg_t rd_key4_data0;
+    volatile efuse_rd_key4_data1_reg_t rd_key4_data1;
+    volatile efuse_rd_key4_data2_reg_t rd_key4_data2;
+    volatile efuse_rd_key4_data3_reg_t rd_key4_data3;
+    volatile efuse_rd_key4_data4_reg_t rd_key4_data4;
+    volatile efuse_rd_key4_data5_reg_t rd_key4_data5;
+    volatile efuse_rd_key4_data6_reg_t rd_key4_data6;
+    volatile efuse_rd_key4_data7_reg_t rd_key4_data7;
+    volatile efuse_rd_key5_data0_reg_t rd_key5_data0;
+    volatile efuse_rd_key5_data1_reg_t rd_key5_data1;
+    volatile efuse_rd_key5_data2_reg_t rd_key5_data2;
+    volatile efuse_rd_key5_data3_reg_t rd_key5_data3;
+    volatile efuse_rd_key5_data4_reg_t rd_key5_data4;
+    volatile efuse_rd_key5_data5_reg_t rd_key5_data5;
+    volatile efuse_rd_key5_data6_reg_t rd_key5_data6;
+    volatile efuse_rd_key5_data7_reg_t rd_key5_data7;
+    volatile efuse_rd_sys_part2_data0_reg_t rd_sys_part2_data0;
+    volatile efuse_rd_sys_part2_data1_reg_t rd_sys_part2_data1;
+    volatile efuse_rd_sys_part2_data2_reg_t rd_sys_part2_data2;
+    volatile efuse_rd_sys_part2_data3_reg_t rd_sys_part2_data3;
+    volatile efuse_rd_sys_part2_data4_reg_t rd_sys_part2_data4;
+    volatile efuse_rd_sys_part2_data5_reg_t rd_sys_part2_data5;
+    volatile efuse_rd_sys_part2_data6_reg_t rd_sys_part2_data6;
+    volatile efuse_rd_sys_part2_data7_reg_t rd_sys_part2_data7;
+    volatile efuse_rd_repeat_err0_reg_t rd_repeat_err0;
+    volatile efuse_rd_repeat_err1_reg_t rd_repeat_err1;
+    volatile efuse_rd_repeat_err2_reg_t rd_repeat_err2;
+    volatile efuse_rd_repeat_err3_reg_t rd_repeat_err3;
+    uint32_t reserved_18c;
+    volatile efuse_rd_repeat_err4_reg_t rd_repeat_err4;
+    uint32_t reserved_194[11];
+    volatile efuse_rd_rs_err0_reg_t rd_rs_err0;
+    volatile efuse_rd_rs_err1_reg_t rd_rs_err1;
+    volatile efuse_clk_reg_t clk;
+    volatile efuse_conf_reg_t conf;
+    volatile efuse_status_reg_t status;
+    volatile efuse_cmd_reg_t cmd;
+    volatile efuse_int_raw_reg_t int_raw;
+    volatile efuse_int_st_reg_t int_st;
+    volatile efuse_int_ena_reg_t int_ena;
+    volatile efuse_int_clr_reg_t int_clr;
+    volatile efuse_dac_conf_reg_t dac_conf;
+    volatile efuse_rd_tim_conf_reg_t rd_tim_conf;
+    volatile efuse_wr_tim_conf1_reg_t wr_tim_conf1;
+    volatile efuse_wr_tim_conf2_reg_t wr_tim_conf2;
+    uint32_t reserved_1f8;
+    volatile efuse_date_reg_t date;
+} efuse_dev_t;
+
+
+#ifndef __cplusplus
+_Static_assert(sizeof(efuse_dev_t) == 0x200, "Invalid size of efuse_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32h2/include/rev2/soc/gpio_sd_reg.h

@@ -1,175 +1,229 @@
-/*
- * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
+/**
+ * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
  *
- * SPDX-License-Identifier: Apache-2.0
+ *  SPDX-License-Identifier: Apache-2.0
  */
-#ifndef _SOC_GPIO_SD_REG_H_
-#define _SOC_GPIO_SD_REG_H_
+#pragma once
 
+#include <stdint.h>
 #include "soc/soc.h"
-
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-#define GPIO_SIGMADELTA0_REG          (DR_REG_GPIO_SD_BASE + 0x0)
-/* GPIO_SD0_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
-/*description: This field is used to set a divider value to divide APB clock..*/
-#define GPIO_SD0_PRESCALE    0x000000FF
-#define GPIO_SD0_PRESCALE_M  ((GPIO_SD0_PRESCALE_V)<<(GPIO_SD0_PRESCALE_S))
-#define GPIO_SD0_PRESCALE_V  0xFF
-#define GPIO_SD0_PRESCALE_S  8
-/* GPIO_SD0_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: This field is used to configure the duty cycle of sigma delta modulation output..*/
-#define GPIO_SD0_IN    0x000000FF
-#define GPIO_SD0_IN_M  ((GPIO_SD0_IN_V)<<(GPIO_SD0_IN_S))
-#define GPIO_SD0_IN_V  0xFF
-#define GPIO_SD0_IN_S  0
+/** GPIO_SD_SIGMADELTA0_REG register
+ *  Duty Cycle Configure Register of SDM0
+ */
+#define GPIO_SD_SIGMADELTA0_REG (DR_REG_GPIO_SD_BASE + 0x0)
+/** GPIO_SD_SD0_IN : R/W; bitpos: [7:0]; default: 0;
+ *  This field is used to configure the duty cycle of sigma delta modulation output.
+ */
+#define GPIO_SD_SD0_IN    0x000000FFU
+#define GPIO_SD_SD0_IN_M  (GPIO_SD_SD0_IN_V << GPIO_SD_SD0_IN_S)
+#define GPIO_SD_SD0_IN_V  0x000000FFU
+#define GPIO_SD_SD0_IN_S  0
+/** GPIO_SD_SD0_PRESCALE : R/W; bitpos: [15:8]; default: 255;
+ *  This field is used to set a divider value to divide APB clock.
+ */
+#define GPIO_SD_SD0_PRESCALE    0x000000FFU
+#define GPIO_SD_SD0_PRESCALE_M  (GPIO_SD_SD0_PRESCALE_V << GPIO_SD_SD0_PRESCALE_S)
+#define GPIO_SD_SD0_PRESCALE_V  0x000000FFU
+#define GPIO_SD_SD0_PRESCALE_S  8
 
-#define GPIO_SIGMADELTA1_REG          (DR_REG_GPIO_SD_BASE + 0x4)
-/* GPIO_SD1_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
-/*description: This field is used to set a divider value to divide APB clock..*/
-#define GPIO_SD1_PRESCALE    0x000000FF
-#define GPIO_SD1_PRESCALE_M  ((GPIO_SD1_PRESCALE_V)<<(GPIO_SD1_PRESCALE_S))
-#define GPIO_SD1_PRESCALE_V  0xFF
-#define GPIO_SD1_PRESCALE_S  8
-/* GPIO_SD1_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: This field is used to configure the duty cycle of sigma delta modulation output..*/
-#define GPIO_SD1_IN    0x000000FF
-#define GPIO_SD1_IN_M  ((GPIO_SD1_IN_V)<<(GPIO_SD1_IN_S))
-#define GPIO_SD1_IN_V  0xFF
-#define GPIO_SD1_IN_S  0
+/** GPIO_SD_SIGMADELTA1_REG register
+ *  Duty Cycle Configure Register of SDM1
+ */
+#define GPIO_SD_SIGMADELTA1_REG (DR_REG_GPIO_SD_BASE + 0x4)
+/** GPIO_SD_SD0_IN : R/W; bitpos: [7:0]; default: 0;
+ *  This field is used to configure the duty cycle of sigma delta modulation output.
+ */
+#define GPIO_SD_SD0_IN    0x000000FFU
+#define GPIO_SD_SD0_IN_M  (GPIO_SD_SD0_IN_V << GPIO_SD_SD0_IN_S)
+#define GPIO_SD_SD0_IN_V  0x000000FFU
+#define GPIO_SD_SD0_IN_S  0
+/** GPIO_SD_SD0_PRESCALE : R/W; bitpos: [15:8]; default: 255;
+ *  This field is used to set a divider value to divide APB clock.
+ */
+#define GPIO_SD_SD0_PRESCALE    0x000000FFU
+#define GPIO_SD_SD0_PRESCALE_M  (GPIO_SD_SD0_PRESCALE_V << GPIO_SD_SD0_PRESCALE_S)
+#define GPIO_SD_SD0_PRESCALE_V  0x000000FFU
+#define GPIO_SD_SD0_PRESCALE_S  8
 
-#define GPIO_SIGMADELTA2_REG          (DR_REG_GPIO_SD_BASE + 0x8)
-/* GPIO_SD2_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
-/*description: This field is used to set a divider value to divide APB clock..*/
-#define GPIO_SD2_PRESCALE    0x000000FF
-#define GPIO_SD2_PRESCALE_M  ((GPIO_SD2_PRESCALE_V)<<(GPIO_SD2_PRESCALE_S))
-#define GPIO_SD2_PRESCALE_V  0xFF
-#define GPIO_SD2_PRESCALE_S  8
-/* GPIO_SD2_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: This field is used to configure the duty cycle of sigma delta modulation output..*/
-#define GPIO_SD2_IN    0x000000FF
-#define GPIO_SD2_IN_M  ((GPIO_SD2_IN_V)<<(GPIO_SD2_IN_S))
-#define GPIO_SD2_IN_V  0xFF
-#define GPIO_SD2_IN_S  0
+/** GPIO_SD_SIGMADELTA2_REG register
+ *  Duty Cycle Configure Register of SDM2
+ */
+#define GPIO_SD_SIGMADELTA2_REG (DR_REG_GPIO_SD_BASE + 0x8)
+/** GPIO_SD_SD0_IN : R/W; bitpos: [7:0]; default: 0;
+ *  This field is used to configure the duty cycle of sigma delta modulation output.
+ */
+#define GPIO_SD_SD0_IN    0x000000FFU
+#define GPIO_SD_SD0_IN_M  (GPIO_SD_SD0_IN_V << GPIO_SD_SD0_IN_S)
+#define GPIO_SD_SD0_IN_V  0x000000FFU
+#define GPIO_SD_SD0_IN_S  0
+/** GPIO_SD_SD0_PRESCALE : R/W; bitpos: [15:8]; default: 255;
+ *  This field is used to set a divider value to divide APB clock.
+ */
+#define GPIO_SD_SD0_PRESCALE    0x000000FFU
+#define GPIO_SD_SD0_PRESCALE_M  (GPIO_SD_SD0_PRESCALE_V << GPIO_SD_SD0_PRESCALE_S)
+#define GPIO_SD_SD0_PRESCALE_V  0x000000FFU
+#define GPIO_SD_SD0_PRESCALE_S  8
 
-#define GPIO_SIGMADELTA3_REG          (DR_REG_GPIO_SD_BASE + 0xC)
-/* GPIO_SD3_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
-/*description: This field is used to set a divider value to divide APB clock..*/
-#define GPIO_SD3_PRESCALE    0x000000FF
-#define GPIO_SD3_PRESCALE_M  ((GPIO_SD3_PRESCALE_V)<<(GPIO_SD3_PRESCALE_S))
-#define GPIO_SD3_PRESCALE_V  0xFF
-#define GPIO_SD3_PRESCALE_S  8
-/* GPIO_SD3_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
-/*description: This field is used to configure the duty cycle of sigma delta modulation output..*/
-#define GPIO_SD3_IN    0x000000FF
-#define GPIO_SD3_IN_M  ((GPIO_SD3_IN_V)<<(GPIO_SD3_IN_S))
-#define GPIO_SD3_IN_V  0xFF
-#define GPIO_SD3_IN_S  0
+/** GPIO_SD_SIGMADELTA3_REG register
+ *  Duty Cycle Configure Register of SDM3
+ */
+#define GPIO_SD_SIGMADELTA3_REG (DR_REG_GPIO_SD_BASE + 0xc)
+/** GPIO_SD_SD0_IN : R/W; bitpos: [7:0]; default: 0;
+ *  This field is used to configure the duty cycle of sigma delta modulation output.
+ */
+#define GPIO_SD_SD0_IN    0x000000FFU
+#define GPIO_SD_SD0_IN_M  (GPIO_SD_SD0_IN_V << GPIO_SD_SD0_IN_S)
+#define GPIO_SD_SD0_IN_V  0x000000FFU
+#define GPIO_SD_SD0_IN_S  0
+/** GPIO_SD_SD0_PRESCALE : R/W; bitpos: [15:8]; default: 255;
+ *  This field is used to set a divider value to divide APB clock.
+ */
+#define GPIO_SD_SD0_PRESCALE    0x000000FFU
+#define GPIO_SD_SD0_PRESCALE_M  (GPIO_SD_SD0_PRESCALE_V << GPIO_SD_SD0_PRESCALE_S)
+#define GPIO_SD_SD0_PRESCALE_V  0x000000FFU
+#define GPIO_SD_SD0_PRESCALE_S  8
 
-#define GPIO_SIGMADELTA_CG_REG          (DR_REG_GPIO_SD_BASE + 0x20)
-/* GPIO_SD_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
-/*description: Clock enable bit of configuration registers for sigma delta modulation..*/
+/** GPIO_SD_SIGMADELTA_CG_REG register
+ *  Clock Gating Configure Register
+ */
+#define GPIO_SD_SIGMADELTA_CG_REG (DR_REG_GPIO_SD_BASE + 0x20)
+/** GPIO_SD_CLK_EN : R/W; bitpos: [31]; default: 0;
+ *  Clock enable bit of configuration registers for sigma delta modulation.
+ */
 #define GPIO_SD_CLK_EN    (BIT(31))
-#define GPIO_SD_CLK_EN_M  (BIT(31))
-#define GPIO_SD_CLK_EN_V  0x1
+#define GPIO_SD_CLK_EN_M  (GPIO_SD_CLK_EN_V << GPIO_SD_CLK_EN_S)
+#define GPIO_SD_CLK_EN_V  0x00000001U
 #define GPIO_SD_CLK_EN_S  31
 
-#define GPIO_SIGMADELTA_MISC_REG          (DR_REG_GPIO_SD_BASE + 0x24)
-/* GPIO_SPI_SWAP : R/W ;bitpos:[31] ;default: 1'h0 ; */
-/*description: Reserved..*/
-#define GPIO_SPI_SWAP    (BIT(31))
-#define GPIO_SPI_SWAP_M  (BIT(31))
-#define GPIO_SPI_SWAP_V  0x1
-#define GPIO_SPI_SWAP_S  31
-/* GPIO_FUNCTION_CLK_EN : R/W ;bitpos:[30] ;default: 1'd0 ; */
-/*description: Clock enable bit of sigma delta modulation..*/
-#define GPIO_FUNCTION_CLK_EN    (BIT(30))
-#define GPIO_FUNCTION_CLK_EN_M  (BIT(30))
-#define GPIO_FUNCTION_CLK_EN_V  0x1
-#define GPIO_FUNCTION_CLK_EN_S  30
-
-#define GPIO_PAD_COMP_CONFIG_REG          (DR_REG_GPIO_SD_BASE + 0x28)
-/* GPIO_ZERO_DET_MODE : R/W ;bitpos:[5:4] ;default: 2'h0 ; */
-/*description: Zero Detect mode select..*/
-#define GPIO_ZERO_DET_MODE    0x00000003
-#define GPIO_ZERO_DET_MODE_M  ((GPIO_ZERO_DET_MODE_V)<<(GPIO_ZERO_DET_MODE_S))
-#define GPIO_ZERO_DET_MODE_V  0x3
-#define GPIO_ZERO_DET_MODE_S  4
-/* GPIO_DREF_COMP : R/W ;bitpos:[3:2] ;default: 2'h0 ; */
-/*description: internal reference voltage tuning bit. 0V to 0.7*VDDPST step 0.1*VDDPST..*/
-#define GPIO_DREF_COMP    0x00000003
-#define GPIO_DREF_COMP_M  ((GPIO_DREF_COMP_V)<<(GPIO_DREF_COMP_S))
-#define GPIO_DREF_COMP_V  0x3
-#define GPIO_DREF_COMP_S  2
-/* GPIO_MODE_COMP : R/W ;bitpos:[1] ;default: 1'h0 ; */
-/*description: 1 to enable external reference from PAD[0]. 0 to enable internal reference, mean
-while PAD[0] can be used as a regular GPIO..*/
-#define GPIO_MODE_COMP    (BIT(1))
-#define GPIO_MODE_COMP_M  (BIT(1))
-#define GPIO_MODE_COMP_V  0x1
-#define GPIO_MODE_COMP_S  1
-/* GPIO_XPD_COMP : R/W ;bitpos:[0] ;default: 1'h0 ; */
-/*description: Pad compare enable bit..*/
-#define GPIO_XPD_COMP    (BIT(0))
-#define GPIO_XPD_COMP_M  (BIT(0))
-#define GPIO_XPD_COMP_V  0x1
-#define GPIO_XPD_COMP_S  0
+/** GPIO_SD_SIGMADELTA_MISC_REG register
+ *  MISC Register
+ */
+#define GPIO_SD_SIGMADELTA_MISC_REG (DR_REG_GPIO_SD_BASE + 0x24)
+/** GPIO_SD_FUNCTION_CLK_EN : R/W; bitpos: [30]; default: 0;
+ *  Clock enable bit of sigma delta modulation.
+ */
+#define GPIO_SD_FUNCTION_CLK_EN    (BIT(30))
+#define GPIO_SD_FUNCTION_CLK_EN_M  (GPIO_SD_FUNCTION_CLK_EN_V << GPIO_SD_FUNCTION_CLK_EN_S)
+#define GPIO_SD_FUNCTION_CLK_EN_V  0x00000001U
+#define GPIO_SD_FUNCTION_CLK_EN_S  30
+/** GPIO_SD_SPI_SWAP : R/W; bitpos: [31]; default: 0;
+ *  Reserved.
+ */
+#define GPIO_SD_SPI_SWAP    (BIT(31))
+#define GPIO_SD_SPI_SWAP_M  (GPIO_SD_SPI_SWAP_V << GPIO_SD_SPI_SWAP_S)
+#define GPIO_SD_SPI_SWAP_V  0x00000001U
+#define GPIO_SD_SPI_SWAP_S  31
 
-#define GPIO_PAD_COMP_FILTER_REG          (DR_REG_GPIO_SD_BASE + 0x2C)
-/* GPIO_ZERO_DET_FILTER_CNT : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Zero Detect filter cycle length.*/
-#define GPIO_ZERO_DET_FILTER_CNT    0xFFFFFFFF
-#define GPIO_ZERO_DET_FILTER_CNT_M  ((GPIO_ZERO_DET_FILTER_CNT_V)<<(GPIO_ZERO_DET_FILTER_CNT_S))
-#define GPIO_ZERO_DET_FILTER_CNT_V  0xFFFFFFFF
-#define GPIO_ZERO_DET_FILTER_CNT_S  0
+/** GPIO_SD_PAD_COMP_CONFIG_REG register
+ *  PAD Compare configure Register
+ */
+#define GPIO_SD_PAD_COMP_CONFIG_REG (DR_REG_GPIO_SD_BASE + 0x28)
+/** GPIO_SD_XPD_COMP : R/W; bitpos: [0]; default: 0;
+ *  Pad compare enable bit.
+ */
+#define GPIO_SD_XPD_COMP    (BIT(0))
+#define GPIO_SD_XPD_COMP_M  (GPIO_SD_XPD_COMP_V << GPIO_SD_XPD_COMP_S)
+#define GPIO_SD_XPD_COMP_V  0x00000001U
+#define GPIO_SD_XPD_COMP_S  0
+/** GPIO_SD_MODE_COMP : R/W; bitpos: [1]; default: 0;
+ *  1 to enable external reference from PAD[0]. 0 to enable internal reference,
+ *  meanwhile PAD[0] can be used as a regular GPIO.
+ */
+#define GPIO_SD_MODE_COMP    (BIT(1))
+#define GPIO_SD_MODE_COMP_M  (GPIO_SD_MODE_COMP_V << GPIO_SD_MODE_COMP_S)
+#define GPIO_SD_MODE_COMP_V  0x00000001U
+#define GPIO_SD_MODE_COMP_S  1
+/** GPIO_SD_DREF_COMP : R/W; bitpos: [4:2]; default: 0;
+ *  internal reference voltage tuning bit. 0V to 0.7*VDDPST step 0.1*VDDPST.
+ */
+#define GPIO_SD_DREF_COMP    0x00000007U
+#define GPIO_SD_DREF_COMP_M  (GPIO_SD_DREF_COMP_V << GPIO_SD_DREF_COMP_S)
+#define GPIO_SD_DREF_COMP_V  0x00000007U
+#define GPIO_SD_DREF_COMP_S  2
+/** GPIO_SD_ZERO_DET_MODE : R/W; bitpos: [6:5]; default: 0;
+ *  Zero Detect mode select.
+ */
+#define GPIO_SD_ZERO_DET_MODE    0x00000003U
+#define GPIO_SD_ZERO_DET_MODE_M  (GPIO_SD_ZERO_DET_MODE_V << GPIO_SD_ZERO_DET_MODE_S)
+#define GPIO_SD_ZERO_DET_MODE_V  0x00000003U
+#define GPIO_SD_ZERO_DET_MODE_S  5
 
-#define GPIO_INT_RAW_REG          (DR_REG_GPIO_SD_BASE + 0x80)
-/* GPIO_PAD_COMP_INT_RAW : RO/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Pad compare raw interrupt.*/
-#define GPIO_PAD_COMP_INT_RAW    (BIT(0))
-#define GPIO_PAD_COMP_INT_RAW_M  (BIT(0))
-#define GPIO_PAD_COMP_INT_RAW_V  0x1
-#define GPIO_PAD_COMP_INT_RAW_S  0
+/** GPIO_SD_PAD_COMP_FILTER_REG register
+ *  Zero Detect filter Register
+ */
+#define GPIO_SD_PAD_COMP_FILTER_REG (DR_REG_GPIO_SD_BASE + 0x2c)
+/** GPIO_SD_ZERO_DET_FILTER_CNT : R/W; bitpos: [31:0]; default: 0;
+ *  Zero Detect filter cycle length
+ */
+#define GPIO_SD_ZERO_DET_FILTER_CNT    0xFFFFFFFFU
+#define GPIO_SD_ZERO_DET_FILTER_CNT_M  (GPIO_SD_ZERO_DET_FILTER_CNT_V << GPIO_SD_ZERO_DET_FILTER_CNT_S)
+#define GPIO_SD_ZERO_DET_FILTER_CNT_V  0xFFFFFFFFU
+#define GPIO_SD_ZERO_DET_FILTER_CNT_S  0
 
-#define GPIO_INT_ST_REG          (DR_REG_GPIO_SD_BASE + 0x84)
-/* GPIO_PAD_COMP_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Pad compare masked interrupt.*/
-#define GPIO_PAD_COMP_INT_ST    (BIT(0))
-#define GPIO_PAD_COMP_INT_ST_M  (BIT(0))
-#define GPIO_PAD_COMP_INT_ST_V  0x1
-#define GPIO_PAD_COMP_INT_ST_S  0
+/** GPIO_SD_INT_RAW_REG register
+ *  GPIO_SD interrupt raw register
+ */
+#define GPIO_SD_INT_RAW_REG (DR_REG_GPIO_SD_BASE + 0x80)
+/** GPIO_SD_PAD_COMP_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
+ *  Pad compare raw interrupt
+ */
+#define GPIO_SD_PAD_COMP_INT_RAW    (BIT(0))
+#define GPIO_SD_PAD_COMP_INT_RAW_M  (GPIO_SD_PAD_COMP_INT_RAW_V << GPIO_SD_PAD_COMP_INT_RAW_S)
+#define GPIO_SD_PAD_COMP_INT_RAW_V  0x00000001U
+#define GPIO_SD_PAD_COMP_INT_RAW_S  0
 
-#define GPIO_INT_ENA_REG          (DR_REG_GPIO_SD_BASE + 0x88)
-/* GPIO_PAD_COMP_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Pad compare interrupt enable.*/
-#define GPIO_PAD_COMP_INT_ENA    (BIT(0))
-#define GPIO_PAD_COMP_INT_ENA_M  (BIT(0))
-#define GPIO_PAD_COMP_INT_ENA_V  0x1
-#define GPIO_PAD_COMP_INT_ENA_S  0
+/** GPIO_SD_INT_ST_REG register
+ *  GPIO_SD interrupt masked register
+ */
+#define GPIO_SD_INT_ST_REG (DR_REG_GPIO_SD_BASE + 0x84)
+/** GPIO_SD_PAD_COMP_INT_ST : RO; bitpos: [0]; default: 0;
+ *  Pad compare masked interrupt
+ */
+#define GPIO_SD_PAD_COMP_INT_ST    (BIT(0))
+#define GPIO_SD_PAD_COMP_INT_ST_M  (GPIO_SD_PAD_COMP_INT_ST_V << GPIO_SD_PAD_COMP_INT_ST_S)
+#define GPIO_SD_PAD_COMP_INT_ST_V  0x00000001U
+#define GPIO_SD_PAD_COMP_INT_ST_S  0
 
-#define GPIO_INT_CLR_REG          (DR_REG_GPIO_SD_BASE + 0x8C)
-/* GPIO_PAD_COMP_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Pad compare interrupt clear.*/
-#define GPIO_PAD_COMP_INT_CLR    (BIT(0))
-#define GPIO_PAD_COMP_INT_CLR_M  (BIT(0))
-#define GPIO_PAD_COMP_INT_CLR_V  0x1
-#define GPIO_PAD_COMP_INT_CLR_S  0
+/** GPIO_SD_INT_ENA_REG register
+ *  GPIO_SD interrupt enable register
+ */
+#define GPIO_SD_INT_ENA_REG (DR_REG_GPIO_SD_BASE + 0x88)
+/** GPIO_SD_PAD_COMP_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Pad compare interrupt enable
+ */
+#define GPIO_SD_PAD_COMP_INT_ENA    (BIT(0))
+#define GPIO_SD_PAD_COMP_INT_ENA_M  (GPIO_SD_PAD_COMP_INT_ENA_V << GPIO_SD_PAD_COMP_INT_ENA_S)
+#define GPIO_SD_PAD_COMP_INT_ENA_V  0x00000001U
+#define GPIO_SD_PAD_COMP_INT_ENA_S  0
 
-#define GPIO_SIGMADELTA_VERSION_REG          (DR_REG_GPIO_SD_BASE + 0xFC)
-/* GPIO_SD_DATE : R/W ;bitpos:[27:0] ;default: 28'h2109250 ; */
-/*description: Version control register..*/
-#define GPIO_SD_DATE    0x0FFFFFFF
-#define GPIO_SD_DATE_M  ((GPIO_SD_DATE_V)<<(GPIO_SD_DATE_S))
-#define GPIO_SD_DATE_V  0xFFFFFFF
-#define GPIO_SD_DATE_S  0
+/** GPIO_SD_INT_CLR_REG register
+ *  GPIO_SD interrupt clear register
+ */
+#define GPIO_SD_INT_CLR_REG (DR_REG_GPIO_SD_BASE + 0x8c)
+/** GPIO_SD_PAD_COMP_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Pad compare interrupt clear
+ */
+#define GPIO_SD_PAD_COMP_INT_CLR    (BIT(0))
+#define GPIO_SD_PAD_COMP_INT_CLR_M  (GPIO_SD_PAD_COMP_INT_CLR_V << GPIO_SD_PAD_COMP_INT_CLR_S)
+#define GPIO_SD_PAD_COMP_INT_CLR_V  0x00000001U
+#define GPIO_SD_PAD_COMP_INT_CLR_S  0
 
+/** GPIO_SD_SIGMADELTA_VERSION_REG register
+ *  Version Control Register
+ */
+#define GPIO_SD_SIGMADELTA_VERSION_REG (DR_REG_GPIO_SD_BASE + 0xfc)
+/** GPIO_SD_GPIO_SD_DATE : R/W; bitpos: [27:0]; default: 34668848;
+ *  Version control register.
+ */
+#define GPIO_SD_GPIO_SD_DATE    0x0FFFFFFFU
+#define GPIO_SD_GPIO_SD_DATE_M  (GPIO_SD_GPIO_SD_DATE_V << GPIO_SD_GPIO_SD_DATE_S)
+#define GPIO_SD_GPIO_SD_DATE_V  0x0FFFFFFFU
+#define GPIO_SD_GPIO_SD_DATE_S  0
 
 #ifdef __cplusplus
 }
 #endif
-
-
-
-#endif /*_SOC_GPIOSD_REG_H_ */

components/soc/esp32h2/include/rev2/soc/interrupt_core0_reg.h

@@ -1,920 +1,1366 @@
-/*
- * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
+/**
+ * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
  *
- * SPDX-License-Identifier: Apache-2.0
+ *  SPDX-License-Identifier: Apache-2.0
  */
-#ifndef _SOC_INTERRUPT_CORE0_REG_H_
-#define _SOC_INTERRUPT_CORE0_REG_H_
+#pragma once
 
 #include "soc/soc.h"
-
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-#define DR_REG_INTERRUPT_CORE0_BASE                 DR_REG_INTERRUPT_BASE
-
-#define INTERRUPT_CORE0_MAC_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x000)
-/* INTERRUPT_CORE0_MAC_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: */
-#define INTERRUPT_CORE0_MAC_INTR_MAP  0x0000001F
-#define INTERRUPT_CORE0_MAC_INTR_MAP_M  ((INTERRUPT_CORE0_MAC_INTR_MAP_V)<<(INTERRUPT_CORE0_MAC_INTR_MAP_S))
-#define INTERRUPT_CORE0_MAC_INTR_MAP_V  0x1F
+/** INTERRUPT_CORE0_MAC_INTR_MAP_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0)
+/** INTERRUPT_CORE0_MAC_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_MAC_INTR_MAP    0x0000001FU
+#define INTERRUPT_CORE0_MAC_INTR_MAP_M  (INTERRUPT_CORE0_MAC_INTR_MAP_V << INTERRUPT_CORE0_MAC_INTR_MAP_S)
+#define INTERRUPT_CORE0_MAC_INTR_MAP_V  0x0000001FU
 #define INTERRUPT_CORE0_MAC_INTR_MAP_S  0
 
-#define INTERRUPT_CORE0_MAC_NMI_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x004)
-/* INTERRUPT_CORE0_MAC_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: */
-#define INTERRUPT_CORE0_MAC_NMI_MAP  0x0000001F
-#define INTERRUPT_CORE0_MAC_NMI_MAP_M  ((INTERRUPT_CORE0_MAC_NMI_MAP_V)<<(INTERRUPT_CORE0_MAC_NMI_MAP_S))
-#define INTERRUPT_CORE0_MAC_NMI_MAP_V  0x1F
+/** INTERRUPT_CORE0_MAC_NMI_MAP_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_MAC_NMI_MAP_REG (DR_REG_INTERRUPT_BASE + 0x4)
+/** INTERRUPT_CORE0_MAC_NMI_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_MAC_NMI_MAP    0x0000001FU
+#define INTERRUPT_CORE0_MAC_NMI_MAP_M  (INTERRUPT_CORE0_MAC_NMI_MAP_V << INTERRUPT_CORE0_MAC_NMI_MAP_S)
+#define INTERRUPT_CORE0_MAC_NMI_MAP_V  0x0000001FU
 #define INTERRUPT_CORE0_MAC_NMI_MAP_S  0
 
-#define INTERRUPT_CORE0_PWR_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x008)
-/* INTERRUPT_CORE0_PWR_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: */
-#define INTERRUPT_CORE0_PWR_INTR_MAP  0x0000001F
-#define INTERRUPT_CORE0_PWR_INTR_MAP_M  ((INTERRUPT_CORE0_PWR_INTR_MAP_V)<<(INTERRUPT_CORE0_PWR_INTR_MAP_S))
-#define INTERRUPT_CORE0_PWR_INTR_MAP_V  0x1F
+/** INTERRUPT_CORE0_PWR_INTR_MAP_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_PWR_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x8)
+/** INTERRUPT_CORE0_PWR_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_PWR_INTR_MAP    0x0000001FU
+#define INTERRUPT_CORE0_PWR_INTR_MAP_M  (INTERRUPT_CORE0_PWR_INTR_MAP_V << INTERRUPT_CORE0_PWR_INTR_MAP_S)
+#define INTERRUPT_CORE0_PWR_INTR_MAP_V  0x0000001FU
 #define INTERRUPT_CORE0_PWR_INTR_MAP_S  0
 
-#define INTERRUPT_CORE0_BB_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x00C)
-/* INTERRUPT_CORE0_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: */
-#define INTERRUPT_CORE0_BB_INT_MAP  0x0000001F
-#define INTERRUPT_CORE0_BB_INT_MAP_M  ((INTERRUPT_CORE0_BB_INT_MAP_V)<<(INTERRUPT_CORE0_BB_INT_MAP_S))
-#define INTERRUPT_CORE0_BB_INT_MAP_V  0x1F
+/** INTERRUPT_CORE0_BB_INT_MAP_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_BB_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0xc)
+/** INTERRUPT_CORE0_BB_INT_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_BB_INT_MAP    0x0000001FU
+#define INTERRUPT_CORE0_BB_INT_MAP_M  (INTERRUPT_CORE0_BB_INT_MAP_V << INTERRUPT_CORE0_BB_INT_MAP_S)
+#define INTERRUPT_CORE0_BB_INT_MAP_V  0x0000001FU
 #define INTERRUPT_CORE0_BB_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_BT_MAC_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x10)
-/* INTERRUPT_CORE0_BT_MAC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_BT_MAC_INT_MAP    0x0000001F
-#define INTERRUPT_CORE0_BT_MAC_INT_MAP_M  ((INTERRUPT_CORE0_BT_MAC_INT_MAP_V)<<(INTERRUPT_CORE0_BT_MAC_INT_MAP_S))
-#define INTERRUPT_CORE0_BT_MAC_INT_MAP_V  0x1F
+/** INTERRUPT_CORE0_BT_MAC_INT_MAP_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_BT_MAC_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x10)
+/** INTERRUPT_CORE0_BT_MAC_INT_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_BT_MAC_INT_MAP    0x0000001FU
+#define INTERRUPT_CORE0_BT_MAC_INT_MAP_M  (INTERRUPT_CORE0_BT_MAC_INT_MAP_V << INTERRUPT_CORE0_BT_MAC_INT_MAP_S)
+#define INTERRUPT_CORE0_BT_MAC_INT_MAP_V  0x0000001FU
 #define INTERRUPT_CORE0_BT_MAC_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_BT_BB_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x14)
-/* INTERRUPT_CORE0_BT_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_BT_BB_INT_MAP    0x0000001F
-#define INTERRUPT_CORE0_BT_BB_INT_MAP_M  ((INTERRUPT_CORE0_BT_BB_INT_MAP_V)<<(INTERRUPT_CORE0_BT_BB_INT_MAP_S))
-#define INTERRUPT_CORE0_BT_BB_INT_MAP_V  0x1F
+/** INTERRUPT_CORE0_BT_BB_INT_MAP_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_BT_BB_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x14)
+/** INTERRUPT_CORE0_BT_BB_INT_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_BT_BB_INT_MAP    0x0000001FU
+#define INTERRUPT_CORE0_BT_BB_INT_MAP_M  (INTERRUPT_CORE0_BT_BB_INT_MAP_V << INTERRUPT_CORE0_BT_BB_INT_MAP_S)
+#define INTERRUPT_CORE0_BT_BB_INT_MAP_V  0x0000001FU
 #define INTERRUPT_CORE0_BT_BB_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_BT_BB_NMI_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x18)
-/* INTERRUPT_CORE0_BT_BB_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_BT_BB_NMI_MAP    0x0000001F
-#define INTERRUPT_CORE0_BT_BB_NMI_MAP_M  ((INTERRUPT_CORE0_BT_BB_NMI_MAP_V)<<(INTERRUPT_CORE0_BT_BB_NMI_MAP_S))
-#define INTERRUPT_CORE0_BT_BB_NMI_MAP_V  0x1F
+/** INTERRUPT_CORE0_BT_BB_NMI_MAP_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_BT_BB_NMI_MAP_REG (DR_REG_INTERRUPT_BASE + 0x18)
+/** INTERRUPT_CORE0_BT_BB_NMI_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_BT_BB_NMI_MAP    0x0000001FU
+#define INTERRUPT_CORE0_BT_BB_NMI_MAP_M  (INTERRUPT_CORE0_BT_BB_NMI_MAP_V << INTERRUPT_CORE0_BT_BB_NMI_MAP_S)
+#define INTERRUPT_CORE0_BT_BB_NMI_MAP_V  0x0000001FU
 #define INTERRUPT_CORE0_BT_BB_NMI_MAP_S  0
 
-#define INTERRUPT_CORE0_RWBT_IRQ_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x1C)
-/* INTERRUPT_CORE0_RWBT_IRQ_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_RWBT_IRQ_MAP    0x0000001F
-#define INTERRUPT_CORE0_RWBT_IRQ_MAP_M  ((INTERRUPT_CORE0_RWBT_IRQ_MAP_V)<<(INTERRUPT_CORE0_RWBT_IRQ_MAP_S))
-#define INTERRUPT_CORE0_RWBT_IRQ_MAP_V  0x1F
+/** INTERRUPT_CORE0_RWBT_IRQ_MAP_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_RWBT_IRQ_MAP_REG (DR_REG_INTERRUPT_BASE + 0x1c)
+/** INTERRUPT_CORE0_RWBT_IRQ_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_RWBT_IRQ_MAP    0x0000001FU
+#define INTERRUPT_CORE0_RWBT_IRQ_MAP_M  (INTERRUPT_CORE0_RWBT_IRQ_MAP_V << INTERRUPT_CORE0_RWBT_IRQ_MAP_S)
+#define INTERRUPT_CORE0_RWBT_IRQ_MAP_V  0x0000001FU
 #define INTERRUPT_CORE0_RWBT_IRQ_MAP_S  0
 
-#define INTERRUPT_CORE0_RWBLE_IRQ_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x20)
-/* INTERRUPT_CORE0_RWBLE_IRQ_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_RWBLE_IRQ_MAP    0x0000001F
-#define INTERRUPT_CORE0_RWBLE_IRQ_MAP_M  ((INTERRUPT_CORE0_RWBLE_IRQ_MAP_V)<<(INTERRUPT_CORE0_RWBLE_IRQ_MAP_S))
-#define INTERRUPT_CORE0_RWBLE_IRQ_MAP_V  0x1F
+/** INTERRUPT_CORE0_RWBLE_IRQ_MAP_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_RWBLE_IRQ_MAP_REG (DR_REG_INTERRUPT_BASE + 0x20)
+/** INTERRUPT_CORE0_RWBLE_IRQ_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_RWBLE_IRQ_MAP    0x0000001FU
+#define INTERRUPT_CORE0_RWBLE_IRQ_MAP_M  (INTERRUPT_CORE0_RWBLE_IRQ_MAP_V << INTERRUPT_CORE0_RWBLE_IRQ_MAP_S)
+#define INTERRUPT_CORE0_RWBLE_IRQ_MAP_V  0x0000001FU
 #define INTERRUPT_CORE0_RWBLE_IRQ_MAP_S  0
 
-#define INTERRUPT_CORE0_RWBT_NMI_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x24)
-/* INTERRUPT_CORE0_RWBT_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_RWBT_NMI_MAP    0x0000001F
-#define INTERRUPT_CORE0_RWBT_NMI_MAP_M  ((INTERRUPT_CORE0_RWBT_NMI_MAP_V)<<(INTERRUPT_CORE0_RWBT_NMI_MAP_S))
-#define INTERRUPT_CORE0_RWBT_NMI_MAP_V  0x1F
+/** INTERRUPT_CORE0_RWBT_NMI_MAP_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_RWBT_NMI_MAP_REG (DR_REG_INTERRUPT_BASE + 0x24)
+/** INTERRUPT_CORE0_RWBT_NMI_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_RWBT_NMI_MAP    0x0000001FU
+#define INTERRUPT_CORE0_RWBT_NMI_MAP_M  (INTERRUPT_CORE0_RWBT_NMI_MAP_V << INTERRUPT_CORE0_RWBT_NMI_MAP_S)
+#define INTERRUPT_CORE0_RWBT_NMI_MAP_V  0x0000001FU
 #define INTERRUPT_CORE0_RWBT_NMI_MAP_S  0
 
-#define INTERRUPT_CORE0_RWBLE_NMI_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x28)
-/* INTERRUPT_CORE0_RWBLE_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_RWBLE_NMI_MAP    0x0000001F
-#define INTERRUPT_CORE0_RWBLE_NMI_MAP_M  ((INTERRUPT_CORE0_RWBLE_NMI_MAP_V)<<(INTERRUPT_CORE0_RWBLE_NMI_MAP_S))
-#define INTERRUPT_CORE0_RWBLE_NMI_MAP_V  0x1F
+/** INTERRUPT_CORE0_RWBLE_NMI_MAP_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_RWBLE_NMI_MAP_REG (DR_REG_INTERRUPT_BASE + 0x28)
+/** INTERRUPT_CORE0_RWBLE_NMI_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_RWBLE_NMI_MAP    0x0000001FU
+#define INTERRUPT_CORE0_RWBLE_NMI_MAP_M  (INTERRUPT_CORE0_RWBLE_NMI_MAP_V << INTERRUPT_CORE0_RWBLE_NMI_MAP_S)
+#define INTERRUPT_CORE0_RWBLE_NMI_MAP_V  0x0000001FU
 #define INTERRUPT_CORE0_RWBLE_NMI_MAP_S  0
 
-#define INTERRUPT_CORE0_I2C_MST_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x2C)
-/* INTERRUPT_CORE0_I2C_MST_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_I2C_MST_INT_MAP    0x0000001F
-#define INTERRUPT_CORE0_I2C_MST_INT_MAP_M  ((INTERRUPT_CORE0_I2C_MST_INT_MAP_V)<<(INTERRUPT_CORE0_I2C_MST_INT_MAP_S))
-#define INTERRUPT_CORE0_I2C_MST_INT_MAP_V  0x1F
+/** INTERRUPT_CORE0_I2C_MST_INT_MAP_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_I2C_MST_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x2c)
+/** INTERRUPT_CORE0_I2C_MST_INT_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_I2C_MST_INT_MAP    0x0000001FU
+#define INTERRUPT_CORE0_I2C_MST_INT_MAP_M  (INTERRUPT_CORE0_I2C_MST_INT_MAP_V << INTERRUPT_CORE0_I2C_MST_INT_MAP_S)
+#define INTERRUPT_CORE0_I2C_MST_INT_MAP_V  0x0000001FU
 #define INTERRUPT_CORE0_I2C_MST_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_SLC0_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x30)
-/* INTERRUPT_CORE0_SLC0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_SLC0_INTR_MAP    0x0000001F
-#define INTERRUPT_CORE0_SLC0_INTR_MAP_M  ((INTERRUPT_CORE0_SLC0_INTR_MAP_V)<<(INTERRUPT_CORE0_SLC0_INTR_MAP_S))
-#define INTERRUPT_CORE0_SLC0_INTR_MAP_V  0x1F
+/** INTERRUPT_CORE0_SLC0_INTR_MAP_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_SLC0_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x30)
+/** INTERRUPT_CORE0_SLC0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_SLC0_INTR_MAP    0x0000001FU
+#define INTERRUPT_CORE0_SLC0_INTR_MAP_M  (INTERRUPT_CORE0_SLC0_INTR_MAP_V << INTERRUPT_CORE0_SLC0_INTR_MAP_S)
+#define INTERRUPT_CORE0_SLC0_INTR_MAP_V  0x0000001FU
 #define INTERRUPT_CORE0_SLC0_INTR_MAP_S  0
 
-#define INTERRUPT_CORE0_SLC1_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x34)
-/* INTERRUPT_CORE0_SLC1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_SLC1_INTR_MAP    0x0000001F
-#define INTERRUPT_CORE0_SLC1_INTR_MAP_M  ((INTERRUPT_CORE0_SLC1_INTR_MAP_V)<<(INTERRUPT_CORE0_SLC1_INTR_MAP_S))
-#define INTERRUPT_CORE0_SLC1_INTR_MAP_V  0x1F
+/** INTERRUPT_CORE0_SLC1_INTR_MAP_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_SLC1_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x34)
+/** INTERRUPT_CORE0_SLC1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_SLC1_INTR_MAP    0x0000001FU
+#define INTERRUPT_CORE0_SLC1_INTR_MAP_M  (INTERRUPT_CORE0_SLC1_INTR_MAP_V << INTERRUPT_CORE0_SLC1_INTR_MAP_S)
+#define INTERRUPT_CORE0_SLC1_INTR_MAP_V  0x0000001FU
 #define INTERRUPT_CORE0_SLC1_INTR_MAP_S  0
 
-#define INTERRUPT_CORE0_APB_CTRL_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x38)
-/* INTERRUPT_CORE0_APB_CTRL_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_APB_CTRL_INTR_MAP    0x0000001F
-#define INTERRUPT_CORE0_APB_CTRL_INTR_MAP_M  ((INTERRUPT_CORE0_APB_CTRL_INTR_MAP_V)<<(INTERRUPT_CORE0_APB_CTRL_INTR_MAP_S))
-#define INTERRUPT_CORE0_APB_CTRL_INTR_MAP_V  0x1F
+/** INTERRUPT_CORE0_APB_CTRL_INTR_MAP_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_APB_CTRL_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x38)
+/** INTERRUPT_CORE0_APB_CTRL_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_APB_CTRL_INTR_MAP    0x0000001FU
+#define INTERRUPT_CORE0_APB_CTRL_INTR_MAP_M  (INTERRUPT_CORE0_APB_CTRL_INTR_MAP_V << INTERRUPT_CORE0_APB_CTRL_INTR_MAP_S)
+#define INTERRUPT_CORE0_APB_CTRL_INTR_MAP_V  0x0000001FU
 #define INTERRUPT_CORE0_APB_CTRL_INTR_MAP_S  0
 
-#define INTERRUPT_CORE0_UHCI0_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x3C)
-/* INTERRUPT_CORE0_UHCI0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_UHCI0_INTR_MAP    0x0000001F
-#define INTERRUPT_CORE0_UHCI0_INTR_MAP_M  ((INTERRUPT_CORE0_UHCI0_INTR_MAP_V)<<(INTERRUPT_CORE0_UHCI0_INTR_MAP_S))
-#define INTERRUPT_CORE0_UHCI0_INTR_MAP_V  0x1F
+/** INTERRUPT_CORE0_UHCI0_INTR_MAP_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_UHCI0_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x3c)
+/** INTERRUPT_CORE0_UHCI0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_UHCI0_INTR_MAP    0x0000001FU
+#define INTERRUPT_CORE0_UHCI0_INTR_MAP_M  (INTERRUPT_CORE0_UHCI0_INTR_MAP_V << INTERRUPT_CORE0_UHCI0_INTR_MAP_S)
+#define INTERRUPT_CORE0_UHCI0_INTR_MAP_V  0x0000001FU
 #define INTERRUPT_CORE0_UHCI0_INTR_MAP_S  0
 
-#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x40)
-/* INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP    0x0000001F
-#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_M  ((INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_V)<<(INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_S))
-#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_V  0x1F
+/** INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_REG (DR_REG_INTERRUPT_BASE + 0x40)
+/** INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP    0x0000001FU
+#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_M  (INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_V << INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_S)
+#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_V  0x0000001FU
 #define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_S  0
 
-#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x44)
-/* INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP    0x0000001F
-#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_M  ((INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_V)<<(INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_S))
-#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_V  0x1F
+/** INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_REG (DR_REG_INTERRUPT_BASE + 0x44)
+/** INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP    0x0000001FU
+#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_M  (INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_V << INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_S)
+#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_V  0x0000001FU
 #define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_S  0
 
-#define INTERRUPT_CORE0_SPI_INTR_1_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x48)
-/* INTERRUPT_CORE0_SPI_INTR_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_SPI_INTR_1_MAP    0x0000001F
-#define INTERRUPT_CORE0_SPI_INTR_1_MAP_M  ((INTERRUPT_CORE0_SPI_INTR_1_MAP_V)<<(INTERRUPT_CORE0_SPI_INTR_1_MAP_S))
-#define INTERRUPT_CORE0_SPI_INTR_1_MAP_V  0x1F
+/** INTERRUPT_CORE0_SPI_INTR_1_MAP_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_SPI_INTR_1_MAP_REG (DR_REG_INTERRUPT_BASE + 0x48)
+/** INTERRUPT_CORE0_SPI_INTR_1_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_SPI_INTR_1_MAP    0x0000001FU
+#define INTERRUPT_CORE0_SPI_INTR_1_MAP_M  (INTERRUPT_CORE0_SPI_INTR_1_MAP_V << INTERRUPT_CORE0_SPI_INTR_1_MAP_S)
+#define INTERRUPT_CORE0_SPI_INTR_1_MAP_V  0x0000001FU
 #define INTERRUPT_CORE0_SPI_INTR_1_MAP_S  0
 
-#define INTERRUPT_CORE0_SPI_INTR_2_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x4C)
-/* INTERRUPT_CORE0_SPI_INTR_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_SPI_INTR_2_MAP    0x0000001F
-#define INTERRUPT_CORE0_SPI_INTR_2_MAP_M  ((INTERRUPT_CORE0_SPI_INTR_2_MAP_V)<<(INTERRUPT_CORE0_SPI_INTR_2_MAP_S))
-#define INTERRUPT_CORE0_SPI_INTR_2_MAP_V  0x1F
+/** INTERRUPT_CORE0_SPI_INTR_2_MAP_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_SPI_INTR_2_MAP_REG (DR_REG_INTERRUPT_BASE + 0x4c)
+/** INTERRUPT_CORE0_SPI_INTR_2_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_SPI_INTR_2_MAP    0x0000001FU
+#define INTERRUPT_CORE0_SPI_INTR_2_MAP_M  (INTERRUPT_CORE0_SPI_INTR_2_MAP_V << INTERRUPT_CORE0_SPI_INTR_2_MAP_S)
+#define INTERRUPT_CORE0_SPI_INTR_2_MAP_V  0x0000001FU
 #define INTERRUPT_CORE0_SPI_INTR_2_MAP_S  0
 
-#define INTERRUPT_CORE0_I2S1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x50)
-/* INTERRUPT_CORE0_I2S1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_I2S1_INT_MAP    0x0000001F
-#define INTERRUPT_CORE0_I2S1_INT_MAP_M  ((INTERRUPT_CORE0_I2S1_INT_MAP_V)<<(INTERRUPT_CORE0_I2S1_INT_MAP_S))
-#define INTERRUPT_CORE0_I2S1_INT_MAP_V  0x1F
+/** INTERRUPT_CORE0_I2S1_INT_MAP_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_I2S1_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x50)
+/** INTERRUPT_CORE0_I2S1_INT_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_I2S1_INT_MAP    0x0000001FU
+#define INTERRUPT_CORE0_I2S1_INT_MAP_M  (INTERRUPT_CORE0_I2S1_INT_MAP_V << INTERRUPT_CORE0_I2S1_INT_MAP_S)
+#define INTERRUPT_CORE0_I2S1_INT_MAP_V  0x0000001FU
 #define INTERRUPT_CORE0_I2S1_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_UART_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x54)
-/* INTERRUPT_CORE0_UART_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_UART_INTR_MAP    0x0000001F
-#define INTERRUPT_CORE0_UART_INTR_MAP_M  ((INTERRUPT_CORE0_UART_INTR_MAP_V)<<(INTERRUPT_CORE0_UART_INTR_MAP_S))
-#define INTERRUPT_CORE0_UART_INTR_MAP_V  0x1F
+/** INTERRUPT_CORE0_UART_INTR_MAP_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_UART_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x54)
+/** INTERRUPT_CORE0_UART_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_UART_INTR_MAP    0x0000001FU
+#define INTERRUPT_CORE0_UART_INTR_MAP_M  (INTERRUPT_CORE0_UART_INTR_MAP_V << INTERRUPT_CORE0_UART_INTR_MAP_S)
+#define INTERRUPT_CORE0_UART_INTR_MAP_V  0x0000001FU
 #define INTERRUPT_CORE0_UART_INTR_MAP_S  0
 
-#define INTERRUPT_CORE0_UART1_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x58)
-/* INTERRUPT_CORE0_UART1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_UART1_INTR_MAP    0x0000001F
-#define INTERRUPT_CORE0_UART1_INTR_MAP_M  ((INTERRUPT_CORE0_UART1_INTR_MAP_V)<<(INTERRUPT_CORE0_UART1_INTR_MAP_S))
-#define INTERRUPT_CORE0_UART1_INTR_MAP_V  0x1F
+/** INTERRUPT_CORE0_UART1_INTR_MAP_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_UART1_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x58)
+/** INTERRUPT_CORE0_UART1_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_UART1_INTR_MAP    0x0000001FU
+#define INTERRUPT_CORE0_UART1_INTR_MAP_M  (INTERRUPT_CORE0_UART1_INTR_MAP_V << INTERRUPT_CORE0_UART1_INTR_MAP_S)
+#define INTERRUPT_CORE0_UART1_INTR_MAP_V  0x0000001FU
 #define INTERRUPT_CORE0_UART1_INTR_MAP_S  0
 
-#define INTERRUPT_CORE0_LEDC_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x5C)
-/* INTERRUPT_CORE0_LEDC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_LEDC_INT_MAP    0x0000001F
-#define INTERRUPT_CORE0_LEDC_INT_MAP_M  ((INTERRUPT_CORE0_LEDC_INT_MAP_V)<<(INTERRUPT_CORE0_LEDC_INT_MAP_S))
-#define INTERRUPT_CORE0_LEDC_INT_MAP_V  0x1F
+/** INTERRUPT_CORE0_LEDC_INT_MAP_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_LEDC_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x5c)
+/** INTERRUPT_CORE0_LEDC_INT_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_LEDC_INT_MAP    0x0000001FU
+#define INTERRUPT_CORE0_LEDC_INT_MAP_M  (INTERRUPT_CORE0_LEDC_INT_MAP_V << INTERRUPT_CORE0_LEDC_INT_MAP_S)
+#define INTERRUPT_CORE0_LEDC_INT_MAP_V  0x0000001FU
 #define INTERRUPT_CORE0_LEDC_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_EFUSE_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x60)
-/* INTERRUPT_CORE0_EFUSE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_EFUSE_INT_MAP    0x0000001F
-#define INTERRUPT_CORE0_EFUSE_INT_MAP_M  ((INTERRUPT_CORE0_EFUSE_INT_MAP_V)<<(INTERRUPT_CORE0_EFUSE_INT_MAP_S))
-#define INTERRUPT_CORE0_EFUSE_INT_MAP_V  0x1F
+/** INTERRUPT_CORE0_EFUSE_INT_MAP_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_EFUSE_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x60)
+/** INTERRUPT_CORE0_EFUSE_INT_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_EFUSE_INT_MAP    0x0000001FU
+#define INTERRUPT_CORE0_EFUSE_INT_MAP_M  (INTERRUPT_CORE0_EFUSE_INT_MAP_V << INTERRUPT_CORE0_EFUSE_INT_MAP_S)
+#define INTERRUPT_CORE0_EFUSE_INT_MAP_V  0x0000001FU
 #define INTERRUPT_CORE0_EFUSE_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_CAN_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x64)
-/* INTERRUPT_CORE0_CAN_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_CAN_INT_MAP    0x0000001F
-#define INTERRUPT_CORE0_CAN_INT_MAP_M  ((INTERRUPT_CORE0_CAN_INT_MAP_V)<<(INTERRUPT_CORE0_CAN_INT_MAP_S))
-#define INTERRUPT_CORE0_CAN_INT_MAP_V  0x1F
-#define INTERRUPT_CORE0_CAN_INT_MAP_S  0
-
-#define INTERRUPT_CORE0_USB_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x68)
-/* INTERRUPT_CORE0_USB_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_USB_INTR_MAP    0x0000001F
-#define INTERRUPT_CORE0_USB_INTR_MAP_M  ((INTERRUPT_CORE0_USB_INTR_MAP_V)<<(INTERRUPT_CORE0_USB_INTR_MAP_S))
-#define INTERRUPT_CORE0_USB_INTR_MAP_V  0x1F
+/** INTERRUPT_CORE0_TWAI_INT_MAP_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_TWAI_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x64)
+/** INTERRUPT_CORE0_TWAI_INT_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_TWAI_INT_MAP    0x0000001FU
+#define INTERRUPT_CORE0_TWAI_INT_MAP_M  (INTERRUPT_CORE0_TWAI_INT_MAP_V << INTERRUPT_CORE0_TWAI_INT_MAP_S)
+#define INTERRUPT_CORE0_TWAI_INT_MAP_V  0x0000001FU
+#define INTERRUPT_CORE0_TWAI_INT_MAP_S  0
+
+/** INTERRUPT_CORE0_USB_INTR_MAP_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_USB_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x68)
+/** INTERRUPT_CORE0_USB_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_USB_INTR_MAP    0x0000001FU
+#define INTERRUPT_CORE0_USB_INTR_MAP_M  (INTERRUPT_CORE0_USB_INTR_MAP_V << INTERRUPT_CORE0_USB_INTR_MAP_S)
+#define INTERRUPT_CORE0_USB_INTR_MAP_V  0x0000001FU
 #define INTERRUPT_CORE0_USB_INTR_MAP_S  0
 
-#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x6C)
-/* INTERRUPT_CORE0_RTC_CORE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP    0x0000001F
-#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_M  ((INTERRUPT_CORE0_RTC_CORE_INTR_MAP_V)<<(INTERRUPT_CORE0_RTC_CORE_INTR_MAP_S))
-#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_V  0x1F
+/** INTERRUPT_CORE0_RTC_CORE_INTR_MAP_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x6c)
+/** INTERRUPT_CORE0_RTC_CORE_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP    0x0000001FU
+#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_M  (INTERRUPT_CORE0_RTC_CORE_INTR_MAP_V << INTERRUPT_CORE0_RTC_CORE_INTR_MAP_S)
+#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_V  0x0000001FU
 #define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_S  0
 
-#define INTERRUPT_CORE0_RMT_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x70)
-/* INTERRUPT_CORE0_RMT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_RMT_INTR_MAP    0x0000001F
-#define INTERRUPT_CORE0_RMT_INTR_MAP_M  ((INTERRUPT_CORE0_RMT_INTR_MAP_V)<<(INTERRUPT_CORE0_RMT_INTR_MAP_S))
-#define INTERRUPT_CORE0_RMT_INTR_MAP_V  0x1F
+/** INTERRUPT_CORE0_RMT_INTR_MAP_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_RMT_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x70)
+/** INTERRUPT_CORE0_RMT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_RMT_INTR_MAP    0x0000001FU
+#define INTERRUPT_CORE0_RMT_INTR_MAP_M  (INTERRUPT_CORE0_RMT_INTR_MAP_V << INTERRUPT_CORE0_RMT_INTR_MAP_S)
+#define INTERRUPT_CORE0_RMT_INTR_MAP_V  0x0000001FU
 #define INTERRUPT_CORE0_RMT_INTR_MAP_S  0
 
-#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x74)
-/* INTERRUPT_CORE0_I2C_EXT0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP    0x0000001F
-#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_M  ((INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_V)<<(INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_S))
-#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_V  0x1F
+/** INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x74)
+/** INTERRUPT_CORE0_I2C_EXT0_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP    0x0000001FU
+#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_M  (INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_V << INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_S)
+#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_V  0x0000001FU
 #define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_S  0
 
-#define INTERRUPT_CORE0_TIMER_INT1_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x78)
-/* INTERRUPT_CORE0_TIMER_INT1_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_TIMER_INT1_MAP    0x0000001F
-#define INTERRUPT_CORE0_TIMER_INT1_MAP_M  ((INTERRUPT_CORE0_TIMER_INT1_MAP_V)<<(INTERRUPT_CORE0_TIMER_INT1_MAP_S))
-#define INTERRUPT_CORE0_TIMER_INT1_MAP_V  0x1F
+/** INTERRUPT_CORE0_TIMER_INT1_MAP_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_TIMER_INT1_MAP_REG (DR_REG_INTERRUPT_BASE + 0x78)
+/** INTERRUPT_CORE0_TIMER_INT1_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_TIMER_INT1_MAP    0x0000001FU
+#define INTERRUPT_CORE0_TIMER_INT1_MAP_M  (INTERRUPT_CORE0_TIMER_INT1_MAP_V << INTERRUPT_CORE0_TIMER_INT1_MAP_S)
+#define INTERRUPT_CORE0_TIMER_INT1_MAP_V  0x0000001FU
 #define INTERRUPT_CORE0_TIMER_INT1_MAP_S  0
 
-#define INTERRUPT_CORE0_TIMER_INT2_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x7C)
-/* INTERRUPT_CORE0_TIMER_INT2_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_TIMER_INT2_MAP    0x0000001F
-#define INTERRUPT_CORE0_TIMER_INT2_MAP_M  ((INTERRUPT_CORE0_TIMER_INT2_MAP_V)<<(INTERRUPT_CORE0_TIMER_INT2_MAP_S))
-#define INTERRUPT_CORE0_TIMER_INT2_MAP_V  0x1F
+/** INTERRUPT_CORE0_TIMER_INT2_MAP_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_TIMER_INT2_MAP_REG (DR_REG_INTERRUPT_BASE + 0x7c)
+/** INTERRUPT_CORE0_TIMER_INT2_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_TIMER_INT2_MAP    0x0000001FU
+#define INTERRUPT_CORE0_TIMER_INT2_MAP_M  (INTERRUPT_CORE0_TIMER_INT2_MAP_V << INTERRUPT_CORE0_TIMER_INT2_MAP_S)
+#define INTERRUPT_CORE0_TIMER_INT2_MAP_V  0x0000001FU
 #define INTERRUPT_CORE0_TIMER_INT2_MAP_S  0
 
-#define INTERRUPT_CORE0_TG_T0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x80)
-/* INTERRUPT_CORE0_TG_T0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_TG_T0_INT_MAP    0x0000001F
-#define INTERRUPT_CORE0_TG_T0_INT_MAP_M  ((INTERRUPT_CORE0_TG_T0_INT_MAP_V)<<(INTERRUPT_CORE0_TG_T0_INT_MAP_S))
-#define INTERRUPT_CORE0_TG_T0_INT_MAP_V  0x1F
+/** INTERRUPT_CORE0_TG_T0_INT_MAP_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_TG_T0_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x80)
+/** INTERRUPT_CORE0_TG_T0_INT_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_TG_T0_INT_MAP    0x0000001FU
+#define INTERRUPT_CORE0_TG_T0_INT_MAP_M  (INTERRUPT_CORE0_TG_T0_INT_MAP_V << INTERRUPT_CORE0_TG_T0_INT_MAP_S)
+#define INTERRUPT_CORE0_TG_T0_INT_MAP_V  0x0000001FU
 #define INTERRUPT_CORE0_TG_T0_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_TG_WDT_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x84)
-/* INTERRUPT_CORE0_TG_WDT_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_TG_WDT_INT_MAP    0x0000001F
-#define INTERRUPT_CORE0_TG_WDT_INT_MAP_M  ((INTERRUPT_CORE0_TG_WDT_INT_MAP_V)<<(INTERRUPT_CORE0_TG_WDT_INT_MAP_S))
-#define INTERRUPT_CORE0_TG_WDT_INT_MAP_V  0x1F
+/** INTERRUPT_CORE0_TG_WDT_INT_MAP_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_TG_WDT_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x84)
+/** INTERRUPT_CORE0_TG_WDT_INT_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_TG_WDT_INT_MAP    0x0000001FU
+#define INTERRUPT_CORE0_TG_WDT_INT_MAP_M  (INTERRUPT_CORE0_TG_WDT_INT_MAP_V << INTERRUPT_CORE0_TG_WDT_INT_MAP_S)
+#define INTERRUPT_CORE0_TG_WDT_INT_MAP_V  0x0000001FU
 #define INTERRUPT_CORE0_TG_WDT_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_TG1_T0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x88)
-/* INTERRUPT_CORE0_TG1_T0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_TG1_T0_INT_MAP    0x0000001F
-#define INTERRUPT_CORE0_TG1_T0_INT_MAP_M  ((INTERRUPT_CORE0_TG1_T0_INT_MAP_V)<<(INTERRUPT_CORE0_TG1_T0_INT_MAP_S))
-#define INTERRUPT_CORE0_TG1_T0_INT_MAP_V  0x1F
+/** INTERRUPT_CORE0_TG1_T0_INT_MAP_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_TG1_T0_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x88)
+/** INTERRUPT_CORE0_TG1_T0_INT_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_TG1_T0_INT_MAP    0x0000001FU
+#define INTERRUPT_CORE0_TG1_T0_INT_MAP_M  (INTERRUPT_CORE0_TG1_T0_INT_MAP_V << INTERRUPT_CORE0_TG1_T0_INT_MAP_S)
+#define INTERRUPT_CORE0_TG1_T0_INT_MAP_V  0x0000001FU
 #define INTERRUPT_CORE0_TG1_T0_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_TG1_WDT_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x8C)
-/* INTERRUPT_CORE0_TG1_WDT_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_TG1_WDT_INT_MAP    0x0000001F
-#define INTERRUPT_CORE0_TG1_WDT_INT_MAP_M  ((INTERRUPT_CORE0_TG1_WDT_INT_MAP_V)<<(INTERRUPT_CORE0_TG1_WDT_INT_MAP_S))
-#define INTERRUPT_CORE0_TG1_WDT_INT_MAP_V  0x1F
+/** INTERRUPT_CORE0_TG1_WDT_INT_MAP_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_TG1_WDT_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x8c)
+/** INTERRUPT_CORE0_TG1_WDT_INT_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_TG1_WDT_INT_MAP    0x0000001FU
+#define INTERRUPT_CORE0_TG1_WDT_INT_MAP_M  (INTERRUPT_CORE0_TG1_WDT_INT_MAP_V << INTERRUPT_CORE0_TG1_WDT_INT_MAP_S)
+#define INTERRUPT_CORE0_TG1_WDT_INT_MAP_V  0x0000001FU
 #define INTERRUPT_CORE0_TG1_WDT_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_CACHE_IA_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x90)
-/* INTERRUPT_CORE0_CACHE_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_CACHE_IA_INT_MAP    0x0000001F
-#define INTERRUPT_CORE0_CACHE_IA_INT_MAP_M  ((INTERRUPT_CORE0_CACHE_IA_INT_MAP_V)<<(INTERRUPT_CORE0_CACHE_IA_INT_MAP_S))
-#define INTERRUPT_CORE0_CACHE_IA_INT_MAP_V  0x1F
+/** INTERRUPT_CORE0_CACHE_IA_INT_MAP_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_CACHE_IA_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x90)
+/** INTERRUPT_CORE0_CACHE_IA_INT_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_CACHE_IA_INT_MAP    0x0000001FU
+#define INTERRUPT_CORE0_CACHE_IA_INT_MAP_M  (INTERRUPT_CORE0_CACHE_IA_INT_MAP_V << INTERRUPT_CORE0_CACHE_IA_INT_MAP_S)
+#define INTERRUPT_CORE0_CACHE_IA_INT_MAP_V  0x0000001FU
 #define INTERRUPT_CORE0_CACHE_IA_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x94)
-/* INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP    0x0000001F
-#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_M  ((INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_V)<<(INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_S))
-#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_V  0x1F
+/** INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x94)
+/** INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP    0x0000001FU
+#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_M  (INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_V << INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_S)
+#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_V  0x0000001FU
 #define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x98)
-/* INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP    0x0000001F
-#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_M  ((INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_V)<<(INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_S))
-#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_V  0x1F
+/** INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x98)
+/** INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP    0x0000001FU
+#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_M  (INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_V << INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_S)
+#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_V  0x0000001FU
 #define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x9C)
-/* INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP    0x0000001F
-#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_M  ((INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_V)<<(INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_S))
-#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_V  0x1F
+/** INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x9c)
+/** INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP    0x0000001FU
+#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_M  (INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_V << INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_S)
+#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_V  0x0000001FU
 #define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xA0)
-/* INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP    0x0000001F
-#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_M  ((INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_V)<<(INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_S))
-#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_V  0x1F
+/** INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0xa0)
+/** INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP    0x0000001FU
+#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_M  (INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_V << INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_S)
+#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_V  0x0000001FU
 #define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_S  0
 
-#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xA4)
-/* INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP    0x0000001F
-#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_M  ((INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_V)<<(INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_S))
-#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_V  0x1F
+/** INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0xa4)
+/** INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP    0x0000001FU
+#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_M  (INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_V << INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_S)
+#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_V  0x0000001FU
 #define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xA8)
-/* INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP    0x0000001F
-#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_M  ((INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_V)<<(INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_S))
-#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_V  0x1F
+/** INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0xa8)
+/** INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP    0x0000001FU
+#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_M  (INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_V << INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_S)
+#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_V  0x0000001FU
 #define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_APB_ADC_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xAC)
-/* INTERRUPT_CORE0_APB_ADC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_APB_ADC_INT_MAP    0x0000001F
-#define INTERRUPT_CORE0_APB_ADC_INT_MAP_M  ((INTERRUPT_CORE0_APB_ADC_INT_MAP_V)<<(INTERRUPT_CORE0_APB_ADC_INT_MAP_S))
-#define INTERRUPT_CORE0_APB_ADC_INT_MAP_V  0x1F
+/** INTERRUPT_CORE0_APB_ADC_INT_MAP_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_APB_ADC_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0xac)
+/** INTERRUPT_CORE0_APB_ADC_INT_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_APB_ADC_INT_MAP    0x0000001FU
+#define INTERRUPT_CORE0_APB_ADC_INT_MAP_M  (INTERRUPT_CORE0_APB_ADC_INT_MAP_V << INTERRUPT_CORE0_APB_ADC_INT_MAP_S)
+#define INTERRUPT_CORE0_APB_ADC_INT_MAP_V  0x0000001FU
 #define INTERRUPT_CORE0_APB_ADC_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_DMA_CH0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xB0)
-/* INTERRUPT_CORE0_DMA_CH0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_DMA_CH0_INT_MAP    0x0000001F
-#define INTERRUPT_CORE0_DMA_CH0_INT_MAP_M  ((INTERRUPT_CORE0_DMA_CH0_INT_MAP_V)<<(INTERRUPT_CORE0_DMA_CH0_INT_MAP_S))
-#define INTERRUPT_CORE0_DMA_CH0_INT_MAP_V  0x1F
+/** INTERRUPT_CORE0_DMA_CH0_INT_MAP_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_DMA_CH0_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0xb0)
+/** INTERRUPT_CORE0_DMA_CH0_INT_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_DMA_CH0_INT_MAP    0x0000001FU
+#define INTERRUPT_CORE0_DMA_CH0_INT_MAP_M  (INTERRUPT_CORE0_DMA_CH0_INT_MAP_V << INTERRUPT_CORE0_DMA_CH0_INT_MAP_S)
+#define INTERRUPT_CORE0_DMA_CH0_INT_MAP_V  0x0000001FU
 #define INTERRUPT_CORE0_DMA_CH0_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_DMA_CH1_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xB4)
-/* INTERRUPT_CORE0_DMA_CH1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_DMA_CH1_INT_MAP    0x0000001F
-#define INTERRUPT_CORE0_DMA_CH1_INT_MAP_M  ((INTERRUPT_CORE0_DMA_CH1_INT_MAP_V)<<(INTERRUPT_CORE0_DMA_CH1_INT_MAP_S))
-#define INTERRUPT_CORE0_DMA_CH1_INT_MAP_V  0x1F
+/** INTERRUPT_CORE0_DMA_CH1_INT_MAP_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_DMA_CH1_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0xb4)
+/** INTERRUPT_CORE0_DMA_CH1_INT_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_DMA_CH1_INT_MAP    0x0000001FU
+#define INTERRUPT_CORE0_DMA_CH1_INT_MAP_M  (INTERRUPT_CORE0_DMA_CH1_INT_MAP_V << INTERRUPT_CORE0_DMA_CH1_INT_MAP_S)
+#define INTERRUPT_CORE0_DMA_CH1_INT_MAP_V  0x0000001FU
 #define INTERRUPT_CORE0_DMA_CH1_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_DMA_CH2_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xB8)
-/* INTERRUPT_CORE0_DMA_CH2_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_DMA_CH2_INT_MAP    0x0000001F
-#define INTERRUPT_CORE0_DMA_CH2_INT_MAP_M  ((INTERRUPT_CORE0_DMA_CH2_INT_MAP_V)<<(INTERRUPT_CORE0_DMA_CH2_INT_MAP_S))
-#define INTERRUPT_CORE0_DMA_CH2_INT_MAP_V  0x1F
+/** INTERRUPT_CORE0_DMA_CH2_INT_MAP_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_DMA_CH2_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0xb8)
+/** INTERRUPT_CORE0_DMA_CH2_INT_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_DMA_CH2_INT_MAP    0x0000001FU
+#define INTERRUPT_CORE0_DMA_CH2_INT_MAP_M  (INTERRUPT_CORE0_DMA_CH2_INT_MAP_V << INTERRUPT_CORE0_DMA_CH2_INT_MAP_S)
+#define INTERRUPT_CORE0_DMA_CH2_INT_MAP_V  0x0000001FU
 #define INTERRUPT_CORE0_DMA_CH2_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_RSA_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xBC)
-/* INTERRUPT_CORE0_RSA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_RSA_INT_MAP    0x0000001F
-#define INTERRUPT_CORE0_RSA_INT_MAP_M  ((INTERRUPT_CORE0_RSA_INT_MAP_V)<<(INTERRUPT_CORE0_RSA_INT_MAP_S))
-#define INTERRUPT_CORE0_RSA_INT_MAP_V  0x1F
+/** INTERRUPT_CORE0_RSA_INT_MAP_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_RSA_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0xbc)
+/** INTERRUPT_CORE0_RSA_INT_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_RSA_INT_MAP    0x0000001FU
+#define INTERRUPT_CORE0_RSA_INT_MAP_M  (INTERRUPT_CORE0_RSA_INT_MAP_V << INTERRUPT_CORE0_RSA_INT_MAP_S)
+#define INTERRUPT_CORE0_RSA_INT_MAP_V  0x0000001FU
 #define INTERRUPT_CORE0_RSA_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_AES_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xC0)
-/* INTERRUPT_CORE0_AES_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_AES_INT_MAP    0x0000001F
-#define INTERRUPT_CORE0_AES_INT_MAP_M  ((INTERRUPT_CORE0_AES_INT_MAP_V)<<(INTERRUPT_CORE0_AES_INT_MAP_S))
-#define INTERRUPT_CORE0_AES_INT_MAP_V  0x1F
+/** INTERRUPT_CORE0_AES_INT_MAP_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_AES_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0xc0)
+/** INTERRUPT_CORE0_AES_INT_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_AES_INT_MAP    0x0000001FU
+#define INTERRUPT_CORE0_AES_INT_MAP_M  (INTERRUPT_CORE0_AES_INT_MAP_V << INTERRUPT_CORE0_AES_INT_MAP_S)
+#define INTERRUPT_CORE0_AES_INT_MAP_V  0x0000001FU
 #define INTERRUPT_CORE0_AES_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_SHA_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xC4)
-/* INTERRUPT_CORE0_SHA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_SHA_INT_MAP    0x0000001F
-#define INTERRUPT_CORE0_SHA_INT_MAP_M  ((INTERRUPT_CORE0_SHA_INT_MAP_V)<<(INTERRUPT_CORE0_SHA_INT_MAP_S))
-#define INTERRUPT_CORE0_SHA_INT_MAP_V  0x1F
+/** INTERRUPT_CORE0_SHA_INT_MAP_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_SHA_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0xc4)
+/** INTERRUPT_CORE0_SHA_INT_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_SHA_INT_MAP    0x0000001FU
+#define INTERRUPT_CORE0_SHA_INT_MAP_M  (INTERRUPT_CORE0_SHA_INT_MAP_V << INTERRUPT_CORE0_SHA_INT_MAP_S)
+#define INTERRUPT_CORE0_SHA_INT_MAP_V  0x0000001FU
 #define INTERRUPT_CORE0_SHA_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xC8)
-/* INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP    0x0000001F
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_M  ((INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_V)<<(INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_S))
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_V  0x1F
+/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_INTERRUPT_BASE + 0xc8)
+/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP    0x0000001FU
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_M  (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_S)
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_V  0x0000001FU
 #define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_S  0
 
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xCC)
-/* INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP    0x0000001F
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_M  ((INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_V)<<(INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_S))
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_V  0x1F
+/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_INTERRUPT_BASE + 0xcc)
+/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP    0x0000001FU
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_M  (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_S)
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_V  0x0000001FU
 #define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_S  0
 
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xD0)
-/* INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP    0x0000001F
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_M  ((INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_V)<<(INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_S))
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_V  0x1F
+/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_INTERRUPT_BASE + 0xd0)
+/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP    0x0000001FU
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_M  (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_S)
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_V  0x0000001FU
 #define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_S  0
 
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xD4)
-/* INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP    0x0000001F
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_M  ((INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_V)<<(INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_S))
-#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_V  0x1F
+/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_INTERRUPT_BASE + 0xd4)
+/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP    0x0000001FU
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_M  (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_S)
+#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_V  0x0000001FU
 #define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_S  0
 
-#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xD8)
-/* INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP    0x0000001F
-#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_M  ((INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_V)<<(INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_S))
-#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_V  0x1F
+/** INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0xd8)
+/** INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP    0x0000001FU
+#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_M  (INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_V << INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_S)
+#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_V  0x0000001FU
 #define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_S  0
 
-#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xDC)
-/* INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP    0x0000001F
-#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_M  ((INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_S))
-#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_V  0x1F
+/** INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0xdc)
+/** INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP : R/W; bitpos: [4:0];
+ *  default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP    0x0000001FU
+#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_M  (INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_V << INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_S)
+#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_V  0x0000001FU
 #define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_S  0
 
-#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xE0)
-/* INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP    0x0000001F
-#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_M  ((INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S))
-#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V  0x1F
+/** INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0xe0)
+/** INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP : R/W; bitpos: [4:0];
+ *  default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP    0x0000001FU
+#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_M  (INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V << INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S)
+#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V  0x0000001FU
 #define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S  0
 
-#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xE4)
-/* INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP    0x0000001F
-#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_M  ((INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S))
-#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V  0x1F
+/** INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0xe4)
+/** INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP : R/W; bitpos: [4:0];
+ *  default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP    0x0000001FU
+#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_M  (INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V << INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S)
+#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V  0x0000001FU
 #define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S  0
 
-#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xE8)
-/* INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP    0x0000001F
-#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_M  ((INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_S))
-#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_V  0x1F
+/** INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0xe8)
+/** INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP : R/W; bitpos: [4:0];
+ *  default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP    0x0000001FU
+#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_M  (INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_V << INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_S)
+#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_V  0x0000001FU
 #define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_S  0
 
-#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xEC)
-/* INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP    0x0000001F
-#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_M  ((INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V)<<(INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S))
-#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V  0x1F
+/** INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0xec)
+/** INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP : R/W; bitpos: [4:0];
+ *  default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP    0x0000001FU
+#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_M  (INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V << INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S)
+#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V  0x0000001FU
 #define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S  0
 
-#define INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xF0)
-/* INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP    0x0000001F
-#define INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_M  ((INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_S))
-#define INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_V  0x1F
+/** INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0xf0)
+/** INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP    0x0000001FU
+#define INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_M  (INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_V << INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_S)
+#define INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_V  0x0000001FU
 #define INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_S  0
 
-#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xF4)
-/* INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP    0x0000001F
-#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_M  ((INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_V)<<(INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_S))
-#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_V  0x1F
+/** INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0xf4)
+/** INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP    0x0000001FU
+#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_M  (INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_V << INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_S)
+#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_V  0x0000001FU
 #define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_TG3_T0_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xF8)
-/* INTERRUPT_CORE0_TG3_T0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_TG3_T0_INT_MAP    0x0000001F
-#define INTERRUPT_CORE0_TG3_T0_INT_MAP_M  ((INTERRUPT_CORE0_TG3_T0_INT_MAP_V)<<(INTERRUPT_CORE0_TG3_T0_INT_MAP_S))
-#define INTERRUPT_CORE0_TG3_T0_INT_MAP_V  0x1F
+/** INTERRUPT_CORE0_TG3_T0_INT_MAP_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_TG3_T0_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0xf8)
+/** INTERRUPT_CORE0_TG3_T0_INT_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_TG3_T0_INT_MAP    0x0000001FU
+#define INTERRUPT_CORE0_TG3_T0_INT_MAP_M  (INTERRUPT_CORE0_TG3_T0_INT_MAP_V << INTERRUPT_CORE0_TG3_T0_INT_MAP_S)
+#define INTERRUPT_CORE0_TG3_T0_INT_MAP_V  0x0000001FU
 #define INTERRUPT_CORE0_TG3_T0_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_TG3_WDT_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0xFC)
-/* INTERRUPT_CORE0_TG3_WDT_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_TG3_WDT_INT_MAP    0x0000001F
-#define INTERRUPT_CORE0_TG3_WDT_INT_MAP_M  ((INTERRUPT_CORE0_TG3_WDT_INT_MAP_V)<<(INTERRUPT_CORE0_TG3_WDT_INT_MAP_S))
-#define INTERRUPT_CORE0_TG3_WDT_INT_MAP_V  0x1F
+/** INTERRUPT_CORE0_TG3_WDT_INT_MAP_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_TG3_WDT_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0xfc)
+/** INTERRUPT_CORE0_TG3_WDT_INT_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_TG3_WDT_INT_MAP    0x0000001FU
+#define INTERRUPT_CORE0_TG3_WDT_INT_MAP_M  (INTERRUPT_CORE0_TG3_WDT_INT_MAP_V << INTERRUPT_CORE0_TG3_WDT_INT_MAP_S)
+#define INTERRUPT_CORE0_TG3_WDT_INT_MAP_V  0x0000001FU
 #define INTERRUPT_CORE0_TG3_WDT_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_BLE_SEC_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x100)
-/* INTERRUPT_CORE0_BLE_SEC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_BLE_SEC_INT_MAP    0x0000001F
-#define INTERRUPT_CORE0_BLE_SEC_INT_MAP_M  ((INTERRUPT_CORE0_BLE_SEC_INT_MAP_V)<<(INTERRUPT_CORE0_BLE_SEC_INT_MAP_S))
-#define INTERRUPT_CORE0_BLE_SEC_INT_MAP_V  0x1F
+/** INTERRUPT_CORE0_BLE_SEC_INT_MAP_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_BLE_SEC_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x100)
+/** INTERRUPT_CORE0_BLE_SEC_INT_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_BLE_SEC_INT_MAP    0x0000001FU
+#define INTERRUPT_CORE0_BLE_SEC_INT_MAP_M  (INTERRUPT_CORE0_BLE_SEC_INT_MAP_V << INTERRUPT_CORE0_BLE_SEC_INT_MAP_S)
+#define INTERRUPT_CORE0_BLE_SEC_INT_MAP_V  0x0000001FU
 #define INTERRUPT_CORE0_BLE_SEC_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_ZIGBEEMAC_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x104)
-/* INTERRUPT_CORE0_ZIGBEEMAC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_ZIGBEEMAC_INT_MAP    0x0000001F
-#define INTERRUPT_CORE0_ZIGBEEMAC_INT_MAP_M  ((INTERRUPT_CORE0_ZIGBEEMAC_INT_MAP_V)<<(INTERRUPT_CORE0_ZIGBEEMAC_INT_MAP_S))
-#define INTERRUPT_CORE0_ZIGBEEMAC_INT_MAP_V  0x1F
-#define INTERRUPT_CORE0_ZIGBEEMAC_INT_MAP_S  0
-
-#define INTERRUPT_CORE0_ZIGBEEBB_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x108)
-/* INTERRUPT_CORE0_ZIGBEEBB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_ZIGBEEBB_INT_MAP    0x0000001F
-#define INTERRUPT_CORE0_ZIGBEEBB_INT_MAP_M  ((INTERRUPT_CORE0_ZIGBEEBB_INT_MAP_V)<<(INTERRUPT_CORE0_ZIGBEEBB_INT_MAP_S))
-#define INTERRUPT_CORE0_ZIGBEEBB_INT_MAP_V  0x1F
-#define INTERRUPT_CORE0_ZIGBEEBB_INT_MAP_S  0
-
-#define INTERRUPT_CORE0_COEX_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x10C)
-/* INTERRUPT_CORE0_COEX_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_COEX_INT_MAP    0x0000001F
-#define INTERRUPT_CORE0_COEX_INT_MAP_M  ((INTERRUPT_CORE0_COEX_INT_MAP_V)<<(INTERRUPT_CORE0_COEX_INT_MAP_S))
-#define INTERRUPT_CORE0_COEX_INT_MAP_V  0x1F
+/** INTERRUPT_CORE0_IEEE802154MAC_INT_MAP_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_IEEE802154MAC_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x104)
+/** INTERRUPT_CORE0_IEEE802154MAC_INT_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_IEEE802154MAC_INT_MAP    0x0000001FU
+#define INTERRUPT_CORE0_IEEE802154MAC_INT_MAP_M  (INTERRUPT_CORE0_IEEE802154MAC_INT_MAP_V << INTERRUPT_CORE0_IEEE802154MAC_INT_MAP_S)
+#define INTERRUPT_CORE0_IEEE802154MAC_INT_MAP_V  0x0000001FU
+#define INTERRUPT_CORE0_IEEE802154MAC_INT_MAP_S  0
+
+/** INTERRUPT_CORE0_IEEE802154BB_INT_MAP_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_IEEE802154BB_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x108)
+/** INTERRUPT_CORE0_IEEE802154BB_INT_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_IEEE802154BB_INT_MAP    0x0000001FU
+#define INTERRUPT_CORE0_IEEE802154BB_INT_MAP_M  (INTERRUPT_CORE0_IEEE802154BB_INT_MAP_V << INTERRUPT_CORE0_IEEE802154BB_INT_MAP_S)
+#define INTERRUPT_CORE0_IEEE802154BB_INT_MAP_V  0x0000001FU
+#define INTERRUPT_CORE0_IEEE802154BB_INT_MAP_S  0
+
+/** INTERRUPT_CORE0_COEX_INT_MAP_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_COEX_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x10c)
+/** INTERRUPT_CORE0_COEX_INT_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_COEX_INT_MAP    0x0000001FU
+#define INTERRUPT_CORE0_COEX_INT_MAP_M  (INTERRUPT_CORE0_COEX_INT_MAP_V << INTERRUPT_CORE0_COEX_INT_MAP_S)
+#define INTERRUPT_CORE0_COEX_INT_MAP_V  0x0000001FU
 #define INTERRUPT_CORE0_COEX_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_RTC_BLE_TMR_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x110)
-/* INTERRUPT_CORE0_RTC_BLE_TMR_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_RTC_BLE_TMR_INT_MAP    0x0000001F
-#define INTERRUPT_CORE0_RTC_BLE_TMR_INT_MAP_M  ((INTERRUPT_CORE0_RTC_BLE_TMR_INT_MAP_V)<<(INTERRUPT_CORE0_RTC_BLE_TMR_INT_MAP_S))
-#define INTERRUPT_CORE0_RTC_BLE_TMR_INT_MAP_V  0x1F
+/** INTERRUPT_CORE0_RTC_BLE_TMR_INT_MAP_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_RTC_BLE_TMR_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x110)
+/** INTERRUPT_CORE0_RTC_BLE_TMR_INT_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_RTC_BLE_TMR_INT_MAP    0x0000001FU
+#define INTERRUPT_CORE0_RTC_BLE_TMR_INT_MAP_M  (INTERRUPT_CORE0_RTC_BLE_TMR_INT_MAP_V << INTERRUPT_CORE0_RTC_BLE_TMR_INT_MAP_S)
+#define INTERRUPT_CORE0_RTC_BLE_TMR_INT_MAP_V  0x0000001FU
 #define INTERRUPT_CORE0_RTC_BLE_TMR_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_ECC_INT_MAP_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x114)
-/* INTERRUPT_CORE0_ECC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_ECC_INT_MAP    0x0000001F
-#define INTERRUPT_CORE0_ECC_INT_MAP_M  ((INTERRUPT_CORE0_ECC_INT_MAP_V)<<(INTERRUPT_CORE0_ECC_INT_MAP_S))
-#define INTERRUPT_CORE0_ECC_INT_MAP_V  0x1F
+/** INTERRUPT_CORE0_ECC_INT_MAP_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_ECC_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x114)
+/** INTERRUPT_CORE0_ECC_INT_MAP : R/W; bitpos: [4:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_ECC_INT_MAP    0x0000001FU
+#define INTERRUPT_CORE0_ECC_INT_MAP_M  (INTERRUPT_CORE0_ECC_INT_MAP_V << INTERRUPT_CORE0_ECC_INT_MAP_S)
+#define INTERRUPT_CORE0_ECC_INT_MAP_V  0x0000001FU
 #define INTERRUPT_CORE0_ECC_INT_MAP_S  0
 
-#define INTERRUPT_CORE0_INTR_STATUS_REG_0_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x118)
-/* INTERRUPT_CORE0_INTR_STATUS_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_INTR_STATUS_0    0xFFFFFFFF
-#define INTERRUPT_CORE0_INTR_STATUS_0_M  ((INTERRUPT_CORE0_INTR_STATUS_0_V)<<(INTERRUPT_CORE0_INTR_STATUS_0_S))
-#define INTERRUPT_CORE0_INTR_STATUS_0_V  0xFFFFFFFF
+/** INTERRUPT_CORE0_INTR_STATUS_REG_0_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_INTR_STATUS_REG_0_REG (DR_REG_INTERRUPT_BASE + 0x118)
+/** INTERRUPT_CORE0_INTR_STATUS_0 : RO; bitpos: [31:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_INTR_STATUS_0    0xFFFFFFFFU
+#define INTERRUPT_CORE0_INTR_STATUS_0_M  (INTERRUPT_CORE0_INTR_STATUS_0_V << INTERRUPT_CORE0_INTR_STATUS_0_S)
+#define INTERRUPT_CORE0_INTR_STATUS_0_V  0xFFFFFFFFU
 #define INTERRUPT_CORE0_INTR_STATUS_0_S  0
 
-#define INTERRUPT_CORE0_INTR_STATUS_REG_1_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x11C)
-/* INTERRUPT_CORE0_INTR_STATUS_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_INTR_STATUS_1    0xFFFFFFFF
-#define INTERRUPT_CORE0_INTR_STATUS_1_M  ((INTERRUPT_CORE0_INTR_STATUS_1_V)<<(INTERRUPT_CORE0_INTR_STATUS_1_S))
-#define INTERRUPT_CORE0_INTR_STATUS_1_V  0xFFFFFFFF
+/** INTERRUPT_CORE0_INTR_STATUS_REG_1_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_INTR_STATUS_REG_1_REG (DR_REG_INTERRUPT_BASE + 0x11c)
+/** INTERRUPT_CORE0_INTR_STATUS_1 : RO; bitpos: [31:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_INTR_STATUS_1    0xFFFFFFFFU
+#define INTERRUPT_CORE0_INTR_STATUS_1_M  (INTERRUPT_CORE0_INTR_STATUS_1_V << INTERRUPT_CORE0_INTR_STATUS_1_S)
+#define INTERRUPT_CORE0_INTR_STATUS_1_V  0xFFFFFFFFU
 #define INTERRUPT_CORE0_INTR_STATUS_1_S  0
 
-#define INTERRUPT_CORE0_INTR_STATUS_REG_2_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x120)
-/* INTERRUPT_CORE0_INTR_STATUS_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_INTR_STATUS_2    0xFFFFFFFF
-#define INTERRUPT_CORE0_INTR_STATUS_2_M  ((INTERRUPT_CORE0_INTR_STATUS_2_V)<<(INTERRUPT_CORE0_INTR_STATUS_2_S))
-#define INTERRUPT_CORE0_INTR_STATUS_2_V  0xFFFFFFFF
+/** INTERRUPT_CORE0_INTR_STATUS_REG_2_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_INTR_STATUS_REG_2_REG (DR_REG_INTERRUPT_BASE + 0x120)
+/** INTERRUPT_CORE0_INTR_STATUS_2 : RO; bitpos: [31:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_INTR_STATUS_2    0xFFFFFFFFU
+#define INTERRUPT_CORE0_INTR_STATUS_2_M  (INTERRUPT_CORE0_INTR_STATUS_2_V << INTERRUPT_CORE0_INTR_STATUS_2_S)
+#define INTERRUPT_CORE0_INTR_STATUS_2_V  0xFFFFFFFFU
 #define INTERRUPT_CORE0_INTR_STATUS_2_S  0
 
-#define INTERRUPT_CORE0_CLOCK_GATE_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x124)
-/* INTERRUPT_CORE0_REG_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: Need add description.*/
+/** INTERRUPT_CORE0_CLOCK_GATE_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_CLOCK_GATE_REG (DR_REG_INTERRUPT_BASE + 0x124)
+/** INTERRUPT_CORE0_REG_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Need add description
+ */
 #define INTERRUPT_CORE0_REG_CLK_EN    (BIT(0))
-#define INTERRUPT_CORE0_REG_CLK_EN_M  (BIT(0))
-#define INTERRUPT_CORE0_REG_CLK_EN_V  0x1
+#define INTERRUPT_CORE0_REG_CLK_EN_M  (INTERRUPT_CORE0_REG_CLK_EN_V << INTERRUPT_CORE0_REG_CLK_EN_S)
+#define INTERRUPT_CORE0_REG_CLK_EN_V  0x00000001U
 #define INTERRUPT_CORE0_REG_CLK_EN_S  0
 
-#define INTERRUPT_CORE0_CPU_INT_ENABLE_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x128)
-/* INTERRUPT_CORE0_CPU_INT_ENABLE : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_CPU_INT_ENABLE    0xFFFFFFFF
-#define INTERRUPT_CORE0_CPU_INT_ENABLE_M  ((INTERRUPT_CORE0_CPU_INT_ENABLE_V)<<(INTERRUPT_CORE0_CPU_INT_ENABLE_S))
-#define INTERRUPT_CORE0_CPU_INT_ENABLE_V  0xFFFFFFFF
+/** INTERRUPT_CORE0_CPU_INT_ENABLE_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_CPU_INT_ENABLE_REG (DR_REG_INTERRUPT_BASE + 0x128)
+/** INTERRUPT_CORE0_CPU_INT_ENABLE : R/W; bitpos: [31:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_CPU_INT_ENABLE    0xFFFFFFFFU
+#define INTERRUPT_CORE0_CPU_INT_ENABLE_M  (INTERRUPT_CORE0_CPU_INT_ENABLE_V << INTERRUPT_CORE0_CPU_INT_ENABLE_S)
+#define INTERRUPT_CORE0_CPU_INT_ENABLE_V  0xFFFFFFFFU
 #define INTERRUPT_CORE0_CPU_INT_ENABLE_S  0
 
-#define INTERRUPT_CORE0_CPU_INT_TYPE_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x12C)
-/* INTERRUPT_CORE0_CPU_INT_TYPE : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_CPU_INT_TYPE    0xFFFFFFFF
-#define INTERRUPT_CORE0_CPU_INT_TYPE_M  ((INTERRUPT_CORE0_CPU_INT_TYPE_V)<<(INTERRUPT_CORE0_CPU_INT_TYPE_S))
-#define INTERRUPT_CORE0_CPU_INT_TYPE_V  0xFFFFFFFF
+/** INTERRUPT_CORE0_CPU_INT_TYPE_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_CPU_INT_TYPE_REG (DR_REG_INTERRUPT_BASE + 0x12c)
+/** INTERRUPT_CORE0_CPU_INT_TYPE : R/W; bitpos: [31:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_CPU_INT_TYPE    0xFFFFFFFFU
+#define INTERRUPT_CORE0_CPU_INT_TYPE_M  (INTERRUPT_CORE0_CPU_INT_TYPE_V << INTERRUPT_CORE0_CPU_INT_TYPE_S)
+#define INTERRUPT_CORE0_CPU_INT_TYPE_V  0xFFFFFFFFU
 #define INTERRUPT_CORE0_CPU_INT_TYPE_S  0
 
-#define INTERRUPT_CORE0_CPU_INT_CLEAR_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x130)
-/* INTERRUPT_CORE0_CPU_INT_CLEAR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_CPU_INT_CLEAR    0xFFFFFFFF
-#define INTERRUPT_CORE0_CPU_INT_CLEAR_M  ((INTERRUPT_CORE0_CPU_INT_CLEAR_V)<<(INTERRUPT_CORE0_CPU_INT_CLEAR_S))
-#define INTERRUPT_CORE0_CPU_INT_CLEAR_V  0xFFFFFFFF
+/** INTERRUPT_CORE0_CPU_INT_CLEAR_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_CPU_INT_CLEAR_REG (DR_REG_INTERRUPT_BASE + 0x130)
+/** INTERRUPT_CORE0_CPU_INT_CLEAR : R/W; bitpos: [31:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_CPU_INT_CLEAR    0xFFFFFFFFU
+#define INTERRUPT_CORE0_CPU_INT_CLEAR_M  (INTERRUPT_CORE0_CPU_INT_CLEAR_V << INTERRUPT_CORE0_CPU_INT_CLEAR_S)
+#define INTERRUPT_CORE0_CPU_INT_CLEAR_V  0xFFFFFFFFU
 #define INTERRUPT_CORE0_CPU_INT_CLEAR_S  0
 
-#define INTERRUPT_CORE0_CPU_INT_EIP_STATUS_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x134)
-/* INTERRUPT_CORE0_CPU_INT_EIP_STATUS : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_CPU_INT_EIP_STATUS    0xFFFFFFFF
-#define INTERRUPT_CORE0_CPU_INT_EIP_STATUS_M  ((INTERRUPT_CORE0_CPU_INT_EIP_STATUS_V)<<(INTERRUPT_CORE0_CPU_INT_EIP_STATUS_S))
-#define INTERRUPT_CORE0_CPU_INT_EIP_STATUS_V  0xFFFFFFFF
+/** INTERRUPT_CORE0_CPU_INT_EIP_STATUS_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_CPU_INT_EIP_STATUS_REG (DR_REG_INTERRUPT_BASE + 0x134)
+/** INTERRUPT_CORE0_CPU_INT_EIP_STATUS : RO; bitpos: [31:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_CPU_INT_EIP_STATUS    0xFFFFFFFFU
+#define INTERRUPT_CORE0_CPU_INT_EIP_STATUS_M  (INTERRUPT_CORE0_CPU_INT_EIP_STATUS_V << INTERRUPT_CORE0_CPU_INT_EIP_STATUS_S)
+#define INTERRUPT_CORE0_CPU_INT_EIP_STATUS_V  0xFFFFFFFFU
 #define INTERRUPT_CORE0_CPU_INT_EIP_STATUS_S  0
 
-#define INTERRUPT_CORE0_CPU_INT_PRI_0_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x138)
-/* INTERRUPT_CORE0_CPU_PRI_0_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_CPU_PRI_0_MAP    0x0000000F
-#define INTERRUPT_CORE0_CPU_PRI_0_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_0_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_0_MAP_S))
-#define INTERRUPT_CORE0_CPU_PRI_0_MAP_V  0xF
+/** INTERRUPT_CORE0_CPU_INT_PRI_0_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_CPU_INT_PRI_0_REG (DR_REG_INTERRUPT_BASE + 0x138)
+
+#define INTC_INT_PRIO_REG(n)                        (INTERRUPT_CORE0_CPU_INT_PRI_0_REG + (n)*4)
+/** INTERRUPT_CORE0_CPU_PRI_0_MAP : R/W; bitpos: [3:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_CPU_PRI_0_MAP    0x0000000FU
+#define INTERRUPT_CORE0_CPU_PRI_0_MAP_M  (INTERRUPT_CORE0_CPU_PRI_0_MAP_V << INTERRUPT_CORE0_CPU_PRI_0_MAP_S)
+#define INTERRUPT_CORE0_CPU_PRI_0_MAP_V  0x0000000FU
 #define INTERRUPT_CORE0_CPU_PRI_0_MAP_S  0
 
-#define INTERRUPT_CORE0_CPU_INT_PRI_1_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x13C)
-/* INTERRUPT_CORE0_CPU_PRI_1_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_CPU_PRI_1_MAP    0x0000000F
-#define INTERRUPT_CORE0_CPU_PRI_1_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_1_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_1_MAP_S))
-#define INTERRUPT_CORE0_CPU_PRI_1_MAP_V  0xF
+/** INTERRUPT_CORE0_CPU_INT_PRI_1_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_CPU_INT_PRI_1_REG (DR_REG_INTERRUPT_BASE + 0x13c)
+/** INTERRUPT_CORE0_CPU_PRI_1_MAP : R/W; bitpos: [3:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_CPU_PRI_1_MAP    0x0000000FU
+#define INTERRUPT_CORE0_CPU_PRI_1_MAP_M  (INTERRUPT_CORE0_CPU_PRI_1_MAP_V << INTERRUPT_CORE0_CPU_PRI_1_MAP_S)
+#define INTERRUPT_CORE0_CPU_PRI_1_MAP_V  0x0000000FU
 #define INTERRUPT_CORE0_CPU_PRI_1_MAP_S  0
 
-#define INTERRUPT_CORE0_CPU_INT_PRI_2_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x140)
-/* INTERRUPT_CORE0_CPU_PRI_2_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_CPU_PRI_2_MAP    0x0000000F
-#define INTERRUPT_CORE0_CPU_PRI_2_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_2_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_2_MAP_S))
-#define INTERRUPT_CORE0_CPU_PRI_2_MAP_V  0xF
+/** INTERRUPT_CORE0_CPU_INT_PRI_2_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_CPU_INT_PRI_2_REG (DR_REG_INTERRUPT_BASE + 0x140)
+/** INTERRUPT_CORE0_CPU_PRI_2_MAP : R/W; bitpos: [3:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_CPU_PRI_2_MAP    0x0000000FU
+#define INTERRUPT_CORE0_CPU_PRI_2_MAP_M  (INTERRUPT_CORE0_CPU_PRI_2_MAP_V << INTERRUPT_CORE0_CPU_PRI_2_MAP_S)
+#define INTERRUPT_CORE0_CPU_PRI_2_MAP_V  0x0000000FU
 #define INTERRUPT_CORE0_CPU_PRI_2_MAP_S  0
 
-#define INTERRUPT_CORE0_CPU_INT_PRI_3_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x144)
-/* INTERRUPT_CORE0_CPU_PRI_3_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_CPU_PRI_3_MAP    0x0000000F
-#define INTERRUPT_CORE0_CPU_PRI_3_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_3_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_3_MAP_S))
-#define INTERRUPT_CORE0_CPU_PRI_3_MAP_V  0xF
+/** INTERRUPT_CORE0_CPU_INT_PRI_3_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_CPU_INT_PRI_3_REG (DR_REG_INTERRUPT_BASE + 0x144)
+/** INTERRUPT_CORE0_CPU_PRI_3_MAP : R/W; bitpos: [3:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_CPU_PRI_3_MAP    0x0000000FU
+#define INTERRUPT_CORE0_CPU_PRI_3_MAP_M  (INTERRUPT_CORE0_CPU_PRI_3_MAP_V << INTERRUPT_CORE0_CPU_PRI_3_MAP_S)
+#define INTERRUPT_CORE0_CPU_PRI_3_MAP_V  0x0000000FU
 #define INTERRUPT_CORE0_CPU_PRI_3_MAP_S  0
 
-#define INTERRUPT_CORE0_CPU_INT_PRI_4_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x148)
-/* INTERRUPT_CORE0_CPU_PRI_4_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_CPU_PRI_4_MAP    0x0000000F
-#define INTERRUPT_CORE0_CPU_PRI_4_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_4_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_4_MAP_S))
-#define INTERRUPT_CORE0_CPU_PRI_4_MAP_V  0xF
+/** INTERRUPT_CORE0_CPU_INT_PRI_4_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_CPU_INT_PRI_4_REG (DR_REG_INTERRUPT_BASE + 0x148)
+/** INTERRUPT_CORE0_CPU_PRI_4_MAP : R/W; bitpos: [3:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_CPU_PRI_4_MAP    0x0000000FU
+#define INTERRUPT_CORE0_CPU_PRI_4_MAP_M  (INTERRUPT_CORE0_CPU_PRI_4_MAP_V << INTERRUPT_CORE0_CPU_PRI_4_MAP_S)
+#define INTERRUPT_CORE0_CPU_PRI_4_MAP_V  0x0000000FU
 #define INTERRUPT_CORE0_CPU_PRI_4_MAP_S  0
 
-#define INTERRUPT_CORE0_CPU_INT_PRI_5_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x14C)
-/* INTERRUPT_CORE0_CPU_PRI_5_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_CPU_PRI_5_MAP    0x0000000F
-#define INTERRUPT_CORE0_CPU_PRI_5_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_5_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_5_MAP_S))
-#define INTERRUPT_CORE0_CPU_PRI_5_MAP_V  0xF
+/** INTERRUPT_CORE0_CPU_INT_PRI_5_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_CPU_INT_PRI_5_REG (DR_REG_INTERRUPT_BASE + 0x14c)
+/** INTERRUPT_CORE0_CPU_PRI_5_MAP : R/W; bitpos: [3:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_CPU_PRI_5_MAP    0x0000000FU
+#define INTERRUPT_CORE0_CPU_PRI_5_MAP_M  (INTERRUPT_CORE0_CPU_PRI_5_MAP_V << INTERRUPT_CORE0_CPU_PRI_5_MAP_S)
+#define INTERRUPT_CORE0_CPU_PRI_5_MAP_V  0x0000000FU
 #define INTERRUPT_CORE0_CPU_PRI_5_MAP_S  0
 
-#define INTERRUPT_CORE0_CPU_INT_PRI_6_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x150)
-/* INTERRUPT_CORE0_CPU_PRI_6_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_CPU_PRI_6_MAP    0x0000000F
-#define INTERRUPT_CORE0_CPU_PRI_6_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_6_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_6_MAP_S))
-#define INTERRUPT_CORE0_CPU_PRI_6_MAP_V  0xF
+/** INTERRUPT_CORE0_CPU_INT_PRI_6_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_CPU_INT_PRI_6_REG (DR_REG_INTERRUPT_BASE + 0x150)
+/** INTERRUPT_CORE0_CPU_PRI_6_MAP : R/W; bitpos: [3:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_CPU_PRI_6_MAP    0x0000000FU
+#define INTERRUPT_CORE0_CPU_PRI_6_MAP_M  (INTERRUPT_CORE0_CPU_PRI_6_MAP_V << INTERRUPT_CORE0_CPU_PRI_6_MAP_S)
+#define INTERRUPT_CORE0_CPU_PRI_6_MAP_V  0x0000000FU
 #define INTERRUPT_CORE0_CPU_PRI_6_MAP_S  0
 
-#define INTERRUPT_CORE0_CPU_INT_PRI_7_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x154)
-/* INTERRUPT_CORE0_CPU_PRI_7_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_CPU_PRI_7_MAP    0x0000000F
-#define INTERRUPT_CORE0_CPU_PRI_7_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_7_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_7_MAP_S))
-#define INTERRUPT_CORE0_CPU_PRI_7_MAP_V  0xF
+/** INTERRUPT_CORE0_CPU_INT_PRI_7_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_CPU_INT_PRI_7_REG (DR_REG_INTERRUPT_BASE + 0x154)
+/** INTERRUPT_CORE0_CPU_PRI_7_MAP : R/W; bitpos: [3:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_CPU_PRI_7_MAP    0x0000000FU
+#define INTERRUPT_CORE0_CPU_PRI_7_MAP_M  (INTERRUPT_CORE0_CPU_PRI_7_MAP_V << INTERRUPT_CORE0_CPU_PRI_7_MAP_S)
+#define INTERRUPT_CORE0_CPU_PRI_7_MAP_V  0x0000000FU
 #define INTERRUPT_CORE0_CPU_PRI_7_MAP_S  0
 
-#define INTERRUPT_CORE0_CPU_INT_PRI_8_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x158)
-/* INTERRUPT_CORE0_CPU_PRI_8_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_CPU_PRI_8_MAP    0x0000000F
-#define INTERRUPT_CORE0_CPU_PRI_8_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_8_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_8_MAP_S))
-#define INTERRUPT_CORE0_CPU_PRI_8_MAP_V  0xF
+/** INTERRUPT_CORE0_CPU_INT_PRI_8_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_CPU_INT_PRI_8_REG (DR_REG_INTERRUPT_BASE + 0x158)
+/** INTERRUPT_CORE0_CPU_PRI_8_MAP : R/W; bitpos: [3:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_CPU_PRI_8_MAP    0x0000000FU
+#define INTERRUPT_CORE0_CPU_PRI_8_MAP_M  (INTERRUPT_CORE0_CPU_PRI_8_MAP_V << INTERRUPT_CORE0_CPU_PRI_8_MAP_S)
+#define INTERRUPT_CORE0_CPU_PRI_8_MAP_V  0x0000000FU
 #define INTERRUPT_CORE0_CPU_PRI_8_MAP_S  0
 
-#define INTERRUPT_CORE0_CPU_INT_PRI_9_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x15C)
-/* INTERRUPT_CORE0_CPU_PRI_9_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_CPU_PRI_9_MAP    0x0000000F
-#define INTERRUPT_CORE0_CPU_PRI_9_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_9_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_9_MAP_S))
-#define INTERRUPT_CORE0_CPU_PRI_9_MAP_V  0xF
+/** INTERRUPT_CORE0_CPU_INT_PRI_9_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_CPU_INT_PRI_9_REG (DR_REG_INTERRUPT_BASE + 0x15c)
+/** INTERRUPT_CORE0_CPU_PRI_9_MAP : R/W; bitpos: [3:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_CPU_PRI_9_MAP    0x0000000FU
+#define INTERRUPT_CORE0_CPU_PRI_9_MAP_M  (INTERRUPT_CORE0_CPU_PRI_9_MAP_V << INTERRUPT_CORE0_CPU_PRI_9_MAP_S)
+#define INTERRUPT_CORE0_CPU_PRI_9_MAP_V  0x0000000FU
 #define INTERRUPT_CORE0_CPU_PRI_9_MAP_S  0
 
-#define INTERRUPT_CORE0_CPU_INT_PRI_10_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x160)
-/* INTERRUPT_CORE0_CPU_PRI_10_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_CPU_PRI_10_MAP    0x0000000F
-#define INTERRUPT_CORE0_CPU_PRI_10_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_10_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_10_MAP_S))
-#define INTERRUPT_CORE0_CPU_PRI_10_MAP_V  0xF
+/** INTERRUPT_CORE0_CPU_INT_PRI_10_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_CPU_INT_PRI_10_REG (DR_REG_INTERRUPT_BASE + 0x160)
+/** INTERRUPT_CORE0_CPU_PRI_10_MAP : R/W; bitpos: [3:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_CPU_PRI_10_MAP    0x0000000FU
+#define INTERRUPT_CORE0_CPU_PRI_10_MAP_M  (INTERRUPT_CORE0_CPU_PRI_10_MAP_V << INTERRUPT_CORE0_CPU_PRI_10_MAP_S)
+#define INTERRUPT_CORE0_CPU_PRI_10_MAP_V  0x0000000FU
 #define INTERRUPT_CORE0_CPU_PRI_10_MAP_S  0
 
-#define INTERRUPT_CORE0_CPU_INT_PRI_11_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x164)
-/* INTERRUPT_CORE0_CPU_PRI_11_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_CPU_PRI_11_MAP    0x0000000F
-#define INTERRUPT_CORE0_CPU_PRI_11_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_11_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_11_MAP_S))
-#define INTERRUPT_CORE0_CPU_PRI_11_MAP_V  0xF
+/** INTERRUPT_CORE0_CPU_INT_PRI_11_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_CPU_INT_PRI_11_REG (DR_REG_INTERRUPT_BASE + 0x164)
+/** INTERRUPT_CORE0_CPU_PRI_11_MAP : R/W; bitpos: [3:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_CPU_PRI_11_MAP    0x0000000FU
+#define INTERRUPT_CORE0_CPU_PRI_11_MAP_M  (INTERRUPT_CORE0_CPU_PRI_11_MAP_V << INTERRUPT_CORE0_CPU_PRI_11_MAP_S)
+#define INTERRUPT_CORE0_CPU_PRI_11_MAP_V  0x0000000FU
 #define INTERRUPT_CORE0_CPU_PRI_11_MAP_S  0
 
-#define INTERRUPT_CORE0_CPU_INT_PRI_12_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x168)
-/* INTERRUPT_CORE0_CPU_PRI_12_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_CPU_PRI_12_MAP    0x0000000F
-#define INTERRUPT_CORE0_CPU_PRI_12_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_12_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_12_MAP_S))
-#define INTERRUPT_CORE0_CPU_PRI_12_MAP_V  0xF
+/** INTERRUPT_CORE0_CPU_INT_PRI_12_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_CPU_INT_PRI_12_REG (DR_REG_INTERRUPT_BASE + 0x168)
+/** INTERRUPT_CORE0_CPU_PRI_12_MAP : R/W; bitpos: [3:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_CPU_PRI_12_MAP    0x0000000FU
+#define INTERRUPT_CORE0_CPU_PRI_12_MAP_M  (INTERRUPT_CORE0_CPU_PRI_12_MAP_V << INTERRUPT_CORE0_CPU_PRI_12_MAP_S)
+#define INTERRUPT_CORE0_CPU_PRI_12_MAP_V  0x0000000FU
 #define INTERRUPT_CORE0_CPU_PRI_12_MAP_S  0
 
-#define INTERRUPT_CORE0_CPU_INT_PRI_13_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x16C)
-/* INTERRUPT_CORE0_CPU_PRI_13_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_CPU_PRI_13_MAP    0x0000000F
-#define INTERRUPT_CORE0_CPU_PRI_13_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_13_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_13_MAP_S))
-#define INTERRUPT_CORE0_CPU_PRI_13_MAP_V  0xF
+/** INTERRUPT_CORE0_CPU_INT_PRI_13_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_CPU_INT_PRI_13_REG (DR_REG_INTERRUPT_BASE + 0x16c)
+/** INTERRUPT_CORE0_CPU_PRI_13_MAP : R/W; bitpos: [3:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_CPU_PRI_13_MAP    0x0000000FU
+#define INTERRUPT_CORE0_CPU_PRI_13_MAP_M  (INTERRUPT_CORE0_CPU_PRI_13_MAP_V << INTERRUPT_CORE0_CPU_PRI_13_MAP_S)
+#define INTERRUPT_CORE0_CPU_PRI_13_MAP_V  0x0000000FU
 #define INTERRUPT_CORE0_CPU_PRI_13_MAP_S  0
 
-#define INTERRUPT_CORE0_CPU_INT_PRI_14_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x170)
-/* INTERRUPT_CORE0_CPU_PRI_14_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_CPU_PRI_14_MAP    0x0000000F
-#define INTERRUPT_CORE0_CPU_PRI_14_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_14_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_14_MAP_S))
-#define INTERRUPT_CORE0_CPU_PRI_14_MAP_V  0xF
+/** INTERRUPT_CORE0_CPU_INT_PRI_14_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_CPU_INT_PRI_14_REG (DR_REG_INTERRUPT_BASE + 0x170)
+/** INTERRUPT_CORE0_CPU_PRI_14_MAP : R/W; bitpos: [3:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_CPU_PRI_14_MAP    0x0000000FU
+#define INTERRUPT_CORE0_CPU_PRI_14_MAP_M  (INTERRUPT_CORE0_CPU_PRI_14_MAP_V << INTERRUPT_CORE0_CPU_PRI_14_MAP_S)
+#define INTERRUPT_CORE0_CPU_PRI_14_MAP_V  0x0000000FU
 #define INTERRUPT_CORE0_CPU_PRI_14_MAP_S  0
 
-#define INTERRUPT_CORE0_CPU_INT_PRI_15_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x174)
-/* INTERRUPT_CORE0_CPU_PRI_15_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_CPU_PRI_15_MAP    0x0000000F
-#define INTERRUPT_CORE0_CPU_PRI_15_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_15_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_15_MAP_S))
-#define INTERRUPT_CORE0_CPU_PRI_15_MAP_V  0xF
+/** INTERRUPT_CORE0_CPU_INT_PRI_15_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_CPU_INT_PRI_15_REG (DR_REG_INTERRUPT_BASE + 0x174)
+/** INTERRUPT_CORE0_CPU_PRI_15_MAP : R/W; bitpos: [3:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_CPU_PRI_15_MAP    0x0000000FU
+#define INTERRUPT_CORE0_CPU_PRI_15_MAP_M  (INTERRUPT_CORE0_CPU_PRI_15_MAP_V << INTERRUPT_CORE0_CPU_PRI_15_MAP_S)
+#define INTERRUPT_CORE0_CPU_PRI_15_MAP_V  0x0000000FU
 #define INTERRUPT_CORE0_CPU_PRI_15_MAP_S  0
 
-#define INTERRUPT_CORE0_CPU_INT_PRI_16_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x178)
-/* INTERRUPT_CORE0_CPU_PRI_16_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_CPU_PRI_16_MAP    0x0000000F
-#define INTERRUPT_CORE0_CPU_PRI_16_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_16_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_16_MAP_S))
-#define INTERRUPT_CORE0_CPU_PRI_16_MAP_V  0xF
+/** INTERRUPT_CORE0_CPU_INT_PRI_16_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_CPU_INT_PRI_16_REG (DR_REG_INTERRUPT_BASE + 0x178)
+/** INTERRUPT_CORE0_CPU_PRI_16_MAP : R/W; bitpos: [3:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_CPU_PRI_16_MAP    0x0000000FU
+#define INTERRUPT_CORE0_CPU_PRI_16_MAP_M  (INTERRUPT_CORE0_CPU_PRI_16_MAP_V << INTERRUPT_CORE0_CPU_PRI_16_MAP_S)
+#define INTERRUPT_CORE0_CPU_PRI_16_MAP_V  0x0000000FU
 #define INTERRUPT_CORE0_CPU_PRI_16_MAP_S  0
 
-#define INTERRUPT_CORE0_CPU_INT_PRI_17_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x17C)
-/* INTERRUPT_CORE0_CPU_PRI_17_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_CPU_PRI_17_MAP    0x0000000F
-#define INTERRUPT_CORE0_CPU_PRI_17_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_17_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_17_MAP_S))
-#define INTERRUPT_CORE0_CPU_PRI_17_MAP_V  0xF
+/** INTERRUPT_CORE0_CPU_INT_PRI_17_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_CPU_INT_PRI_17_REG (DR_REG_INTERRUPT_BASE + 0x17c)
+/** INTERRUPT_CORE0_CPU_PRI_17_MAP : R/W; bitpos: [3:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_CPU_PRI_17_MAP    0x0000000FU
+#define INTERRUPT_CORE0_CPU_PRI_17_MAP_M  (INTERRUPT_CORE0_CPU_PRI_17_MAP_V << INTERRUPT_CORE0_CPU_PRI_17_MAP_S)
+#define INTERRUPT_CORE0_CPU_PRI_17_MAP_V  0x0000000FU
 #define INTERRUPT_CORE0_CPU_PRI_17_MAP_S  0
 
-#define INTERRUPT_CORE0_CPU_INT_PRI_18_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x180)
-/* INTERRUPT_CORE0_CPU_PRI_18_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_CPU_PRI_18_MAP    0x0000000F
-#define INTERRUPT_CORE0_CPU_PRI_18_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_18_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_18_MAP_S))
-#define INTERRUPT_CORE0_CPU_PRI_18_MAP_V  0xF
+/** INTERRUPT_CORE0_CPU_INT_PRI_18_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_CPU_INT_PRI_18_REG (DR_REG_INTERRUPT_BASE + 0x180)
+/** INTERRUPT_CORE0_CPU_PRI_18_MAP : R/W; bitpos: [3:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_CPU_PRI_18_MAP    0x0000000FU
+#define INTERRUPT_CORE0_CPU_PRI_18_MAP_M  (INTERRUPT_CORE0_CPU_PRI_18_MAP_V << INTERRUPT_CORE0_CPU_PRI_18_MAP_S)
+#define INTERRUPT_CORE0_CPU_PRI_18_MAP_V  0x0000000FU
 #define INTERRUPT_CORE0_CPU_PRI_18_MAP_S  0
 
-#define INTERRUPT_CORE0_CPU_INT_PRI_19_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x184)
-/* INTERRUPT_CORE0_CPU_PRI_19_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_CPU_PRI_19_MAP    0x0000000F
-#define INTERRUPT_CORE0_CPU_PRI_19_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_19_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_19_MAP_S))
-#define INTERRUPT_CORE0_CPU_PRI_19_MAP_V  0xF
+/** INTERRUPT_CORE0_CPU_INT_PRI_19_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_CPU_INT_PRI_19_REG (DR_REG_INTERRUPT_BASE + 0x184)
+/** INTERRUPT_CORE0_CPU_PRI_19_MAP : R/W; bitpos: [3:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_CPU_PRI_19_MAP    0x0000000FU
+#define INTERRUPT_CORE0_CPU_PRI_19_MAP_M  (INTERRUPT_CORE0_CPU_PRI_19_MAP_V << INTERRUPT_CORE0_CPU_PRI_19_MAP_S)
+#define INTERRUPT_CORE0_CPU_PRI_19_MAP_V  0x0000000FU
 #define INTERRUPT_CORE0_CPU_PRI_19_MAP_S  0
 
-#define INTERRUPT_CORE0_CPU_INT_PRI_20_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x188)
-/* INTERRUPT_CORE0_CPU_PRI_20_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_CPU_PRI_20_MAP    0x0000000F
-#define INTERRUPT_CORE0_CPU_PRI_20_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_20_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_20_MAP_S))
-#define INTERRUPT_CORE0_CPU_PRI_20_MAP_V  0xF
+/** INTERRUPT_CORE0_CPU_INT_PRI_20_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_CPU_INT_PRI_20_REG (DR_REG_INTERRUPT_BASE + 0x188)
+/** INTERRUPT_CORE0_CPU_PRI_20_MAP : R/W; bitpos: [3:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_CPU_PRI_20_MAP    0x0000000FU
+#define INTERRUPT_CORE0_CPU_PRI_20_MAP_M  (INTERRUPT_CORE0_CPU_PRI_20_MAP_V << INTERRUPT_CORE0_CPU_PRI_20_MAP_S)
+#define INTERRUPT_CORE0_CPU_PRI_20_MAP_V  0x0000000FU
 #define INTERRUPT_CORE0_CPU_PRI_20_MAP_S  0
 
-#define INTERRUPT_CORE0_CPU_INT_PRI_21_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x18C)
-/* INTERRUPT_CORE0_CPU_PRI_21_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_CPU_PRI_21_MAP    0x0000000F
-#define INTERRUPT_CORE0_CPU_PRI_21_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_21_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_21_MAP_S))
-#define INTERRUPT_CORE0_CPU_PRI_21_MAP_V  0xF
+/** INTERRUPT_CORE0_CPU_INT_PRI_21_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_CPU_INT_PRI_21_REG (DR_REG_INTERRUPT_BASE + 0x18c)
+/** INTERRUPT_CORE0_CPU_PRI_21_MAP : R/W; bitpos: [3:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_CPU_PRI_21_MAP    0x0000000FU
+#define INTERRUPT_CORE0_CPU_PRI_21_MAP_M  (INTERRUPT_CORE0_CPU_PRI_21_MAP_V << INTERRUPT_CORE0_CPU_PRI_21_MAP_S)
+#define INTERRUPT_CORE0_CPU_PRI_21_MAP_V  0x0000000FU
 #define INTERRUPT_CORE0_CPU_PRI_21_MAP_S  0
 
-#define INTERRUPT_CORE0_CPU_INT_PRI_22_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x190)
-/* INTERRUPT_CORE0_CPU_PRI_22_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_CPU_PRI_22_MAP    0x0000000F
-#define INTERRUPT_CORE0_CPU_PRI_22_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_22_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_22_MAP_S))
-#define INTERRUPT_CORE0_CPU_PRI_22_MAP_V  0xF
+/** INTERRUPT_CORE0_CPU_INT_PRI_22_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_CPU_INT_PRI_22_REG (DR_REG_INTERRUPT_BASE + 0x190)
+/** INTERRUPT_CORE0_CPU_PRI_22_MAP : R/W; bitpos: [3:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_CPU_PRI_22_MAP    0x0000000FU
+#define INTERRUPT_CORE0_CPU_PRI_22_MAP_M  (INTERRUPT_CORE0_CPU_PRI_22_MAP_V << INTERRUPT_CORE0_CPU_PRI_22_MAP_S)
+#define INTERRUPT_CORE0_CPU_PRI_22_MAP_V  0x0000000FU
 #define INTERRUPT_CORE0_CPU_PRI_22_MAP_S  0
 
-#define INTERRUPT_CORE0_CPU_INT_PRI_23_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x194)
-/* INTERRUPT_CORE0_CPU_PRI_23_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_CPU_PRI_23_MAP    0x0000000F
-#define INTERRUPT_CORE0_CPU_PRI_23_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_23_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_23_MAP_S))
-#define INTERRUPT_CORE0_CPU_PRI_23_MAP_V  0xF
+/** INTERRUPT_CORE0_CPU_INT_PRI_23_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_CPU_INT_PRI_23_REG (DR_REG_INTERRUPT_BASE + 0x194)
+/** INTERRUPT_CORE0_CPU_PRI_23_MAP : R/W; bitpos: [3:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_CPU_PRI_23_MAP    0x0000000FU
+#define INTERRUPT_CORE0_CPU_PRI_23_MAP_M  (INTERRUPT_CORE0_CPU_PRI_23_MAP_V << INTERRUPT_CORE0_CPU_PRI_23_MAP_S)
+#define INTERRUPT_CORE0_CPU_PRI_23_MAP_V  0x0000000FU
 #define INTERRUPT_CORE0_CPU_PRI_23_MAP_S  0
 
-#define INTERRUPT_CORE0_CPU_INT_PRI_24_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x198)
-/* INTERRUPT_CORE0_CPU_PRI_24_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_CPU_PRI_24_MAP    0x0000000F
-#define INTERRUPT_CORE0_CPU_PRI_24_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_24_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_24_MAP_S))
-#define INTERRUPT_CORE0_CPU_PRI_24_MAP_V  0xF
+/** INTERRUPT_CORE0_CPU_INT_PRI_24_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_CPU_INT_PRI_24_REG (DR_REG_INTERRUPT_BASE + 0x198)
+/** INTERRUPT_CORE0_CPU_PRI_24_MAP : R/W; bitpos: [3:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_CPU_PRI_24_MAP    0x0000000FU
+#define INTERRUPT_CORE0_CPU_PRI_24_MAP_M  (INTERRUPT_CORE0_CPU_PRI_24_MAP_V << INTERRUPT_CORE0_CPU_PRI_24_MAP_S)
+#define INTERRUPT_CORE0_CPU_PRI_24_MAP_V  0x0000000FU
 #define INTERRUPT_CORE0_CPU_PRI_24_MAP_S  0
 
-#define INTERRUPT_CORE0_CPU_INT_PRI_25_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x19C)
-/* INTERRUPT_CORE0_CPU_PRI_25_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_CPU_PRI_25_MAP    0x0000000F
-#define INTERRUPT_CORE0_CPU_PRI_25_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_25_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_25_MAP_S))
-#define INTERRUPT_CORE0_CPU_PRI_25_MAP_V  0xF
+/** INTERRUPT_CORE0_CPU_INT_PRI_25_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_CPU_INT_PRI_25_REG (DR_REG_INTERRUPT_BASE + 0x19c)
+/** INTERRUPT_CORE0_CPU_PRI_25_MAP : R/W; bitpos: [3:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_CPU_PRI_25_MAP    0x0000000FU
+#define INTERRUPT_CORE0_CPU_PRI_25_MAP_M  (INTERRUPT_CORE0_CPU_PRI_25_MAP_V << INTERRUPT_CORE0_CPU_PRI_25_MAP_S)
+#define INTERRUPT_CORE0_CPU_PRI_25_MAP_V  0x0000000FU
 #define INTERRUPT_CORE0_CPU_PRI_25_MAP_S  0
 
-#define INTERRUPT_CORE0_CPU_INT_PRI_26_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x1A0)
-/* INTERRUPT_CORE0_CPU_PRI_26_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_CPU_PRI_26_MAP    0x0000000F
-#define INTERRUPT_CORE0_CPU_PRI_26_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_26_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_26_MAP_S))
-#define INTERRUPT_CORE0_CPU_PRI_26_MAP_V  0xF
+/** INTERRUPT_CORE0_CPU_INT_PRI_26_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_CPU_INT_PRI_26_REG (DR_REG_INTERRUPT_BASE + 0x1a0)
+/** INTERRUPT_CORE0_CPU_PRI_26_MAP : R/W; bitpos: [3:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_CPU_PRI_26_MAP    0x0000000FU
+#define INTERRUPT_CORE0_CPU_PRI_26_MAP_M  (INTERRUPT_CORE0_CPU_PRI_26_MAP_V << INTERRUPT_CORE0_CPU_PRI_26_MAP_S)
+#define INTERRUPT_CORE0_CPU_PRI_26_MAP_V  0x0000000FU
 #define INTERRUPT_CORE0_CPU_PRI_26_MAP_S  0
 
-#define INTERRUPT_CORE0_CPU_INT_PRI_27_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x1A4)
-/* INTERRUPT_CORE0_CPU_PRI_27_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_CPU_PRI_27_MAP    0x0000000F
-#define INTERRUPT_CORE0_CPU_PRI_27_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_27_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_27_MAP_S))
-#define INTERRUPT_CORE0_CPU_PRI_27_MAP_V  0xF
+/** INTERRUPT_CORE0_CPU_INT_PRI_27_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_CPU_INT_PRI_27_REG (DR_REG_INTERRUPT_BASE + 0x1a4)
+/** INTERRUPT_CORE0_CPU_PRI_27_MAP : R/W; bitpos: [3:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_CPU_PRI_27_MAP    0x0000000FU
+#define INTERRUPT_CORE0_CPU_PRI_27_MAP_M  (INTERRUPT_CORE0_CPU_PRI_27_MAP_V << INTERRUPT_CORE0_CPU_PRI_27_MAP_S)
+#define INTERRUPT_CORE0_CPU_PRI_27_MAP_V  0x0000000FU
 #define INTERRUPT_CORE0_CPU_PRI_27_MAP_S  0
 
-#define INTERRUPT_CORE0_CPU_INT_PRI_28_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x1A8)
-/* INTERRUPT_CORE0_CPU_PRI_28_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_CPU_PRI_28_MAP    0x0000000F
-#define INTERRUPT_CORE0_CPU_PRI_28_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_28_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_28_MAP_S))
-#define INTERRUPT_CORE0_CPU_PRI_28_MAP_V  0xF
+/** INTERRUPT_CORE0_CPU_INT_PRI_28_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_CPU_INT_PRI_28_REG (DR_REG_INTERRUPT_BASE + 0x1a8)
+/** INTERRUPT_CORE0_CPU_PRI_28_MAP : R/W; bitpos: [3:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_CPU_PRI_28_MAP    0x0000000FU
+#define INTERRUPT_CORE0_CPU_PRI_28_MAP_M  (INTERRUPT_CORE0_CPU_PRI_28_MAP_V << INTERRUPT_CORE0_CPU_PRI_28_MAP_S)
+#define INTERRUPT_CORE0_CPU_PRI_28_MAP_V  0x0000000FU
 #define INTERRUPT_CORE0_CPU_PRI_28_MAP_S  0
 
-#define INTERRUPT_CORE0_CPU_INT_PRI_29_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x1AC)
-/* INTERRUPT_CORE0_CPU_PRI_29_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_CPU_PRI_29_MAP    0x0000000F
-#define INTERRUPT_CORE0_CPU_PRI_29_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_29_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_29_MAP_S))
-#define INTERRUPT_CORE0_CPU_PRI_29_MAP_V  0xF
+/** INTERRUPT_CORE0_CPU_INT_PRI_29_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_CPU_INT_PRI_29_REG (DR_REG_INTERRUPT_BASE + 0x1ac)
+/** INTERRUPT_CORE0_CPU_PRI_29_MAP : R/W; bitpos: [3:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_CPU_PRI_29_MAP    0x0000000FU
+#define INTERRUPT_CORE0_CPU_PRI_29_MAP_M  (INTERRUPT_CORE0_CPU_PRI_29_MAP_V << INTERRUPT_CORE0_CPU_PRI_29_MAP_S)
+#define INTERRUPT_CORE0_CPU_PRI_29_MAP_V  0x0000000FU
 #define INTERRUPT_CORE0_CPU_PRI_29_MAP_S  0
 
-#define INTERRUPT_CORE0_CPU_INT_PRI_30_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x1B0)
-/* INTERRUPT_CORE0_CPU_PRI_30_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_CPU_PRI_30_MAP    0x0000000F
-#define INTERRUPT_CORE0_CPU_PRI_30_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_30_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_30_MAP_S))
-#define INTERRUPT_CORE0_CPU_PRI_30_MAP_V  0xF
+/** INTERRUPT_CORE0_CPU_INT_PRI_30_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_CPU_INT_PRI_30_REG (DR_REG_INTERRUPT_BASE + 0x1b0)
+/** INTERRUPT_CORE0_CPU_PRI_30_MAP : R/W; bitpos: [3:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_CPU_PRI_30_MAP    0x0000000FU
+#define INTERRUPT_CORE0_CPU_PRI_30_MAP_M  (INTERRUPT_CORE0_CPU_PRI_30_MAP_V << INTERRUPT_CORE0_CPU_PRI_30_MAP_S)
+#define INTERRUPT_CORE0_CPU_PRI_30_MAP_V  0x0000000FU
 #define INTERRUPT_CORE0_CPU_PRI_30_MAP_S  0
 
-#define INTERRUPT_CORE0_CPU_INT_PRI_31_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x1B4)
-/* INTERRUPT_CORE0_CPU_PRI_31_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_CPU_PRI_31_MAP    0x0000000F
-#define INTERRUPT_CORE0_CPU_PRI_31_MAP_M  ((INTERRUPT_CORE0_CPU_PRI_31_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_31_MAP_S))
-#define INTERRUPT_CORE0_CPU_PRI_31_MAP_V  0xF
+/** INTERRUPT_CORE0_CPU_INT_PRI_31_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_CPU_INT_PRI_31_REG (DR_REG_INTERRUPT_BASE + 0x1b4)
+/** INTERRUPT_CORE0_CPU_PRI_31_MAP : R/W; bitpos: [3:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_CPU_PRI_31_MAP    0x0000000FU
+#define INTERRUPT_CORE0_CPU_PRI_31_MAP_M  (INTERRUPT_CORE0_CPU_PRI_31_MAP_V << INTERRUPT_CORE0_CPU_PRI_31_MAP_S)
+#define INTERRUPT_CORE0_CPU_PRI_31_MAP_V  0x0000000FU
 #define INTERRUPT_CORE0_CPU_PRI_31_MAP_S  0
 
-#define INTERRUPT_CORE0_CPU_INT_THRESH_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x1B8)
-/* INTERRUPT_CORE0_CPU_INT_THRESH : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_CPU_INT_THRESH    0x0000000F
-#define INTERRUPT_CORE0_CPU_INT_THRESH_M  ((INTERRUPT_CORE0_CPU_INT_THRESH_V)<<(INTERRUPT_CORE0_CPU_INT_THRESH_S))
-#define INTERRUPT_CORE0_CPU_INT_THRESH_V  0xF
+/** INTERRUPT_CORE0_CPU_INT_THRESH_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_CPU_INT_THRESH_REG (DR_REG_INTERRUPT_BASE + 0x1b8)
+/** INTERRUPT_CORE0_CPU_INT_THRESH : R/W; bitpos: [3:0]; default: 0;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_CPU_INT_THRESH    0x0000000FU
+#define INTERRUPT_CORE0_CPU_INT_THRESH_M  (INTERRUPT_CORE0_CPU_INT_THRESH_V << INTERRUPT_CORE0_CPU_INT_THRESH_S)
+#define INTERRUPT_CORE0_CPU_INT_THRESH_V  0x0000000FU
 #define INTERRUPT_CORE0_CPU_INT_THRESH_S  0
 
-#define INTERRUPT_CORE0_INTERRUPT_DATE_REG          (DR_REG_INTERRUPT_CORE0_BASE + 0x7FC)
-/* INTERRUPT_CORE0_INTERRUPT_DATE : R/W ;bitpos:[27:0] ;default: 28'h2011090 ; */
-/*description: Need add description.*/
-#define INTERRUPT_CORE0_INTERRUPT_DATE    0x0FFFFFFF
-#define INTERRUPT_CORE0_INTERRUPT_DATE_M  ((INTERRUPT_CORE0_INTERRUPT_DATE_V)<<(INTERRUPT_CORE0_INTERRUPT_DATE_S))
-#define INTERRUPT_CORE0_INTERRUPT_DATE_V  0xFFFFFFF
-#define INTERRUPT_CORE0_INTERRUPT_DATE_S  0
+/** INTERRUPT_CORE0_INTERRUPT_REG_DATE_REG register
+ *  register description
+ */
+#define INTERRUPT_CORE0_INTERRUPT_REG_DATE_REG (DR_REG_INTERRUPT_BASE + 0x7fc)
+/** INTERRUPT_CORE0_INTERRUPT_REG_DATE : R/W; bitpos: [27:0]; default: 33624208;
+ *  Need add description
+ */
+#define INTERRUPT_CORE0_INTERRUPT_REG_DATE    0x0FFFFFFFU
+#define INTERRUPT_CORE0_INTERRUPT_REG_DATE_M  (INTERRUPT_CORE0_INTERRUPT_REG_DATE_V << INTERRUPT_CORE0_INTERRUPT_REG_DATE_S)
+#define INTERRUPT_CORE0_INTERRUPT_REG_DATE_V  0x0FFFFFFFU
+#define INTERRUPT_CORE0_INTERRUPT_REG_DATE_S  0
 
-#define INTC_INT_PRIO_REG(n)                        (INTERRUPT_CORE0_CPU_INT_PRI_0_REG + (n)*4)
 #ifdef __cplusplus
 }
 #endif
-
-
-
-#endif /*_SOC_INTERRUPT_CORE0_REG_H_ */

components/soc/esp32h2/include/rev2/soc/io_mux_reg.h

@@ -266,3 +266,16 @@
 #define PERIPHS_IO_MUX_GPIO25_U              (REG_IO_MUX_BASE + 0x68)
 #define FUNC_GPIO25_GPIO25                                          1
 #define FUNC_GPIO25_GPIO25_0                                        0
+
+/** IO_MUX_DATE_REG register
+ *  IO MUX Version Control Register
+ */
+#define IO_MUX_DATE_REG (REG_IO_MUX_BASE + 0xfc)
+/** IO_MUX_DATE : R/W; bitpos: [27:0]; default: 0x2109090;
+ *  Version control register
+ */
+#define IO_MUX_DATE 0x0FFFFFFF
+#define IO_MUX_DATE_M  (IO_MUX_DATE_V << IO_MUX_DATE_S)
+#define IO_MUX_DATE_V  0x0FFFFFFFU
+#define IO_MUX_DATE_S  0
+#define IO_MUX_DATE_VERSION 0x2109090

components/soc/esp32h2/include/rev2/soc/rtc_cntl_struct.h

@@ -1,1020 +1,2984 @@
-/*
- * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
+/**
+ * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
  *
- * SPDX-License-Identifier: Apache-2.0
+ *  SPDX-License-Identifier: Apache-2.0
  */
-#ifndef _SOC_RTC_CNTL_STRUCT_H_
-#define _SOC_RTC_CNTL_STRUCT_H_
-
+#pragma once
 
+#include <stdint.h>
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-typedef volatile struct rtc_cntl_dev_s{
-    union {
-        struct {
-            uint32_t sw_stall_appcpu_c0            :    2;  /*{reg_sw_stall_appcpu_c1[5:0],  reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU*/
-            uint32_t sw_stall_procpu_c0            :    2;  /*{reg_sw_stall_procpu_c1[5:0],  reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall PRO CPU*/
-            uint32_t sw_appcpu_rst                 :    1;  /*APP CPU SW reset*/
-            uint32_t sw_procpu_rst                 :    1;  /*PRO CPU SW reset*/
-            uint32_t bb_i2c_force_pd               :    1;  /*BB_I2C force power down*/
-            uint32_t bb_i2c_force_pu               :    1;  /*BB_I2C force power up*/
-            uint32_t bbpll_i2c_force_pd            :    1;  /*BB_PLL _I2C force power down*/
-            uint32_t bbpll_i2c_force_pu            :    1;  /*BB_PLL_I2C force power up*/
-            uint32_t bbpll_force_pd                :    1;  /*BB_PLL force power down*/
-            uint32_t bbpll_force_pu                :    1;  /*BB_PLL force power up*/
-            uint32_t xtl_force_pd                  :    1;  /*crystall force power down*/
-            uint32_t xtl_force_pu                  :    1;  /*crystall force power up*/
-            uint32_t xtl_en_wait                   :    4;  /*wait bias_sleep and current source wakeup*/
-            uint32_t xpd_rfpll                     :    1;  /*Need add description*/
-            uint32_t xpd_rfpll_force               :    1;  /*Need add description*/
-            uint32_t ctr_sel                       :    3;  /*Need add description*/
-            uint32_t xtl_force_iso                 :    1;  /*Need add description*/
-            uint32_t pll_force_iso                 :    1;  /*Need add description*/
-            uint32_t analog_force_iso              :    1;  /*Need add description*/
-            uint32_t xtl_force_noiso               :    1;  /*Need add description*/
-            uint32_t pll_force_noiso               :    1;  /*Need add description*/
-            uint32_t analog_force_noiso            :    1;  /*Need add description*/
-            uint32_t dg_wrap_force_rst             :    1;  /*digital wrap force reset in deep sleep*/
-            uint32_t dg_wrap_force_norst           :    1;  /*digital core force no reset in deep sleep*/
-            uint32_t sw_sys_rst                    :    1;  /*SW system  reset*/
-        };
-        uint32_t val;
-    } options0;
-    uint32_t slp_timer0;
-    union {
-        struct {
-            uint32_t slp_val_hi                    :    16;  /*RTC sleep timer high 16 bits*/
-            uint32_t main_timer_alarm_en           :    1;  /*timer alarm enable bit*/
-            uint32_t reserved17                    :    15;  /*Reserved*/
-        };
-        uint32_t val;
-    } slp_timer1;
-    union {
-        struct {
-            uint32_t reserved0                     :    27;  /*Reserved*/
-            uint32_t timer_sys_stall               :    1;  /*Enable to record system stall time*/
-            uint32_t timer_xtl_off                 :    1;  /*Enable to record 40M XTAL OFF time*/
-            uint32_t timer_sys_rst                 :    1;  /*enable to record system reset time*/
-            uint32_t reserved30                    :    1;  /*Reserved*/
-            uint32_t update                        :    1;  /*Set 1: to update register with RTC timer*/
-        };
-        uint32_t val;
-    } time_update;
-    uint32_t time_low0;
-    union {
-        struct {
-            uint32_t rtc_timer_value0_high         :    16;  /*RTC timer high 16 bits*/
-            uint32_t reserved16                    :    16;  /*Reserved*/
-        };
-        uint32_t val;
-    } time_high0;
-    union {
-        struct {
-            uint32_t rtc_sw_cpu_int                :    1;  /*rtc software interrupt to main cpu*/
-            uint32_t rtc_slp_reject_cause_clr      :    1;  /*clear rtc sleep reject cause*/
-            uint32_t reserved2                     :    20;  /*Reserved*/
-            uint32_t apb2rtc_bridge_sel            :    1;  /*1: APB to RTC using bridge,  0: APB to RTC using sync*/
-            uint32_t reserved23                    :    5;  /*Reserved*/
-            uint32_t sdio_active_ind               :    1;  /*SDIO active indication*/
-            uint32_t slp_wakeup                    :    1;  /*leep wakeup bit*/
-            uint32_t slp_reject                    :    1;  /*leep reject bit*/
-            uint32_t sleep_en                      :    1;  /*sleep enable bit*/
-        };
-        uint32_t val;
-    } state0;
-    union {
-        struct {
-            uint32_t cpu_stall_en                  :    1;  /*CPU stall enable bit*/
-            uint32_t cpu_stall_wait                :    5;  /*CPU stall wait cycles in fast_clk_rtc*/
-            uint32_t ck8m_wait                     :    8;  /*CK8M wait cycles in slow_clk_rtc*/
-            uint32_t xtl_buf_wait                  :    10;  /*XTAL wait cycles in slow_clk_rtc*/
-            uint32_t pll_buf_wait                  :    8;  /*PLL wait cycles in slow_clk_rtc*/
-        };
-        uint32_t val;
-    } timer1;
-    union {
-        struct {
-            uint32_t reserved0                     :    24;  /*Reserved*/
-            uint32_t min_time_ck8m_off             :    8;  /*minimal cycles in slow_clk_rtc for CK8M in power down state*/
-        };
-        uint32_t val;
-    } timer2;
-    union {
-        struct {
-            uint32_t wifi_wait_timer               :    9;  /*Need add description*/
-            uint32_t wifi_powerup_timer            :    7;  /*Need add description*/
-            uint32_t bt_wait_timer                 :    9;  /*Need add description*/
-            uint32_t bt_powerup_timer              :    7;  /*Need add description*/
-        };
-        uint32_t val;
-    } timer3;
-    union {
-        struct {
-            uint32_t cpu_top_wait_timer            :    9;  /*Need add description*/
-            uint32_t cpu_top_powerup_timer         :    7;  /*Need add description*/
-            uint32_t dg_wrap_wait_timer            :    9;  /*Need add description*/
-            uint32_t dg_wrap_powerup_timer         :    7;  /*Need add description*/
-        };
-        uint32_t val;
-    } timer4;
-    union {
-        struct {
-            uint32_t reserved0                     :    8;  /*Reserved*/
-            uint32_t min_slp_val                   :    8;  /*minimal sleep cycles in slow_clk_rtc*/
-            uint32_t reserved16                    :    16;  /*Reserved*/
-        };
-        uint32_t val;
-    } timer5;
-    union {
-        struct {
-            uint32_t reserved0                     :    16;  /*Reserved*/
-            uint32_t dg_peri_wait_timer            :    9;  /*Need add description*/
-            uint32_t dg_peri_powerup_timer         :    7;  /*Need add description*/
-        };
-        uint32_t val;
-    } timer6;
-    union {
-        struct {
-            uint32_t reserved0                     :    16;  /*Reserved*/
-            uint32_t xpd_trx_force_pd              :    1;  /*Need add description*/
-            uint32_t xpd_trx_force_pu              :    1;  /*Need add description*/
-            uint32_t i2c_reset_por_force_pd        :    1;  /*Need add description*/
-            uint32_t i2c_reset_por_force_pu        :    1;  /*Need add description*/
-            uint32_t glitch_rst_en                 :    1;  /*Need add description*/
-            uint32_t reserved21                    :    1;  /*ReservedPLLA force power down*/
-            uint32_t peri_i2c_pu                   :    1;  /*PLLA force power up*/
-            uint32_t plla_force_pd                 :    1;  /*PLLA force power down*/
-            uint32_t plla_force_pu                 :    1;  /*PLLA force power up*/
-            uint32_t bbpll_cal_slp_start           :    1;  /*start BBPLL calibration during sleep*/
-            uint32_t pvtmon_pu                     :    1;  /*1: PVTMON power up , otherwise power down*/
-            uint32_t txrf_i2c_pu                   :    1;  /*1: TXRF_I2C power up , otherwise power down*/
-            uint32_t rfrx_pbus_pu                  :    1;  /*1: RFRX_PBUS power up , otherwise power down*/
-            uint32_t reserved29                    :    1;  /*Reserved*/
-            uint32_t ckgen_i2c_pu                  :    1;  /*1: CKGEN_I2C power up , otherwise power down*/
-            uint32_t pll_i2c_pu                    :    1;  /*Need add description*/
-        };
-        uint32_t val;
-    } ana_conf;
-    union {
-        struct {
-            uint32_t reset_cause_procpu            :    6;  /*reset cause of PRO CPU*/
-            uint32_t reset_cause_appcpu            :    6;  /*reset cause of APP CPU*/
-            uint32_t stat_vector_sel_appcpu        :    1;  /*APP CPU state vector sel*/
-            uint32_t stat_vector_sel_procpu        :    1;  /*PRO CPU state vector sel*/
-            uint32_t all_reset_flag_procpu         :    1;  /*PRO CPU reset_flag*/
-            uint32_t all_reset_flag_appcpu         :    1;  /*APP CPU reset flag*/
-            uint32_t all_reset_flag_clr_procpu     :    1;  /*clear PRO CPU reset_flag*/
-            uint32_t all_reset_flag_clr_appcpu     :    1;  /*clear APP CPU reset flag*/
-            uint32_t ocd_halt_on_reset_appcpu      :    1;  /*APPCPU OcdHaltOnReset*/
-            uint32_t ocd_halt_on_reset_procpu      :    1;  /*PROCPU OcdHaltOnReset*/
-            uint32_t jtag_reset_flag_procpu        :    1;  /*Need add description*/
-            uint32_t jtag_reset_flag_appcpu        :    1;  /*Need add description*/
-            uint32_t jtag_reset_flag_clr_procpu    :    1;  /*Need add description*/
-            uint32_t jtag_reset_flag_clr_appcpu    :    1;  /*Need add description*/
-            uint32_t rtc_dreset_mask_appcpu        :    1;  /*Need add description*/
-            uint32_t rtc_dreset_mask_procpu        :    1;  /*Need add description*/
-            uint32_t reserved26                    :    6;  /*Reserved*/
-        };
-        uint32_t val;
-    } reset_state;
-    union {
-        struct {
-            uint32_t reserved0                     :    13;  /*Reserved*/
-            uint32_t rtc_wakeup_ena                :    19;  /*wakeup enable bitmap*/
-        };
-        uint32_t val;
-    } wakeup_state;
-    union {
-        struct {
-            uint32_t slp_wakeup                    :    1;  /*enable sleep wakeup interrupt*/
-            uint32_t slp_reject                    :    1;  /*enable sleep reject interrupt*/
-            uint32_t reserved2                     :    1;  /*Reservedenable SDIO idle interrupt*/
-            uint32_t rtc_wdt                       :    1;  /*enable RTC WDT interrupt*/
-            uint32_t reserved4                     :    5;  /*Reserved*/
-            uint32_t rtc_brown_out                 :    1;  /*enable brown out interrupt*/
-            uint32_t rtc_main_timer                :    1;  /*enable RTC main timer interrupt*/
-            uint32_t reserved11                    :    4;  /*Reservedenable saradc2 interrupt*/
-            uint32_t rtc_swd                       :    1;  /*enable super watch dog interrupt*/
-            uint32_t rtc_xtal32k_dead              :    1;  /*enable xtal32k_dead  interrupt*/
-            uint32_t reserved17                    :    2;  /*Reservedenable touch timeout interrupt*/
-            uint32_t rtc_glitch_det                :    1;  /*enbale gitch det interrupt*/
-            uint32_t rtc_bbpll_cal                 :    1;  /*Need add description*/
-            uint32_t rtc_ble_compare_wake          :    1;  /*Need add description*/
-            uint32_t vset_dcdc_done                :    1;  /*Need add description*/
-            uint32_t reserved23                    :    9;  /*Reserved*/
-        };
-        uint32_t val;
-    } int_ena;
-    union {
-        struct {
-            uint32_t slp_wakeup                    :    1;  /*sleep wakeup interrupt raw*/
-            uint32_t slp_reject                    :    1;  /*sleep reject interrupt raw*/
-            uint32_t reserved2                     :    1;  /*ReservedSDIO idle interrupt raw*/
-            uint32_t rtc_wdt                       :    1;  /*RTC WDT interrupt raw*/
-            uint32_t reserved4                     :    5;  /*Reservedtouch inactive interrupt raw*/
-            uint32_t rtc_brown_out                 :    1;  /*brown out interrupt raw*/
-            uint32_t rtc_main_timer                :    1;  /*RTC main timer interrupt raw*/
-            uint32_t reserved11                    :    4;  /*Reservedsaradc2 interrupt raw*/
-            uint32_t rtc_swd                       :    1;  /*super watch dog interrupt raw*/
-            uint32_t rtc_xtal32k_dead              :    1;  /*xtal32k dead detection interrupt raw*/
-            uint32_t reserved17                    :    2;  /*Reservedtouch timeout interrupt raw*/
-            uint32_t rtc_glitch_det                :    1;  /*glitch_det_interrupt_raw*/
-            uint32_t rtc_bbpll_cal                 :    1;  /*Need add description*/
-            uint32_t rtc_ble_compare_wake          :    1;  /*Need add description*/
-            uint32_t vset_dcdc_done                :    1;  /*Need add description*/
-            uint32_t reserved23                    :    9;  /*Reserved*/
-        };
-        uint32_t val;
-    } int_raw;
-    union {
-        struct {
-            uint32_t slp_wakeup                    :    1;  /*sleep wakeup interrupt state*/
-            uint32_t slp_reject                    :    1;  /*sleep reject interrupt state*/
-            uint32_t reserved2                     :    1;  /*Reserved*/
-            uint32_t rtc_wdt                       :    1;  /*RTC WDT interrupt state*/
-            uint32_t reserved4                     :    5;  /*Reserved*/
-            uint32_t rtc_brown_out                 :    1;  /*brown out interrupt state*/
-            uint32_t rtc_main_timer                :    1;  /*RTC main timer interrupt state*/
-            uint32_t reserved11                    :    4;  /*Reserved*/
-            uint32_t rtc_swd                       :    1;  /*super watch dog interrupt state*/
-            uint32_t rtc_xtal32k_dead              :    1;  /*xtal32k dead detection interrupt state*/
-            uint32_t reserved17                    :    2;  /*Reserved*/
-            uint32_t rtc_glitch_det                :    1;  /*glitch_det_interrupt state*/
-            uint32_t rtc_bbpll_cal                 :    1;  /*Need add description*/
-            uint32_t rtc_ble_compare_wake          :    1;  /*Need add description*/
-            uint32_t vset_dcdc_done                :    1;  /*Need add description*/
-            uint32_t reserved23                    :    9;  /*Reserved*/
-        };
-        uint32_t val;
-    } int_st;
-    union {
-        struct {
-            uint32_t slp_wakeup                    :    1;  /*Clear sleep wakeup interrupt state*/
-            uint32_t slp_reject                    :    1;  /*Clear sleep reject interrupt state*/
-            uint32_t reserved2                     :    1;  /*Reserved*/
-            uint32_t rtc_wdt                       :    1;  /*Clear RTC WDT interrupt state*/
-            uint32_t reserved4                     :    5;  /*Reserved*/
-            uint32_t rtc_brown_out                 :    1;  /*Clear brown out interrupt state*/
-            uint32_t rtc_main_timer                :    1;  /*Clear RTC main timer interrupt state*/
-            uint32_t reserved11                    :    4;  /*Reserved*/
-            uint32_t rtc_swd                       :    1;  /*Clear super watch dog interrupt state*/
-            uint32_t rtc_xtal32k_dead              :    1;  /*Clear RTC WDT interrupt state*/
-            uint32_t reserved17                    :    2;  /*Reserved*/
-            uint32_t rtc_glitch_det                :    1;  /*Clear glitch det interrupt state*/
-            uint32_t rtc_bbpll_cal                 :    1;  /*Need add description*/
-            uint32_t rtc_ble_compare_wake          :    1;  /*Need add description*/
-            uint32_t vset_dcdc_done                :    1;  /*Need add description*/
-            uint32_t reserved23                    :    9;  /*Reserved*/
-        };
-        uint32_t val;
-    } int_clr;
-    uint32_t store[4];
-    union {
-        struct {
-            uint32_t xtal32k_wdt_en                :    1;  /*xtal 32k watch dog enable*/
-            uint32_t xtal32k_wdt_clk_fo            :    1;  /*xtal 32k watch dog clock force on*/
-            uint32_t xtal32k_wdt_reset             :    1;  /*xtal 32k watch dog sw reset*/
-            uint32_t xtal32k_ext_clk_fo            :    1;  /*xtal 32k external xtal clock force on*/
-            uint32_t xtal32k_auto_backup           :    1;  /*xtal 32k switch to back up clock when xtal is dead*/
-            uint32_t xtal32k_auto_restart          :    1;  /*xtal 32k restart xtal when xtal is dead*/
-            uint32_t xtal32k_auto_return           :    1;  /*xtal 32k switch back xtal when xtal is restarted*/
-            uint32_t xtal32k_xpd_force             :    1;  /*Xtal 32k xpd control by sw or fsm*/
-            uint32_t enckinit_xtal_32k             :    1;  /*apply an internal clock to help xtal 32k to start*/
-            uint32_t dbuf_xtal_32k                 :    1;  /*0: single-end buffer 1: differential buffer*/
-            uint32_t dgm_xtal_32k                  :    3;  /*xtal_32k gm control*/
-            uint32_t dres_xtal_32k                 :    3;  /*DRES_XTAL_32K*/
-            uint32_t xpd_xtal_32k                  :    1;  /*XPD_XTAL_32K*/
-            uint32_t dac_xtal_32k                  :    3;  /*DAC_XTAL_32K*/
-            uint32_t rtc_wdt_state                 :    3;  /*state of 32k_wdt*/
-            uint32_t rtc_xtal32k_gpio_sel          :    1;  /*XTAL_32K sel. 0: external XTAL_32K, 1: CLK from RTC pad X32P_C*/
-            uint32_t reserved24                    :    6;  /*Reserved*/
-            uint32_t ctr_lv                        :    1;  /*0: power down XTAL at high level, 1: power down XTAL at low level*/
-            uint32_t ctr_en                        :    1;  /*Need add description*/
-        };
-        uint32_t val;
-    } ext_xtl_conf;
-    union {
-        struct {
-            uint32_t reserved0                     :    31;  /*Reserved*/
-            uint32_t gpio_wakeup_filter            :    1;  /*enable filter for gpio wakeup event*/
-        };
-        uint32_t val;
-    } ext_wakeup_conf;
-    union {
-        struct {
-            uint32_t reserved0                     :    11;  /*Reserved*/
-            uint32_t rtc_sleep_reject_ena          :    19;  /*sleep reject enable*/
-            uint32_t light_slp_reject_en           :    1;  /*enable reject for light sleep*/
-            uint32_t deep_slp_reject_en            :    1;  /*enable reject for deep sleep*/
-        };
-        uint32_t val;
-    } slp_reject_conf;
-    union {
-        struct {
-            uint32_t reserved0                     :    29;  /*Reserved*/
-            uint32_t cpusel_conf                   :    1;  /*CPU sel option*/
-            uint32_t cpuperiod_sel                 :    2;  /*Need add description*/
-        };
-        uint32_t val;
-    } cpu_period_conf;
-    union {
-        struct {
-            uint32_t rtc_ble_tmr_rst               :    1;  /*Need add description*/
-            uint32_t efuse_clk_force_gating        :    1;  /*Need add description*/
-            uint32_t efuse_clk_force_nogating      :    1;  /*Need add description*/
-            uint32_t ck8m_div_sel_vld              :    1;  /*used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel, then set vld to actually switch the clk*/
-            uint32_t dig_xtal32k_en                :    1;  /*enable CK_XTAL_32K for digital core (no relationship with RTC core)*/
-            uint32_t dig_rc32k_en                  :    1;  /*enable RC32K for digital core (no relationship with RTC core)*/
-            uint32_t dig_clk8m_en                  :    1;  /*enable CK8M for digital core (no relationship with RTC core)*/
-            uint32_t rtc_ble_timer_sel             :    1;  /*Need add description*/
-            uint32_t reserved8                     :    2;  /*Reserved*/
-            uint32_t ck8m_div_sel                  :    3;  /*divider = reg_ck8m_div_sel + 1*/
-            uint32_t xtal_force_nogating           :    1;  /*XTAL force no gating during sleep*/
-            uint32_t ck8m_force_nogating           :    1;  /*CK8M force no gating during sleep*/
-            uint32_t ck8m_dfreq                    :    10;  /*CK8M_DFREQ*/
-            uint32_t ck8m_force_pd                 :    1;  /*CK8M force power down*/
-            uint32_t ck8m_force_pu                 :    1;  /*CK8M force power up*/
-            uint32_t xtal_global_force_gating      :    1;  /*Need add description*/
-            uint32_t xtal_global_force_nogating    :    1;  /*Need add description*/
-            uint32_t fast_clk_rtc_sel              :    1;  /*fast_clk_rtc sel. 0: XTAL div 4, 1: CK8M */
-            uint32_t ana_clk_rtc_sel               :    2;  /*Need add description*/
-        };
-        uint32_t val;
-    } clk_conf;
-    union {
-        struct {
-            uint32_t reserved0                     :    19;  /*Reserved*/
-            uint32_t rtc_ana_clk_pd_slp            :    1;  /*Need add description*/
-            uint32_t rtc_ana_clk_pd_monitor        :    1;  /*Need add description*/
-            uint32_t rtc_ana_clk_pd_idle           :    1;  /*Need add description*/
-            uint32_t rtc_ana_clk_div_vld           :    1;  /*used to sync div bus. clear vld before set reg_rtc_ana_clk_div, then set vld to actually switch the clk */
-            uint32_t rtc_ana_clk_div               :    8;  /*Need add description*/
-            uint32_t slow_clk_next_edge            :    1;  /*Need add description*/
-        };
-        uint32_t val;
-    } slow_clk_conf;
-    union {
-        struct {
-            uint32_t sdio_timer_target             :    8;  /*timer count to apply reg_sdio_dcap after sdio power on*/
-            uint32_t reserved8                     :    1;  /*Reserved*/
-            uint32_t sdio_dthdrv                   :    2;  /*Tieh = 1 mode drive ability. Initially set to 0 to limit charge current, set to 3 after several us.*/
-            uint32_t sdio_dcap                     :    2;  /*ability to prevent LDO from overshoot*/
-            uint32_t sdio_initi                    :    2;  /*add resistor from ldo output to ground. 0: no res, 1: 6k, 2: 4k, 3: 2k */
-            uint32_t sdio_en_initi                 :    1;  /*0 to set init[1:0]=0*/
-            uint32_t sdio_dcurlim                  :    3;  /*tune current limit threshold when tieh = 0. About 800mA/(8+d)*/
-            uint32_t sdio_modecurlim               :    1;  /*select current limit mode*/
-            uint32_t sdio_encurlim                 :    1;  /*enable current limit*/
-            uint32_t sdio_pd_en                    :    1;  /*power down SDIO_REG in sleep. Only active when reg_sdio_force = 0*/
-            uint32_t sdio_force                    :    1;  /*1: use SW option to control SDIO_REG ,0: use state machine*/
-            uint32_t sdio_tieh                     :    1;  /*SW option for SDIO_TIEH. Only active when reg_sdio_force = 1*/
-            uint32_t reg1p8_ready                  :    1;  /*read only register for REG1P8_READY*/
-            uint32_t drefl_sdio                    :    2;  /*SW option for DREFL_SDIO. Only active when reg_sdio_force = 1*/
-            uint32_t drefm_sdio                    :    2;  /*SW option for DREFM_SDIO. Only active when reg_sdio_force = 1*/
-            uint32_t drefh_sdio                    :    2;  /*SW option for DREFH_SDIO. Only active when reg_sdio_force = 1*/
-            uint32_t xpd_sdio                      :    1;  /*Need add description*/
-        };
-        uint32_t val;
-    } sdio_conf;
-    union {
-        struct {
-            uint32_t reserved0                     :    10;  /*Reserved*/
-            uint32_t bias_buf_idle                 :    1;  /*Need add description*/
-            uint32_t bias_buf_wake                 :    1;  /*Need add description*/
-            uint32_t bias_buf_deep_slp             :    1;  /*Need add description*/
-            uint32_t bias_buf_monitor              :    1;  /*Need add description*/
-            uint32_t pd_cur_deep_slp               :    1;  /*xpd cur when rtc in sleep_state*/
-            uint32_t pd_cur_monitor                :    1;  /*xpd cur when rtc in monitor state*/
-            uint32_t bias_sleep_deep_slp           :    1;  /*bias_sleep when rtc in sleep_state*/
-            uint32_t bias_sleep_monitor            :    1;  /*bias_sleep when rtc in monitor state*/
-            uint32_t dbg_atten_deep_slp            :    4;  /*DBG_ATTEN when rtc in sleep state*/
-            uint32_t dbg_atten_monitor             :    4;  /*DBG_ATTEN when rtc in monitor state*/
-            uint32_t xpd_dcdc_slp                  :    1;  /*Need add description*/
-            uint32_t xpd_dcdc_monitor              :    1;  /*Need add description*/
-            uint32_t xpd_dcdc_idle                 :    1;  /*Need add description*/
-            uint32_t reserved29                    :    3;  /*Reserved*/
-        };
-        uint32_t val;
-    } bias_conf;
-    union {
-        struct {
-            uint32_t dbias_switch_slp              :    1;  /*Need add description*/
-            uint32_t dbias_switch_monitor          :    1;  /*Need add description*/
-            uint32_t dbias_switch_idle             :    1;  /*Need add description*/
-            uint32_t dig_cal_en                    :    1;  /*Need add description*/
-            uint32_t sck_dcap                      :    8;  /*Need add description*/
-            uint32_t reserved12                    :    3;  /*Reserved*/
-            uint32_t rtc_vdd_drv_b_active          :    6;  /*SCK_DCAP*/
-            uint32_t rtc_vdd_drv_b_slp             :    6;  /*Need add description*/
-            uint32_t rtc_vdd_drv_b_slp_en          :    1;  /*Need add description*/
-            uint32_t rtc_dboost_force_pd           :    1;  /*RTC_DBOOST force power down*/
-            uint32_t rtc_dboost_force_pu           :    1;  /*RTC_DBOOST force power up*/
-            uint32_t rtculator_force_pd            :    1;  /*RTC_REG force power down (for RTC_REG power down means decrease the voltage to 0.8v or lower )*/
-            uint32_t rtculator_force_pu            :    1;  /*Need add description*/
-        };
-        uint32_t val;
-    } rtculator;
-    union {
-        struct {
-            uint32_t reserved0                     :    15;  /*Reserved*/
-            uint32_t pvt_rtc_dbias                 :    5;  /*get pvt dbias value*/
-            uint32_t rtculator0_dbias_slp          :    5;  /*the rtc regulator0 dbias when chip in sleep state*/
-            uint32_t rtculator0_dbias_active       :    5;  /*the rtc regulator0 dbias when chip in active state*/
-            uint32_t reserved30                    :    1;  /*Reserved*/
-            uint32_t rtculator0_dbias_sel          :    1;  /*1: select sw dbias_active 0: select pvt value*/
-        };
-        uint32_t val;
-    } rtculator0_dbias;
-    union {
-        struct {
-            uint32_t reserved0                     :    20;  /*Reserved*/
-            uint32_t rtculator1_dbias_slp          :    4;  /*the rtc regulator1 dbias when chip in sleep state*/
-            uint32_t reserved24                    :    1;  /*Reserved*/
-            uint32_t rtculator1_dbias_active       :    4;  /*the rtc regulator1 dbias when chip in active state*/
-            uint32_t reserved29                    :    3;  /*Reserved*/
-        };
-        uint32_t val;
-    } rtculator1_dbias;
-    union {
-        struct {
-            uint32_t reserved0                     :    1;  /*Reserved*/
-            uint32_t memulator_slp_force_pd        :    1;  /*Need add description*/
-            uint32_t memulator_slp_force_pu        :    1;  /*Need add description*/
-            uint32_t dg_vdd_drv_b_slp              :    24;  /*Need add description*/
-            uint32_t dg_vdd_drv_b_slp_en           :    1;  /*Need add description*/
-            uint32_t dgulator_slp_force_pd         :    1;  /*Need add description*/
-            uint32_t dgulator_slp_force_pu         :    1;  /*Need add description*/
-            uint32_t dgulator_force_pd             :    1;  /*Need add description*/
-            uint32_t dgulator_force_pu             :    1;  /*Need add description*/
-        };
-        uint32_t val;
-    } digulator;
-    union {
-        struct {
-            uint32_t dg_vdd_drv_b_active           :    24;  /*Need add description*/
-            uint32_t reserved24                    :    8;  /*Reserved*/
-        };
-        uint32_t val;
-    } digulator_drvb;
-    union {
-        struct {
-            uint32_t reserved0                     :    15;  /*Reserved*/
-            uint32_t pvt_dig_dbias                 :    5;  /*get pvt dbias value*/
-            uint32_t digulator0_dbias_slp          :    5;  /*the dig regulator0 dbias when chip in sleep state*/
-            uint32_t digulator0_dbias_active       :    5;  /*the dig regulator0 dbias when chip in active state*/
-            uint32_t digulator0_dbias_init         :    1;  /*initial pvt dbias value*/
-            uint32_t digulator0_dbias_sel          :    1;  /*1: select sw dbias_active 0: select pvt value*/
-        };
-        uint32_t val;
-    } digulator0_dbias;
-    union {
-        struct {
-            uint32_t reserved0                     :    12;  /*Reserved*/
-            uint32_t memulator1_dbias_slp          :    4;  /*Need add description*/
-            uint32_t memulator1_dbias_active       :    4;  /*Need add description*/
-            uint32_t digulator1_dbias_slp          :    4;  /*the dig regulator1 dbias when chip in sleep state*/
-            uint32_t reserved24                    :    1;  /*Reserved*/
-            uint32_t digulator1_dbias_active       :    4;  /*the dig regulator1 dbias when chip in active state*/
-            uint32_t reserved29                    :    3;  /*Reserved*/
-        };
-        uint32_t val;
-    } digulator1_dbias;
-    union {
-        struct {
-            uint32_t reserved0                     :    21;  /*Reserved*/
-            uint32_t rtc_pad_force_hold            :    1;  /*rtc pad force hold*/
-            uint32_t reserved22                    :    10;  /*Reserved*/
-        };
-        uint32_t val;
-    } pwc;
-    union {
-        struct {
-            uint32_t vdd_spi_pwr_drv               :    2;  /*Need add description*/
-            uint32_t vdd_spi_pwr_force             :    1;  /*Need add description*/
-            uint32_t lslp_mem_force_pd             :    1;  /*memories in digital core force PD in sleep*/
-            uint32_t lslp_mem_force_pu             :    1;  /*memories in digital core force no PD in sleep*/
-            uint32_t reserved5                     :    2;  /*Reserved*/
-            uint32_t dg_mem_force_pd               :    1;  /*Need add description*/
-            uint32_t dg_mem_force_pu               :    1;  /*Need add description*/
-            uint32_t dg_wrap_force_pd              :    1;  /*Need add description*/
-            uint32_t dg_wrap_force_pu              :    1;  /*Need add description*/
-            uint32_t bt_force_pd                   :    1;  /*Need add description*/
-            uint32_t bt_force_pu                   :    1;  /*Need add description*/
-            uint32_t dg_peri_force_pd              :    1;  /*Need add description*/
-            uint32_t dg_peri_force_pu              :    1;  /*Need add description*/
-            uint32_t fastmem_force_lpd             :    1;  /*Need add description*/
-            uint32_t fastmem_force_lpu             :    1;  /*Need add description*/
-            uint32_t wifi_force_pd                 :    1;  /*wifi force power down*/
-            uint32_t wifi_force_pu                 :    1;  /*wifi force power up*/
-            uint32_t reserved19                    :    2;  /*Reserveddigital core force power down*/
-            uint32_t cpu_top_force_pd              :    1;  /*Need add description*/
-            uint32_t cpu_top_force_pu              :    1;  /*Need add description*/
-            uint32_t reserved23                    :    3;  /*Reserved*/
-            uint32_t dg_wrap_ret_pd_en             :    1;  /*Need add description*/
-            uint32_t bt_pd_en                      :    1;  /*Need add description*/
-            uint32_t dg_peri_pd_en                 :    1;  /*Need add description*/
-            uint32_t cpu_top_pd_en                 :    1;  /*Need add description*/
-            uint32_t wifi_pd_en                    :    1;  /*enable power down wifi in sleep*/
-            uint32_t dg_wrap_pd_en                 :    1;  /*Need add description*/
-        };
-        uint32_t val;
-    } dig_pwc;
-    union {
-        struct {
-            uint32_t reserved0                     :    2;  /*Reserved*/
-            uint32_t pd_dg_peri_switch_mask        :    5;  /*Need add description*/
-            uint32_t pd_dg_wrap_switch_mask        :    5;  /*Need add description*/
-            uint32_t pd_mem_switch_mask            :    20;  /*Need add description*/
-        };
-        uint32_t val;
-    } dig_power_slave0_pd;
-    union {
-        struct {
-            uint32_t reserved0                     :    22;  /*Reserved*/
-            uint32_t pd_wifi_switch_mask           :    5;  /*Need add description*/
-            uint32_t pd_cpu_switch_mask            :    5;  /*Need add description*/
-        };
-        uint32_t val;
-    } dig_power_slave1_pd;
-    union {
-        struct {
-            uint32_t reserved0                     :    2;  /*Reserved*/
-            uint32_t xpd_dg_peri_switch_mask       :    5;  /*Need add description*/
-            uint32_t xpd_dg_wrap_switch_mask       :    5;  /*Need add description*/
-            uint32_t xpd_mem_switch_mask           :    20;  /*Need add description*/
-        };
-        uint32_t val;
-    } dig_power_slave0_fpu;
-    union {
-        struct {
-            uint32_t reserved0                     :    22;  /*Reserved*/
-            uint32_t xpd_wifi_switch_mask          :    5;  /*Need add description*/
-            uint32_t xpd_cpu_switch_mask           :    5;  /*Need add description*/
-        };
-        uint32_t val;
-    } dig_power_slave1_fpu;
-    union {
-        struct {
-            uint32_t reserved0                     :    5;  /*Reserved*/
-            uint32_t dg_mem_force_noiso            :    1;  /*Need add description*/
-            uint32_t dg_mem_force_iso              :    1;  /*Need add description*/
-            uint32_t dig_iso_force_off             :    1;  /*Need add description*/
-            uint32_t dig_iso_force_on              :    1;  /*Need add description*/
-            uint32_t dg_pad_autohold               :    1;  /*read only register to indicate digital pad auto-hold status*/
-            uint32_t clr_dg_pad_autohold           :    1;  /*wtite only register to clear digital pad auto-hold*/
-            uint32_t dg_pad_autohold_en            :    1;  /*digital pad enable auto-hold*/
-            uint32_t dg_pad_force_noiso            :    1;  /*digital pad force no ISO*/
-            uint32_t dg_pad_force_iso              :    1;  /*digital pad force ISO*/
-            uint32_t dg_pad_force_unhold           :    1;  /*digital pad force un-hold*/
-            uint32_t dg_pad_force_hold             :    1;  /*digital pad force hold*/
-            uint32_t reserved16                    :    6;  /*Reserved*/
-            uint32_t bt_force_iso                  :    1;  /*Need add description*/
-            uint32_t bt_force_noiso                :    1;  /*Need add description*/
-            uint32_t dg_peri_force_iso             :    1;  /*Need add description*/
-            uint32_t dg_peri_force_noiso           :    1;  /*Need add description*/
-            uint32_t cpu_top_force_iso             :    1;  /*cpu force ISO*/
-            uint32_t cpu_top_force_noiso           :    1;  /*cpu force no ISO*/
-            uint32_t wifi_force_iso                :    1;  /*wifi force ISO*/
-            uint32_t wifi_force_noiso              :    1;  /*wifi force no ISO*/
-            uint32_t dg_wrap_force_iso             :    1;  /*digital core force ISO*/
-            uint32_t dg_wrap_force_noiso           :    1;  /*Need add description*/
-        };
-        uint32_t val;
-    } dig_iso;
-    union {
-        struct {
-            uint32_t chip_reset_width              :    8;  /*chip reset siginal pulse width*/
-            uint32_t chip_reset_en                 :    1;  /*wdt reset whole chip enable*/
-            uint32_t pause_in_slp                  :    1;  /*pause WDT in sleep*/
-            uint32_t appcpu_reset_en               :    1;  /*enable WDT reset APP CPU*/
-            uint32_t procpu_reset_en               :    1;  /*enable WDT reset PRO CPU*/
-            uint32_t flashboot_mod_en              :    1;  /*enable WDT in flash boot*/
-            uint32_t sys_reset_length              :    3;  /*system reset counter length*/
-            uint32_t cpu_reset_length              :    3;  /*CPU reset counter length*/
-            uint32_t stg3                          :    3;  /*1: interrupt stage en, 2: CPU reset stage en, 3: system reset stage en, 4: RTC reset stage en*/
-            uint32_t stg2                          :    3;  /*1: interrupt stage en, 2: CPU reset stage en, 3: system reset stage en, 4: RTC reset stage en*/
-            uint32_t stg1                          :    3;  /*1: interrupt stage en, 2: CPU reset stage en, 3: system reset stage en, 4: RTC reset stage en*/
-            uint32_t stg0                          :    3;  /*1: interrupt stage en, 2: CPU reset stage en, 3: system reset stage en, 4: RTC reset stage en*/
-            uint32_t en                            :    1;  /*Need add description*/
-        };
-        uint32_t val;
-    } wdt_config0;
-    uint32_t wdt_config1;
-    uint32_t wdt_config2;
-    uint32_t wdt_config3;
-    uint32_t wdt_config4;
-    union {
-        struct {
-            uint32_t reserved0                     :    31;  /*Reserved*/
-            uint32_t feed                          :    1;  /*Need add description*/
-        };
-        uint32_t val;
-    } wdt_feed;
-    uint32_t wdt_wprotect;
-    union {
-        struct {
-            uint32_t reserved0                     :    16;  /*Reserved*/
-            uint32_t reset_chip_target             :    8;  /*Need add description*/
-            uint32_t reset_chip_key                :    8;  /*Need add description*/
-        };
-        uint32_t val;
-    } wdtreset_chip;
-    union {
-        struct {
-            uint32_t swd_reset_flag                :    1;  /*swd reset flag*/
-            uint32_t swd_feed_int                  :    1;  /*swd interrupt for feeding*/
-            uint32_t reserved2                     :    15;  /*Reserved*/
-            uint32_t swd_bypass_rst                :    1;  /*Need add description*/
-            uint32_t swd_signal_width              :    10;  /*adjust signal width send to swd*/
-            uint32_t swd_rst_flag_clr              :    1;  /*reset swd reset flag*/
-            uint32_t swd_feed                      :    1;  /*Sw feed swd*/
-            uint32_t swd_disable                   :    1;  /*disabel SWD*/
-            uint32_t swd_auto_feed_en              :    1;  /*automatically feed swd when int comes*/
-        };
-        uint32_t val;
-    } swd_conf;
-    uint32_t swd_wprotect;
-    union {
-        struct {
-            uint32_t reserved0                     :    20;  /*Reserved*/
-            uint32_t appcpu_c1                     :    6;  /*{reg_sw_stall_appcpu_c1[5:0],  reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU*/
-            uint32_t procpu_c1                     :    6;  /*Need add description*/
-        };
-        uint32_t val;
-    } sw_cpu_stall;
-    uint32_t store4;
-    uint32_t store5;
-    uint32_t store6;
-    uint32_t store7;
-    union {
-        struct {
-            uint32_t xpd_rom0                      :    1;  /*rom0 power down*/
-            uint32_t reserved1                     :    1;  /*Reserved*/
-            uint32_t xpd_dig_dcdc                  :    1;  /*External DCDC power down*/
-            uint32_t rtc_peri_iso                  :    1;  /*rtc peripheral iso*/
-            uint32_t xpd_rtc_peri                  :    1;  /*rtc peripheral power down */
-            uint32_t wifi_iso                      :    1;  /*wifi iso*/
-            uint32_t xpd_wifi                      :    1;  /*wifi wrap power down*/
-            uint32_t dig_iso                       :    1;  /*digital wrap iso*/
-            uint32_t xpd_dig                       :    1;  /*digital wrap power down*/
-            uint32_t rtc_touch_state_start         :    1;  /*touch should start to work*/
-            uint32_t rtc_touch_state_switch        :    1;  /*touch is about to working. Switch rtc main state*/
-            uint32_t rtc_touch_state_slp           :    1;  /*touch is in sleep state*/
-            uint32_t rtc_touch_state_done          :    1;  /*touch is done*/
-            uint32_t rtc_cocpu_state_start         :    1;  /*ulp/cocpu should start to work*/
-            uint32_t rtc_cocpu_state_switch        :    1;  /*ulp/cocpu is about to working. Switch rtc main state*/
-            uint32_t rtc_cocpu_state_slp           :    1;  /*ulp/cocpu is in sleep state*/
-            uint32_t rtc_cocpu_state_done          :    1;  /*ulp/cocpu is done*/
-            uint32_t rtc_main_state_xtal_iso       :    1;  /*no use any more*/
-            uint32_t rtc_main_state_pll_on         :    1;  /*rtc main state machine is in states that pll should be running*/
-            uint32_t rtc_rdy_for_wakeup            :    1;  /*rtc is ready to receive wake up trigger from wake up source*/
-            uint32_t rtc_main_state_wait_end       :    1;  /*rtc main state machine has been waited for some cycles*/
-            uint32_t rtc_in_wakeup_state           :    1;  /*rtc main state machine is in the states of wakeup process*/
-            uint32_t rtc_in_low_power_state        :    1;  /*rtc main state machine is in the states of low power*/
-            uint32_t rtc_main_state_in_wait_8m     :    1;  /*rtc main state machine is in wait 8m state*/
-            uint32_t rtc_main_state_in_wait_pll    :    1;  /*rtc main state machine is in wait pll state*/
-            uint32_t rtc_main_state_in_wait_xtl    :    1;  /*rtc main state machine is in wait xtal state*/
-            uint32_t rtc_main_state_in_slp         :    1;  /*rtc main state machine is in sleep state*/
-            uint32_t rtc_main_state_in_idle        :    1;  /*rtc main state machine is in idle state*/
-            uint32_t rtc_main_state                :    4;  /*rtc main state machine status*/
-        };
-        uint32_t val;
-    } low_power_st;
-    uint32_t diag0;
-    union {
-        struct {
-            uint32_t rtc_gpio_pin0_hold            :    1;  /*Need add description*/
-            uint32_t rtc_gpio_pin1_hold            :    1;  /*Need add description*/
-            uint32_t rtc_gpio_pin2_hold            :    1;  /*Need add description*/
-            uint32_t rtc_gpio_pin3_hold            :    1;  /*Need add description*/
-            uint32_t rtc_gpio_pin4_hold            :    1;  /*Need add description*/
-            uint32_t rtc_gpio_pin5_hold            :    1;  /*Need add description*/
-            uint32_t reserved6                     :    26;  /*Reserved*/
-        };
-        uint32_t val;
-    } pad_hold;
-    uint32_t dig_pad_hold;
-    union {
-        struct {
-            uint32_t dig_pad_hold1                 :    9;  /*Need add description*/
-            uint32_t reserved9                     :    23;  /*Reserved*/
-        };
-        uint32_t val;
-    } dig_pad_hold1;
-    union {
-        struct {
-            uint32_t reserved0                     :    4;  /*Reserved*/
-            uint32_t int_wait                      :    10;  /*brown out interrupt wait cycles*/
-            uint32_t close_flash_ena               :    1;  /*enable close flash when brown out happens*/
-            uint32_t pd_rf_ena                     :    1;  /*enable power down RF when brown out happens*/
-            uint32_t rst_wait                      :    10;  /*brown out reset wait cycles*/
-            uint32_t rst_ena                       :    1;  /*enable brown out reset*/
-            uint32_t rst_sel                       :    1;  /*1:  4-pos reset,    0:  sys_reset*/
-            uint32_t ana_rst_en                    :    1;  /*Need add description*/
-            uint32_t cnt_clr                       :    1;  /*clear brown out counter*/
-            uint32_t ena                           :    1;  /*enable brown out*/
-            uint32_t det                           :    1;  /*Need add description*/
-        };
-        uint32_t val;
-    } brown_out;
-    uint32_t time_low1;
-    union {
-        struct {
-            uint32_t rtc_timer_value1_high         :    16;  /*RTC timer high 16 bits*/
-            uint32_t reserved16                    :    16;  /*Reserved*/
-        };
-        uint32_t val;
-    } time_high1;
-    uint32_t xtal32k_clk_factor;
-    union {
-        struct {
-            uint32_t xtal32k_return_wait           :    4;  /*cycles to wait to return noral xtal 32k*/
-            uint32_t xtal32k_restart_wait          :    16;  /*cycles to wait to repower on xtal 32k*/
-            uint32_t xtal32k_wdt_timeout           :    8;  /*If no clock detected for this amount of time, 32k is regarded as dead*/
-            uint32_t xtal32k_stable_thres          :    4;  /*if restarted xtal32k period is smaller than this, it is regarded as stable*/
-        };
-        uint32_t val;
-    } xtal32k_conf;
-    union {
-        struct {
-            uint32_t reserved0                     :    18;  /*Reserved*/
-            uint32_t io_mux_reset_disable          :    1;  /*Need add description*/
-            uint32_t reserved19                    :    13;  /*Reserved*/
-        };
-        uint32_t val;
-    } usb_conf;
-    union {
-        struct {
-            uint32_t reject_cause                  :    19;  /*sleep reject cause*/
-            uint32_t reserved19                    :    13;  /*Reserved*/
-        };
-        uint32_t val;
-    } slp_reject_cause;
-    union {
-        struct {
-            uint32_t force_download_boot           :    1;  /*Need add description*/
-            uint32_t reserved1                     :    31;  /*Reserved*/
-        };
-        uint32_t val;
-    } option1;
-    union {
-        struct {
-            uint32_t wakeup_cause                  :    19;  /*sleep wakeup cause*/
-            uint32_t reserved19                    :    13;  /*Reserved*/
-        };
-        uint32_t val;
-    } slp_wakeup_cause;
-    union {
-        struct {
-            uint32_t reserved0                     :    8;  /*Reserved*/
-            uint32_t ulp_cp_timer_slp_cycle        :    24;  /*sleep cycles for ULP-coprocessor timer*/
-        };
-        uint32_t val;
-    } ulp_cp_timer_1;
-    union {
-        struct {
-            uint32_t slp_wakeup_w1ts               :    1;  /*enable sleep wakeup interrupt*/
-            uint32_t slp_reject_w1ts               :    1;  /*enable sleep reject interrupt*/
-            uint32_t reserved2                     :    1;  /*Reserved*/
-            uint32_t rtc_wdt_w1ts                  :    1;  /*enable RTC WDT interrupt*/
-            uint32_t reserved4                     :    5;  /*Reserved*/
-            uint32_t w1ts                          :    1;  /*enable brown out interrupt*/
-            uint32_t rtc_main_timer_w1ts           :    1;  /*enable RTC main timer interrupt*/
-            uint32_t reserved11                    :    4;  /*Reserved*/
-            uint32_t rtc_swd_w1ts                  :    1;  /*enable super watch dog interrupt*/
-            uint32_t rtc_xtal32k_dead_w1ts         :    1;  /*enable xtal32k_dead  interrupt*/
-            uint32_t reserved17                    :    2;  /*Reserved*/
-            uint32_t rtc_glitch_det_w1ts           :    1;  /*enbale gitch det interrupt*/
-            uint32_t rtc_bbpll_cal_w1ts            :    1;  /*Need add description*/
-            uint32_t rtc_ble_compare_wake_w1ts     :    1;  /*Need add description*/
-            uint32_t vset_dcdc_done_w1ts           :    1;  /*Need add description*/
-            uint32_t reserved23                    :    9;  /*Reserved*/
-        };
-        uint32_t val;
-    } int_ena_w1ts;
-    union {
-        struct {
-            uint32_t slp_wakeup_w1tc               :    1;  /*enable sleep wakeup interrupt*/
-            uint32_t slp_reject_w1tc               :    1;  /*enable sleep reject interrupt*/
-            uint32_t reserved2                     :    1;  /*Reserved*/
-            uint32_t rtc_wdt_w1tc                  :    1;  /*enable RTC WDT interrupt*/
-            uint32_t reserved4                     :    5;  /*Reserved*/
-            uint32_t w1tc                          :    1;  /*enable brown out interrupt*/
-            uint32_t rtc_main_timer_w1tc           :    1;  /*enable RTC main timer interrupt*/
-            uint32_t reserved11                    :    4;  /*Reserved*/
-            uint32_t rtc_swd_w1tc                  :    1;  /*enable super watch dog interrupt*/
-            uint32_t rtc_xtal32k_dead_w1tc         :    1;  /*enable xtal32k_dead  interrupt*/
-            uint32_t reserved17                    :    2;  /*Reserved*/
-            uint32_t rtc_glitch_det_w1tc           :    1;  /*enbale gitch det interrupt*/
-            uint32_t rtc_bbpll_cal_w1tc            :    1;  /*Need add description*/
-            uint32_t rtc_ble_compare_wake_w1tc     :    1;  /*Need add description*/
-            uint32_t vset_dcdc_done_w1tc           :    1;  /*Need add description*/
-            uint32_t reserved23                    :    9;  /*Reserved*/
-        };
-        uint32_t val;
-    } int_ena_w1tc;
-    union {
-        struct {
-            uint32_t reserved0                     :    17;  /*Reserved*/
-            uint32_t rtc_cntl_clk_en               :    1;  /*Need add description*/
-            uint32_t retention_clk_sel             :    1;  /*Need add description*/
-            uint32_t retention_done_wait           :    3;  /*Need add description*/
-            uint32_t retention_clkoff_wait         :    4;  /*Need add description*/
-            uint32_t retention_en                  :    1;  /*Need add description*/
-            uint32_t retention_wait                :    5;  /*wait cycles for rention operation*/
-        };
-        uint32_t val;
-    } retention_ctrl;
-    union {
-        struct {
-            uint32_t retention_link_addr           :    27;  /*Need add description*/
-            uint32_t reserved27                    :    5;  /*Reserved*/
-        };
-        uint32_t val;
-    } retention_ctrl1;
-    union {
-        struct {
-            uint32_t rtc_fib_sel                   :    3;  /*select use analog fib signal*/
-            uint32_t reserved3                     :    29;  /*Reserved*/
-        };
-        uint32_t val;
-    } fib_sel;
-    union {
-        struct {
-            uint32_t rtc_gpio_wakeup_status        :    6;  /*Need add description*/
-            uint32_t rtc_gpio_wakeup_status_clr    :    1;  /*Need add description*/
-            uint32_t rtc_gpio_pin_clk_gate         :    1;  /*Need add description*/
-            uint32_t rtc_gpio_pin5_int_type        :    3;  /*Need add description*/
-            uint32_t rtc_gpio_pin4_int_type        :    3;  /*Need add description*/
-            uint32_t rtc_gpio_pin3_int_type        :    3;  /*Need add description*/
-            uint32_t rtc_gpio_pin2_int_type        :    3;  /*Need add description*/
-            uint32_t rtc_gpio_pin1_int_type        :    3;  /*Need add description*/
-            uint32_t rtc_gpio_pin0_int_type        :    3;  /*Need add description*/
-            uint32_t rtc_gpio_pin5_wakeup_enable   :    1;  /*Need add description*/
-            uint32_t rtc_gpio_pin4_wakeup_enable   :    1;  /*Need add description*/
-            uint32_t rtc_gpio_pin3_wakeup_enable   :    1;  /*Need add description*/
-            uint32_t rtc_gpio_pin2_wakeup_enable   :    1;  /*Need add description*/
-            uint32_t rtc_gpio_pin1_wakeup_enable   :    1;  /*Need add description*/
-            uint32_t rtc_gpio_pin0_wakeup_enable   :    1;  /*Need add description*/
-        };
-        uint32_t val;
-    } gpio_wakeup;
-    union {
-        struct {
-            uint32_t rtc_mtdi_enamux               :    1;  /*Need add description*/
-            uint32_t rtc_debug_12m_no_gating       :    1;  /*Need add description*/
-            uint32_t rtc_debug_bit_sel             :    5;  /*Need add description*/
-            uint32_t rtc_debug_sel0                :    5;  /*Need add description*/
-            uint32_t rtc_debug_sel1                :    5;  /*Need add description*/
-            uint32_t rtc_debug_sel2                :    5;  /*Need add description*/
-            uint32_t rtc_debug_sel3                :    5;  /*Need add description*/
-            uint32_t rtc_debug_sel4                :    5;  /*Need add description*/
-        };
-        uint32_t val;
-    } dbg_sel;
-    union {
-        struct {
-            uint32_t vdd_dig_test                  :    2;  /*Need add description*/
-            uint32_t rtc_gpio_pin5_mux_sel         :    1;  /*Need add description*/
-            uint32_t rtc_gpio_pin4_mux_sel         :    1;  /*Need add description*/
-            uint32_t rtc_gpio_pin3_mux_sel         :    1;  /*Need add description*/
-            uint32_t rtc_gpio_pin2_mux_sel         :    1;  /*Need add description*/
-            uint32_t rtc_gpio_pin1_mux_sel         :    1;  /*Need add description*/
-            uint32_t rtc_gpio_pin0_mux_sel         :    1;  /*Need add description*/
-            uint32_t rtc_gpio_pin5_fun_sel         :    4;  /*Need add description*/
-            uint32_t rtc_gpio_pin4_fun_sel         :    4;  /*Need add description*/
-            uint32_t rtc_gpio_pin3_fun_sel         :    4;  /*Need add description*/
-            uint32_t rtc_gpio_pin2_fun_sel         :    4;  /*Need add description*/
-            uint32_t rtc_gpio_pin1_fun_sel         :    4;  /*Need add description*/
-            uint32_t rtc_gpio_pin0_fun_sel         :    4;  /*Need add description*/
-        };
-        uint32_t val;
-    } dbg_map;
-    union {
-        struct {
-            uint32_t reserved0                     :    27;  /*Reserved*/
-            uint32_t sar_debug_sel                 :    5;  /*Need add description*/
-        };
-        uint32_t val;
-    } dbg_sar_sel;
-    union {
-        struct {
-            uint32_t reserved0                     :    26;  /*Reserved*/
-            uint32_t power_glitch_dsense           :    2;  /*Need add description*/
-            uint32_t power_glitch_force_pd         :    1;  /*Need add description*/
-            uint32_t power_glitch_force_pu         :    1;  /*Need add description*/
-            uint32_t power_glitch_efuse_sel        :    1;  /*Need add description*/
-            uint32_t power_glitch_en               :    1;  /*Need add description*/
-        };
-        uint32_t val;
-    } pg_ctrl;
-    union {
-        struct {
-            uint32_t vset_dcdc_value               :    5;  /*Need add description*/
-            uint32_t power_good_dcdc               :    1;  /*Need add description*/
-            uint32_t reserved6                     :    13;  /*Reserved*/
-            uint32_t pmu_mode                      :    2;  /*Need add description*/
-            uint32_t ramplevel_dcdc                :    1;  /*Need add description*/
-            uint32_t ramp_dcdc                     :    1;  /*Need add description*/
-            uint32_t dcm2enb_dcdc                  :    1;  /*Need add description*/
-            uint32_t dcmlevel_dcdc                 :    2;  /*Need add description*/
-            uint32_t fsw_dcdc                      :    3;  /*Need add description*/
-            uint32_t ccm_dcdc                      :    1;  /*Need add description*/
-            uint32_t sstime_dcdc                   :    1;  /*Need add description*/
-            uint32_t pocpenb_dcdc                  :    1;  /*Need add description*/
-        };
-        uint32_t val;
-    } dcdc_ctrl0;
-    union {
-        struct {
-            uint32_t reserved0                     :    23;  /*Reserved*/
-            uint32_t dcdc_mode_slp                 :    3;  /*Need add description*/
-            uint32_t dcdc_mode_monitor             :    3;  /*Need add description*/
-            uint32_t dcdc_mode_idle                :    3;  /*Need add description*/
-        };
-        uint32_t val;
-    } dcdc_ctrl1;
-    union {
-        struct {
-            uint32_t vset_dcdc_target_value1       :    5;  /*Need add description*/
-            uint32_t vset_dcdc_target_value0       :    5;  /*Need add description*/
-            uint32_t vset_dcdc_init_value          :    5;  /*Need add description*/
-            uint32_t vset_dcdc_init                :    1;  /*Need add description*/
-            uint32_t vset_dcdc_fix                 :    1;  /*Need add description*/
-            uint32_t vset_dcdc_step                :    5;  /*Need add description*/
-            uint32_t vset_dcdc_gap                 :    5;  /*Need add description*/
-            uint32_t vset_dcdc_sel_hw_sw           :    1;  /*Need add description*/
-            uint32_t vset_dcdc_sw_sel              :    1;  /*Need add description*/
-            uint32_t reserved29                    :    3;  /*Reserved*/
-        };
-        uint32_t val;
-    } dcdc_ctrl2;
-    union {
-        struct {
-            uint32_t reserved0                     :    21;  /*Reserved*/
-            uint32_t rc32k_dfreq                   :    10;  /*Need add description*/
-            uint32_t rc32k_xpd                     :    1;  /*Need add description*/
-        };
-        uint32_t val;
-    } rc32k_ctrl;
-    union {
-        struct {
-            uint32_t reserved0                     :    30;  /*Reserved*/
-            uint32_t ckref_pll8m_sel               :    1;  /*Need add description*/
-            uint32_t xpd_pll8m                     :    1;  /*Need add description*/
-        };
-        uint32_t val;
-    } pll8m;
-    uint32_t reserved_16c;
-    uint32_t reserved_170;
-    uint32_t reserved_174;
-    uint32_t reserved_178;
-    uint32_t reserved_17c;
-    uint32_t reserved_180;
-    uint32_t reserved_184;
-    uint32_t reserved_188;
-    uint32_t reserved_18c;
-    uint32_t reserved_190;
-    uint32_t reserved_194;
-    uint32_t reserved_198;
-    uint32_t reserved_19c;
-    uint32_t reserved_1a0;
-    uint32_t reserved_1a4;
-    uint32_t reserved_1a8;
-    uint32_t reserved_1ac;
-    uint32_t reserved_1b0;
-    uint32_t reserved_1b4;
-    uint32_t reserved_1b8;
-    uint32_t reserved_1bc;
-    uint32_t reserved_1c0;
-    uint32_t reserved_1c4;
-    uint32_t reserved_1c8;
-    uint32_t reserved_1cc;
-    uint32_t reserved_1d0;
-    uint32_t reserved_1d4;
-    uint32_t reserved_1d8;
-    uint32_t reserved_1dc;
-    uint32_t reserved_1e0;
-    uint32_t reserved_1e4;
-    uint32_t reserved_1e8;
-    uint32_t reserved_1ec;
-    uint32_t reserved_1f0;
-    uint32_t reserved_1f4;
-    uint32_t reserved_1f8;
-    union {
-        struct {
-            uint32_t date                          :    28;  /*Need add description*/
-            uint32_t reserved28                    :    4;  /*Reserved*/
-        };
-        uint32_t val;
-    } date;
+/** Group: Configuration Registers */
+/** Type of rtc_options0 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** sw_stall_appcpu_c0 : R/W; bitpos: [1:0]; default: 0;
+         *  {reg_sw_stall_appcpu_c1[5:0],  reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP
+         *  CPU
+         */
+        uint32_t sw_stall_appcpu_c0:2;
+        /** sw_stall_procpu_c0 : R/W; bitpos: [3:2]; default: 0;
+         *  {reg_sw_stall_procpu_c1[5:0],  reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall PRO
+         *  CPU
+         */
+        uint32_t sw_stall_procpu_c0:2;
+        /** sw_appcpu_rst : WO; bitpos: [4]; default: 0;
+         *  APP CPU SW reset
+         */
+        uint32_t sw_appcpu_rst:1;
+        /** sw_procpu_rst : WO; bitpos: [5]; default: 0;
+         *  PRO CPU SW reset
+         */
+        uint32_t sw_procpu_rst:1;
+        /** bb_i2c_force_pd : R/W; bitpos: [6]; default: 0;
+         *  BB_I2C force power down
+         */
+        uint32_t bb_i2c_force_pd:1;
+        /** bb_i2c_force_pu : R/W; bitpos: [7]; default: 0;
+         *  BB_I2C force power up
+         */
+        uint32_t bb_i2c_force_pu:1;
+        /** bbpll_i2c_force_pd : R/W; bitpos: [8]; default: 0;
+         *  BB_PLL _I2C force power down
+         */
+        uint32_t bbpll_i2c_force_pd:1;
+        /** bbpll_i2c_force_pu : R/W; bitpos: [9]; default: 0;
+         *  BB_PLL_I2C force power up
+         */
+        uint32_t bbpll_i2c_force_pu:1;
+        /** bbpll_force_pd : R/W; bitpos: [10]; default: 0;
+         *  BB_PLL force power down
+         */
+        uint32_t bbpll_force_pd:1;
+        /** bbpll_force_pu : R/W; bitpos: [11]; default: 0;
+         *  BB_PLL force power up
+         */
+        uint32_t bbpll_force_pu:1;
+        /** xtl_force_pd : R/W; bitpos: [12]; default: 0;
+         *  crystall force power down
+         */
+        uint32_t xtl_force_pd:1;
+        /** xtl_force_pu : R/W; bitpos: [13]; default: 1;
+         *  crystall force power up
+         */
+        uint32_t xtl_force_pu:1;
+        /** xtl_en_wait : R/W; bitpos: [17:14]; default: 2;
+         *  wait bias_sleep and current source wakeup
+         */
+        uint32_t xtl_en_wait:4;
+        /** xpd_rfpll : R/W; bitpos: [18]; default: 0;
+         *  Need add description
+         */
+        uint32_t xpd_rfpll:1;
+        /** xpd_rfpll_force : R/W; bitpos: [19]; default: 0;
+         *  Need add description
+         */
+        uint32_t xpd_rfpll_force:1;
+        /** xtl_ext_ctr_sel : R/W; bitpos: [22:20]; default: 0;
+         *  Need add description
+         */
+        uint32_t xtl_ext_ctr_sel:3;
+        /** xtl_force_iso : R/W; bitpos: [23]; default: 0;
+         *  Need add description
+         */
+        uint32_t xtl_force_iso:1;
+        /** pll_force_iso : R/W; bitpos: [24]; default: 0;
+         *  Need add description
+         */
+        uint32_t pll_force_iso:1;
+        /** analog_force_iso : R/W; bitpos: [25]; default: 0;
+         *  Need add description
+         */
+        uint32_t analog_force_iso:1;
+        /** xtl_force_noiso : R/W; bitpos: [26]; default: 1;
+         *  Need add description
+         */
+        uint32_t xtl_force_noiso:1;
+        /** pll_force_noiso : R/W; bitpos: [27]; default: 1;
+         *  Need add description
+         */
+        uint32_t pll_force_noiso:1;
+        /** analog_force_noiso : R/W; bitpos: [28]; default: 1;
+         *  Need add description
+         */
+        uint32_t analog_force_noiso:1;
+        /** dg_wrap_force_rst : R/W; bitpos: [29]; default: 0;
+         *  digital wrap force reset in deep sleep
+         */
+        uint32_t dg_wrap_force_rst:1;
+        /** dg_wrap_force_norst : R/W; bitpos: [30]; default: 0;
+         *  digital core force no reset in deep sleep
+         */
+        uint32_t dg_wrap_force_norst:1;
+        /** sw_sys_rst : WO; bitpos: [31]; default: 0;
+         *  SW system  reset
+         */
+        uint32_t sw_sys_rst:1;
+    };
+    uint32_t val;
+} rtc_cntl_options0_reg_t;
+
+/** Type of rtc_slp_timer0 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** slp_val_lo : R/W; bitpos: [31:0]; default: 0;
+         *  RTC sleep timer low 32 bits
+         */
+        uint32_t slp_val_lo:32;
+    };
+    uint32_t val;
+} rtc_cntl_slp_timer0_reg_t;
+
+/** Type of rtc_slp_timer1 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** slp_val_hi : R/W; bitpos: [15:0]; default: 0;
+         *  RTC sleep timer high 16 bits
+         */
+        uint32_t slp_val_hi:16;
+        /** main_timer_alarm_en : WO; bitpos: [16]; default: 0;
+         *  timer alarm enable bit
+         */
+        uint32_t main_timer_alarm_en:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} rtc_cntl_slp_timer1_reg_t;
+
+/** Type of rtc_time_update register
+ *  register description
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:27;
+        /** timer_sys_stall : R/W; bitpos: [27]; default: 0;
+         *  Enable to record system stall time
+         */
+        uint32_t timer_sys_stall:1;
+        /** timer_xtl_off : R/W; bitpos: [28]; default: 0;
+         *  Enable to record 40M XTAL OFF time
+         */
+        uint32_t timer_xtl_off:1;
+        /** timer_sys_rst : R/W; bitpos: [29]; default: 0;
+         *  enable to record system reset time
+         */
+        uint32_t timer_sys_rst:1;
+        uint32_t reserved_30:1;
+        /** update : WO; bitpos: [31]; default: 0;
+         *  Set 1: to update register with RTC timer
+         */
+        uint32_t update:1;
+    };
+    uint32_t val;
+} rtc_cntl_time_update_reg_t;
+
+/** Type of rtc_time_low0 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** rtc_timer_value0_low : RO; bitpos: [31:0]; default: 0;
+         *  RTC timer low 32 bits
+         */
+        uint32_t rtc_timer_value0_low:32;
+    };
+    uint32_t val;
+} rtc_cntl_time_low0_reg_t;
+
+/** Type of rtc_time_high0 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** rtc_timer_value0_high : RO; bitpos: [15:0]; default: 0;
+         *  RTC timer high 16 bits
+         */
+        uint32_t rtc_timer_value0_high:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} rtc_cntl_time_high0_reg_t;
+
+/** Type of rtc_state0 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** rtc_sw_cpu_int : WO; bitpos: [0]; default: 0;
+         *  rtc software interrupt to main cpu
+         */
+        uint32_t rtc_sw_cpu_int:1;
+        /** rtc_slp_reject_cause_clr : WO; bitpos: [1]; default: 0;
+         *  clear rtc sleep reject cause
+         */
+        uint32_t rtc_slp_reject_cause_clr:1;
+        uint32_t reserved_2:20;
+        /** apb2rtc_bridge_sel : R/W; bitpos: [22]; default: 0;
+         *  1: APB to RTC using bridge,  0: APB to RTC using sync
+         */
+        uint32_t apb2rtc_bridge_sel:1;
+        uint32_t reserved_23:5;
+        /** sdio_active_ind : RO; bitpos: [28]; default: 0;
+         *  SDIO active indication
+         */
+        uint32_t sdio_active_ind:1;
+        /** slp_wakeup : R/W; bitpos: [29]; default: 0;
+         *  leep wakeup bit
+         */
+        uint32_t slp_wakeup:1;
+        /** slp_reject : R/W; bitpos: [30]; default: 0;
+         *  leep reject bit
+         */
+        uint32_t slp_reject:1;
+        /** sleep_en : R/W; bitpos: [31]; default: 0;
+         *  sleep enable bit
+         */
+        uint32_t sleep_en:1;
+    };
+    uint32_t val;
+} rtc_cntl_state0_reg_t;
+
+/** Type of rtc_timer1 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** cpu_stall_en : R/W; bitpos: [0]; default: 1;
+         *  CPU stall enable bit
+         */
+        uint32_t cpu_stall_en:1;
+        /** cpu_stall_wait : R/W; bitpos: [5:1]; default: 1;
+         *  CPU stall wait cycles in fast_clk_rtc
+         */
+        uint32_t cpu_stall_wait:5;
+        /** ck8m_wait : R/W; bitpos: [13:6]; default: 16;
+         *  CK8M wait cycles in slow_clk_rtc
+         */
+        uint32_t ck8m_wait:8;
+        /** xtl_buf_wait : R/W; bitpos: [23:14]; default: 80;
+         *  XTAL wait cycles in slow_clk_rtc
+         */
+        uint32_t xtl_buf_wait:10;
+        /** pll_buf_wait : R/W; bitpos: [31:24]; default: 40;
+         *  PLL wait cycles in slow_clk_rtc
+         */
+        uint32_t pll_buf_wait:8;
+    };
+    uint32_t val;
+} rtc_cntl_timer1_reg_t;
+
+/** Type of rtc_timer2 register
+ *  register description
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:24;
+        /** min_time_ck8m_off : R/W; bitpos: [31:24]; default: 1;
+         *  minimal cycles in slow_clk_rtc for CK8M in power down state
+         */
+        uint32_t min_time_ck8m_off:8;
+    };
+    uint32_t val;
+} rtc_cntl_timer2_reg_t;
+
+/** Type of rtc_timer3 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** wifi_wait_timer : R/W; bitpos: [8:0]; default: 8;
+         *  Need add description
+         */
+        uint32_t wifi_wait_timer:9;
+        /** wifi_powerup_timer : R/W; bitpos: [15:9]; default: 5;
+         *  Need add description
+         */
+        uint32_t wifi_powerup_timer:7;
+        /** bt_wait_timer : R/W; bitpos: [24:16]; default: 8;
+         *  Need add description
+         */
+        uint32_t bt_wait_timer:9;
+        /** bt_powerup_timer : R/W; bitpos: [31:25]; default: 5;
+         *  Need add description
+         */
+        uint32_t bt_powerup_timer:7;
+    };
+    uint32_t val;
+} rtc_cntl_timer3_reg_t;
+
+/** Type of rtc_timer4 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** cpu_top_wait_timer : R/W; bitpos: [8:0]; default: 8;
+         *  Need add description
+         */
+        uint32_t cpu_top_wait_timer:9;
+        /** cpu_top_powerup_timer : R/W; bitpos: [15:9]; default: 5;
+         *  Need add description
+         */
+        uint32_t cpu_top_powerup_timer:7;
+        /** dg_wrap_wait_timer : R/W; bitpos: [24:16]; default: 32;
+         *  Need add description
+         */
+        uint32_t dg_wrap_wait_timer:9;
+        /** dg_wrap_powerup_timer : R/W; bitpos: [31:25]; default: 8;
+         *  Need add description
+         */
+        uint32_t dg_wrap_powerup_timer:7;
+    };
+    uint32_t val;
+} rtc_cntl_timer4_reg_t;
+
+/** Type of rtc_timer5 register
+ *  register description
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:8;
+        /** min_slp_val : R/W; bitpos: [15:8]; default: 128;
+         *  minimal sleep cycles in slow_clk_rtc
+         */
+        uint32_t min_slp_val:8;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} rtc_cntl_timer5_reg_t;
+
+/** Type of rtc_timer6 register
+ *  register description
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:16;
+        /** dg_peri_wait_timer : R/W; bitpos: [24:16]; default: 8;
+         *  Need add description
+         */
+        uint32_t dg_peri_wait_timer:9;
+        /** dg_peri_powerup_timer : R/W; bitpos: [31:25]; default: 5;
+         *  Need add description
+         */
+        uint32_t dg_peri_powerup_timer:7;
+    };
+    uint32_t val;
+} rtc_cntl_timer6_reg_t;
+
+/** Type of rtc_ana_conf register
+ *  register description
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:16;
+        /** xpd_trx_force_pd : R/W; bitpos: [16]; default: 0;
+         *  Need add description
+         */
+        uint32_t xpd_trx_force_pd:1;
+        /** xpd_trx_force_pu : R/W; bitpos: [17]; default: 1;
+         *  Need add description
+         */
+        uint32_t xpd_trx_force_pu:1;
+        /** i2c_reset_por_force_pd : R/W; bitpos: [18]; default: 1;
+         *  Need add description
+         */
+        uint32_t i2c_reset_por_force_pd:1;
+        /** i2c_reset_por_force_pu : R/W; bitpos: [19]; default: 0;
+         *  Need add description
+         */
+        uint32_t i2c_reset_por_force_pu:1;
+        /** glitch_rst_en : R/W; bitpos: [20]; default: 0;
+         *  Need add description
+         */
+        uint32_t glitch_rst_en:1;
+        uint32_t reserved_21:1;
+        /** peri_i2c_pu : R/W; bitpos: [22]; default: 1;
+         *  PLLA force power up
+         */
+        uint32_t peri_i2c_pu:1;
+        /** plla_force_pd : R/W; bitpos: [23]; default: 1;
+         *  PLLA force power down
+         */
+        uint32_t plla_force_pd:1;
+        /** plla_force_pu : R/W; bitpos: [24]; default: 0;
+         *  PLLA force power up
+         */
+        uint32_t plla_force_pu:1;
+        /** bbpll_cal_slp_start : R/W; bitpos: [25]; default: 0;
+         *  start BBPLL calibration during sleep
+         */
+        uint32_t bbpll_cal_slp_start:1;
+        /** pvtmon_pu : R/W; bitpos: [26]; default: 0;
+         *  1: PVTMON power up , otherwise power down
+         */
+        uint32_t pvtmon_pu:1;
+        /** txrf_i2c_pu : R/W; bitpos: [27]; default: 0;
+         *  1: TXRF_I2C power up , otherwise power down
+         */
+        uint32_t txrf_i2c_pu:1;
+        /** rfrx_pbus_pu : R/W; bitpos: [28]; default: 0;
+         *  1: RFRX_PBUS power up , otherwise power down
+         */
+        uint32_t rfrx_pbus_pu:1;
+        uint32_t reserved_29:1;
+        /** ckgen_i2c_pu : R/W; bitpos: [30]; default: 0;
+         *  1: CKGEN_I2C power up , otherwise power down
+         */
+        uint32_t ckgen_i2c_pu:1;
+        /** pll_i2c_pu : R/W; bitpos: [31]; default: 0;
+         *  Need add description
+         */
+        uint32_t pll_i2c_pu:1;
+    };
+    uint32_t val;
+} rtc_cntl_ana_conf_reg_t;
+
+/** Type of rtc_reset_state register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** reset_cause_procpu : RO; bitpos: [5:0]; default: 0;
+         *  reset cause of PRO CPU
+         */
+        uint32_t reset_cause_procpu:6;
+        /** reset_cause_appcpu : RO; bitpos: [11:6]; default: 0;
+         *  reset cause of APP CPU
+         */
+        uint32_t reset_cause_appcpu:6;
+        /** stat_vector_sel_appcpu : R/W; bitpos: [12]; default: 1;
+         *  APP CPU state vector sel
+         */
+        uint32_t stat_vector_sel_appcpu:1;
+        /** stat_vector_sel_procpu : R/W; bitpos: [13]; default: 1;
+         *  PRO CPU state vector sel
+         */
+        uint32_t stat_vector_sel_procpu:1;
+        /** all_reset_flag_procpu : RO; bitpos: [14]; default: 0;
+         *  PRO CPU reset_flag
+         */
+        uint32_t all_reset_flag_procpu:1;
+        /** all_reset_flag_appcpu : RO; bitpos: [15]; default: 0;
+         *  APP CPU reset flag
+         */
+        uint32_t all_reset_flag_appcpu:1;
+        /** all_reset_flag_clr_procpu : WO; bitpos: [16]; default: 0;
+         *  clear PRO CPU reset_flag
+         */
+        uint32_t all_reset_flag_clr_procpu:1;
+        /** all_reset_flag_clr_appcpu : WO; bitpos: [17]; default: 0;
+         *  clear APP CPU reset flag
+         */
+        uint32_t all_reset_flag_clr_appcpu:1;
+        /** ocd_halt_on_reset_appcpu : R/W; bitpos: [18]; default: 0;
+         *  APPCPU OcdHaltOnReset
+         */
+        uint32_t ocd_halt_on_reset_appcpu:1;
+        /** ocd_halt_on_reset_procpu : R/W; bitpos: [19]; default: 0;
+         *  PROCPU OcdHaltOnReset
+         */
+        uint32_t ocd_halt_on_reset_procpu:1;
+        /** jtag_reset_flag_procpu : RO; bitpos: [20]; default: 0;
+         *  Need add description
+         */
+        uint32_t jtag_reset_flag_procpu:1;
+        /** jtag_reset_flag_appcpu : RO; bitpos: [21]; default: 0;
+         *  Need add description
+         */
+        uint32_t jtag_reset_flag_appcpu:1;
+        /** jtag_reset_flag_clr_procpu : WO; bitpos: [22]; default: 0;
+         *  Need add description
+         */
+        uint32_t jtag_reset_flag_clr_procpu:1;
+        /** jtag_reset_flag_clr_appcpu : WO; bitpos: [23]; default: 0;
+         *  Need add description
+         */
+        uint32_t jtag_reset_flag_clr_appcpu:1;
+        /** rtc_dreset_mask_appcpu : R/W; bitpos: [24]; default: 0;
+         *  Need add description
+         */
+        uint32_t rtc_dreset_mask_appcpu:1;
+        /** rtc_dreset_mask_procpu : R/W; bitpos: [25]; default: 0;
+         *  Need add description
+         */
+        uint32_t rtc_dreset_mask_procpu:1;
+        uint32_t reserved_26:6;
+    };
+    uint32_t val;
+} rtc_cntl_reset_state_reg_t;
+
+/** Type of rtc_wakeup_state register
+ *  register description
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:13;
+        /** rtc_wakeup_ena : R/W; bitpos: [31:13]; default: 12;
+         *  wakeup enable bitmap
+         */
+        uint32_t rtc_wakeup_ena:19;
+    };
+    uint32_t val;
+} rtc_cntl_wakeup_state_reg_t;
+
+/** Type of int_ena register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** slp_wakeup : R/W; bitpos: [0]; default: 0;
+         *  enable sleep wakeup interrupt
+         */
+        uint32_t slp_wakeup:1;
+        /** slp_reject : R/W; bitpos: [1]; default: 0;
+         *  enable sleep reject interrupt
+         */
+        uint32_t slp_reject:1;
+        uint32_t reserved_2:1;
+        /** rtc_wdt : R/W; bitpos: [3]; default: 0;
+         *  enable RTC WDT interrupt
+         */
+        uint32_t rtc_wdt:1;
+        uint32_t reserved_4:5;
+        /** rtc_brown_out : R/W; bitpos: [9]; default: 0;
+         *  enable brown out interrupt
+         */
+        uint32_t rtc_brown_out:1;
+        /** rtc_main_timer : R/W; bitpos: [10]; default: 0;
+         *  enable RTC main timer interrupt
+         */
+        uint32_t rtc_main_timer:1;
+        uint32_t reserved_11:4;
+        /** rtc_swd : R/W; bitpos: [15]; default: 0;
+         *  enable super watch dog interrupt
+         */
+        uint32_t rtc_swd:1;
+        /** rtc_xtal32k_dead : R/W; bitpos: [16]; default: 0;
+         *  enable xtal32k_dead  interrupt
+         */
+        uint32_t rtc_xtal32k_dead:1;
+        uint32_t reserved_17:2;
+        /** rtc_glitch_det : R/W; bitpos: [19]; default: 0;
+         *  enbale gitch det interrupt
+         */
+        uint32_t rtc_glitch_det:1;
+        /** rtc_bbpll_cal : R/W; bitpos: [20]; default: 0;
+         *  Need add description
+         */
+        uint32_t rtc_bbpll_cal:1;
+        /** rtc_ble_compare_wake : RW; bitpos: [21]; default: 0;
+         *  Need add description
+         */
+        uint32_t rtc_ble_compare_wake:1;
+        /** vset_dcdc_done : R/W; bitpos: [22]; default: 0;
+         *  Need add description
+         */
+        uint32_t vset_dcdc_done:1;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} rtc_cntl_int_ena_reg_t;
+
+/** Type of int_raw register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** slp_wakeup : RO; bitpos: [0]; default: 0;
+         *  sleep wakeup interrupt raw
+         */
+        uint32_t slp_wakeup:1;
+        /** slp_reject : RO; bitpos: [1]; default: 0;
+         *  sleep reject interrupt raw
+         */
+        uint32_t slp_reject:1;
+        uint32_t reserved_2:1;
+        /** rtc_wdt : RO; bitpos: [3]; default: 0;
+         *  RTC WDT interrupt raw
+         */
+        uint32_t rtc_wdt:1;
+        uint32_t reserved_4:5;
+        /** rtc_brown_out : RO; bitpos: [9]; default: 0;
+         *  brown out interrupt raw
+         */
+        uint32_t rtc_brown_out:1;
+        /** rtc_main_timer : RO; bitpos: [10]; default: 0;
+         *  RTC main timer interrupt raw
+         */
+        uint32_t rtc_main_timer:1;
+        uint32_t reserved_11:4;
+        /** rtc_swd : RO; bitpos: [15]; default: 0;
+         *  super watch dog interrupt raw
+         */
+        uint32_t rtc_swd:1;
+        /** rtc_xtal32k_dead : RO; bitpos: [16]; default: 0;
+         *  xtal32k dead detection interrupt raw
+         */
+        uint32_t rtc_xtal32k_dead:1;
+        uint32_t reserved_17:2;
+        /** rtc_glitch_det : RO; bitpos: [19]; default: 0;
+         *  glitch_det_interrupt_raw
+         */
+        uint32_t rtc_glitch_det:1;
+        /** rtc_bbpll_cal : RO; bitpos: [20]; default: 0;
+         *  Need add description
+         */
+        uint32_t rtc_bbpll_cal:1;
+        /** rtc_ble_compare_wake : RO; bitpos: [21]; default: 0;
+         *  Need add description
+         */
+        uint32_t rtc_ble_compare_wake:1;
+        /** vset_dcdc_done : RO; bitpos: [22]; default: 0;
+         *  Need add description
+         */
+        uint32_t vset_dcdc_done:1;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} rtc_cntl_int_raw_reg_t;
+
+/** Type of int_st register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** slp_wakeup : RO; bitpos: [0]; default: 0;
+         *  sleep wakeup interrupt state
+         */
+        uint32_t slp_wakeup:1;
+        /** slp_reject : RO; bitpos: [1]; default: 0;
+         *  sleep reject interrupt state
+         */
+        uint32_t slp_reject:1;
+        uint32_t reserved_2:1;
+        /** rtc_wdt : RO; bitpos: [3]; default: 0;
+         *  RTC WDT interrupt state
+         */
+        uint32_t rtc_wdt:1;
+        uint32_t reserved_4:5;
+        /** rtc_brown_out : RO; bitpos: [9]; default: 0;
+         *  brown out interrupt state
+         */
+        uint32_t rtc_brown_out:1;
+        /** rtc_main_timer : RO; bitpos: [10]; default: 0;
+         *  RTC main timer interrupt state
+         */
+        uint32_t rtc_main_timer:1;
+        uint32_t reserved_11:4;
+        /** rtc_swd : RO; bitpos: [15]; default: 0;
+         *  super watch dog interrupt state
+         */
+        uint32_t rtc_swd:1;
+        /** rtc_xtal32k_dead : RO; bitpos: [16]; default: 0;
+         *  xtal32k dead detection interrupt state
+         */
+        uint32_t rtc_xtal32k_dead:1;
+        uint32_t reserved_17:2;
+        /** rtc_glitch_det : RO; bitpos: [19]; default: 0;
+         *  glitch_det_interrupt state
+         */
+        uint32_t rtc_glitch_det:1;
+        /** rtc_bbpll_cal : RO; bitpos: [20]; default: 0;
+         *  Need add description
+         */
+        uint32_t rtc_bbpll_cal:1;
+        /** rtc_ble_compare_wake : RO; bitpos: [21]; default: 0;
+         *  Need add description
+         */
+        uint32_t rtc_ble_compare_wake:1;
+        /** vset_dcdc_done : RO; bitpos: [22]; default: 0;
+         *  Need add description
+         */
+        uint32_t vset_dcdc_done:1;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} rtc_cntl_int_st_reg_t;
+
+/** Type of int_clr register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** slp_wakeup : WO; bitpos: [0]; default: 0;
+         *  Clear sleep wakeup interrupt state
+         */
+        uint32_t slp_wakeup:1;
+        /** slp_reject : WO; bitpos: [1]; default: 0;
+         *  Clear sleep reject interrupt state
+         */
+        uint32_t slp_reject:1;
+        uint32_t reserved_2:1;
+        /** rtc_wdt : WO; bitpos: [3]; default: 0;
+         *  Clear RTC WDT interrupt state
+         */
+        uint32_t rtc_wdt:1;
+        uint32_t reserved_4:5;
+        /** rtc_brown_out : WO; bitpos: [9]; default: 0;
+         *  Clear brown out interrupt state
+         */
+        uint32_t rtc_brown_out:1;
+        /** rtc_main_timer : WO; bitpos: [10]; default: 0;
+         *  Clear RTC main timer interrupt state
+         */
+        uint32_t rtc_main_timer:1;
+        uint32_t reserved_11:4;
+        /** rtc_swd : WO; bitpos: [15]; default: 0;
+         *  Clear super watch dog interrupt state
+         */
+        uint32_t rtc_swd:1;
+        /** rtc_xtal32k_dead : WO; bitpos: [16]; default: 0;
+         *  Clear RTC WDT interrupt state
+         */
+        uint32_t rtc_xtal32k_dead:1;
+        uint32_t reserved_17:2;
+        /** rtc_glitch_det : WO; bitpos: [19]; default: 0;
+         *  Clear glitch det interrupt state
+         */
+        uint32_t rtc_glitch_det:1;
+        /** rtc_bbpll_cal : WO; bitpos: [20]; default: 0;
+         *  Need add description
+         */
+        uint32_t rtc_bbpll_cal:1;
+        /** rtc_ble_compare_wake : WO; bitpos: [21]; default: 0;
+         *  Need add description
+         */
+        uint32_t rtc_ble_compare_wake:1;
+        /** vset_dcdc_done : WO; bitpos: [22]; default: 0;
+         *  Need add description
+         */
+        uint32_t vset_dcdc_done:1;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} rtc_cntl_int_clr_reg_t;
+
+/** Type of  register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** rtc_scratch : R/W; bitpos: [31:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t rtc_scratch:32;
+    };
+    uint32_t val;
+} rtc_cntl_store_reg_t;
+
+
+/** Type of rtc_ext_xtl_conf register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** xtal32k_wdt_en : R/W; bitpos: [0]; default: 0;
+         *  xtal 32k watch dog enable
+         */
+        uint32_t xtal32k_wdt_en:1;
+        /** xtal32k_wdt_clk_fo : R/W; bitpos: [1]; default: 0;
+         *  xtal 32k watch dog clock force on
+         */
+        uint32_t xtal32k_wdt_clk_fo:1;
+        /** xtal32k_wdt_reset : R/W; bitpos: [2]; default: 0;
+         *  xtal 32k watch dog sw reset
+         */
+        uint32_t xtal32k_wdt_reset:1;
+        /** xtal32k_ext_clk_fo : R/W; bitpos: [3]; default: 0;
+         *  xtal 32k external xtal clock force on
+         */
+        uint32_t xtal32k_ext_clk_fo:1;
+        /** xtal32k_auto_backup : R/W; bitpos: [4]; default: 0;
+         *  xtal 32k switch to back up clock when xtal is dead
+         */
+        uint32_t xtal32k_auto_backup:1;
+        /** xtal32k_auto_restart : R/W; bitpos: [5]; default: 0;
+         *  xtal 32k restart xtal when xtal is dead
+         */
+        uint32_t xtal32k_auto_restart:1;
+        /** xtal32k_auto_return : R/W; bitpos: [6]; default: 0;
+         *  xtal 32k switch back xtal when xtal is restarted
+         */
+        uint32_t xtal32k_auto_return:1;
+        /** xtal32k_xpd_force : R/W; bitpos: [7]; default: 1;
+         *  Xtal 32k xpd control by sw or fsm
+         */
+        uint32_t xtal32k_xpd_force:1;
+        /** enckinit_xtal_32k : R/W; bitpos: [8]; default: 0;
+         *  apply an internal clock to help xtal 32k to start
+         */
+        uint32_t enckinit_xtal_32k:1;
+        /** dbuf_xtal_32k : R/W; bitpos: [9]; default: 0;
+         *  0: single-end buffer 1: differential buffer
+         */
+        uint32_t dbuf_xtal_32k:1;
+        /** dgm_xtal_32k : R/W; bitpos: [12:10]; default: 3;
+         *  xtal_32k gm control
+         */
+        uint32_t dgm_xtal_32k:3;
+        /** dres_xtal_32k : R/W; bitpos: [15:13]; default: 3;
+         *  DRES_XTAL_32K
+         */
+        uint32_t dres_xtal_32k:3;
+        /** xpd_xtal_32k : R/W; bitpos: [16]; default: 0;
+         *  XPD_XTAL_32K
+         */
+        uint32_t xpd_xtal_32k:1;
+        /** dac_xtal_32k : R/W; bitpos: [19:17]; default: 3;
+         *  DAC_XTAL_32K
+         */
+        uint32_t dac_xtal_32k:3;
+        /** rtc_wdt_state : RO; bitpos: [22:20]; default: 0;
+         *  state of 32k_wdt
+         */
+        uint32_t rtc_wdt_state:3;
+        /** rtc_xtal32k_gpio_sel : R/W; bitpos: [23]; default: 0;
+         *  XTAL_32K sel. 0: external XTAL_32K, 1: CLK from RTC pad X32P_C
+         */
+        uint32_t rtc_xtal32k_gpio_sel:1;
+        uint32_t reserved_24:6;
+        /** ctr_lv : R/W; bitpos: [30]; default: 0;
+         *  0: power down XTAL at high level, 1: power down XTAL at low level
+         */
+        uint32_t ctr_lv:1;
+        /** ctr_en : R/W; bitpos: [31]; default: 0;
+         *  Need add description
+         */
+        uint32_t ctr_en:1;
+    };
+    uint32_t val;
+} rtc_cntl_ext_xtl_conf_reg_t;
+
+/** Type of rtc_ext_wakeup_conf register
+ *  register description
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** gpio_wakeup_filter : R/W; bitpos: [31]; default: 0;
+         *  enable filter for gpio wakeup event
+         */
+        uint32_t gpio_wakeup_filter:1;
+    };
+    uint32_t val;
+} rtc_cntl_ext_wakeup_conf_reg_t;
+
+/** Type of rtc_slp_reject_conf register
+ *  register description
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:11;
+        /** rtc_sleep_reject_ena : R/W; bitpos: [29:11]; default: 0;
+         *  sleep reject enable
+         */
+        uint32_t rtc_sleep_reject_ena:19;
+        /** light_slp_reject_en : R/W; bitpos: [30]; default: 0;
+         *  enable reject for light sleep
+         */
+        uint32_t light_slp_reject_en:1;
+        /** deep_slp_reject_en : R/W; bitpos: [31]; default: 0;
+         *  enable reject for deep sleep
+         */
+        uint32_t deep_slp_reject_en:1;
+    };
+    uint32_t val;
+} rtc_cntl_slp_reject_conf_reg_t;
+
+/** Type of rtc_cpu_period_conf register
+ *  register description
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:29;
+        /** cpusel_conf : R/W; bitpos: [29]; default: 0;
+         *  CPU sel option
+         */
+        uint32_t cpusel_conf:1;
+        /** cpuperiod_sel : R/W; bitpos: [31:30]; default: 0;
+         *  Need add description
+         */
+        uint32_t cpuperiod_sel:2;
+    };
+    uint32_t val;
+} rtc_cntl_cpu_period_conf_reg_t;
+
+/** Type of rtc_clk_conf register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** rtc_ble_tmr_rst : R/W; bitpos: [0]; default: 0;
+         *  Need add description
+         */
+        uint32_t rtc_ble_tmr_rst:1;
+        /** efuse_clk_force_gating : R/W; bitpos: [1]; default: 0;
+         *  Need add description
+         */
+        uint32_t efuse_clk_force_gating:1;
+        /** efuse_clk_force_nogating : R/W; bitpos: [2]; default: 0;
+         *  Need add description
+         */
+        uint32_t efuse_clk_force_nogating:1;
+        /** ck8m_div_sel_vld : R/W; bitpos: [3]; default: 1;
+         *  used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel, then set
+         *  vld to actually switch the clk
+         */
+        uint32_t ck8m_div_sel_vld:1;
+        /** dig_xtal32k_en : R/W; bitpos: [4]; default: 0;
+         *  enable CK_XTAL_32K for digital core (no relationship with RTC core)
+         */
+        uint32_t dig_xtal32k_en:1;
+        /** dig_rc32k_en : R/W; bitpos: [5]; default: 1;
+         *  enable RC32K for digital core (no relationship with RTC core)
+         */
+        uint32_t dig_rc32k_en:1;
+        /** dig_clk8m_en : R/W; bitpos: [6]; default: 0;
+         *  enable CK8M for digital core (no relationship with RTC core)
+         */
+        uint32_t dig_clk8m_en:1;
+        /** rtc_ble_timer_sel : R/W; bitpos: [7]; default: 0;
+         *  Need add description
+         */
+        uint32_t rtc_ble_timer_sel:1;
+        uint32_t reserved_8:2;
+        /** ck8m_div_sel : R/W; bitpos: [12:10]; default: 3;
+         *  divider = reg_ck8m_div_sel + 1
+         */
+        uint32_t ck8m_div_sel:3;
+        /** xtal_force_nogating : R/W; bitpos: [13]; default: 0;
+         *  XTAL force no gating during sleep
+         */
+        uint32_t xtal_force_nogating:1;
+        /** ck8m_force_nogating : R/W; bitpos: [14]; default: 0;
+         *  CK8M force no gating during sleep
+         */
+        uint32_t ck8m_force_nogating:1;
+        /** ck8m_dfreq : R/W; bitpos: [24:15]; default: 600;
+         *  CK8M_DFREQ
+         */
+        uint32_t ck8m_dfreq:10;
+        /** ck8m_force_pd : R/W; bitpos: [25]; default: 0;
+         *  CK8M force power down
+         */
+        uint32_t ck8m_force_pd:1;
+        /** ck8m_force_pu : R/W; bitpos: [26]; default: 0;
+         *  CK8M force power up
+         */
+        uint32_t ck8m_force_pu:1;
+        /** xtal_global_force_gating : R/W; bitpos: [27]; default: 0;
+         *  Need add description
+         */
+        uint32_t xtal_global_force_gating:1;
+        /** xtal_global_force_nogating : R/W; bitpos: [28]; default: 1;
+         *  Need add description
+         */
+        uint32_t xtal_global_force_nogating:1;
+        /** fast_clk_rtc_sel : R/W; bitpos: [29]; default: 0;
+         *  fast_clk_rtc sel. 0: XTAL div 4, 1: CK8M
+         */
+        uint32_t fast_clk_rtc_sel:1;
+        /** ana_clk_rtc_sel : R/W; bitpos: [31:30]; default: 0;
+         *  Need add description
+         */
+        uint32_t ana_clk_rtc_sel:2;
+    };
+    uint32_t val;
+} rtc_cntl_clk_conf_reg_t;
+
+/** Type of rtc_slow_clk_conf register
+ *  register description
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:19;
+        /** rtc_ana_clk_pd_slp : R/W; bitpos: [19]; default: 0;
+         *  Need add description
+         */
+        uint32_t rtc_ana_clk_pd_slp:1;
+        /** rtc_ana_clk_pd_monitor : R/W; bitpos: [20]; default: 0;
+         *  Need add description
+         */
+        uint32_t rtc_ana_clk_pd_monitor:1;
+        /** rtc_ana_clk_pd_idle : R/W; bitpos: [21]; default: 0;
+         *  Need add description
+         */
+        uint32_t rtc_ana_clk_pd_idle:1;
+        /** rtc_ana_clk_div_vld : R/W; bitpos: [22]; default: 1;
+         *  used to sync div bus. clear vld before set reg_rtc_ana_clk_div, then set vld to
+         *  actually switch the clk
+         */
+        uint32_t rtc_ana_clk_div_vld:1;
+        /** rtc_ana_clk_div : R/W; bitpos: [30:23]; default: 0;
+         *  Need add description
+         */
+        uint32_t rtc_ana_clk_div:8;
+        /** slow_clk_next_edge : R/W; bitpos: [31]; default: 0;
+         *  Need add description
+         */
+        uint32_t slow_clk_next_edge:1;
+    };
+    uint32_t val;
+} rtc_cntl_slow_clk_conf_reg_t;
+
+/** Type of rtc_sdio_conf register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** sdio_timer_target : R/W; bitpos: [7:0]; default: 10;
+         *  timer count to apply reg_sdio_dcap after sdio power on
+         */
+        uint32_t sdio_timer_target:8;
+        uint32_t reserved_8:1;
+        /** sdio_dthdrv : R/W; bitpos: [10:9]; default: 3;
+         *  Tieh = 1 mode drive ability. Initially set to 0 to limit charge current, set to 3
+         *  after several us.
+         */
+        uint32_t sdio_dthdrv:2;
+        /** sdio_dcap : R/W; bitpos: [12:11]; default: 3;
+         *  ability to prevent LDO from overshoot
+         */
+        uint32_t sdio_dcap:2;
+        /** sdio_initi : R/W; bitpos: [14:13]; default: 1;
+         *  add resistor from ldo output to ground. 0: no res, 1: 6k, 2: 4k, 3: 2k
+         */
+        uint32_t sdio_initi:2;
+        /** sdio_en_initi : R/W; bitpos: [15]; default: 1;
+         *  0 to set init[1:0]=0
+         */
+        uint32_t sdio_en_initi:1;
+        /** sdio_dcurlim : R/W; bitpos: [18:16]; default: 0;
+         *  tune current limit threshold when tieh = 0. About 800mA/(8+d)
+         */
+        uint32_t sdio_dcurlim:3;
+        /** sdio_modecurlim : R/W; bitpos: [19]; default: 0;
+         *  select current limit mode
+         */
+        uint32_t sdio_modecurlim:1;
+        /** sdio_encurlim : R/W; bitpos: [20]; default: 1;
+         *  enable current limit
+         */
+        uint32_t sdio_encurlim:1;
+        /** sdio_reg_pd_en : R/W; bitpos: [21]; default: 1;
+         *  power down SDIO_REG in sleep. Only active when reg_sdio_force = 0
+         */
+        uint32_t sdio_reg_pd_en:1;
+        /** sdio_force : R/W; bitpos: [22]; default: 0;
+         *  1: use SW option to control SDIO_REG ,0: use state machine
+         */
+        uint32_t sdio_force:1;
+        /** sdio_tieh : R/W; bitpos: [23]; default: 1;
+         *  SW option for SDIO_TIEH. Only active when reg_sdio_force = 1
+         */
+        uint32_t sdio_tieh:1;
+        /** reg1p8_ready : RO; bitpos: [24]; default: 0;
+         *  read only register for REG1P8_READY
+         */
+        uint32_t reg1p8_ready:1;
+        /** drefl_sdio : R/W; bitpos: [26:25]; default: 1;
+         *  SW option for DREFL_SDIO. Only active when reg_sdio_force = 1
+         */
+        uint32_t drefl_sdio:2;
+        /** drefm_sdio : R/W; bitpos: [28:27]; default: 1;
+         *  SW option for DREFM_SDIO. Only active when reg_sdio_force = 1
+         */
+        uint32_t drefm_sdio:2;
+        /** drefh_sdio : R/W; bitpos: [30:29]; default: 0;
+         *  SW option for DREFH_SDIO. Only active when reg_sdio_force = 1
+         */
+        uint32_t drefh_sdio:2;
+        /** xpd_sdio_reg : R/W; bitpos: [31]; default: 0;
+         *  Need add description
+         */
+        uint32_t xpd_sdio_reg:1;
+    };
+    uint32_t val;
+} rtc_cntl_sdio_conf_reg_t;
+
+/** Type of rtc_bias_conf register
+ *  register description
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:10;
+        /** bias_buf_idle : R/W; bitpos: [10]; default: 0;
+         *  Need add description
+         */
+        uint32_t bias_buf_idle:1;
+        /** bias_buf_wake : R/W; bitpos: [11]; default: 1;
+         *  Need add description
+         */
+        uint32_t bias_buf_wake:1;
+        /** bias_buf_deep_slp : R/W; bitpos: [12]; default: 0;
+         *  Need add description
+         */
+        uint32_t bias_buf_deep_slp:1;
+        /** bias_buf_monitor : R/W; bitpos: [13]; default: 0;
+         *  Need add description
+         */
+        uint32_t bias_buf_monitor:1;
+        /** pd_cur_deep_slp : R/W; bitpos: [14]; default: 0;
+         *  xpd cur when rtc in sleep_state
+         */
+        uint32_t pd_cur_deep_slp:1;
+        /** pd_cur_monitor : R/W; bitpos: [15]; default: 0;
+         *  xpd cur when rtc in monitor state
+         */
+        uint32_t pd_cur_monitor:1;
+        /** bias_sleep_deep_slp : R/W; bitpos: [16]; default: 1;
+         *  bias_sleep when rtc in sleep_state
+         */
+        uint32_t bias_sleep_deep_slp:1;
+        /** bias_sleep_monitor : R/W; bitpos: [17]; default: 0;
+         *  bias_sleep when rtc in monitor state
+         */
+        uint32_t bias_sleep_monitor:1;
+        /** dbg_atten_deep_slp : R/W; bitpos: [21:18]; default: 0;
+         *  DBG_ATTEN when rtc in sleep state
+         */
+        uint32_t dbg_atten_deep_slp:4;
+        /** dbg_atten_monitor : R/W; bitpos: [25:22]; default: 0;
+         *  DBG_ATTEN when rtc in monitor state
+         */
+        uint32_t dbg_atten_monitor:4;
+        /** xpd_dcdc_slp : R/W; bitpos: [26]; default: 1;
+         *  Need add description
+         */
+        uint32_t xpd_dcdc_slp:1;
+        /** xpd_dcdc_monitor : R/W; bitpos: [27]; default: 1;
+         *  Need add description
+         */
+        uint32_t xpd_dcdc_monitor:1;
+        /** xpd_dcdc_idle : R/W; bitpos: [28]; default: 1;
+         *  Need add description
+         */
+        uint32_t xpd_dcdc_idle:1;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} rtc_cntl_bias_conf_reg_t;
+
+/** Type of rtc_regulator register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** dbias_switch_slp : R/W; bitpos: [0]; default: 0;
+         *  Need add description
+         */
+        uint32_t dbias_switch_slp:1;
+        /** dbias_switch_monitor : R/W; bitpos: [1]; default: 0;
+         *  Need add description
+         */
+        uint32_t dbias_switch_monitor:1;
+        /** dbias_switch_idle : R/W; bitpos: [2]; default: 0;
+         *  Need add description
+         */
+        uint32_t dbias_switch_idle:1;
+        /** dig_reg_cal_en : R/W; bitpos: [3]; default: 0;
+         *  Need add description
+         */
+        uint32_t dig_reg_cal_en:1;
+        /** sck_dcap : R/W; bitpos: [11:4]; default: 0;
+         *  Need add description
+         */
+        uint32_t sck_dcap:8;
+        uint32_t reserved_12:3;
+        /** rtc_vdd_drv_b_active : R/W; bitpos: [20:15]; default: 0;
+         *  SCK_DCAP
+         */
+        uint32_t rtc_vdd_drv_b_active:6;
+        /** rtc_vdd_drv_b_slp : R/W; bitpos: [26:21]; default: 0;
+         *  Need add description
+         */
+        uint32_t rtc_vdd_drv_b_slp:6;
+        /** rtc_vdd_drv_b_slp_en : R/W; bitpos: [27]; default: 0;
+         *  Need add description
+         */
+        uint32_t rtc_vdd_drv_b_slp_en:1;
+        /** rtc_dboost_force_pd : R/W; bitpos: [28]; default: 0;
+         *  RTC_DBOOST force power down
+         */
+        uint32_t rtc_dboost_force_pd:1;
+        /** rtc_dboost_force_pu : R/W; bitpos: [29]; default: 1;
+         *  RTC_DBOOST force power up
+         */
+        uint32_t rtc_dboost_force_pu:1;
+        /** rtc_regulator_force_pd : R/W; bitpos: [30]; default: 0;
+         *  RTC_REG force power down (for RTC_REG power down means decrease the voltage to 0.8v
+         *  or lower )
+         */
+        uint32_t rtc_regulator_force_pd:1;
+        /** rtc_regulator_force_pu : R/W; bitpos: [31]; default: 1;
+         *  Need add description
+         */
+        uint32_t rtc_regulator_force_pu:1;
+    };
+    uint32_t val;
+} rtc_cntl_regulator_reg_t;
+
+/** Type of rtc_regulator0_dbias register
+ *  register description
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:15;
+        /** pvt_rtc_dbias : RO; bitpos: [19:15]; default: 20;
+         *  get pvt dbias value
+         */
+        uint32_t pvt_rtc_dbias:5;
+        /** rtc_regulator0_dbias_slp : R/W; bitpos: [24:20]; default: 20;
+         *  the rtc regulator0 dbias when chip in sleep state
+         */
+        uint32_t rtc_regulator0_dbias_slp:5;
+        /** rtc_regulator0_dbias_active : R/W; bitpos: [29:25]; default: 20;
+         *  the rtc regulator0 dbias when chip in active state
+         */
+        uint32_t rtc_regulator0_dbias_active:5;
+        uint32_t reserved_30:1;
+        /** rtc_regulator0_dbias_sel : R/W; bitpos: [31]; default: 1;
+         *  1: select sw dbias_active 0: select pvt value
+         */
+        uint32_t rtc_regulator0_dbias_sel:1;
+    };
+    uint32_t val;
+} rtc_cntl_regulator0_dbias_reg_t;
+
+/** Type of rtc_regulator1_dbias register
+ *  register description
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** rtc_regulator1_dbias_slp : R/W; bitpos: [23:20]; default: 8;
+         *  the rtc regulator1 dbias when chip in sleep state
+         */
+        uint32_t rtc_regulator1_dbias_slp:4;
+        uint32_t reserved_24:1;
+        /** rtc_regulator1_dbias_active : R/W; bitpos: [28:25]; default: 8;
+         *  the rtc regulator1 dbias when chip in active state
+         */
+        uint32_t rtc_regulator1_dbias_active:4;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} rtc_cntl_regulator1_dbias_reg_t;
+
+/** Type of dig_regulator register
+ *  register description
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:1;
+        /** mem_regulator_slp_force_pd : R/W; bitpos: [1]; default: 0;
+         *  Need add description
+         */
+        uint32_t mem_regulator_slp_force_pd:1;
+        /** mem_regulator_slp_force_pu : R/W; bitpos: [2]; default: 1;
+         *  Need add description
+         */
+        uint32_t mem_regulator_slp_force_pu:1;
+        /** dg_vdd_drv_b_slp : R/W; bitpos: [26:3]; default: 0;
+         *  Need add description
+         */
+        uint32_t dg_vdd_drv_b_slp:24;
+        /** dg_vdd_drv_b_slp_en : R/W; bitpos: [27]; default: 0;
+         *  Need add description
+         */
+        uint32_t dg_vdd_drv_b_slp_en:1;
+        /** dg_regulator_slp_force_pd : R/W; bitpos: [28]; default: 0;
+         *  Need add description
+         */
+        uint32_t dg_regulator_slp_force_pd:1;
+        /** dg_regulator_slp_force_pu : R/W; bitpos: [29]; default: 1;
+         *  Need add description
+         */
+        uint32_t dg_regulator_slp_force_pu:1;
+        /** dg_regulator_force_pd : R/W; bitpos: [30]; default: 0;
+         *  Need add description
+         */
+        uint32_t dg_regulator_force_pd:1;
+        /** dg_regulator_force_pu : R/W; bitpos: [31]; default: 1;
+         *  Need add description
+         */
+        uint32_t dg_regulator_force_pu:1;
+    };
+    uint32_t val;
+} rtc_cntl_dig_regulator_reg_t;
+
+/** Type of dig_regulator_drvb register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** dg_vdd_drv_b_active : R/W; bitpos: [23:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t dg_vdd_drv_b_active:24;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} rtc_cntl_dig_regulator_drvb_reg_t;
+
+/** Type of dig_regulator0_dbias register
+ *  register description
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:15;
+        /** pvt_dig_dbias : RO; bitpos: [19:15]; default: 20;
+         *  get pvt dbias value
+         */
+        uint32_t pvt_dig_dbias:5;
+        /** dig_regulator0_dbias_slp : R/W; bitpos: [24:20]; default: 20;
+         *  the dig regulator0 dbias when chip in sleep state
+         */
+        uint32_t dig_regulator0_dbias_slp:5;
+        /** dig_regulator0_dbias_active : R/W; bitpos: [29:25]; default: 20;
+         *  the dig regulator0 dbias when chip in active state
+         */
+        uint32_t dig_regulator0_dbias_active:5;
+        /** dig_regulator0_dbias_init : WO; bitpos: [30]; default: 0;
+         *  initial pvt dbias value
+         */
+        uint32_t dig_regulator0_dbias_init:1;
+        /** dig_regulator0_dbias_sel : R/W; bitpos: [31]; default: 1;
+         *  1: select sw dbias_active 0: select pvt value
+         */
+        uint32_t dig_regulator0_dbias_sel:1;
+    };
+    uint32_t val;
+} rtc_cntl_dig_regulator0_dbias_reg_t;
+
+/** Type of dig_regulator1_dbias register
+ *  register description
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:12;
+        /** mem_regulator1_dbias_slp : R/W; bitpos: [15:12]; default: 8;
+         *  Need add description
+         */
+        uint32_t mem_regulator1_dbias_slp:4;
+        /** mem_regulator1_dbias_active : R/W; bitpos: [19:16]; default: 8;
+         *  Need add description
+         */
+        uint32_t mem_regulator1_dbias_active:4;
+        /** dig_regulator1_dbias_slp : R/W; bitpos: [23:20]; default: 8;
+         *  the dig regulator1 dbias when chip in sleep state
+         */
+        uint32_t dig_regulator1_dbias_slp:4;
+        uint32_t reserved_24:1;
+        /** dig_regulator1_dbias_active : R/W; bitpos: [28:25]; default: 8;
+         *  the dig regulator1 dbias when chip in active state
+         */
+        uint32_t dig_regulator1_dbias_active:4;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} rtc_cntl_dig_regulator1_dbias_reg_t;
+
+/** Type of rtc_pwc register
+ *  register description
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:21;
+        /** rtc_pad_force_hold : R/W; bitpos: [21]; default: 0;
+         *  rtc pad force hold
+         */
+        uint32_t rtc_pad_force_hold:1;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} rtc_cntl_pwc_reg_t;
+
+/** Type of dig_pwc register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** vdd_spi_pwr_drv : R/W; bitpos: [1:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t vdd_spi_pwr_drv:2;
+        /** vdd_spi_pwr_force : R/W; bitpos: [2]; default: 0;
+         *  Need add description
+         */
+        uint32_t vdd_spi_pwr_force:1;
+        /** lslp_mem_force_pd : R/W; bitpos: [3]; default: 0;
+         *  memories in digital core force PD in sleep
+         */
+        uint32_t lslp_mem_force_pd:1;
+        /** lslp_mem_force_pu : R/W; bitpos: [4]; default: 1;
+         *  memories in digital core force no PD in sleep
+         */
+        uint32_t lslp_mem_force_pu:1;
+        uint32_t reserved_5:2;
+        /** dg_mem_force_pd : R/W; bitpos: [7]; default: 0;
+         *  Need add description
+         */
+        uint32_t dg_mem_force_pd:1;
+        /** dg_mem_force_pu : R/W; bitpos: [8]; default: 1;
+         *  Need add description
+         */
+        uint32_t dg_mem_force_pu:1;
+        /** dg_wrap_force_pd : R/W; bitpos: [9]; default: 0;
+         *  Need add description
+         */
+        uint32_t dg_wrap_force_pd:1;
+        /** dg_wrap_force_pu : R/W; bitpos: [10]; default: 1;
+         *  Need add description
+         */
+        uint32_t dg_wrap_force_pu:1;
+        /** bt_force_pd : R/W; bitpos: [11]; default: 0;
+         *  Need add description
+         */
+        uint32_t bt_force_pd:1;
+        /** bt_force_pu : R/W; bitpos: [12]; default: 1;
+         *  Need add description
+         */
+        uint32_t bt_force_pu:1;
+        /** dg_peri_force_pd : R/W; bitpos: [13]; default: 0;
+         *  Need add description
+         */
+        uint32_t dg_peri_force_pd:1;
+        /** dg_peri_force_pu : R/W; bitpos: [14]; default: 1;
+         *  Need add description
+         */
+        uint32_t dg_peri_force_pu:1;
+        /** fastmem_force_lpd : R/W; bitpos: [15]; default: 0;
+         *  Need add description
+         */
+        uint32_t fastmem_force_lpd:1;
+        /** fastmem_force_lpu : R/W; bitpos: [16]; default: 1;
+         *  Need add description
+         */
+        uint32_t fastmem_force_lpu:1;
+        /** wifi_force_pd : R/W; bitpos: [17]; default: 0;
+         *  wifi force power down
+         */
+        uint32_t wifi_force_pd:1;
+        /** wifi_force_pu : R/W; bitpos: [18]; default: 1;
+         *  wifi force power up
+         */
+        uint32_t wifi_force_pu:1;
+        uint32_t reserved_19:2;
+        /** cpu_top_force_pd : R/W; bitpos: [21]; default: 0;
+         *  Need add description
+         */
+        uint32_t cpu_top_force_pd:1;
+        /** cpu_top_force_pu : R/W; bitpos: [22]; default: 1;
+         *  Need add description
+         */
+        uint32_t cpu_top_force_pu:1;
+        uint32_t reserved_23:3;
+        /** dg_wrap_ret_pd_en : R/W; bitpos: [26]; default: 0;
+         *  Need add description
+         */
+        uint32_t dg_wrap_ret_pd_en:1;
+        /** bt_pd_en : R/W; bitpos: [27]; default: 0;
+         *  Need add description
+         */
+        uint32_t bt_pd_en:1;
+        /** dg_peri_pd_en : R/W; bitpos: [28]; default: 0;
+         *  Need add description
+         */
+        uint32_t dg_peri_pd_en:1;
+        /** cpu_top_pd_en : R/W; bitpos: [29]; default: 0;
+         *  Need add description
+         */
+        uint32_t cpu_top_pd_en:1;
+        /** wifi_pd_en : R/W; bitpos: [30]; default: 0;
+         *  enable power down wifi in sleep
+         */
+        uint32_t wifi_pd_en:1;
+        /** dg_wrap_pd_en : R/W; bitpos: [31]; default: 0;
+         *  Need add description
+         */
+        uint32_t dg_wrap_pd_en:1;
+    };
+    uint32_t val;
+} rtc_cntl_dig_pwc_reg_t;
+
+/** Type of dig_power_slave0_pd register
+ *  register description
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:2;
+        /** pd_dg_peri_switch_mask : R/W; bitpos: [6:2]; default: 0;
+         *  Need add description
+         */
+        uint32_t pd_dg_peri_switch_mask:5;
+        /** pd_dg_wrap_switch_mask : R/W; bitpos: [11:7]; default: 0;
+         *  Need add description
+         */
+        uint32_t pd_dg_wrap_switch_mask:5;
+        /** pd_mem_switch_mask : R/W; bitpos: [31:12]; default: 0;
+         *  Need add description
+         */
+        uint32_t pd_mem_switch_mask:20;
+    };
+    uint32_t val;
+} rtc_cntl_dig_power_slave0_pd_reg_t;
+
+/** Type of dig_power_slave1_pd register
+ *  register description
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:22;
+        /** pd_wifi_switch_mask : R/W; bitpos: [26:22]; default: 0;
+         *  Need add description
+         */
+        uint32_t pd_wifi_switch_mask:5;
+        /** pd_cpu_switch_mask : R/W; bitpos: [31:27]; default: 0;
+         *  Need add description
+         */
+        uint32_t pd_cpu_switch_mask:5;
+    };
+    uint32_t val;
+} rtc_cntl_dig_power_slave1_pd_reg_t;
+
+/** Type of dig_power_slave0_fpu register
+ *  register description
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:2;
+        /** xpd_dg_peri_switch_mask : R/W; bitpos: [6:2]; default: 31;
+         *  Need add description
+         */
+        uint32_t xpd_dg_peri_switch_mask:5;
+        /** xpd_dg_wrap_switch_mask : R/W; bitpos: [11:7]; default: 31;
+         *  Need add description
+         */
+        uint32_t xpd_dg_wrap_switch_mask:5;
+        /** xpd_mem_switch_mask : R/W; bitpos: [31:12]; default: 1048575;
+         *  Need add description
+         */
+        uint32_t xpd_mem_switch_mask:20;
+    };
+    uint32_t val;
+} rtc_cntl_dig_power_slave0_fpu_reg_t;
+
+/** Type of dig_power_slave1_fpu register
+ *  register description
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:22;
+        /** xpd_wifi_switch_mask : R/W; bitpos: [26:22]; default: 31;
+         *  Need add description
+         */
+        uint32_t xpd_wifi_switch_mask:5;
+        /** xpd_cpu_switch_mask : R/W; bitpos: [31:27]; default: 31;
+         *  Need add description
+         */
+        uint32_t xpd_cpu_switch_mask:5;
+    };
+    uint32_t val;
+} rtc_cntl_dig_power_slave1_fpu_reg_t;
+
+/** Type of dig_iso register
+ *  register description
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:5;
+        /** dg_mem_force_noiso : R/W; bitpos: [5]; default: 1;
+         *  Need add description
+         */
+        uint32_t dg_mem_force_noiso:1;
+        /** dg_mem_force_iso : R/W; bitpos: [6]; default: 0;
+         *  Need add description
+         */
+        uint32_t dg_mem_force_iso:1;
+        /** dig_iso_force_off : R/W; bitpos: [7]; default: 1;
+         *  Need add description
+         */
+        uint32_t dig_iso_force_off:1;
+        /** dig_iso_force_on : R/W; bitpos: [8]; default: 0;
+         *  Need add description
+         */
+        uint32_t dig_iso_force_on:1;
+        /** dg_pad_autohold : RO; bitpos: [9]; default: 0;
+         *  read only register to indicate digital pad auto-hold status
+         */
+        uint32_t dg_pad_autohold:1;
+        /** clr_dg_pad_autohold : WO; bitpos: [10]; default: 0;
+         *  wtite only register to clear digital pad auto-hold
+         */
+        uint32_t clr_dg_pad_autohold:1;
+        /** dg_pad_autohold_en : R/W; bitpos: [11]; default: 0;
+         *  digital pad enable auto-hold
+         */
+        uint32_t dg_pad_autohold_en:1;
+        /** dg_pad_force_noiso : R/W; bitpos: [12]; default: 1;
+         *  digital pad force no ISO
+         */
+        uint32_t dg_pad_force_noiso:1;
+        /** dg_pad_force_iso : R/W; bitpos: [13]; default: 0;
+         *  digital pad force ISO
+         */
+        uint32_t dg_pad_force_iso:1;
+        /** dg_pad_force_unhold : R/W; bitpos: [14]; default: 1;
+         *  digital pad force un-hold
+         */
+        uint32_t dg_pad_force_unhold:1;
+        /** dg_pad_force_hold : R/W; bitpos: [15]; default: 0;
+         *  digital pad force hold
+         */
+        uint32_t dg_pad_force_hold:1;
+        uint32_t reserved_16:6;
+        /** bt_force_iso : R/W; bitpos: [22]; default: 0;
+         *  Need add description
+         */
+        uint32_t bt_force_iso:1;
+        /** bt_force_noiso : R/W; bitpos: [23]; default: 1;
+         *  Need add description
+         */
+        uint32_t bt_force_noiso:1;
+        /** dg_peri_force_iso : R/W; bitpos: [24]; default: 0;
+         *  Need add description
+         */
+        uint32_t dg_peri_force_iso:1;
+        /** dg_peri_force_noiso : R/W; bitpos: [25]; default: 1;
+         *  Need add description
+         */
+        uint32_t dg_peri_force_noiso:1;
+        /** cpu_top_force_iso : R/W; bitpos: [26]; default: 0;
+         *  cpu force ISO
+         */
+        uint32_t cpu_top_force_iso:1;
+        /** cpu_top_force_noiso : R/W; bitpos: [27]; default: 1;
+         *  cpu force no ISO
+         */
+        uint32_t cpu_top_force_noiso:1;
+        /** wifi_force_iso : R/W; bitpos: [28]; default: 0;
+         *  wifi force ISO
+         */
+        uint32_t wifi_force_iso:1;
+        /** wifi_force_noiso : R/W; bitpos: [29]; default: 1;
+         *  wifi force no ISO
+         */
+        uint32_t wifi_force_noiso:1;
+        /** dg_wrap_force_iso : R/W; bitpos: [30]; default: 0;
+         *  digital core force ISO
+         */
+        uint32_t dg_wrap_force_iso:1;
+        /** dg_wrap_force_noiso : R/W; bitpos: [31]; default: 1;
+         *  Need add description
+         */
+        uint32_t dg_wrap_force_noiso:1;
+    };
+    uint32_t val;
+} rtc_cntl_dig_iso_reg_t;
+
+/** Type of rtc_wdtconfig0 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** wdt_chip_reset_width : R/W; bitpos: [7:0]; default: 20;
+         *  chip reset siginal pulse width
+         */
+        uint32_t chip_reset_width:8;
+        /** chip_reset_en : R/W; bitpos: [8]; default: 0;
+         *  wdt reset whole chip enable
+         */
+        uint32_t chip_reset_en:1;
+        /** pause_in_slp : R/W; bitpos: [9]; default: 1;
+         *  pause WDT in sleep
+         */
+        uint32_t pause_in_slp:1;
+        /** appcpu_reset_en : R/W; bitpos: [10]; default: 0;
+         *  enable WDT reset APP CPU
+         */
+        uint32_t appcpu_reset_en:1;
+        /** procpu_reset_en : R/W; bitpos: [11]; default: 0;
+         *  enable WDT reset PRO CPU
+         */
+        uint32_t procpu_reset_en:1;
+        /** flashboot_mod_en : R/W; bitpos: [12]; default: 1;
+         *  enable WDT in flash boot
+         */
+        uint32_t flashboot_mod_en:1;
+        /** sys_reset_length : R/W; bitpos: [15:13]; default: 1;
+         *  system reset counter length
+         */
+        uint32_t sys_reset_length:3;
+        /** cpu_reset_length : R/W; bitpos: [18:16]; default: 1;
+         *  CPU reset counter length
+         */
+        uint32_t cpu_reset_length:3;
+        /** stg3 : R/W; bitpos: [21:19]; default: 0;
+         *  1: interrupt stage en, 2: CPU reset stage en, 3: system reset stage en, 4: RTC
+         *  reset stage en
+         */
+        uint32_t stg3:3;
+        /** stg2 : R/W; bitpos: [24:22]; default: 0;
+         *  1: interrupt stage en, 2: CPU reset stage en, 3: system reset stage en, 4: RTC
+         *  reset stage en
+         */
+        uint32_t stg2:3;
+        /** stg1 : R/W; bitpos: [27:25]; default: 0;
+         *  1: interrupt stage en, 2: CPU reset stage en, 3: system reset stage en, 4: RTC
+         *  reset stage en
+         */
+        uint32_t stg1:3;
+        /** stg0 : R/W; bitpos: [30:28]; default: 0;
+         *  1: interrupt stage en, 2: CPU reset stage en, 3: system reset stage en, 4: RTC
+         *  reset stage en
+         */
+        uint32_t stg0:3;
+        /** en : R/W; bitpos: [31]; default: 0;
+         *  Need add description
+         */
+        uint32_t en:1;
+    };
+    uint32_t val;
+} rtc_cntl_wdtconfig0_reg_t;
+
+/** Type of rtc_wdtconfig1 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** wdt_stg0_hold : R/W; bitpos: [31:0]; default: 200000;
+         *  Need add description
+         */
+        uint32_t wdt_stg0_hold:32;
+    };
+    uint32_t val;
+} rtc_cntl_wdtconfig1_reg_t;
+
+/** Type of rtc_wdtconfig2 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** wdt_stg1_hold : R/W; bitpos: [31:0]; default: 80000;
+         *  Need add description
+         */
+        uint32_t wdt_stg1_hold:32;
+    };
+    uint32_t val;
+} rtc_cntl_wdtconfig2_reg_t;
+
+/** Type of rtc_wdtconfig3 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** wdt_stg2_hold : R/W; bitpos: [31:0]; default: 4095;
+         *  Need add description
+         */
+        uint32_t wdt_stg2_hold:32;
+    };
+    uint32_t val;
+} rtc_cntl_wdtconfig3_reg_t;
+
+/** Type of rtc_wdtconfig4 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** wdt_stg3_hold : R/W; bitpos: [31:0]; default: 4095;
+         *  Need add description
+         */
+        uint32_t wdt_stg3_hold:32;
+    };
+    uint32_t val;
+} rtc_cntl_wdtconfig4_reg_t;
+
+/** Type of rtc_wdtfeed register
+ *  register description
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:31;
+        /** feed : WO; bitpos: [31]; default: 0;
+         *  Need add description
+         */
+        uint32_t feed:1;
+    };
+    uint32_t val;
+} rtc_cntl_wdtfeed_reg_t;
+
+/** Type of rtc_wdtwprotect register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** wdt_wkey : R/W; bitpos: [31:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t wdt_wkey:32;
+    };
+    uint32_t val;
+} rtc_cntl_wdtwprotect_reg_t;
+
+/** Type of rtc_wdtreset_chip register
+ *  register description
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:16;
+        /** reset_chip_target : R/W; bitpos: [23:16]; default: 165;
+         *  Need add description
+         */
+        uint32_t reset_chip_target:8;
+        /** reset_chip_key : R/W; bitpos: [31:24]; default: 0;
+         *  Need add description
+         */
+        uint32_t reset_chip_key:8;
+    };
+    uint32_t val;
+} rtc_cntl_wdtreset_chip_reg_t;
+
+/** Type of rtc_swd_conf register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** swd_reset_flag : RO; bitpos: [0]; default: 0;
+         *  swd reset flag
+         */
+        uint32_t swd_reset_flag:1;
+        /** swd_feed_int : RO; bitpos: [1]; default: 0;
+         *  swd interrupt for feeding
+         */
+        uint32_t swd_feed_int:1;
+        uint32_t reserved_2:15;
+        /** swd_bypass_rst : R/W; bitpos: [17]; default: 0;
+         *  Need add description
+         */
+        uint32_t swd_bypass_rst:1;
+        /** swd_signal_width : R/W; bitpos: [27:18]; default: 300;
+         *  adjust signal width send to swd
+         */
+        uint32_t swd_signal_width:10;
+        /** swd_rst_flag_clr : WO; bitpos: [28]; default: 0;
+         *  reset swd reset flag
+         */
+        uint32_t swd_rst_flag_clr:1;
+        /** swd_feed : WO; bitpos: [29]; default: 0;
+         *  Sw feed swd
+         */
+        uint32_t swd_feed:1;
+        /** swd_disable : R/W; bitpos: [30]; default: 0;
+         *  disabel SWD
+         */
+        uint32_t swd_disable:1;
+        /** swd_auto_feed_en : R/W; bitpos: [31]; default: 0;
+         *  automatically feed swd when int comes
+         */
+        uint32_t swd_auto_feed_en:1;
+    };
+    uint32_t val;
+} rtc_cntl_swd_conf_reg_t;
+
+/** Type of rtc_swd_wprotect register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** swd_wkey : R/W; bitpos: [31:0]; default: 0;
+         *  swd write protect
+         */
+        uint32_t swd_wkey:32;
+    };
+    uint32_t val;
+} rtc_cntl_swd_wprotect_reg_t;
+
+/** Type of rtc_sw_cpu_stall register
+ *  register description
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:20;
+        /** appcpu_c1 : R/W; bitpos: [25:20]; default: 0;
+         *  {reg_sw_stall_appcpu_c1[5:0],  reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP
+         *  CPU
+         */
+        uint32_t appcpu_c1:6;
+        /** procpu_c1 : R/W; bitpos: [31:26]; default: 0;
+         *  Need add description
+         */
+        uint32_t procpu_c1:6;
+    };
+    uint32_t val;
+} rtc_cntl_sw_cpu_stall_reg_t;
+
+/** Type of rtc_low_power_st register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** xpd_rom0 : RO; bitpos: [0]; default: 0;
+         *  rom0 power down
+         */
+        uint32_t xpd_rom0:1;
+        uint32_t reserved_1:1;
+        /** xpd_dig_dcdc : RO; bitpos: [2]; default: 0;
+         *  External DCDC power down
+         */
+        uint32_t xpd_dig_dcdc:1;
+        /** rtc_peri_iso : RO; bitpos: [3]; default: 0;
+         *  rtc peripheral iso
+         */
+        uint32_t rtc_peri_iso:1;
+        /** xpd_rtc_peri : RO; bitpos: [4]; default: 0;
+         *  rtc peripheral power down
+         */
+        uint32_t xpd_rtc_peri:1;
+        /** wifi_iso : RO; bitpos: [5]; default: 0;
+         *  wifi iso
+         */
+        uint32_t wifi_iso:1;
+        /** xpd_wifi : RO; bitpos: [6]; default: 0;
+         *  wifi wrap power down
+         */
+        uint32_t xpd_wifi:1;
+        /** dig_iso : RO; bitpos: [7]; default: 0;
+         *  digital wrap iso
+         */
+        uint32_t dig_iso:1;
+        /** xpd_dig : RO; bitpos: [8]; default: 0;
+         *  digital wrap power down
+         */
+        uint32_t xpd_dig:1;
+        /** rtc_touch_state_start : RO; bitpos: [9]; default: 0;
+         *  touch should start to work
+         */
+        uint32_t rtc_touch_state_start:1;
+        /** rtc_touch_state_switch : RO; bitpos: [10]; default: 0;
+         *  touch is about to working. Switch rtc main state
+         */
+        uint32_t rtc_touch_state_switch:1;
+        /** rtc_touch_state_slp : RO; bitpos: [11]; default: 0;
+         *  touch is in sleep state
+         */
+        uint32_t rtc_touch_state_slp:1;
+        /** rtc_touch_state_done : RO; bitpos: [12]; default: 0;
+         *  touch is done
+         */
+        uint32_t rtc_touch_state_done:1;
+        /** rtc_cocpu_state_start : RO; bitpos: [13]; default: 0;
+         *  ulp/cocpu should start to work
+         */
+        uint32_t rtc_cocpu_state_start:1;
+        /** rtc_cocpu_state_switch : RO; bitpos: [14]; default: 0;
+         *  ulp/cocpu is about to working. Switch rtc main state
+         */
+        uint32_t rtc_cocpu_state_switch:1;
+        /** rtc_cocpu_state_slp : RO; bitpos: [15]; default: 0;
+         *  ulp/cocpu is in sleep state
+         */
+        uint32_t rtc_cocpu_state_slp:1;
+        /** rtc_cocpu_state_done : RO; bitpos: [16]; default: 0;
+         *  ulp/cocpu is done
+         */
+        uint32_t rtc_cocpu_state_done:1;
+        /** rtc_main_state_xtal_iso : RO; bitpos: [17]; default: 0;
+         *  no use any more
+         */
+        uint32_t rtc_main_state_xtal_iso:1;
+        /** rtc_main_state_pll_on : RO; bitpos: [18]; default: 0;
+         *  rtc main state machine is in states that pll should be running
+         */
+        uint32_t rtc_main_state_pll_on:1;
+        /** rtc_rdy_for_wakeup : RO; bitpos: [19]; default: 0;
+         *  rtc is ready to receive wake up trigger from wake up source
+         */
+        uint32_t rtc_rdy_for_wakeup:1;
+        /** rtc_main_state_wait_end : RO; bitpos: [20]; default: 0;
+         *  rtc main state machine has been waited for some cycles
+         */
+        uint32_t rtc_main_state_wait_end:1;
+        /** rtc_in_wakeup_state : RO; bitpos: [21]; default: 0;
+         *  rtc main state machine is in the states of wakeup process
+         */
+        uint32_t rtc_in_wakeup_state:1;
+        /** rtc_in_low_power_state : RO; bitpos: [22]; default: 0;
+         *  rtc main state machine is in the states of low power
+         */
+        uint32_t rtc_in_low_power_state:1;
+        /** rtc_main_state_in_wait_8m : RO; bitpos: [23]; default: 0;
+         *  rtc main state machine is in wait 8m state
+         */
+        uint32_t rtc_main_state_in_wait_8m:1;
+        /** rtc_main_state_in_wait_pll : RO; bitpos: [24]; default: 0;
+         *  rtc main state machine is in wait pll state
+         */
+        uint32_t rtc_main_state_in_wait_pll:1;
+        /** rtc_main_state_in_wait_xtl : RO; bitpos: [25]; default: 0;
+         *  rtc main state machine is in wait xtal state
+         */
+        uint32_t rtc_main_state_in_wait_xtl:1;
+        /** rtc_main_state_in_slp : RO; bitpos: [26]; default: 0;
+         *  rtc main state machine is in sleep state
+         */
+        uint32_t rtc_main_state_in_slp:1;
+        /** rtc_main_state_in_idle : RO; bitpos: [27]; default: 0;
+         *  rtc main state machine is in idle state
+         */
+        uint32_t rtc_main_state_in_idle:1;
+        /** rtc_main_state : RO; bitpos: [31:28]; default: 0;
+         *  rtc main state machine status
+         */
+        uint32_t rtc_main_state:4;
+    };
+    uint32_t val;
+} rtc_cntl_low_power_st_reg_t;
+
+/** Type of rtc_diag0 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** rtc_low_power_diag1 : RO; bitpos: [31:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t rtc_low_power_diag1:32;
+    };
+    uint32_t val;
+} rtc_cntl_diag0_reg_t;
+
+/** Type of rtc_pad_hold register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** rtc_gpio_pin0_hold : R/W; bitpos: [0]; default: 0;
+         *  Need add description
+         */
+        uint32_t rtc_gpio_pin0_hold:1;
+        /** rtc_gpio_pin1_hold : R/W; bitpos: [1]; default: 0;
+         *  Need add description
+         */
+        uint32_t rtc_gpio_pin1_hold:1;
+        /** rtc_gpio_pin2_hold : R/W; bitpos: [2]; default: 0;
+         *  Need add description
+         */
+        uint32_t rtc_gpio_pin2_hold:1;
+        /** rtc_gpio_pin3_hold : R/W; bitpos: [3]; default: 0;
+         *  Need add description
+         */
+        uint32_t rtc_gpio_pin3_hold:1;
+        /** rtc_gpio_pin4_hold : R/W; bitpos: [4]; default: 0;
+         *  Need add description
+         */
+        uint32_t rtc_gpio_pin4_hold:1;
+        /** rtc_gpio_pin5_hold : R/W; bitpos: [5]; default: 0;
+         *  Need add description
+         */
+        uint32_t rtc_gpio_pin5_hold:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} rtc_cntl_pad_hold_reg_t;
+
+/** Type of dig_pad_hold register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** dig_pad_hold : R/W; bitpos: [31:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t dig_pad_hold:32;
+    };
+    uint32_t val;
+} rtc_cntl_dig_pad_hold_reg_t;
+
+/** Type of dig_pad_hold1 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** dig_pad_hold1 : R/W; bitpos: [8:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t dig_pad_hold1:9;
+        uint32_t reserved_9:23;
+    };
+    uint32_t val;
+} rtc_cntl_dig_pad_hold1_reg_t;
+
+/** Type of rtc_brown_out register
+ *  register description
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:4;
+        /** int_wait : R/W; bitpos: [13:4]; default: 1;
+         *  brown out interrupt wait cycles
+         */
+        uint32_t int_wait:10;
+        /** close_flash_ena : R/W; bitpos: [14]; default: 0;
+         *  enable close flash when brown out happens
+         */
+        uint32_t close_flash_ena:1;
+        /** pd_rf_ena : R/W; bitpos: [15]; default: 0;
+         *  enable power down RF when brown out happens
+         */
+        uint32_t pd_rf_ena:1;
+        /** rst_wait : R/W; bitpos: [25:16]; default: 1023;
+         *  brown out reset wait cycles
+         */
+        uint32_t rst_wait:10;
+        /** rst_ena : R/W; bitpos: [26]; default: 0;
+         *  enable brown out reset
+         */
+        uint32_t rst_ena:1;
+        /** rst_sel : R/W; bitpos: [27]; default: 0;
+         *  1:  4-pos reset,    0:  sys_reset
+         */
+        uint32_t rst_sel:1;
+        /** ana_rst_en : R/W; bitpos: [28]; default: 0;
+         *  Need add description
+         */
+        uint32_t ana_rst_en:1;
+        /** cnt_clr : WO; bitpos: [29]; default: 0;
+         *  clear brown out counter
+         */
+        uint32_t cnt_clr:1;
+        /** ena : R/W; bitpos: [30]; default: 1;
+         *  enable brown out
+         */
+        uint32_t ena:1;
+        /** det : RO; bitpos: [31]; default: 0;
+         *  Need add description
+         */
+        uint32_t det:1;
+    };
+    uint32_t val;
+} rtc_cntl_brown_out_reg_t;
+
+/** Type of rtc_time_low1 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** rtc_timer_value1_low : RO; bitpos: [31:0]; default: 0;
+         *  RTC timer low 32 bits
+         */
+        uint32_t rtc_timer_value1_low:32;
+    };
+    uint32_t val;
+} rtc_cntl_time_low1_reg_t;
+
+/** Type of rtc_time_high1 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** rtc_timer_value1_high : RO; bitpos: [15:0]; default: 0;
+         *  RTC timer high 16 bits
+         */
+        uint32_t rtc_timer_value1_high:16;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} rtc_cntl_time_high1_reg_t;
+
+/** Type of rtc_xtal32k_clk_factor register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** xtal32k_clk_factor : R/W; bitpos: [31:0]; default: 0;
+         *  xtal 32k watch dog backup clock factor
+         */
+        uint32_t xtal32k_clk_factor:32;
+    };
+    uint32_t val;
+} rtc_cntl_xtal32k_clk_factor_reg_t;
+
+/** Type of rtc_xtal32k_conf register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** xtal32k_return_wait : R/W; bitpos: [3:0]; default: 0;
+         *  cycles to wait to return noral xtal 32k
+         */
+        uint32_t xtal32k_return_wait:4;
+        /** xtal32k_restart_wait : R/W; bitpos: [19:4]; default: 0;
+         *  cycles to wait to repower on xtal 32k
+         */
+        uint32_t xtal32k_restart_wait:16;
+        /** xtal32k_wdt_timeout : R/W; bitpos: [27:20]; default: 255;
+         *  If no clock detected for this amount of time, 32k is regarded as dead
+         */
+        uint32_t xtal32k_wdt_timeout:8;
+        /** xtal32k_stable_thres : R/W; bitpos: [31:28]; default: 0;
+         *  if restarted xtal32k period is smaller than this, it is regarded as stable
+         */
+        uint32_t xtal32k_stable_thres:4;
+    };
+    uint32_t val;
+} rtc_cntl_xtal32k_conf_reg_t;
+
+/** Type of rtc_usb_conf register
+ *  register description
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:18;
+        /** io_mux_reset_disable : R/W; bitpos: [18]; default: 0;
+         *  Need add description
+         */
+        uint32_t io_mux_reset_disable:1;
+        uint32_t reserved_19:13;
+    };
+    uint32_t val;
+} rtc_cntl_usb_conf_reg_t;
+
+/** Type of rtc_slp_reject_cause register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** reject_cause : RO; bitpos: [18:0]; default: 0;
+         *  sleep reject cause
+         */
+        uint32_t reject_cause:19;
+        uint32_t reserved_19:13;
+    };
+    uint32_t val;
+} rtc_cntl_slp_reject_cause_reg_t;
+
+/** Type of rtc_option1 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** force_download_boot : R/W; bitpos: [0]; default: 0;
+         *  Need add description
+         */
+        uint32_t force_download_boot:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} rtc_cntl_option1_reg_t;
+
+/** Type of rtc_slp_wakeup_cause register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** wakeup_cause : RO; bitpos: [18:0]; default: 0;
+         *  sleep wakeup cause
+         */
+        uint32_t wakeup_cause:19;
+        uint32_t reserved_19:13;
+    };
+    uint32_t val;
+} rtc_cntl_slp_wakeup_cause_reg_t;
+
+/** Type of rtc_ulp_cp_timer_1 register
+ *  register description
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:8;
+        /** ulp_cp_timer_slp_cycle : R/W; bitpos: [31:8]; default: 200;
+         *  sleep cycles for ULP-coprocessor timer
+         */
+        uint32_t ulp_cp_timer_slp_cycle:24;
+    };
+    uint32_t val;
+} rtc_cntl_ulp_cp_timer_1_reg_t;
+
+/** Type of int_ena_w1ts register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** slp_wakeup_w1ts : WO; bitpos: [0]; default: 0;
+         *  enable sleep wakeup interrupt
+         */
+        uint32_t slp_wakeup_w1ts:1;
+        /** slp_reject_w1ts : WO; bitpos: [1]; default: 0;
+         *  enable sleep reject interrupt
+         */
+        uint32_t slp_reject_w1ts:1;
+        uint32_t reserved_2:1;
+        /** rtc_wdt_w1ts : WO; bitpos: [3]; default: 0;
+         *  enable RTC WDT interrupt
+         */
+        uint32_t rtc_wdt_w1ts:1;
+        uint32_t reserved_4:5;
+        /** w1ts : WO; bitpos: [9]; default: 0;
+         *  enable brown out interrupt
+         */
+        uint32_t w1ts:1;
+        /** rtc_main_timer_w1ts : WO; bitpos: [10]; default: 0;
+         *  enable RTC main timer interrupt
+         */
+        uint32_t rtc_main_timer_w1ts:1;
+        uint32_t reserved_11:4;
+        /** rtc_swd_w1ts : WO; bitpos: [15]; default: 0;
+         *  enable super watch dog interrupt
+         */
+        uint32_t rtc_swd_w1ts:1;
+        /** rtc_xtal32k_dead_w1ts : WO; bitpos: [16]; default: 0;
+         *  enable xtal32k_dead  interrupt
+         */
+        uint32_t rtc_xtal32k_dead_w1ts:1;
+        uint32_t reserved_17:2;
+        /** rtc_glitch_det_w1ts : WO; bitpos: [19]; default: 0;
+         *  enbale gitch det interrupt
+         */
+        uint32_t rtc_glitch_det_w1ts:1;
+        /** rtc_bbpll_cal_w1ts : WO; bitpos: [20]; default: 0;
+         *  Need add description
+         */
+        uint32_t rtc_bbpll_cal_w1ts:1;
+        /** rtc_ble_compare_wake_w1ts : WO; bitpos: [21]; default: 0;
+         *  Need add description
+         */
+        uint32_t rtc_ble_compare_wake_w1ts:1;
+        /** vset_dcdc_done_w1ts : WO; bitpos: [22]; default: 0;
+         *  Need add description
+         */
+        uint32_t vset_dcdc_done_w1ts:1;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} rtc_cntl_int_ena_w1ts_reg_t;
+
+/** Type of int_ena_w1tc register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** slp_wakeup_w1tc : WO; bitpos: [0]; default: 0;
+         *  enable sleep wakeup interrupt
+         */
+        uint32_t slp_wakeup_w1tc:1;
+        /** slp_reject_w1tc : WO; bitpos: [1]; default: 0;
+         *  enable sleep reject interrupt
+         */
+        uint32_t slp_reject_w1tc:1;
+        uint32_t reserved_2:1;
+        /** rtc_wdt_w1tc : WO; bitpos: [3]; default: 0;
+         *  enable RTC WDT interrupt
+         */
+        uint32_t rtc_wdt_w1tc:1;
+        uint32_t reserved_4:5;
+        /** rtc_brown_out_w1tc : WO; bitpos: [9]; default: 0;
+         *  enable brown out interrupt
+         */
+        uint32_t rtc_brown_out_w1tc:1;
+        /** rtc_main_timer_w1tc : WO; bitpos: [10]; default: 0;
+         *  enable RTC main timer interrupt
+         */
+        uint32_t rtc_main_timer_w1tc:1;
+        uint32_t reserved_11:4;
+        /** rtc_swd_w1tc : WO; bitpos: [15]; default: 0;
+         *  enable super watch dog interrupt
+         */
+        uint32_t rtc_swd_w1tc:1;
+        /** rtc_xtal32k_dead_w1tc : WO; bitpos: [16]; default: 0;
+         *  enable xtal32k_dead  interrupt
+         */
+        uint32_t rtc_xtal32k_dead_w1tc:1;
+        uint32_t reserved_17:2;
+        /** rtc_glitch_det_w1tc : WO; bitpos: [19]; default: 0;
+         *  enbale gitch det interrupt
+         */
+        uint32_t rtc_glitch_det_w1tc:1;
+        /** rtc_bbpll_cal_w1tc : WO; bitpos: [20]; default: 0;
+         *  Need add description
+         */
+        uint32_t rtc_bbpll_cal_w1tc:1;
+        /** rtc_ble_compare_wake_w1tc : WO; bitpos: [21]; default: 0;
+         *  Need add description
+         */
+        uint32_t rtc_ble_compare_wake_w1tc:1;
+        /** vset_dcdc_done_w1tc : WO; bitpos: [22]; default: 0;
+         *  Need add description
+         */
+        uint32_t vset_dcdc_done_w1tc:1;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} rtc_cntl_int_ena_w1tc_reg_t;
+
+/** Type of rtc_cntl_retention_ctrl register
+ *  register description
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:17;
+        /** clk_en : R/W; bitpos: [17]; default: 0;
+         *  Need add description
+         */
+        uint32_t clk_en:1;
+        /** retention_clk_sel : R/W; bitpos: [18]; default: 0;
+         *  Need add description
+         */
+        uint32_t retention_clk_sel:1;
+        /** retention_done_wait : R/W; bitpos: [21:19]; default: 2;
+         *  Need add description
+         */
+        uint32_t retention_done_wait:3;
+        /** retention_clkoff_wait : R/W; bitpos: [25:22]; default: 3;
+         *  Need add description
+         */
+        uint32_t retention_clkoff_wait:4;
+        /** retention_en : R/W; bitpos: [26]; default: 0;
+         *  Need add description
+         */
+        uint32_t retention_en:1;
+        /** retention_wait : R/W; bitpos: [31:27]; default: 20;
+         *  wait cycles for rention operation
+         */
+        uint32_t retention_wait:5;
+    };
+    uint32_t val;
+} rtc_cntl_retention_ctrl_reg_t;
+
+/** Type of rtc_cntl_retention_ctrl1 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** retention_link_addr : R/W; bitpos: [26:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t retention_link_addr:27;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} rtc_cntl_retention_ctrl1_reg_t;
+
+/** Type of rtc_fib_sel register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** rtc_fib_sel : R/W; bitpos: [2:0]; default: 7;
+         *  select use analog fib signal
+         */
+        uint32_t rtc_fib_sel:3;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} rtc_cntl_fib_sel_reg_t;
+
+/** Type of rtc_cntl_gpio_wakeup register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** rtc_gpio_wakeup_status : RO; bitpos: [5:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t rtc_gpio_wakeup_status:6;
+        /** rtc_gpio_wakeup_status_clr : R/W; bitpos: [6]; default: 0;
+         *  Need add description
+         */
+        uint32_t rtc_gpio_wakeup_status_clr:1;
+        /** rtc_gpio_pin_clk_gate : R/W; bitpos: [7]; default: 0;
+         *  Need add description
+         */
+        uint32_t rtc_gpio_pin_clk_gate:1;
+        /** rtc_gpio_pin5_int_type : R/W; bitpos: [10:8]; default: 0;
+         *  Need add description
+         */
+        uint32_t rtc_gpio_pin5_int_type:3;
+        /** rtc_gpio_pin4_int_type : R/W; bitpos: [13:11]; default: 0;
+         *  Need add description
+         */
+        uint32_t rtc_gpio_pin4_int_type:3;
+        /** rtc_gpio_pin3_int_type : R/W; bitpos: [16:14]; default: 0;
+         *  Need add description
+         */
+        uint32_t rtc_gpio_pin3_int_type:3;
+        /** rtc_gpio_pin2_int_type : R/W; bitpos: [19:17]; default: 0;
+         *  Need add description
+         */
+        uint32_t rtc_gpio_pin2_int_type:3;
+        /** rtc_gpio_pin1_int_type : R/W; bitpos: [22:20]; default: 0;
+         *  Need add description
+         */
+        uint32_t rtc_gpio_pin1_int_type:3;
+        /** rtc_gpio_pin0_int_type : R/W; bitpos: [25:23]; default: 0;
+         *  Need add description
+         */
+        uint32_t rtc_gpio_pin0_int_type:3;
+        /** rtc_gpio_pin5_wakeup_enable : R/W; bitpos: [26]; default: 0;
+         *  Need add description
+         */
+        uint32_t rtc_gpio_pin5_wakeup_enable:1;
+        /** rtc_gpio_pin4_wakeup_enable : R/W; bitpos: [27]; default: 0;
+         *  Need add description
+         */
+        uint32_t rtc_gpio_pin4_wakeup_enable:1;
+        /** rtc_gpio_pin3_wakeup_enable : R/W; bitpos: [28]; default: 0;
+         *  Need add description
+         */
+        uint32_t rtc_gpio_pin3_wakeup_enable:1;
+        /** rtc_gpio_pin2_wakeup_enable : R/W; bitpos: [29]; default: 0;
+         *  Need add description
+         */
+        uint32_t rtc_gpio_pin2_wakeup_enable:1;
+        /** rtc_gpio_pin1_wakeup_enable : R/W; bitpos: [30]; default: 0;
+         *  Need add description
+         */
+        uint32_t rtc_gpio_pin1_wakeup_enable:1;
+        /** rtc_gpio_pin0_wakeup_enable : R/W; bitpos: [31]; default: 0;
+         *  Need add description
+         */
+        uint32_t rtc_gpio_pin0_wakeup_enable:1;
+    };
+    uint32_t val;
+} rtc_cntl_gpio_wakeup_reg_t;
+
+/** Type of rtc_cntl_dbg_sel register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** rtc_mtdi_enamux : R/W; bitpos: [0]; default: 0;
+         *  Need add description
+         */
+        uint32_t rtc_mtdi_enamux:1;
+        /** rtc_debug_12m_no_gating : R/W; bitpos: [1]; default: 0;
+         *  Need add description
+         */
+        uint32_t rtc_debug_12m_no_gating:1;
+        /** rtc_debug_bit_sel : R/W; bitpos: [6:2]; default: 0;
+         *  Need add description
+         */
+        uint32_t rtc_debug_bit_sel:5;
+        /** rtc_debug_sel0 : R/W; bitpos: [11:7]; default: 0;
+         *  Need add description
+         */
+        uint32_t rtc_debug_sel0:5;
+        /** rtc_debug_sel1 : R/W; bitpos: [16:12]; default: 0;
+         *  Need add description
+         */
+        uint32_t rtc_debug_sel1:5;
+        /** rtc_debug_sel2 : R/W; bitpos: [21:17]; default: 0;
+         *  Need add description
+         */
+        uint32_t rtc_debug_sel2:5;
+        /** rtc_debug_sel3 : R/W; bitpos: [26:22]; default: 0;
+         *  Need add description
+         */
+        uint32_t rtc_debug_sel3:5;
+        /** rtc_debug_sel4 : R/W; bitpos: [31:27]; default: 0;
+         *  Need add description
+         */
+        uint32_t rtc_debug_sel4:5;
+    };
+    uint32_t val;
+} rtc_cntl_dbg_sel_reg_t;
+
+/** Type of rtc_cntl_dbg_map register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** vdd_dig_test : R/W; bitpos: [1:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t vdd_dig_test:2;
+        /** rtc_gpio_pin5_mux_sel : R/W; bitpos: [2]; default: 0;
+         *  Need add description
+         */
+        uint32_t rtc_gpio_pin5_mux_sel:1;
+        /** rtc_gpio_pin4_mux_sel : R/W; bitpos: [3]; default: 0;
+         *  Need add description
+         */
+        uint32_t rtc_gpio_pin4_mux_sel:1;
+        /** rtc_gpio_pin3_mux_sel : R/W; bitpos: [4]; default: 0;
+         *  Need add description
+         */
+        uint32_t rtc_gpio_pin3_mux_sel:1;
+        /** rtc_gpio_pin2_mux_sel : R/W; bitpos: [5]; default: 0;
+         *  Need add description
+         */
+        uint32_t rtc_gpio_pin2_mux_sel:1;
+        /** rtc_gpio_pin1_mux_sel : R/W; bitpos: [6]; default: 0;
+         *  Need add description
+         */
+        uint32_t rtc_gpio_pin1_mux_sel:1;
+        /** rtc_gpio_pin0_mux_sel : R/W; bitpos: [7]; default: 0;
+         *  Need add description
+         */
+        uint32_t rtc_gpio_pin0_mux_sel:1;
+        /** rtc_gpio_pin5_fun_sel : R/W; bitpos: [11:8]; default: 0;
+         *  Need add description
+         */
+        uint32_t rtc_gpio_pin5_fun_sel:4;
+        /** rtc_gpio_pin4_fun_sel : R/W; bitpos: [15:12]; default: 0;
+         *  Need add description
+         */
+        uint32_t rtc_gpio_pin4_fun_sel:4;
+        /** rtc_gpio_pin3_fun_sel : R/W; bitpos: [19:16]; default: 0;
+         *  Need add description
+         */
+        uint32_t rtc_gpio_pin3_fun_sel:4;
+        /** rtc_gpio_pin2_fun_sel : R/W; bitpos: [23:20]; default: 0;
+         *  Need add description
+         */
+        uint32_t rtc_gpio_pin2_fun_sel:4;
+        /** rtc_gpio_pin1_fun_sel : R/W; bitpos: [27:24]; default: 0;
+         *  Need add description
+         */
+        uint32_t rtc_gpio_pin1_fun_sel:4;
+        /** rtc_gpio_pin0_fun_sel : R/W; bitpos: [31:28]; default: 0;
+         *  Need add description
+         */
+        uint32_t rtc_gpio_pin0_fun_sel:4;
+    };
+    uint32_t val;
+} rtc_cntl_dbg_map_reg_t;
+
+/** Type of rtc_cntl_dbg_sar_sel register
+ *  register description
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:27;
+        /** sar_debug_sel : R/W; bitpos: [31:27]; default: 0;
+         *  Need add description
+         */
+        uint32_t sar_debug_sel:5;
+    };
+    uint32_t val;
+} rtc_cntl_dbg_sar_sel_reg_t;
+
+/** Type of rtc_cntl_pg_ctrl register
+ *  register description
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:26;
+        /** power_glitch_dsense : R/W; bitpos: [27:26]; default: 0;
+         *  Need add description
+         */
+        uint32_t power_glitch_dsense:2;
+        /** power_glitch_force_pd : R/W; bitpos: [28]; default: 0;
+         *  Need add description
+         */
+        uint32_t power_glitch_force_pd:1;
+        /** power_glitch_force_pu : R/W; bitpos: [29]; default: 0;
+         *  Need add description
+         */
+        uint32_t power_glitch_force_pu:1;
+        /** power_glitch_efuse_sel : R/W; bitpos: [30]; default: 0;
+         *  Need add description
+         */
+        uint32_t power_glitch_efuse_sel:1;
+        /** power_glitch_en : R/W; bitpos: [31]; default: 0;
+         *  Need add description
+         */
+        uint32_t power_glitch_en:1;
+    };
+    uint32_t val;
+} rtc_cntl_pg_ctrl_reg_t;
+
+/** Type of rtc_cntl_dcdc_ctrl0 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** vset_dcdc_value : RO; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t vset_dcdc_value:5;
+        /** power_good_dcdc : RO; bitpos: [5]; default: 1;
+         *  Need add description
+         */
+        uint32_t power_good_dcdc:1;
+        uint32_t reserved_6:13;
+        /** pmu_mode : R/W; bitpos: [20:19]; default: 0;
+         *  Need add description
+         */
+        uint32_t pmu_mode:2;
+        /** ramplevel_dcdc : R/W; bitpos: [21]; default: 0;
+         *  Need add description
+         */
+        uint32_t ramplevel_dcdc:1;
+        /** ramp_dcdc : R/W; bitpos: [22]; default: 0;
+         *  Need add description
+         */
+        uint32_t ramp_dcdc:1;
+        /** dcm2enb_dcdc : R/W; bitpos: [23]; default: 0;
+         *  Need add description
+         */
+        uint32_t dcm2enb_dcdc:1;
+        /** dcmlevel_dcdc : R/W; bitpos: [25:24]; default: 0;
+         *  Need add description
+         */
+        uint32_t dcmlevel_dcdc:2;
+        /** fsw_dcdc : R/W; bitpos: [28:26]; default: 0;
+         *  Need add description
+         */
+        uint32_t fsw_dcdc:3;
+        /** ccm_dcdc : R/W; bitpos: [29]; default: 0;
+         *  Need add description
+         */
+        uint32_t ccm_dcdc:1;
+        /** sstime_dcdc : R/W; bitpos: [30]; default: 0;
+         *  Need add description
+         */
+        uint32_t sstime_dcdc:1;
+        /** pocpenb_dcdc : R/W; bitpos: [31]; default: 0;
+         *  Need add description
+         */
+        uint32_t pocpenb_dcdc:1;
+    };
+    uint32_t val;
+} rtc_cntl_dcdc_ctrl0_reg_t;
+
+/** Type of rtc_cntl_dcdc_ctrl1 register
+ *  register description
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:23;
+        /** dcdc_mode_slp : R/W; bitpos: [25:23]; default: 4;
+         *  Need add description
+         */
+        uint32_t dcdc_mode_slp:3;
+        /** dcdc_mode_monitor : R/W; bitpos: [28:26]; default: 4;
+         *  Need add description
+         */
+        uint32_t dcdc_mode_monitor:3;
+        /** dcdc_mode_idle : R/W; bitpos: [31:29]; default: 4;
+         *  Need add description
+         */
+        uint32_t dcdc_mode_idle:3;
+    };
+    uint32_t val;
+} rtc_cntl_dcdc_ctrl1_reg_t;
+
+/** Type of rtc_cntl_dcdc_ctrl2 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** vset_dcdc_target_value1 : R/W; bitpos: [4:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t vset_dcdc_target_value1:5;
+        /** vset_dcdc_target_value0 : R/W; bitpos: [9:5]; default: 0;
+         *  Need add description
+         */
+        uint32_t vset_dcdc_target_value0:5;
+        /** vset_dcdc_init_value : R/W; bitpos: [14:10]; default: 0;
+         *  Need add description
+         */
+        uint32_t vset_dcdc_init_value:5;
+        /** vset_dcdc_init : WO; bitpos: [15]; default: 0;
+         *  Need add description
+         */
+        uint32_t vset_dcdc_init:1;
+        /** vset_dcdc_fix : R/W; bitpos: [16]; default: 1;
+         *  Need add description
+         */
+        uint32_t vset_dcdc_fix:1;
+        /** vset_dcdc_step : R/W; bitpos: [21:17]; default: 0;
+         *  Need add description
+         */
+        uint32_t vset_dcdc_step:5;
+        /** vset_dcdc_gap : R/W; bitpos: [26:22]; default: 0;
+         *  Need add description
+         */
+        uint32_t vset_dcdc_gap:5;
+        /** vset_dcdc_sel_hw_sw : R/W; bitpos: [27]; default: 0;
+         *  Need add description
+         */
+        uint32_t vset_dcdc_sel_hw_sw:1;
+        /** vset_dcdc_sw_sel : R/W; bitpos: [28]; default: 0;
+         *  Need add description
+         */
+        uint32_t vset_dcdc_sw_sel:1;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} rtc_cntl_dcdc_ctrl2_reg_t;
+
+/** Type of rtc_cntl_rc32k_ctrl register
+ *  register description
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:21;
+        /** rc32k_dfreq : R/W; bitpos: [30:21]; default: 511;
+         *  Need add description
+         */
+        uint32_t rc32k_dfreq:10;
+        /** rc32k_xpd : R/W; bitpos: [31]; default: 0;
+         *  Need add description
+         */
+        uint32_t rc32k_xpd:1;
+    };
+    uint32_t val;
+} rtc_cntl_rc32k_ctrl_reg_t;
+
+/** Type of rtc_cntl_pll8m register
+ *  register description
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:30;
+        /** ckref_pll8m_sel : R/W; bitpos: [30]; default: 0;
+         *  Need add description
+         */
+        uint32_t ckref_pll8m_sel:1;
+        /** xpd_pll8m : R/W; bitpos: [31]; default: 0;
+         *  Need add description
+         */
+        uint32_t xpd_pll8m:1;
+    };
+    uint32_t val;
+} rtc_cntl_pll8m_reg_t;
+
+/** Type of rtc_cntl_date register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** rtc_cntl_date : R/W; bitpos: [27:0]; default: 34640480;
+         *  Need add description
+         */
+        uint32_t rtc_cntl_date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} rtc_cntl_date_reg_t;
+
+
+typedef struct {
+    volatile rtc_cntl_options0_reg_t options0;
+    volatile rtc_cntl_slp_timer0_reg_t slp_timer0;
+    volatile rtc_cntl_slp_timer1_reg_t slp_timer1;
+    volatile rtc_cntl_time_update_reg_t time_update;
+    volatile rtc_cntl_time_low0_reg_t time_low0;
+    volatile rtc_cntl_time_high0_reg_t time_high0;
+    volatile rtc_cntl_state0_reg_t state0;
+    volatile rtc_cntl_timer1_reg_t timer1;
+    volatile rtc_cntl_timer2_reg_t timer2;
+    volatile rtc_cntl_timer3_reg_t timer3;
+    volatile rtc_cntl_timer4_reg_t timer4;
+    volatile rtc_cntl_timer5_reg_t timer5;
+    volatile rtc_cntl_timer6_reg_t timer6;
+    volatile rtc_cntl_ana_conf_reg_t ana_conf;
+    volatile rtc_cntl_reset_state_reg_t reset_state;
+    volatile rtc_cntl_wakeup_state_reg_t wakeup_state;
+    volatile rtc_cntl_int_ena_reg_t int_ena;
+    volatile rtc_cntl_int_raw_reg_t int_raw;
+    volatile rtc_cntl_int_st_reg_t int_st;
+    volatile rtc_cntl_int_clr_reg_t int_clr;
+    volatile rtc_cntl_store_reg_t store[4];
+    volatile rtc_cntl_ext_xtl_conf_reg_t ext_xtl_conf;
+    volatile rtc_cntl_ext_wakeup_conf_reg_t ext_wakeup_conf;
+    volatile rtc_cntl_slp_reject_conf_reg_t slp_reject_conf;
+    volatile rtc_cntl_cpu_period_conf_reg_t cpu_period_conf;
+    volatile rtc_cntl_clk_conf_reg_t clk_conf;
+    volatile rtc_cntl_slow_clk_conf_reg_t slow_clk_conf;
+    volatile rtc_cntl_sdio_conf_reg_t sdio_conf;
+    volatile rtc_cntl_bias_conf_reg_t bias_conf;
+    volatile rtc_cntl_regulator_reg_t regulator;
+    volatile rtc_cntl_regulator0_dbias_reg_t regulator0_dbias;
+    volatile rtc_cntl_regulator1_dbias_reg_t regulator1_dbias;
+    volatile rtc_cntl_dig_regulator_reg_t dig_regulator;
+    volatile rtc_cntl_dig_regulator_drvb_reg_t dig_regulator_drvb;
+    volatile rtc_cntl_dig_regulator0_dbias_reg_t dig_regulator0_dbias;
+    volatile rtc_cntl_dig_regulator1_dbias_reg_t dig_regulator1_dbias;
+    volatile rtc_cntl_pwc_reg_t rtc_pwc;
+    volatile rtc_cntl_dig_pwc_reg_t dig_pwc;
+    volatile rtc_cntl_dig_power_slave0_pd_reg_t dig_power_slave0_pd;
+    volatile rtc_cntl_dig_power_slave1_pd_reg_t dig_power_slave1_pd;
+    volatile rtc_cntl_dig_power_slave0_fpu_reg_t dig_power_slave0_fpu;
+    volatile rtc_cntl_dig_power_slave1_fpu_reg_t dig_power_slave1_fpu;
+    volatile rtc_cntl_dig_iso_reg_t dig_iso;
+    volatile rtc_cntl_wdtconfig0_reg_t wdt_config0;
+    union  {
+        volatile rtc_cntl_wdtconfig1_reg_t wdtconfig1;
+        volatile uint32_t wdt_config1;
+    };
+    union  {
+        volatile rtc_cntl_wdtconfig2_reg_t wdtconfig2;
+        volatile uint32_t wdt_config2;
+    };
+    union  {
+        volatile rtc_cntl_wdtconfig3_reg_t wdtconfig3;
+        volatile uint32_t wdt_config3;
+    };
+    union  {
+        volatile rtc_cntl_wdtconfig4_reg_t wdtconfig4;
+        volatile uint32_t wdt_config4;
+    };
+    volatile rtc_cntl_wdtfeed_reg_t wdt_feed;
+    union {
+        volatile rtc_cntl_wdtwprotect_reg_t wdtwprotect;
+        volatile uint32_t wdt_wprotect;
+    };
+    volatile rtc_cntl_wdtreset_chip_reg_t wdtreset_chip;
+    volatile rtc_cntl_swd_conf_reg_t swd_conf;
+    volatile rtc_cntl_swd_wprotect_reg_t swd_wprotect;
+    volatile rtc_cntl_sw_cpu_stall_reg_t sw_cpu_stall;
+    volatile rtc_cntl_store_reg_t store4[4];
+    volatile rtc_cntl_low_power_st_reg_t low_power_st;
+    volatile rtc_cntl_diag0_reg_t diag0;
+    volatile rtc_cntl_pad_hold_reg_t pad_hold;
+    volatile rtc_cntl_dig_pad_hold_reg_t dig_pad_hold;
+    volatile rtc_cntl_dig_pad_hold1_reg_t dig_pad_hold1;
+    volatile rtc_cntl_brown_out_reg_t brown_out;
+    volatile rtc_cntl_time_low1_reg_t time_low1;
+    volatile rtc_cntl_time_high1_reg_t time_high1;
+    volatile rtc_cntl_xtal32k_clk_factor_reg_t xtal32k_clk_factor;
+    volatile rtc_cntl_xtal32k_conf_reg_t xtal32k_conf;
+    volatile rtc_cntl_usb_conf_reg_t usb_conf;
+    volatile rtc_cntl_slp_reject_cause_reg_t slp_reject_cause;
+    volatile rtc_cntl_option1_reg_t option1;
+    volatile rtc_cntl_slp_wakeup_cause_reg_t slp_wakeup_cause;
+    volatile rtc_cntl_ulp_cp_timer_1_reg_t ulp_cp_timer_1;
+    volatile rtc_cntl_int_ena_w1ts_reg_t int_ena_w1ts;
+    volatile rtc_cntl_int_ena_w1tc_reg_t int_ena_w1tc;
+    volatile rtc_cntl_retention_ctrl_reg_t retention_ctrl;
+    volatile rtc_cntl_retention_ctrl1_reg_t retention_ctrl1;
+    volatile rtc_cntl_fib_sel_reg_t fib_sel;
+    volatile rtc_cntl_gpio_wakeup_reg_t gpio_wakeup;
+    volatile rtc_cntl_dbg_sel_reg_t dbg_sel;
+    volatile rtc_cntl_dbg_map_reg_t dbg_map;
+    volatile rtc_cntl_dbg_sar_sel_reg_t dbg_sar_sel;
+    volatile rtc_cntl_pg_ctrl_reg_t pg_ctrl;
+    volatile rtc_cntl_dcdc_ctrl0_reg_t dcdc_ctrl0;
+    volatile rtc_cntl_dcdc_ctrl1_reg_t dcdc_ctrl1;
+    volatile rtc_cntl_dcdc_ctrl2_reg_t dcdc_ctrl2;
+    volatile rtc_cntl_rc32k_ctrl_reg_t rc32k_ctrl;
+    volatile rtc_cntl_pll8m_reg_t pll8m;
+    uint32_t reserved_16c[36];
+    volatile rtc_cntl_date_reg_t date;
 } rtc_cntl_dev_t;
+
 extern rtc_cntl_dev_t RTCCNTL;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(rtc_cntl_dev_t) == 0x200, "Invalid size of rtc_cntl_dev_t structure");
+#endif
+
 #ifdef __cplusplus
 }
 #endif
-
-
-
-#endif /*_SOC_RTC_CNTL_STRUCT_H_ */

components/soc/esp32h2/include/rev2/soc/sensitive_reg.h

@@ -1,2532 +1,3405 @@
-/*
- * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
+/**
+ * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
  *
- * SPDX-License-Identifier: Apache-2.0
+ *  SPDX-License-Identifier: Apache-2.0
  */
-#ifndef _SOC_SENSITIVE_REG_H_
-#define _SOC_SENSITIVE_REG_H_
+#pragma once
 
+#include <stdint.h>
 #include "soc/soc.h"
-
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-#define SENSITIVE_ROM_TABLE_LOCK_REG          (DR_REG_SENSITIVE_BASE + 0x0)
-/* SENSITIVE_ROM_TABLE_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Need add description.*/
+/** SENSITIVE_ROM_TABLE_LOCK_REG register
+ *  register description
+ */
+#define SENSITIVE_ROM_TABLE_LOCK_REG (DR_REG_SENSITIVE_BASE + 0x0)
+/** SENSITIVE_ROM_TABLE_LOCK : R/W; bitpos: [0]; default: 0;
+ *  Need add description
+ */
 #define SENSITIVE_ROM_TABLE_LOCK    (BIT(0))
-#define SENSITIVE_ROM_TABLE_LOCK_M  (BIT(0))
-#define SENSITIVE_ROM_TABLE_LOCK_V  0x1
+#define SENSITIVE_ROM_TABLE_LOCK_M  (SENSITIVE_ROM_TABLE_LOCK_V << SENSITIVE_ROM_TABLE_LOCK_S)
+#define SENSITIVE_ROM_TABLE_LOCK_V  0x00000001U
 #define SENSITIVE_ROM_TABLE_LOCK_S  0
 
-#define SENSITIVE_ROM_TABLE_REG          (DR_REG_SENSITIVE_BASE + 0x4)
-/* SENSITIVE_ROM_TABLE : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: Need add description.*/
-#define SENSITIVE_ROM_TABLE    0xFFFFFFFF
-#define SENSITIVE_ROM_TABLE_M  ((SENSITIVE_ROM_TABLE_V)<<(SENSITIVE_ROM_TABLE_S))
-#define SENSITIVE_ROM_TABLE_V  0xFFFFFFFF
+/** SENSITIVE_ROM_TABLE_REG register
+ *  register description
+ */
+#define SENSITIVE_ROM_TABLE_REG (DR_REG_SENSITIVE_BASE + 0x4)
+/** SENSITIVE_ROM_TABLE : R/W; bitpos: [31:0]; default: 0;
+ *  Need add description
+ */
+#define SENSITIVE_ROM_TABLE    0xFFFFFFFFU
+#define SENSITIVE_ROM_TABLE_M  (SENSITIVE_ROM_TABLE_V << SENSITIVE_ROM_TABLE_S)
+#define SENSITIVE_ROM_TABLE_V  0xFFFFFFFFU
 #define SENSITIVE_ROM_TABLE_S  0
 
-#define SENSITIVE_PRIVILEGE_MODE_SEL_LOCK_REG          (DR_REG_SENSITIVE_BASE + 0x8)
-/* SENSITIVE_PRIVILEGE_MODE_SEL_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Need add description.*/
+/** SENSITIVE_PRIVILEGE_MODE_SEL_LOCK_REG register
+ *  register description
+ */
+#define SENSITIVE_PRIVILEGE_MODE_SEL_LOCK_REG (DR_REG_SENSITIVE_BASE + 0x8)
+/** SENSITIVE_PRIVILEGE_MODE_SEL_LOCK : R/W; bitpos: [0]; default: 0;
+ *  Need add description
+ */
 #define SENSITIVE_PRIVILEGE_MODE_SEL_LOCK    (BIT(0))
-#define SENSITIVE_PRIVILEGE_MODE_SEL_LOCK_M  (BIT(0))
-#define SENSITIVE_PRIVILEGE_MODE_SEL_LOCK_V  0x1
+#define SENSITIVE_PRIVILEGE_MODE_SEL_LOCK_M  (SENSITIVE_PRIVILEGE_MODE_SEL_LOCK_V << SENSITIVE_PRIVILEGE_MODE_SEL_LOCK_S)
+#define SENSITIVE_PRIVILEGE_MODE_SEL_LOCK_V  0x00000001U
 #define SENSITIVE_PRIVILEGE_MODE_SEL_LOCK_S  0
 
-#define SENSITIVE_PRIVILEGE_MODE_SEL_REG          (DR_REG_SENSITIVE_BASE + 0xC)
-/* SENSITIVE_PRIVILEGE_MODE_SEL : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Need add description.*/
+/** SENSITIVE_PRIVILEGE_MODE_SEL_REG register
+ *  register description
+ */
+#define SENSITIVE_PRIVILEGE_MODE_SEL_REG (DR_REG_SENSITIVE_BASE + 0xc)
+/** SENSITIVE_PRIVILEGE_MODE_SEL : R/W; bitpos: [0]; default: 0;
+ *  Need add description
+ */
 #define SENSITIVE_PRIVILEGE_MODE_SEL    (BIT(0))
-#define SENSITIVE_PRIVILEGE_MODE_SEL_M  (BIT(0))
-#define SENSITIVE_PRIVILEGE_MODE_SEL_V  0x1
+#define SENSITIVE_PRIVILEGE_MODE_SEL_M  (SENSITIVE_PRIVILEGE_MODE_SEL_V << SENSITIVE_PRIVILEGE_MODE_SEL_S)
+#define SENSITIVE_PRIVILEGE_MODE_SEL_V  0x00000001U
 #define SENSITIVE_PRIVILEGE_MODE_SEL_S  0
 
-#define SENSITIVE_APB_PERIPHERAL_ACCESS_0_REG          (DR_REG_SENSITIVE_BASE + 0x10)
-/* SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Need add description.*/
+/** SENSITIVE_APB_PERIPHERAL_ACCESS_0_REG register
+ *  register description
+ */
+#define SENSITIVE_APB_PERIPHERAL_ACCESS_0_REG (DR_REG_SENSITIVE_BASE + 0x10)
+/** SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK : R/W; bitpos: [0]; default: 0;
+ *  Need add description
+ */
 #define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK    (BIT(0))
-#define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK_M  (BIT(0))
-#define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK_V  0x1
+#define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK_M  (SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK_V << SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK_S)
+#define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK_V  0x00000001U
 #define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK_S  0
 
-#define SENSITIVE_APB_PERIPHERAL_ACCESS_1_REG          (DR_REG_SENSITIVE_BASE + 0x14)
-/* SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: Need add description.*/
+/** SENSITIVE_APB_PERIPHERAL_ACCESS_1_REG register
+ *  register description
+ */
+#define SENSITIVE_APB_PERIPHERAL_ACCESS_1_REG (DR_REG_SENSITIVE_BASE + 0x14)
+/** SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST : R/W; bitpos: [0]; default: 1;
+ *  Need add description
+ */
 #define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST    (BIT(0))
-#define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST_M  (BIT(0))
-#define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST_V  0x1
+#define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST_M  (SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST_V << SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST_S)
+#define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST_V  0x00000001U
 #define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST_S  0
 
-#define SENSITIVE_INTERNAL_SRAM_USAGE_0_REG          (DR_REG_SENSITIVE_BASE + 0x18)
-/* SENSITIVE_INTERNAL_SRAM_USAGE_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Need add description.*/
+/** SENSITIVE_INTERNAL_SRAM_USAGE_0_REG register
+ *  register description
+ */
+#define SENSITIVE_INTERNAL_SRAM_USAGE_0_REG (DR_REG_SENSITIVE_BASE + 0x18)
+/** SENSITIVE_INTERNAL_SRAM_USAGE_LOCK : R/W; bitpos: [0]; default: 0;
+ *  Need add description
+ */
 #define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK    (BIT(0))
-#define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK_M  (BIT(0))
-#define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK_V  0x1
+#define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK_M  (SENSITIVE_INTERNAL_SRAM_USAGE_LOCK_V << SENSITIVE_INTERNAL_SRAM_USAGE_LOCK_S)
+#define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK_V  0x00000001U
 #define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK_S  0
 
-#define SENSITIVE_INTERNAL_SRAM_USAGE_1_REG          (DR_REG_SENSITIVE_BASE + 0x1C)
-/* SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM : R/W ;bitpos:[3:1] ;default: 3'b111 ; */
-/*description: Need add description.*/
-#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM    0x00000007
-#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM_M  ((SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM_V)<<(SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM_S))
-#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM_V  0x7
-#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM_S  1
-/* SENSITIVE_INTERNAL_SRAM_USAGE_CPU_CACHE : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: Need add description.*/
+/** SENSITIVE_INTERNAL_SRAM_USAGE_1_REG register
+ *  register description
+ */
+#define SENSITIVE_INTERNAL_SRAM_USAGE_1_REG (DR_REG_SENSITIVE_BASE + 0x1c)
+/** SENSITIVE_INTERNAL_SRAM_USAGE_CPU_CACHE : R/W; bitpos: [0]; default: 1;
+ *  Need add description
+ */
 #define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_CACHE    (BIT(0))
-#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_CACHE_M  (BIT(0))
-#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_CACHE_V  0x1
+#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_CACHE_M  (SENSITIVE_INTERNAL_SRAM_USAGE_CPU_CACHE_V << SENSITIVE_INTERNAL_SRAM_USAGE_CPU_CACHE_S)
+#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_CACHE_V  0x00000001U
 #define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_CACHE_S  0
+/** SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM : R/W; bitpos: [3:1]; default: 7;
+ *  Need add description
+ */
+#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM    0x00000007U
+#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM_M  (SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM_V << SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM_S)
+#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM_V  0x00000007U
+#define SENSITIVE_INTERNAL_SRAM_USAGE_CPU_SRAM_S  1
 
-#define SENSITIVE_INTERNAL_SRAM_USAGE_3_REG          (DR_REG_SENSITIVE_BASE + 0x20)
-/* SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP : R/W ;bitpos:[3] ;default: 1'b0 ; */
-/*description: Need add description.*/
+/** SENSITIVE_INTERNAL_SRAM_USAGE_3_REG register
+ *  register description
+ */
+#define SENSITIVE_INTERNAL_SRAM_USAGE_3_REG (DR_REG_SENSITIVE_BASE + 0x20)
+/** SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM : R/W; bitpos: [2:0]; default: 0;
+ *  Need add description
+ */
+#define SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM    0x00000007U
+#define SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM_M  (SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM_V << SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM_S)
+#define SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM_V  0x00000007U
+#define SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM_S  0
+/** SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP : R/W; bitpos: [3]; default: 0;
+ *  Need add description
+ */
 #define SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP    (BIT(3))
-#define SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP_M  (BIT(3))
-#define SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP_V  0x1
+#define SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP_M  (SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP_V << SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP_S)
+#define SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP_V  0x00000001U
 #define SENSITIVE_INTERNAL_SRAM_ALLOC_MAC_DUMP_S  3
-/* SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM : R/W ;bitpos:[2:0] ;default: 3'b0 ; */
-/*description: Need add description.*/
-#define SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM    0x00000007
-#define SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM_M  ((SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM_V)<<(SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM_S))
-#define SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM_V  0x7
-#define SENSITIVE_INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM_S  0
 
-#define SENSITIVE_INTERNAL_SRAM_USAGE_4_REG          (DR_REG_SENSITIVE_BASE + 0x24)
-/* SENSITIVE_INTERNAL_SRAM_USAGE_LOG_SRAM : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Need add description.*/
+/** SENSITIVE_INTERNAL_SRAM_USAGE_4_REG register
+ *  register description
+ */
+#define SENSITIVE_INTERNAL_SRAM_USAGE_4_REG (DR_REG_SENSITIVE_BASE + 0x24)
+/** SENSITIVE_INTERNAL_SRAM_USAGE_LOG_SRAM : R/W; bitpos: [0]; default: 0;
+ *  Need add description
+ */
 #define SENSITIVE_INTERNAL_SRAM_USAGE_LOG_SRAM    (BIT(0))
-#define SENSITIVE_INTERNAL_SRAM_USAGE_LOG_SRAM_M  (BIT(0))
-#define SENSITIVE_INTERNAL_SRAM_USAGE_LOG_SRAM_V  0x1
+#define SENSITIVE_INTERNAL_SRAM_USAGE_LOG_SRAM_M  (SENSITIVE_INTERNAL_SRAM_USAGE_LOG_SRAM_V << SENSITIVE_INTERNAL_SRAM_USAGE_LOG_SRAM_S)
+#define SENSITIVE_INTERNAL_SRAM_USAGE_LOG_SRAM_V  0x00000001U
 #define SENSITIVE_INTERNAL_SRAM_USAGE_LOG_SRAM_S  0
 
-#define SENSITIVE_CACHE_TAG_ACCESS_0_REG          (DR_REG_SENSITIVE_BASE + 0x28)
-/* SENSITIVE_CACHE_TAG_ACCESS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Need add description.*/
+/** SENSITIVE_CACHE_TAG_ACCESS_0_REG register
+ *  register description
+ */
+#define SENSITIVE_CACHE_TAG_ACCESS_0_REG (DR_REG_SENSITIVE_BASE + 0x28)
+/** SENSITIVE_CACHE_TAG_ACCESS_LOCK : R/W; bitpos: [0]; default: 0;
+ *  Need add description
+ */
 #define SENSITIVE_CACHE_TAG_ACCESS_LOCK    (BIT(0))
-#define SENSITIVE_CACHE_TAG_ACCESS_LOCK_M  (BIT(0))
-#define SENSITIVE_CACHE_TAG_ACCESS_LOCK_V  0x1
+#define SENSITIVE_CACHE_TAG_ACCESS_LOCK_M  (SENSITIVE_CACHE_TAG_ACCESS_LOCK_V << SENSITIVE_CACHE_TAG_ACCESS_LOCK_S)
+#define SENSITIVE_CACHE_TAG_ACCESS_LOCK_V  0x00000001U
 #define SENSITIVE_CACHE_TAG_ACCESS_LOCK_S  0
 
-#define SENSITIVE_CACHE_TAG_ACCESS_1_REG          (DR_REG_SENSITIVE_BASE + 0x2C)
-/* SENSITIVE_PRO_D_TAG_WR_ACS : R/W ;bitpos:[3] ;default: 1'b1 ; */
-/*description: Need add description.*/
-#define SENSITIVE_PRO_D_TAG_WR_ACS    (BIT(3))
-#define SENSITIVE_PRO_D_TAG_WR_ACS_M  (BIT(3))
-#define SENSITIVE_PRO_D_TAG_WR_ACS_V  0x1
-#define SENSITIVE_PRO_D_TAG_WR_ACS_S  3
-/* SENSITIVE_PRO_D_TAG_RD_ACS : R/W ;bitpos:[2] ;default: 1'b1 ; */
-/*description: Need add description.*/
-#define SENSITIVE_PRO_D_TAG_RD_ACS    (BIT(2))
-#define SENSITIVE_PRO_D_TAG_RD_ACS_M  (BIT(2))
-#define SENSITIVE_PRO_D_TAG_RD_ACS_V  0x1
-#define SENSITIVE_PRO_D_TAG_RD_ACS_S  2
-/* SENSITIVE_PRO_I_TAG_WR_ACS : R/W ;bitpos:[1] ;default: 1'b1 ; */
-/*description: Need add description.*/
-#define SENSITIVE_PRO_I_TAG_WR_ACS    (BIT(1))
-#define SENSITIVE_PRO_I_TAG_WR_ACS_M  (BIT(1))
-#define SENSITIVE_PRO_I_TAG_WR_ACS_V  0x1
-#define SENSITIVE_PRO_I_TAG_WR_ACS_S  1
-/* SENSITIVE_PRO_I_TAG_RD_ACS : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: Need add description.*/
+/** SENSITIVE_CACHE_TAG_ACCESS_1_REG register
+ *  register description
+ */
+#define SENSITIVE_CACHE_TAG_ACCESS_1_REG (DR_REG_SENSITIVE_BASE + 0x2c)
+/** SENSITIVE_PRO_I_TAG_RD_ACS : R/W; bitpos: [0]; default: 1;
+ *  Need add description
+ */
 #define SENSITIVE_PRO_I_TAG_RD_ACS    (BIT(0))
-#define SENSITIVE_PRO_I_TAG_RD_ACS_M  (BIT(0))
-#define SENSITIVE_PRO_I_TAG_RD_ACS_V  0x1
+#define SENSITIVE_PRO_I_TAG_RD_ACS_M  (SENSITIVE_PRO_I_TAG_RD_ACS_V << SENSITIVE_PRO_I_TAG_RD_ACS_S)
+#define SENSITIVE_PRO_I_TAG_RD_ACS_V  0x00000001U
 #define SENSITIVE_PRO_I_TAG_RD_ACS_S  0
+/** SENSITIVE_PRO_I_TAG_WR_ACS : R/W; bitpos: [1]; default: 1;
+ *  Need add description
+ */
+#define SENSITIVE_PRO_I_TAG_WR_ACS    (BIT(1))
+#define SENSITIVE_PRO_I_TAG_WR_ACS_M  (SENSITIVE_PRO_I_TAG_WR_ACS_V << SENSITIVE_PRO_I_TAG_WR_ACS_S)
+#define SENSITIVE_PRO_I_TAG_WR_ACS_V  0x00000001U
+#define SENSITIVE_PRO_I_TAG_WR_ACS_S  1
+/** SENSITIVE_PRO_D_TAG_RD_ACS : R/W; bitpos: [2]; default: 1;
+ *  Need add description
+ */
+#define SENSITIVE_PRO_D_TAG_RD_ACS    (BIT(2))
+#define SENSITIVE_PRO_D_TAG_RD_ACS_M  (SENSITIVE_PRO_D_TAG_RD_ACS_V << SENSITIVE_PRO_D_TAG_RD_ACS_S)
+#define SENSITIVE_PRO_D_TAG_RD_ACS_V  0x00000001U
+#define SENSITIVE_PRO_D_TAG_RD_ACS_S  2
+/** SENSITIVE_PRO_D_TAG_WR_ACS : R/W; bitpos: [3]; default: 1;
+ *  Need add description
+ */
+#define SENSITIVE_PRO_D_TAG_WR_ACS    (BIT(3))
+#define SENSITIVE_PRO_D_TAG_WR_ACS_M  (SENSITIVE_PRO_D_TAG_WR_ACS_V << SENSITIVE_PRO_D_TAG_WR_ACS_S)
+#define SENSITIVE_PRO_D_TAG_WR_ACS_V  0x00000001U
+#define SENSITIVE_PRO_D_TAG_WR_ACS_S  3
 
-#define SENSITIVE_CACHE_MMU_ACCESS_0_REG          (DR_REG_SENSITIVE_BASE + 0x30)
-/* SENSITIVE_CACHE_MMU_ACCESS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Need add description.*/
+/** SENSITIVE_CACHE_MMU_ACCESS_0_REG register
+ *  register description
+ */
+#define SENSITIVE_CACHE_MMU_ACCESS_0_REG (DR_REG_SENSITIVE_BASE + 0x30)
+/** SENSITIVE_CACHE_MMU_ACCESS_LOCK : R/W; bitpos: [0]; default: 0;
+ *  Need add description
+ */
 #define SENSITIVE_CACHE_MMU_ACCESS_LOCK    (BIT(0))
-#define SENSITIVE_CACHE_MMU_ACCESS_LOCK_M  (BIT(0))
-#define SENSITIVE_CACHE_MMU_ACCESS_LOCK_V  0x1
+#define SENSITIVE_CACHE_MMU_ACCESS_LOCK_M  (SENSITIVE_CACHE_MMU_ACCESS_LOCK_V << SENSITIVE_CACHE_MMU_ACCESS_LOCK_S)
+#define SENSITIVE_CACHE_MMU_ACCESS_LOCK_V  0x00000001U
 #define SENSITIVE_CACHE_MMU_ACCESS_LOCK_S  0
 
-#define SENSITIVE_CACHE_MMU_ACCESS_1_REG          (DR_REG_SENSITIVE_BASE + 0x34)
-/* SENSITIVE_PRO_MMU_WR_ACS : R/W ;bitpos:[1] ;default: 1'b1 ; */
-/*description: Need add description.*/
-#define SENSITIVE_PRO_MMU_WR_ACS    (BIT(1))
-#define SENSITIVE_PRO_MMU_WR_ACS_M  (BIT(1))
-#define SENSITIVE_PRO_MMU_WR_ACS_V  0x1
-#define SENSITIVE_PRO_MMU_WR_ACS_S  1
-/* SENSITIVE_PRO_MMU_RD_ACS : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: Need add description.*/
+/** SENSITIVE_CACHE_MMU_ACCESS_1_REG register
+ *  register description
+ */
+#define SENSITIVE_CACHE_MMU_ACCESS_1_REG (DR_REG_SENSITIVE_BASE + 0x34)
+/** SENSITIVE_PRO_MMU_RD_ACS : R/W; bitpos: [0]; default: 1;
+ *  Need add description
+ */
 #define SENSITIVE_PRO_MMU_RD_ACS    (BIT(0))
-#define SENSITIVE_PRO_MMU_RD_ACS_M  (BIT(0))
-#define SENSITIVE_PRO_MMU_RD_ACS_V  0x1
+#define SENSITIVE_PRO_MMU_RD_ACS_M  (SENSITIVE_PRO_MMU_RD_ACS_V << SENSITIVE_PRO_MMU_RD_ACS_S)
+#define SENSITIVE_PRO_MMU_RD_ACS_V  0x00000001U
 #define SENSITIVE_PRO_MMU_RD_ACS_S  0
+/** SENSITIVE_PRO_MMU_WR_ACS : R/W; bitpos: [1]; default: 1;
+ *  Need add description
+ */
+#define SENSITIVE_PRO_MMU_WR_ACS    (BIT(1))
+#define SENSITIVE_PRO_MMU_WR_ACS_M  (SENSITIVE_PRO_MMU_WR_ACS_V << SENSITIVE_PRO_MMU_WR_ACS_S)
+#define SENSITIVE_PRO_MMU_WR_ACS_V  0x00000001U
+#define SENSITIVE_PRO_MMU_WR_ACS_S  1
 
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x38)
-/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Need add description.*/
+/** SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_0_REG register
+ *  register description
+ */
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x38)
+/** SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK : R/W; bitpos: [0]; default: 0;
+ *  Need add description
+ */
 #define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK    (BIT(0))
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK_M  (BIT(0))
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK_V  0x1
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK_M  (SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK_V << SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK_S)
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK_V  0x00000001U
 #define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK_S  0
 
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x3C)
-/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3    0x00000003
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M  ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S))
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V  0x3
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S  18
-/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2    0x00000003
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M  ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S))
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V  0x3
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S  16
-/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1    0x00000003
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M  ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S))
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V  0x3
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S  14
-/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0    0x00000003
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M  ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S))
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V  0x3
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S  12
-/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3    0x00000003
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M  ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S))
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V  0x3
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S  6
-/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2    0x00000003
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M  ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S))
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V  0x3
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S  4
-/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1    0x00000003
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M  ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S))
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V  0x3
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S  2
-/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0    0x00000003
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M  ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S))
-#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V  0x3
+/** SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_1_REG register
+ *  register description
+ */
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x3c)
+/** SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W; bitpos: [1:0];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0    0x00000003U
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M  (SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V << SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V  0x00000003U
 #define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S  0
+/** SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W; bitpos: [3:2];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1    0x00000003U
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M  (SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V << SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V  0x00000003U
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S  2
+/** SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W; bitpos: [5:4];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2    0x00000003U
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M  (SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V << SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V  0x00000003U
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S  4
+/** SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W; bitpos: [7:6];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3    0x00000003U
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M  (SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V << SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V  0x00000003U
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S  6
+/** SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W; bitpos: [13:12];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0    0x00000003U
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M  (SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V << SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V  0x00000003U
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S  12
+/** SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W; bitpos: [15:14];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1    0x00000003U
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M  (SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V << SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V  0x00000003U
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S  14
+/** SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W; bitpos: [17:16];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2    0x00000003U
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M  (SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V << SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V  0x00000003U
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S  16
+/** SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W; bitpos: [19:18];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3    0x00000003U
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M  (SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V << SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V  0x00000003U
+#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S  18
 
-#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x40)
-/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Need add description.*/
+/** SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_0_REG register
+ *  register description
+ */
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x40)
+/** SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_LOCK : R/W; bitpos: [0]; default: 0;
+ *  Need add description
+ */
 #define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_LOCK    (BIT(0))
-#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_LOCK_M  (BIT(0))
-#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_LOCK_V  0x1
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_LOCK_M  (SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_LOCK_V << SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_LOCK_S)
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_LOCK_V  0x00000001U
 #define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_LOCK_S  0
 
-#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x44)
-/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3    0x00000003
-#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M  ((SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S))
-#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V  0x3
-#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S  18
-/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2    0x00000003
-#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M  ((SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S))
-#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V  0x3
-#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S  16
-/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1    0x00000003
-#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M  ((SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S))
-#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V  0x3
-#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S  14
-/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0    0x00000003
-#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M  ((SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S))
-#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V  0x3
-#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S  12
-/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3    0x00000003
-#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M  ((SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S))
-#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V  0x3
-#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S  6
-/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2    0x00000003
-#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M  ((SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S))
-#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V  0x3
-#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S  4
-/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1    0x00000003
-#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M  ((SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S))
-#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V  0x3
-#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S  2
-/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0    0x00000003
-#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M  ((SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S))
-#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V  0x3
+/** SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1_REG register
+ *  register description
+ */
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x44)
+/** SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W; bitpos: [1:0];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0    0x00000003U
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M  (SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V << SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V  0x00000003U
 #define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S  0
+/** SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W; bitpos: [3:2];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1    0x00000003U
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M  (SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V << SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V  0x00000003U
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S  2
+/** SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W; bitpos: [5:4];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2    0x00000003U
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M  (SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V << SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V  0x00000003U
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S  4
+/** SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W; bitpos: [7:6];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3    0x00000003U
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M  (SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V << SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V  0x00000003U
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S  6
+/** SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W; bitpos:
+ *  [13:12]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0    0x00000003U
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M  (SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V << SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V  0x00000003U
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S  12
+/** SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W; bitpos:
+ *  [15:14]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1    0x00000003U
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M  (SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V << SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V  0x00000003U
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S  14
+/** SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W; bitpos:
+ *  [17:16]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2    0x00000003U
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M  (SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V << SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V  0x00000003U
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S  16
+/** SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W; bitpos:
+ *  [19:18]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3    0x00000003U
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M  (SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V << SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V  0x00000003U
+#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S  18
 
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x48)
-/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Need add description.*/
+/** SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_0_REG register
+ *  register description
+ */
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x48)
+/** SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK : R/W; bitpos: [0]; default: 0;
+ *  Need add description
+ */
 #define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK    (BIT(0))
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK_M  (BIT(0))
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK_V  0x1
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK_M  (SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK_V << SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK_S)
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK_V  0x00000001U
 #define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK_S  0
 
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x4C)
-/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3    0x00000003
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M  ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S))
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V  0x3
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S  18
-/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2    0x00000003
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M  ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S))
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V  0x3
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S  16
-/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1    0x00000003
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M  ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S))
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V  0x3
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S  14
-/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0    0x00000003
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M  ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S))
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V  0x3
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S  12
-/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3    0x00000003
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M  ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S))
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V  0x3
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S  6
-/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2    0x00000003
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M  ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S))
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V  0x3
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S  4
-/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1    0x00000003
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M  ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S))
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V  0x3
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S  2
-/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0    0x00000003
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M  ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S))
-#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V  0x3
+/** SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_1_REG register
+ *  register description
+ */
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x4c)
+/** SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W; bitpos: [1:0];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0    0x00000003U
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M  (SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V << SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V  0x00000003U
 #define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S  0
+/** SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W; bitpos: [3:2];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1    0x00000003U
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M  (SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V << SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V  0x00000003U
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S  2
+/** SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W; bitpos: [5:4];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2    0x00000003U
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M  (SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V << SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V  0x00000003U
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S  4
+/** SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W; bitpos: [7:6];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3    0x00000003U
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M  (SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V << SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V  0x00000003U
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S  6
+/** SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W; bitpos: [13:12];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0    0x00000003U
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M  (SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V << SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V  0x00000003U
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S  12
+/** SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W; bitpos: [15:14];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1    0x00000003U
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M  (SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V << SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V  0x00000003U
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S  14
+/** SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W; bitpos: [17:16];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2    0x00000003U
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M  (SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V << SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V  0x00000003U
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S  16
+/** SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W; bitpos: [19:18];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3    0x00000003U
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M  (SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V << SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V  0x00000003U
+#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S  18
 
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x50)
-/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Need add description.*/
+/** SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_0_REG register
+ *  register description
+ */
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x50)
+/** SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK : R/W; bitpos: [0]; default: 0;
+ *  Need add description
+ */
 #define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK    (BIT(0))
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK_M  (BIT(0))
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK_V  0x1
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK_M  (SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK_V << SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK_S)
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK_V  0x00000001U
 #define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK_S  0
 
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x54)
-/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3    0x00000003
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M  ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S))
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V  0x3
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S  18
-/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2    0x00000003
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M  ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S))
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V  0x3
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S  16
-/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1    0x00000003
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M  ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S))
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V  0x3
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S  14
-/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0    0x00000003
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M  ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S))
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V  0x3
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S  12
-/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3    0x00000003
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M  ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S))
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V  0x3
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S  6
-/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2    0x00000003
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M  ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S))
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V  0x3
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S  4
-/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1    0x00000003
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M  ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S))
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V  0x3
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S  2
-/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0    0x00000003
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M  ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S))
-#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V  0x3
+/** SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_1_REG register
+ *  register description
+ */
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x54)
+/** SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W; bitpos: [1:0];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0    0x00000003U
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M  (SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V << SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V  0x00000003U
 #define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S  0
+/** SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W; bitpos: [3:2];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1    0x00000003U
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M  (SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V << SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V  0x00000003U
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S  2
+/** SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W; bitpos: [5:4];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2    0x00000003U
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M  (SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V << SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V  0x00000003U
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S  4
+/** SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W; bitpos: [7:6];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3    0x00000003U
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M  (SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V << SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V  0x00000003U
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S  6
+/** SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W; bitpos: [13:12];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0    0x00000003U
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M  (SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V << SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V  0x00000003U
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S  12
+/** SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W; bitpos: [15:14];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1    0x00000003U
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M  (SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V << SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V  0x00000003U
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S  14
+/** SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W; bitpos: [17:16];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2    0x00000003U
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M  (SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V << SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V  0x00000003U
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S  16
+/** SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W; bitpos: [19:18];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3    0x00000003U
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M  (SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V << SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V  0x00000003U
+#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S  18
 
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x58)
-/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Need add description.*/
+/** SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0_REG register
+ *  register description
+ */
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x58)
+/** SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK : R/W; bitpos: [0]; default: 0;
+ *  Need add description
+ */
 #define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK    (BIT(0))
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK_M  (BIT(0))
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK_V  0x1
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK_M  (SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK_V << SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK_S)
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK_V  0x00000001U
 #define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK_S  0
 
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x5C)
-/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3    0x00000003
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M  ((SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S))
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V  0x3
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S  18
-/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2    0x00000003
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M  ((SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S))
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V  0x3
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S  16
-/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1    0x00000003
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M  ((SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S))
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V  0x3
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S  14
-/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0    0x00000003
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M  ((SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S))
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V  0x3
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S  12
-/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3    0x00000003
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M  ((SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S))
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V  0x3
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S  6
-/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2    0x00000003
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M  ((SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S))
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V  0x3
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S  4
-/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1    0x00000003
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M  ((SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S))
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V  0x3
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S  2
-/* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0    0x00000003
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M  ((SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S))
-#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V  0x3
+/** SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_REG register
+ *  register description
+ */
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x5c)
+/** SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W; bitpos: [1:0];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0    0x00000003U
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M  (SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V << SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V  0x00000003U
 #define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S  0
+/** SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W; bitpos: [3:2];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1    0x00000003U
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M  (SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V << SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V  0x00000003U
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S  2
+/** SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W; bitpos: [5:4];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2    0x00000003U
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M  (SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V << SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V  0x00000003U
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S  4
+/** SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W; bitpos: [7:6];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3    0x00000003U
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M  (SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V << SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V  0x00000003U
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S  6
+/** SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W; bitpos:
+ *  [13:12]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0    0x00000003U
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M  (SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V << SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V  0x00000003U
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S  12
+/** SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W; bitpos:
+ *  [15:14]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1    0x00000003U
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M  (SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V << SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V  0x00000003U
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S  14
+/** SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W; bitpos:
+ *  [17:16]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2    0x00000003U
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M  (SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V << SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V  0x00000003U
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S  16
+/** SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W; bitpos:
+ *  [19:18]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3    0x00000003U
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M  (SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V << SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V  0x00000003U
+#define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S  18
 
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x60)
-/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Need add description.*/
+/** SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_0_REG register
+ *  register description
+ */
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x60)
+/** SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK : R/W; bitpos: [0]; default: 0;
+ *  Need add description
+ */
 #define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK    (BIT(0))
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK_M  (BIT(0))
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK_V  0x1
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK_M  (SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK_V << SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK_S)
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK_V  0x00000001U
 #define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK_S  0
 
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x64)
-/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3    0x00000003
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M  ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S))
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V  0x3
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S  18
-/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2    0x00000003
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M  ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S))
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V  0x3
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S  16
-/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1    0x00000003
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M  ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S))
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V  0x3
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S  14
-/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0    0x00000003
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M  ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S))
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V  0x3
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S  12
-/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3    0x00000003
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M  ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S))
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V  0x3
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S  6
-/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2    0x00000003
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M  ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S))
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V  0x3
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S  4
-/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1    0x00000003
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M  ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S))
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V  0x3
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S  2
-/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0    0x00000003
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M  ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S))
-#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V  0x3
+/** SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_1_REG register
+ *  register description
+ */
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x64)
+/** SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W; bitpos: [1:0];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0    0x00000003U
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M  (SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V << SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V  0x00000003U
 #define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S  0
+/** SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W; bitpos: [3:2];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1    0x00000003U
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M  (SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V << SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V  0x00000003U
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S  2
+/** SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W; bitpos: [5:4];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2    0x00000003U
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M  (SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V << SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V  0x00000003U
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S  4
+/** SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W; bitpos: [7:6];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3    0x00000003U
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M  (SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V << SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V  0x00000003U
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S  6
+/** SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W; bitpos: [13:12];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0    0x00000003U
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M  (SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V << SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V  0x00000003U
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S  12
+/** SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W; bitpos: [15:14];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1    0x00000003U
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M  (SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V << SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V  0x00000003U
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S  14
+/** SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W; bitpos: [17:16];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2    0x00000003U
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M  (SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V << SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V  0x00000003U
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S  16
+/** SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W; bitpos: [19:18];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3    0x00000003U
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M  (SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V << SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V  0x00000003U
+#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S  18
 
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x68)
-/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Need add description.*/
+/** SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_0_REG register
+ *  register description
+ */
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x68)
+/** SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK : R/W; bitpos: [0]; default: 0;
+ *  Need add description
+ */
 #define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK    (BIT(0))
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK_M  (BIT(0))
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK_V  0x1
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK_M  (SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK_V << SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK_S)
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK_V  0x00000001U
 #define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK_S  0
 
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x6C)
-/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3    0x00000003
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M  ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S))
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V  0x3
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S  18
-/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2    0x00000003
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M  ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S))
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V  0x3
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S  16
-/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1    0x00000003
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M  ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S))
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V  0x3
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S  14
-/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0    0x00000003
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M  ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S))
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V  0x3
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S  12
-/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3    0x00000003
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M  ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S))
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V  0x3
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S  6
-/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2    0x00000003
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M  ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S))
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V  0x3
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S  4
-/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1    0x00000003
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M  ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S))
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V  0x3
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S  2
-/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0    0x00000003
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M  ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S))
-#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V  0x3
+/** SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_1_REG register
+ *  register description
+ */
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x6c)
+/** SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W; bitpos: [1:0];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0    0x00000003U
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M  (SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V << SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V  0x00000003U
 #define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S  0
+/** SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W; bitpos: [3:2];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1    0x00000003U
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M  (SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V << SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V  0x00000003U
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S  2
+/** SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W; bitpos: [5:4];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2    0x00000003U
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M  (SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V << SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V  0x00000003U
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S  4
+/** SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W; bitpos: [7:6];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3    0x00000003U
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M  (SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V << SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V  0x00000003U
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S  6
+/** SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W; bitpos: [13:12];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0    0x00000003U
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M  (SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V << SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V  0x00000003U
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S  12
+/** SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W; bitpos: [15:14];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1    0x00000003U
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M  (SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V << SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V  0x00000003U
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S  14
+/** SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W; bitpos: [17:16];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2    0x00000003U
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M  (SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V << SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V  0x00000003U
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S  16
+/** SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W; bitpos: [19:18];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3    0x00000003U
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M  (SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V << SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V  0x00000003U
+#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S  18
 
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x70)
-/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Need add description.*/
+/** SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_0_REG register
+ *  register description
+ */
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x70)
+/** SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK : R/W; bitpos: [0]; default: 0;
+ *  Need add description
+ */
 #define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK    (BIT(0))
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK_M  (BIT(0))
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK_V  0x1
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK_M  (SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK_V << SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK_S)
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK_V  0x00000001U
 #define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK_S  0
 
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x74)
-/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3    0x00000003
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M  ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S))
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V  0x3
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S  18
-/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2    0x00000003
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M  ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S))
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V  0x3
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S  16
-/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1    0x00000003
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M  ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S))
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V  0x3
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S  14
-/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0    0x00000003
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M  ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S))
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V  0x3
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S  12
-/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3    0x00000003
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M  ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S))
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V  0x3
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S  6
-/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2    0x00000003
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M  ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S))
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V  0x3
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S  4
-/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1    0x00000003
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M  ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S))
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V  0x3
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S  2
-/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0    0x00000003
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M  ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S))
-#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V  0x3
+/** SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_1_REG register
+ *  register description
+ */
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x74)
+/** SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W; bitpos: [1:0];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0    0x00000003U
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M  (SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V << SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V  0x00000003U
 #define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S  0
+/** SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W; bitpos: [3:2];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1    0x00000003U
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M  (SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V << SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V  0x00000003U
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S  2
+/** SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W; bitpos: [5:4];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2    0x00000003U
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M  (SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V << SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V  0x00000003U
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S  4
+/** SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W; bitpos: [7:6];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3    0x00000003U
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M  (SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V << SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V  0x00000003U
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S  6
+/** SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W; bitpos: [13:12];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0    0x00000003U
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M  (SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V << SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V  0x00000003U
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S  12
+/** SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W; bitpos: [15:14];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1    0x00000003U
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M  (SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V << SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V  0x00000003U
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S  14
+/** SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W; bitpos: [17:16];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2    0x00000003U
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M  (SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V << SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V  0x00000003U
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S  16
+/** SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W; bitpos: [19:18];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3    0x00000003U
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M  (SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V << SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V  0x00000003U
+#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S  18
 
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x78)
-/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK    (BIT(0))
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK_M  (BIT(0))
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK_V  0x1
+/** SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0_REG register
+ *  register description
+ */
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x78)
+/** SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK : R/W; bitpos: [0]; default: 0;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK    (BIT(0))
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK_M  (SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK_V << SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK_S)
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK_V  0x00000001U
 #define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK_S  0
 
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x7C)
-/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3    0x00000003
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M  ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S))
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V  0x3
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S  18
-/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2    0x00000003
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M  ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S))
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V  0x3
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S  16
-/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1    0x00000003
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M  ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S))
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V  0x3
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S  14
-/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0    0x00000003
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M  ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S))
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V  0x3
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S  12
-/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3    0x00000003
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M  ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S))
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V  0x3
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S  6
-/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2    0x00000003
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M  ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S))
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V  0x3
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S  4
-/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1    0x00000003
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M  ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S))
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V  0x3
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S  2
-/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0    0x00000003
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M  ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S))
-#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V  0x3
+/** SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_REG register
+ *  register description
+ */
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x7c)
+/** SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W; bitpos:
+ *  [1:0]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0    0x00000003U
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M  (SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V << SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V  0x00000003U
 #define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S  0
+/** SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W; bitpos:
+ *  [3:2]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1    0x00000003U
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M  (SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V << SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V  0x00000003U
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S  2
+/** SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W; bitpos:
+ *  [5:4]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2    0x00000003U
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M  (SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V << SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V  0x00000003U
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S  4
+/** SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W; bitpos:
+ *  [7:6]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3    0x00000003U
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M  (SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V << SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V  0x00000003U
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S  6
+/** SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W; bitpos:
+ *  [13:12]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0    0x00000003U
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M  (SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V << SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V  0x00000003U
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S  12
+/** SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W; bitpos:
+ *  [15:14]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1    0x00000003U
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M  (SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V << SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V  0x00000003U
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S  14
+/** SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W; bitpos:
+ *  [17:16]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2    0x00000003U
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M  (SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V << SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V  0x00000003U
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S  16
+/** SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W; bitpos:
+ *  [19:18]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3    0x00000003U
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M  (SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V << SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V  0x00000003U
+#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S  18
 
-#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x80)
-/* SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Need add description.*/
+/** SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_0_REG register
+ *  register description
+ */
+#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x80)
+/** SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_LOCK : R/W; bitpos: [0]; default: 0;
+ *  Need add description
+ */
 #define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_LOCK    (BIT(0))
-#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_LOCK_M  (BIT(0))
-#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_LOCK_V  0x1
+#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_LOCK_M  (SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_LOCK_V << SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_LOCK_S)
+#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_LOCK_V  0x00000001U
 #define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_LOCK_S  0
 
-#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x84)
-/* SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3    0x00000003
-#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M  ((SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S))
-#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V  0x3
-#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S  18
-/* SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2    0x00000003
-#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M  ((SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S))
-#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V  0x3
-#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S  16
-/* SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1    0x00000003
-#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M  ((SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S))
-#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V  0x3
-#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S  14
-/* SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0    0x00000003
-#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M  ((SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S))
-#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V  0x3
-#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S  12
-/* SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3    0x00000003
-#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M  ((SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S))
-#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V  0x3
-#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S  6
-/* SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2    0x00000003
-#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M  ((SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S))
-#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V  0x3
-#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S  4
-/* SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1    0x00000003
-#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M  ((SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S))
-#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V  0x3
-#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S  2
-/* SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0    0x00000003
-#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M  ((SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S))
-#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V  0x3
+/** SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_1_REG register
+ *  register description
+ */
+#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x84)
+/** SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W; bitpos:
+ *  [1:0]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0    0x00000003U
+#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M  (SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V << SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)
+#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V  0x00000003U
 #define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S  0
+/** SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W; bitpos:
+ *  [3:2]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1    0x00000003U
+#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M  (SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V << SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)
+#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V  0x00000003U
+#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S  2
+/** SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W; bitpos:
+ *  [5:4]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2    0x00000003U
+#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M  (SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V << SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)
+#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V  0x00000003U
+#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S  4
+/** SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W; bitpos:
+ *  [7:6]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3    0x00000003U
+#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M  (SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V << SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)
+#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V  0x00000003U
+#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S  6
+/** SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W; bitpos:
+ *  [13:12]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0    0x00000003U
+#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M  (SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V << SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)
+#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V  0x00000003U
+#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S  12
+/** SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W; bitpos:
+ *  [15:14]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1    0x00000003U
+#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M  (SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V << SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)
+#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V  0x00000003U
+#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S  14
+/** SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W; bitpos:
+ *  [17:16]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2    0x00000003U
+#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M  (SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V << SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)
+#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V  0x00000003U
+#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S  16
+/** SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W; bitpos:
+ *  [19:18]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3    0x00000003U
+#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M  (SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V << SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)
+#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V  0x00000003U
+#define SENSITIVE_DMA_APBPERI_BLE_SEC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S  18
 
-#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x88)
-/* SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Need add description.*/
+/** SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_0_REG register
+ *  register description
+ */
+#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x88)
+/** SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_LOCK : R/W; bitpos: [0]; default: 0;
+ *  Need add description
+ */
 #define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_LOCK    (BIT(0))
-#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_LOCK_M  (BIT(0))
-#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_LOCK_V  0x1
+#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_LOCK_M  (SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_LOCK_V << SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_LOCK_S)
+#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_LOCK_V  0x00000001U
 #define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_LOCK_S  0
 
-#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x8C)
-/* SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3    0x00000003
-#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M  ((SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S))
-#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V  0x3
-#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S  18
-/* SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2    0x00000003
-#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M  ((SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S))
-#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V  0x3
-#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S  16
-/* SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1    0x00000003
-#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M  ((SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S))
-#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V  0x3
-#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S  14
-/* SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0    0x00000003
-#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M  ((SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S))
-#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V  0x3
-#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S  12
-/* SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3    0x00000003
-#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M  ((SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S))
-#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V  0x3
-#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S  6
-/* SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2    0x00000003
-#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M  ((SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S))
-#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V  0x3
-#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S  4
-/* SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1    0x00000003
-#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M  ((SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S))
-#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V  0x3
-#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S  2
-/* SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0    0x00000003
-#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M  ((SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S))
-#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V  0x3
+/** SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_1_REG register
+ *  register description
+ */
+#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x8c)
+/** SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W; bitpos:
+ *  [1:0]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0    0x00000003U
+#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M  (SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V << SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)
+#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V  0x00000003U
 #define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S  0
+/** SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W; bitpos:
+ *  [3:2]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1    0x00000003U
+#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M  (SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V << SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)
+#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V  0x00000003U
+#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S  2
+/** SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W; bitpos:
+ *  [5:4]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2    0x00000003U
+#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M  (SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V << SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)
+#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V  0x00000003U
+#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S  4
+/** SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W; bitpos:
+ *  [7:6]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3    0x00000003U
+#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M  (SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V << SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)
+#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V  0x00000003U
+#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S  6
+/** SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W; bitpos:
+ *  [13:12]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0    0x00000003U
+#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M  (SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V << SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)
+#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V  0x00000003U
+#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S  12
+/** SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W; bitpos:
+ *  [15:14]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1    0x00000003U
+#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M  (SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V << SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)
+#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V  0x00000003U
+#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S  14
+/** SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W; bitpos:
+ *  [17:16]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2    0x00000003U
+#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M  (SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V << SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)
+#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V  0x00000003U
+#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S  16
+/** SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W; bitpos:
+ *  [19:18]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3    0x00000003U
+#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M  (SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V << SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)
+#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V  0x00000003U
+#define SENSITIVE_DMA_APBPERI_WHITE_LIST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S  18
 
-#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x90)
-/* SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Need add description.*/
+/** SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_0_REG register
+ *  register description
+ */
+#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x90)
+/** SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_LOCK : R/W; bitpos: [0]; default: 0;
+ *  Need add description
+ */
 #define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_LOCK    (BIT(0))
-#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_LOCK_M  (BIT(0))
-#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_LOCK_V  0x1
+#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_LOCK_M  (SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_LOCK_V << SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_LOCK_S)
+#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_LOCK_V  0x00000001U
 #define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_LOCK_S  0
 
-#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x94)
-/* SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3    0x00000003
-#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M  ((SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S))
-#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V  0x3
-#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S  18
-/* SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2    0x00000003
-#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M  ((SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S))
-#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V  0x3
-#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S  16
-/* SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1    0x00000003
-#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M  ((SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S))
-#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V  0x3
-#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S  14
-/* SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0    0x00000003
-#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M  ((SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S))
-#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V  0x3
-#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S  12
-/* SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3    0x00000003
-#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M  ((SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S))
-#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V  0x3
-#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S  6
-/* SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2    0x00000003
-#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M  ((SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S))
-#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V  0x3
-#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S  4
-/* SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1    0x00000003
-#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M  ((SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S))
-#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V  0x3
-#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S  2
-/* SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0    0x00000003
-#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M  ((SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S))
-#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V  0x3
+/** SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_1_REG register
+ *  register description
+ */
+#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x94)
+/** SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W; bitpos:
+ *  [1:0]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0    0x00000003U
+#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M  (SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V << SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)
+#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V  0x00000003U
 #define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S  0
+/** SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W; bitpos:
+ *  [3:2]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1    0x00000003U
+#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M  (SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V << SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)
+#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V  0x00000003U
+#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S  2
+/** SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W; bitpos:
+ *  [5:4]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2    0x00000003U
+#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M  (SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V << SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)
+#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V  0x00000003U
+#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S  4
+/** SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W; bitpos:
+ *  [7:6]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3    0x00000003U
+#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M  (SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V << SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)
+#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V  0x00000003U
+#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S  6
+/** SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W; bitpos:
+ *  [13:12]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0    0x00000003U
+#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M  (SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V << SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)
+#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V  0x00000003U
+#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S  12
+/** SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W; bitpos:
+ *  [15:14]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1    0x00000003U
+#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M  (SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V << SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)
+#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V  0x00000003U
+#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S  14
+/** SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W; bitpos:
+ *  [17:16]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2    0x00000003U
+#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M  (SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V << SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)
+#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V  0x00000003U
+#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S  16
+/** SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W; bitpos:
+ *  [19:18]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3    0x00000003U
+#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M  (SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V << SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)
+#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V  0x00000003U
+#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S  18
 
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_0_REG          (DR_REG_SENSITIVE_BASE + 0x98)
-/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Need add description.*/
+/** SENSITIVE_DMA_APBPERI_PMS_MONITOR_0_REG register
+ *  register description
+ */
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_0_REG (DR_REG_SENSITIVE_BASE + 0x98)
+/** SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK : R/W; bitpos: [0]; default: 0;
+ *  Need add description
+ */
 #define SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK    (BIT(0))
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK_M  (BIT(0))
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK_V  0x1
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK_M  (SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK_V << SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK_S)
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK_V  0x00000001U
 #define SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK_S  0
 
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_1_REG          (DR_REG_SENSITIVE_BASE + 0x9C)
-/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN    (BIT(1))
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN_M  (BIT(1))
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN_V  0x1
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN_S  1
-/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: Need add description.*/
+/** SENSITIVE_DMA_APBPERI_PMS_MONITOR_1_REG register
+ *  register description
+ */
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_1_REG (DR_REG_SENSITIVE_BASE + 0x9c)
+/** SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR : R/W; bitpos: [0]; default: 1;
+ *  Need add description
+ */
 #define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR    (BIT(0))
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR_M  (BIT(0))
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR_V  0x1
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR_M  (SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR_V << SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR_S)
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR_V  0x00000001U
 #define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR_S  0
+/** SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN : R/W; bitpos: [1]; default: 1;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN    (BIT(1))
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN_M  (SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN_V << SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN_S)
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN_V  0x00000001U
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN_S  1
 
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_2_REG          (DR_REG_SENSITIVE_BASE + 0xA0)
-/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR : RO ;bitpos:[26:3] ;default: 24'b0 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR    0x00FFFFFF
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_M  ((SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_V)<<(SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_S))
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_V  0xFFFFFF
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_S  3
-/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD : RO ;bitpos:[2:1] ;default: 2'b0 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD    0x00000003
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_M  ((SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_V)<<(SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_S))
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_V  0x3
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_S  1
-/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Need add description.*/
+/** SENSITIVE_DMA_APBPERI_PMS_MONITOR_2_REG register
+ *  register description
+ */
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_2_REG (DR_REG_SENSITIVE_BASE + 0xa0)
+/** SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR : RO; bitpos: [0]; default: 0;
+ *  Need add description
+ */
 #define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR    (BIT(0))
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_M  (BIT(0))
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_V  0x1
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_M  (SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_V << SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_S)
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_V  0x00000001U
 #define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_S  0
+/** SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD : RO; bitpos: [2:1];
+ *  default: 0;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD    0x00000003U
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_M  (SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_V << SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_S)
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_V  0x00000003U
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_S  1
+/** SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR : RO; bitpos: [26:3];
+ *  default: 0;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR    0x00FFFFFFU
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_M  (SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_V << SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_S)
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_V  0x00FFFFFFU
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_S  3
 
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_3_REG          (DR_REG_SENSITIVE_BASE + 0xA4)
-/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN : RO ;bitpos:[4:1] ;default: 4'b0 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN    0x0000000F
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_M  ((SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_V)<<(SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_S))
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_V  0xF
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_S  1
-/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Need add description.*/
+/** SENSITIVE_DMA_APBPERI_PMS_MONITOR_3_REG register
+ *  register description
+ */
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_3_REG (DR_REG_SENSITIVE_BASE + 0xa4)
+/** SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR : RO; bitpos: [0]; default: 0;
+ *  Need add description
+ */
 #define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR    (BIT(0))
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR_M  (BIT(0))
-#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR_V  0x1
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR_M  (SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR_V << SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR_S)
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR_V  0x00000001U
 #define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR_S  0
+/** SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN : RO; bitpos: [4:1];
+ *  default: 0;
+ *  Need add description
+ */
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN    0x0000000FU
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_M  (SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_V << SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_S)
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_V  0x0000000FU
+#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_S  1
 
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0xA8)
-/* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Need add description.*/
+/** SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_REG register
+ *  register description
+ */
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0xa8)
+/** SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK : R/W; bitpos: [0];
+ *  default: 0;
+ *  Need add description
+ */
 #define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK    (BIT(0))
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK_M  (BIT(0))
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK_V  0x1
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK_M  (SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK_V << SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK_S)
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK_V  0x00000001U
 #define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK_S  0
 
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0xAC)
-/* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR : R/W ;bitpos:[21:14] ;default: 8'b0 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR    0x000000FF
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_M  ((SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_V)<<(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_S))
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_V  0xFF
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_S  14
-/* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2 : R/W ;bitpos:[5:4] ;default: 2'b0 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2    0x00000003
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_M  ((SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_V)<<(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_S))
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_V  0x3
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_S  4
-/* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1    0x00000003
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_M  ((SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_V)<<(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_S))
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_V  0x3
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_S  2
-/* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0    0x00000003
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_M  ((SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_V)<<(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_S))
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_V  0x3
+/** SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_REG register
+ *  register description
+ */
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0xac)
+/** SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0 : R/W; bitpos: [1:0]; default: 0;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0    0x00000003U
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_M  (SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_V << SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_S)
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_V  0x00000003U
 #define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_S  0
+/** SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1 : R/W; bitpos: [3:2]; default: 0;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1    0x00000003U
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_M  (SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_V << SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_S)
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_V  0x00000003U
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_S  2
+/** SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2 : R/W; bitpos: [5:4]; default: 0;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2    0x00000003U
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_M  (SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_V << SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_S)
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_V  0x00000003U
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_S  4
+/** SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR : R/W; bitpos: [21:14]; default: 0;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR    0x000000FFU
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_M  (SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_V << SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_S)
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_V  0x000000FFU
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_S  14
 
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_REG          (DR_REG_SENSITIVE_BASE + 0xB0)
-/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR : R/W ;bitpos:[21:14] ;default: 8'b0 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR    0x000000FF
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_M  ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_S))
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_V  0xFF
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_S  14
-/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2 : R/W ;bitpos:[5:4] ;default: 2'b0 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2    0x00000003
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_M  ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_S))
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_V  0x3
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_S  4
-/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1    0x00000003
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_M  ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_S))
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_V  0x3
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_S  2
-/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0    0x00000003
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_M  ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_S))
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_V  0x3
+/** SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_REG register
+ *  register description
+ */
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_REG (DR_REG_SENSITIVE_BASE + 0xb0)
+/** SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0 : R/W; bitpos: [1:0]; default: 0;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0    0x00000003U
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_M  (SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_V << SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_S)
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_V  0x00000003U
 #define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_S  0
+/** SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1 : R/W; bitpos: [3:2]; default: 0;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1    0x00000003U
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_M  (SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_V << SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_S)
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_V  0x00000003U
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_S  2
+/** SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2 : R/W; bitpos: [5:4]; default: 0;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2    0x00000003U
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_M  (SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_V << SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_S)
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_V  0x00000003U
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_S  4
+/** SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR : R/W; bitpos: [21:14]; default: 0;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR    0x000000FFU
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_M  (SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_V << SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_S)
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_V  0x000000FFU
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_S  14
 
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_REG          (DR_REG_SENSITIVE_BASE + 0xB4)
-/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR : R/W ;bitpos:[21:14] ;default: 8'b0 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR    0x000000FF
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_M  ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_S))
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_V  0xFF
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_S  14
-/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2 : R/W ;bitpos:[5:4] ;default: 2'b0 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2    0x00000003
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_M  ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_S))
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_V  0x3
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_S  4
-/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1    0x00000003
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_M  ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_S))
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_V  0x3
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_S  2
-/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0    0x00000003
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_M  ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_S))
-#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_V  0x3
+/** SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_REG register
+ *  register description
+ */
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_REG (DR_REG_SENSITIVE_BASE + 0xb4)
+/** SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0 : R/W; bitpos: [1:0]; default: 0;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0    0x00000003U
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_M  (SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_V << SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_S)
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_V  0x00000003U
 #define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_S  0
+/** SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1 : R/W; bitpos: [3:2]; default: 0;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1    0x00000003U
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_M  (SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_V << SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_S)
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_V  0x00000003U
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_S  2
+/** SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2 : R/W; bitpos: [5:4]; default: 0;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2    0x00000003U
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_M  (SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_V << SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_S)
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_V  0x00000003U
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_S  4
+/** SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR : R/W; bitpos: [21:14]; default: 0;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR    0x000000FFU
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_M  (SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_V << SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_S)
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_V  0x000000FFU
+#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_S  14
 
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_REG          (DR_REG_SENSITIVE_BASE + 0xB8)
-/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR : R/W ;bitpos:[21:14] ;default: 8'b0 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR    0x000000FF
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_M  ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_S))
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_V  0xFF
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_S  14
-/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2 : R/W ;bitpos:[5:4] ;default: 2'b0 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2    0x00000003
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_M  ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_S))
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_V  0x3
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_S  4
-/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1    0x00000003
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_M  ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_S))
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_V  0x3
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_S  2
-/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0    0x00000003
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_M  ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_S))
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_V  0x3
+/** SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_REG register
+ *  register description
+ */
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_REG (DR_REG_SENSITIVE_BASE + 0xb8)
+/** SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0 : R/W; bitpos: [1:0]; default: 0;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0    0x00000003U
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_M  (SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_V << SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_S)
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_V  0x00000003U
 #define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_S  0
+/** SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1 : R/W; bitpos: [3:2]; default: 0;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1    0x00000003U
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_M  (SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_V << SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_S)
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_V  0x00000003U
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_S  2
+/** SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2 : R/W; bitpos: [5:4]; default: 0;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2    0x00000003U
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_M  (SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_V << SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_S)
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_V  0x00000003U
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_S  4
+/** SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR : R/W; bitpos: [21:14]; default: 0;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR    0x000000FFU
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_M  (SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_V << SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_S)
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_V  0x000000FFU
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_S  14
 
-#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_REG          (DR_REG_SENSITIVE_BASE + 0xBC)
-/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR : R/W ;bitpos:[21:14] ;default: 8'b0 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR    0x000000FF
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_M  ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_S))
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_V  0xFF
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_S  14
-/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2 : R/W ;bitpos:[5:4] ;default: 2'b0 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2    0x00000003
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_M  ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_S))
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_V  0x3
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_S  4
-/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1    0x00000003
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_M  ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_S))
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_V  0x3
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_S  2
-/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0    0x00000003
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_M  ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_S))
-#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_V  0x3
+/** SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_REG register
+ *  register description
+ */
+#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_REG (DR_REG_SENSITIVE_BASE + 0xbc)
+/** SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0 : R/W; bitpos: [1:0]; default: 0;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0    0x00000003U
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_M  (SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_V << SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_S)
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_V  0x00000003U
 #define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_S  0
+/** SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1 : R/W; bitpos: [3:2]; default: 0;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1    0x00000003U
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_M  (SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_V << SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_S)
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_V  0x00000003U
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_S  2
+/** SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2 : R/W; bitpos: [5:4]; default: 0;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2    0x00000003U
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_M  (SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_V << SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_S)
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_V  0x00000003U
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_S  4
+/** SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR : R/W; bitpos: [21:14]; default: 0;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR    0x000000FFU
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_M  (SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_V << SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_S)
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_V  0x000000FFU
+#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_S  14
 
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0xC0)
-/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Need add description.*/
+/** SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_REG register
+ *  register description
+ */
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0xc0)
+/** SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK : R/W; bitpos: [0]; default: 0;
+ *  Need add description
+ */
 #define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK    (BIT(0))
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK_M  (BIT(0))
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK_V  0x1
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK_M  (SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK_V << SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK_S)
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK_V  0x00000001U
 #define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK_S  0
 
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0xC4)
-/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS : R/W ;bitpos:[20:18] ;default: 3'b111 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS    0x00000007
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_S))
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_V  0x7
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_S  18
-/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[14:12] ;default: 3'b111 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0    0x00000007
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S))
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V  0x7
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S  12
-/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[11:9] ;default: 3'b111 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3    0x00000007
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S))
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V  0x7
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S  9
-/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[8:6] ;default: 3'b111 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2    0x00000007
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S))
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V  0x7
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S  6
-/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[5:3] ;default: 3'b111 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1    0x00000007
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S))
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V  0x7
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S  3
-/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[2:0] ;default: 3'b111 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0    0x00000007
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S))
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V  0x7
+/** SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_1_REG register
+ *  register description
+ */
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0xc4)
+/** SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W; bitpos: [2:0];
+ *  default: 7;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0    0x00000007U
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M  (SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V << SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V  0x00000007U
 #define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S  0
+/** SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W; bitpos: [5:3];
+ *  default: 7;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1    0x00000007U
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M  (SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V << SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V  0x00000007U
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S  3
+/** SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W; bitpos: [8:6];
+ *  default: 7;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2    0x00000007U
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M  (SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V << SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V  0x00000007U
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S  6
+/** SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W; bitpos: [11:9];
+ *  default: 7;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3    0x00000007U
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M  (SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V << SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V  0x00000007U
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S  9
+/** SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 : R/W;
+ *  bitpos: [14:12]; default: 7;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0    0x00000007U
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_M  (SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V << SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S)
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V  0x00000007U
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S  12
+/** SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS : R/W; bitpos: [20:18];
+ *  default: 7;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS    0x00000007U
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_M  (SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_V << SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_S)
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_V  0x00000007U
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_S  18
 
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG          (DR_REG_SENSITIVE_BASE + 0xC8)
-/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS : R/W ;bitpos:[20:18] ;default: 3'b111 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS    0x00000007
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_S))
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_V  0x7
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_S  18
-/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[14:12] ;default: 3'b111 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0    0x00000007
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S))
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V  0x7
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S  12
-/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[11:9] ;default: 3'b111 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3    0x00000007
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S))
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V  0x7
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S  9
-/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[8:6] ;default: 3'b111 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2    0x00000007
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S))
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V  0x7
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S  6
-/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[5:3] ;default: 3'b111 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1    0x00000007
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S))
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V  0x7
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S  3
-/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[2:0] ;default: 3'b111 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0    0x00000007
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S))
-#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V  0x7
+/** SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG register
+ *  register description
+ */
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG (DR_REG_SENSITIVE_BASE + 0xc8)
+/** SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W; bitpos: [2:0];
+ *  default: 7;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0    0x00000007U
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M  (SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V << SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V  0x00000007U
 #define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S  0
+/** SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W; bitpos: [5:3];
+ *  default: 7;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1    0x00000007U
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M  (SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V << SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V  0x00000007U
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S  3
+/** SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W; bitpos: [8:6];
+ *  default: 7;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2    0x00000007U
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M  (SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V << SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V  0x00000007U
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S  6
+/** SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W; bitpos: [11:9];
+ *  default: 7;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3    0x00000007U
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M  (SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V << SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V  0x00000007U
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S  9
+/** SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 : R/W;
+ *  bitpos: [14:12]; default: 7;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0    0x00000007U
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_M  (SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V << SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S)
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V  0x00000007U
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S  12
+/** SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS : R/W; bitpos: [20:18];
+ *  default: 7;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS    0x00000007U
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_M  (SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_V << SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_S)
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_V  0x00000007U
+#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_S  18
 
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0_REG          (DR_REG_SENSITIVE_BASE + 0xCC)
-/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Need add description.*/
+/** SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0_REG register
+ *  register description
+ */
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0_REG (DR_REG_SENSITIVE_BASE + 0xcc)
+/** SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK : R/W; bitpos: [0]; default: 0;
+ *  Need add description
+ */
 #define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK    (BIT(0))
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK_M  (BIT(0))
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK_V  0x1
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK_M  (SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK_V << SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK_S)
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK_V  0x00000001U
 #define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK_S  0
 
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG          (DR_REG_SENSITIVE_BASE + 0xD0)
-/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN    (BIT(1))
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN_M  (BIT(1))
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN_V  0x1
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN_S  1
-/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: Need add description.*/
+/** SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG register
+ *  register description
+ */
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG (DR_REG_SENSITIVE_BASE + 0xd0)
+/** SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR : R/W; bitpos: [0]; default: 1;
+ *  Need add description
+ */
 #define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR    (BIT(0))
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR_M  (BIT(0))
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR_V  0x1
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR_M  (SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR_V << SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR_S)
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR_V  0x00000001U
 #define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR_S  0
+/** SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN : R/W; bitpos: [1]; default: 1;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN    (BIT(1))
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN_M  (SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN_V << SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN_S)
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN_V  0x00000001U
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN_S  1
 
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG          (DR_REG_SENSITIVE_BASE + 0xD4)
-/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR : RO ;bitpos:[28:5] ;default: 24'b0 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR    0x00FFFFFF
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_M  ((SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V)<<(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S))
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V  0xFFFFFF
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S  5
-/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD : RO ;bitpos:[4:3] ;default: 2'b0 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD    0x00000003
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_M  ((SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V)<<(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S))
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V  0x3
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S  3
-/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE : RO ;bitpos:[2] ;default: 1'b0 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE    (BIT(2))
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_M  (BIT(2))
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_V  0x1
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_S  2
-/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR    (BIT(1))
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_M  (BIT(1))
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_V  0x1
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_S  1
-/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Need add description.*/
+/** SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG register
+ *  register description
+ */
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG (DR_REG_SENSITIVE_BASE + 0xd4)
+/** SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR : RO; bitpos: [0]; default: 0;
+ *  Need add description
+ */
 #define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR    (BIT(0))
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_M  (BIT(0))
-#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_V  0x1
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_M  (SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_V << SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_S)
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_V  0x00000001U
 #define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_S  0
+/** SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR : RO; bitpos: [1]; default: 0;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR    (BIT(1))
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_M  (SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_V << SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_S)
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_V  0x00000001U
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_S  1
+/** SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE : RO; bitpos: [2];
+ *  default: 0;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE    (BIT(2))
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_M  (SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_V << SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_S)
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_V  0x00000001U
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_S  2
+/** SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD : RO; bitpos: [4:3];
+ *  default: 0;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD    0x00000003U
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_M  (SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V << SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S)
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V  0x00000003U
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S  3
+/** SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR : RO; bitpos: [28:5];
+ *  default: 0;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR    0x00FFFFFFU
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_M  (SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V << SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S)
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V  0x00FFFFFFU
+#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S  5
 
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0xD8)
-/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Need add description.*/
+/** SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_0_REG register
+ *  register description
+ */
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0xd8)
+/** SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK : R/W; bitpos: [0]; default: 0;
+ *  Need add description
+ */
 #define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK    (BIT(0))
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK_M  (BIT(0))
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK_V  0x1
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK_M  (SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK_V << SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK_S)
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK_V  0x00000001U
 #define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK_S  0
 
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0xDC)
-/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS : R/W ;bitpos:[27:26] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS    0x00000003
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_M  ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_S))
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_V  0x3
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_S  26
-/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS : R/W ;bitpos:[25:24] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS    0x00000003
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_M  ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_S))
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_V  0x3
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_S  24
-/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3    0x00000003
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M  ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S))
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V  0x3
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S  18
-/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2    0x00000003
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M  ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S))
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V  0x3
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S  16
-/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1    0x00000003
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M  ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S))
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V  0x3
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S  14
-/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0    0x00000003
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M  ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S))
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V  0x3
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S  12
-/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3    0x00000003
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M  ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S))
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V  0x3
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S  6
-/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2    0x00000003
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M  ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S))
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V  0x3
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S  4
-/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1    0x00000003
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M  ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S))
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V  0x3
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S  2
-/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0    0x00000003
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M  ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S))
-#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V  0x3
+/** SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG register
+ *  register description
+ */
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0xdc)
+/** SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W; bitpos: [1:0];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0    0x00000003U
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M  (SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V << SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V  0x00000003U
 #define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S  0
+/** SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W; bitpos: [3:2];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1    0x00000003U
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M  (SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V << SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V  0x00000003U
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S  2
+/** SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W; bitpos: [5:4];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2    0x00000003U
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M  (SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V << SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V  0x00000003U
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S  4
+/** SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W; bitpos: [7:6];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3    0x00000003U
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M  (SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V << SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V  0x00000003U
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S  6
+/** SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W; bitpos: [13:12];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0    0x00000003U
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M  (SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V << SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V  0x00000003U
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S  12
+/** SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W; bitpos: [15:14];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1    0x00000003U
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M  (SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V << SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V  0x00000003U
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S  14
+/** SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W; bitpos: [17:16];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2    0x00000003U
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M  (SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V << SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V  0x00000003U
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S  16
+/** SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W; bitpos: [19:18];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3    0x00000003U
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M  (SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V << SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V  0x00000003U
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S  18
+/** SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS : R/W; bitpos: [25:24];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS    0x00000003U
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_M  (SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_V << SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_S)
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_V  0x00000003U
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_S  24
+/** SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS : R/W; bitpos: [27:26];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS    0x00000003U
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_M  (SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_V << SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_S)
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_V  0x00000003U
+#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_S  26
 
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_0_REG          (DR_REG_SENSITIVE_BASE + 0xE0)
-/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Need add description.*/
+/** SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_0_REG register
+ *  register description
+ */
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_0_REG (DR_REG_SENSITIVE_BASE + 0xe0)
+/** SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK : R/W; bitpos: [0]; default: 0;
+ *  Need add description
+ */
 #define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK    (BIT(0))
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK_M  (BIT(0))
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK_V  0x1
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK_M  (SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK_V << SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK_S)
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK_V  0x00000001U
 #define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK_S  0
 
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG          (DR_REG_SENSITIVE_BASE + 0xE4)
-/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN    (BIT(1))
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN_M  (BIT(1))
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN_V  0x1
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN_S  1
-/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: Need add description.*/
+/** SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG register
+ *  register description
+ */
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG (DR_REG_SENSITIVE_BASE + 0xe4)
+/** SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR : R/W; bitpos: [0]; default: 1;
+ *  Need add description
+ */
 #define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR    (BIT(0))
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR_M  (BIT(0))
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR_V  0x1
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR_M  (SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR_V << SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR_S)
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR_V  0x00000001U
 #define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR_S  0
+/** SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN : R/W; bitpos: [1]; default: 1;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN    (BIT(1))
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN_M  (SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN_V << SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN_S)
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN_V  0x00000001U
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN_S  1
 
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG          (DR_REG_SENSITIVE_BASE + 0xE8)
-/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR : RO ;bitpos:[27:4] ;default: 24'b0 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR    0x00FFFFFF
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_M  ((SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V)<<(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S))
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V  0xFFFFFF
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S  4
-/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD : RO ;bitpos:[3:2] ;default: 2'b0 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD    0x00000003
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_M  ((SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V)<<(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S))
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V  0x3
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S  2
-/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK    (BIT(1))
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_M  (BIT(1))
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_V  0x1
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_S  1
-/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Need add description.*/
+/** SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG register
+ *  register description
+ */
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG (DR_REG_SENSITIVE_BASE + 0xe8)
+/** SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR : RO; bitpos: [0]; default: 0;
+ *  Need add description
+ */
 #define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR    (BIT(0))
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_M  (BIT(0))
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_V  0x1
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_M  (SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_V << SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_S)
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_V  0x00000001U
 #define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_S  0
+/** SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK : RO; bitpos: [1]; default:
+ *  0;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK    (BIT(1))
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_M  (SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_V << SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_S)
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_V  0x00000001U
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_S  1
+/** SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD : RO; bitpos: [3:2];
+ *  default: 0;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD    0x00000003U
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_M  (SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V << SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S)
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V  0x00000003U
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S  2
+/** SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR : RO; bitpos: [27:4];
+ *  default: 0;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR    0x00FFFFFFU
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_M  (SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V << SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S)
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V  0x00FFFFFFU
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S  4
 
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_3_REG          (DR_REG_SENSITIVE_BASE + 0xEC)
-/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN : RO ;bitpos:[4:1] ;default: 4'b0 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN    0x0000000F
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_M  ((SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_V)<<(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_S))
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_V  0xF
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_S  1
-/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Need add description.*/
+/** SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_3_REG register
+ *  register description
+ */
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_3_REG (DR_REG_SENSITIVE_BASE + 0xec)
+/** SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR : RO; bitpos: [0]; default: 0;
+ *  Need add description
+ */
 #define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR    (BIT(0))
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_M  (BIT(0))
-#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_V  0x1
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_M  (SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_V << SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_S)
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_V  0x00000001U
 #define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_S  0
+/** SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN : RO; bitpos: [4:1];
+ *  default: 0;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN    0x0000000FU
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_M  (SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_V << SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_S)
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_V  0x0000000FU
+#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_S  1
 
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0xF0)
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Need add description.*/
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_0_REG register
+ *  register description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0xf0)
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK : R/W; bitpos: [0]; default: 0;
+ *  Need add description
+ */
 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK    (BIT(0))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK_M  (BIT(0))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK_V  0x1
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK_V  0x00000001U
 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK_S  0
 
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0xF4)
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1 : R/W ;bitpos:[31:30] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_S  30
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C : R/W ;bitpos:[27:26] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_S  26
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC : R/W ;bitpos:[25:24] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_S  24
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG : R/W ;bitpos:[19:18] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG_S  18
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX : R/W ;bitpos:[17:16] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_S  16
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC : R/W ;bitpos:[15:14] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_S  14
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE : R/W ;bitpos:[11:10] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_S  10
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO : R/W ;bitpos:[7:6] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_S  6
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0 : R/W ;bitpos:[5:4] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_S  4
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1 : R/W ;bitpos:[3:2] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_S  2
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART : R/W ;bitpos:[1:0] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_V  0x3
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_REG register
+ *  register description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0xf4)
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART : R/W; bitpos: [1:0]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_V  0x00000003U
 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_S  0
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1 : R/W; bitpos: [3:2]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_V  0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_S  2
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0 : R/W; bitpos: [5:4]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_V  0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_S  4
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO : R/W; bitpos: [7:6]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_V  0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_S  6
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE : R/W; bitpos: [11:10]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_V  0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_S  10
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC : R/W; bitpos: [15:14]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_V  0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_S  14
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX : R/W; bitpos: [17:16]; default:
+ *  3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_V  0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_S  16
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG : R/W; bitpos: [19:18]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG_V  0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG_S  18
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC : R/W; bitpos: [25:24]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_V  0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_S  24
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C : R/W; bitpos: [27:26]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_V  0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_S  26
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1 : R/W; bitpos: [31:30]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_V  0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_S  30
 
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_REG          (DR_REG_SENSITIVE_BASE + 0xF8)
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER : R/W ;bitpos:[31:30] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_S  30
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1 : R/W ;bitpos:[29:28] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_S  28
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP : R/W ;bitpos:[27:26] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_S  26
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_EFUSE : R/W ;bitpos:[19:18] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_EFUSE    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_EFUSE_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_EFUSE_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_EFUSE_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_EFUSE_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_EFUSE_S  18
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC : R/W ;bitpos:[17:16] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_S  16
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT : R/W ;bitpos:[11:10] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_S  10
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0 : R/W ;bitpos:[7:6] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_S  6
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0 : R/W ;bitpos:[5:4] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_S  4
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT : R/W ;bitpos:[1:0] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_V  0x3
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_REG register
+ *  register description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_REG (DR_REG_SENSITIVE_BASE + 0xf8)
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT : R/W; bitpos: [1:0]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_V  0x00000003U
 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_S  0
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0 : R/W; bitpos: [5:4]; default:
+ *  3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_V  0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_S  4
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0 : R/W; bitpos: [7:6]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_V  0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_S  6
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT : R/W; bitpos: [11:10]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_V  0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_S  10
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC : R/W; bitpos: [17:16]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_V  0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_S  16
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_EFUSE : R/W; bitpos: [19:18]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_EFUSE    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_EFUSE_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_EFUSE_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_EFUSE_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_EFUSE_V  0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_EFUSE_S  18
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP : R/W; bitpos: [27:26];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_V  0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_S  26
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1 : R/W; bitpos: [29:28];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_V  0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_S  28
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER : R/W; bitpos: [31:30];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_V  0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_S  30
 
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_3_REG          (DR_REG_SENSITIVE_BASE + 0xFC)
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT : R/W ;bitpos:[23:22] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_S  22
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1 : R/W ;bitpos:[15:14] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_S  14
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN : R/W ;bitpos:[11:10] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN_S  10
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL : R/W ;bitpos:[5:4] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_S  4
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2 : R/W ;bitpos:[1:0] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_V  0x3
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_3_REG register
+ *  register description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_3_REG (DR_REG_SENSITIVE_BASE + 0xfc)
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2 : R/W; bitpos: [1:0]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_V  0x00000003U
 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_S  0
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL : R/W; bitpos: [5:4]; default:
+ *  3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_V  0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_S  4
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TWAI : R/W; bitpos: [11:10]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TWAI    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TWAI_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TWAI_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TWAI_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TWAI_V  0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TWAI_S  10
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1 : R/W; bitpos: [15:14]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_V  0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_S  14
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT : R/W; bitpos: [23:22]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_V  0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_S  22
 
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_REG          (DR_REG_SENSITIVE_BASE + 0x100)
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CLKRST : R/W ;bitpos:[31:30] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CLKRST    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CLKRST_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CLKRST_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CLKRST_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CLKRST_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CLKRST_S  30
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_BLE_TMR : R/W ;bitpos:[29:28] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_BLE_TMR    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_BLE_TMR_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_BLE_TMR_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_BLE_TMR_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_BLE_TMR_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_BLE_TMR_S  28
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_COEX : R/W ;bitpos:[27:26] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_COEX    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_COEX_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_COEX_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_COEX_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_COEX_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_COEX_S  26
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_ZIGBEEMAC : R/W ;bitpos:[23:22] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_ZIGBEEMAC    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_ZIGBEEMAC_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_ZIGBEEMAC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_ZIGBEEMAC_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_ZIGBEEMAC_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_ZIGBEEMAC_S  22
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BLE_SEC : R/W ;bitpos:[21:20] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BLE_SEC    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BLE_SEC_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BLE_SEC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BLE_SEC_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BLE_SEC_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BLE_SEC_S  20
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP3 : R/W ;bitpos:[19:18] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP3    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP3_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP3_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP3_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP3_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP3_S  18
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_ETM : R/W ;bitpos:[17:16] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_ETM    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_ETM_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_ETM_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_ETM_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_ETM_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_ETM_S  16
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE : R/W ;bitpos:[15:14] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_S  14
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC : R/W ;bitpos:[9:8] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_S  8
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA : R/W ;bitpos:[7:6] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_S  6
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI : R/W ;bitpos:[5:4] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_V  0x3
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_REG register
+ *  register description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_REG (DR_REG_SENSITIVE_BASE + 0x100)
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI : R/W; bitpos: [5:4];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_V  0x00000003U
 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_S  4
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA : R/W; bitpos: [7:6];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_V  0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_S  6
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC : R/W; bitpos: [9:8]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_V  0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_S  8
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE : R/W; bitpos: [15:14];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_V  0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_S  14
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_ETM : R/W; bitpos: [17:16]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_ETM    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_ETM_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_ETM_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_ETM_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_ETM_V  0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_ETM_S  16
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP3 : R/W; bitpos: [19:18];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP3    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP3_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP3_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP3_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP3_V  0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP3_S  18
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BLE_SEC : R/W; bitpos: [21:20]; default:
+ *  3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BLE_SEC    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BLE_SEC_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BLE_SEC_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BLE_SEC_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BLE_SEC_V  0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BLE_SEC_S  20
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IEEE802154MAC : R/W; bitpos: [23:22];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IEEE802154MAC    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IEEE802154MAC_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IEEE802154MAC_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IEEE802154MAC_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IEEE802154MAC_V  0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IEEE802154MAC_S  22
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_COEX : R/W; bitpos: [27:26]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_COEX    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_COEX_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_COEX_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_COEX_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_COEX_V  0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_COEX_S  26
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_BLE_TMR : R/W; bitpos: [29:28];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_BLE_TMR    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_BLE_TMR_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_BLE_TMR_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_BLE_TMR_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_BLE_TMR_V  0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_BLE_TMR_S  28
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CLKRST : R/W; bitpos: [31:30]; default:
+ *  3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CLKRST    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CLKRST_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CLKRST_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CLKRST_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CLKRST_V  0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CLKRST_S  30
 
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_REG          (DR_REG_SENSITIVE_BASE + 0x104)
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER : R/W ;bitpos:[19:18] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_S  18
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO : R/W ;bitpos:[17:16] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_S  16
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD : R/W ;bitpos:[15:14] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_S  14
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG : R/W ;bitpos:[13:12] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_S  12
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY : R/W ;bitpos:[11:10] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_S  10
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT : R/W ;bitpos:[9:8] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_S  8
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE : R/W ;bitpos:[7:6] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_S  6
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM : R/W ;bitpos:[5:4] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_S  4
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MODEM_WIDGETS : R/W ;bitpos:[3:2] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MODEM_WIDGETS    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MODEM_WIDGETS_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MODEM_WIDGETS_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MODEM_WIDGETS_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MODEM_WIDGETS_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MODEM_WIDGETS_S  2
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PVT : R/W ;bitpos:[1:0] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PVT    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PVT_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PVT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PVT_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PVT_V  0x3
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_REG register
+ *  register description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_REG (DR_REG_SENSITIVE_BASE + 0x104)
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PVT : R/W; bitpos: [1:0]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PVT    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PVT_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PVT_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PVT_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PVT_V  0x00000003U
 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PVT_S  0
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MODEM_WIDGETS : R/W; bitpos: [3:2];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MODEM_WIDGETS    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MODEM_WIDGETS_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MODEM_WIDGETS_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MODEM_WIDGETS_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MODEM_WIDGETS_V  0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MODEM_WIDGETS_S  2
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM : R/W; bitpos: [5:4]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_V  0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_S  4
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE : R/W; bitpos: [7:6]; default:
+ *  3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_V  0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_S  6
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT : R/W; bitpos: [9:8]; default:
+ *  3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_V  0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_S  8
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY : R/W; bitpos: [11:10];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_V  0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_S  10
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG : R/W; bitpos: [13:12];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_V  0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_S  12
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD : R/W; bitpos: [15:14]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_V  0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_S  14
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO : R/W; bitpos: [17:16]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_V  0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_S  16
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER : R/W; bitpos: [19:18];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_V  0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_S  18
 
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_REG          (DR_REG_SENSITIVE_BASE + 0x108)
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1 : R/W ;bitpos:[31:30] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_S  30
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C : R/W ;bitpos:[27:26] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_S  26
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC : R/W ;bitpos:[25:24] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_S  24
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG : R/W ;bitpos:[19:18] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG_S  18
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX : R/W ;bitpos:[17:16] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_S  16
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC : R/W ;bitpos:[15:14] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_S  14
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE : R/W ;bitpos:[11:10] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_S  10
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO : R/W ;bitpos:[7:6] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_S  6
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0 : R/W ;bitpos:[5:4] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_S  4
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1 : R/W ;bitpos:[3:2] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_S  2
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART : R/W ;bitpos:[1:0] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_V  0x3
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_REG register
+ *  register description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_REG (DR_REG_SENSITIVE_BASE + 0x108)
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART : R/W; bitpos: [1:0]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_V  0x00000003U
 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_S  0
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1 : R/W; bitpos: [3:2]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_V  0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_S  2
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0 : R/W; bitpos: [5:4]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_V  0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_S  4
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO : R/W; bitpos: [7:6]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_V  0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_S  6
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE : R/W; bitpos: [11:10]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_V  0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_S  10
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC : R/W; bitpos: [15:14]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_V  0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_S  14
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX : R/W; bitpos: [17:16]; default:
+ *  3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_V  0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_S  16
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG : R/W; bitpos: [19:18]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG_V  0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG_S  18
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC : R/W; bitpos: [25:24]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_V  0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_S  24
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C : R/W; bitpos: [27:26]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_V  0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_S  26
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1 : R/W; bitpos: [31:30]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_V  0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_S  30
 
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_7_REG          (DR_REG_SENSITIVE_BASE + 0x10C)
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER : R/W ;bitpos:[31:30] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_S  30
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1 : R/W ;bitpos:[29:28] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_S  28
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP : R/W ;bitpos:[27:26] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_S  26
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_EFUSE : R/W ;bitpos:[19:18] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_EFUSE    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_EFUSE_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_EFUSE_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_EFUSE_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_EFUSE_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_EFUSE_S  18
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC : R/W ;bitpos:[17:16] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_S  16
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT : R/W ;bitpos:[11:10] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_S  10
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0 : R/W ;bitpos:[7:6] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_S  6
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0 : R/W ;bitpos:[5:4] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_S  4
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT : R/W ;bitpos:[1:0] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_V  0x3
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_7_REG register
+ *  register description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_7_REG (DR_REG_SENSITIVE_BASE + 0x10c)
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT : R/W; bitpos: [1:0]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_V  0x00000003U
 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_S  0
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0 : R/W; bitpos: [5:4]; default:
+ *  3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_V  0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_S  4
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0 : R/W; bitpos: [7:6]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_V  0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_S  6
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT : R/W; bitpos: [11:10]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_V  0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_S  10
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC : R/W; bitpos: [17:16]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_V  0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_S  16
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_EFUSE : R/W; bitpos: [19:18]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_EFUSE    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_EFUSE_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_EFUSE_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_EFUSE_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_EFUSE_V  0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_EFUSE_S  18
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP : R/W; bitpos: [27:26];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_V  0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_S  26
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1 : R/W; bitpos: [29:28];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_V  0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_S  28
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER : R/W; bitpos: [31:30];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_V  0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_S  30
 
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_REG          (DR_REG_SENSITIVE_BASE + 0x110)
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT : R/W ;bitpos:[23:22] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_S  22
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1 : R/W ;bitpos:[15:14] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_S  14
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN : R/W ;bitpos:[11:10] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN_S  10
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL : R/W ;bitpos:[5:4] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_S  4
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2 : R/W ;bitpos:[1:0] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_V  0x3
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_REG register
+ *  register description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_REG (DR_REG_SENSITIVE_BASE + 0x110)
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2 : R/W; bitpos: [1:0]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_V  0x00000003U
 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_S  0
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL : R/W; bitpos: [5:4]; default:
+ *  3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_V  0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_S  4
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TWAI : R/W; bitpos: [11:10]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TWAI    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TWAI_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TWAI_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TWAI_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TWAI_V  0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TWAI_S  10
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1 : R/W; bitpos: [15:14]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_V  0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_S  14
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT : R/W; bitpos: [23:22]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_V  0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_S  22
 
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_9_REG          (DR_REG_SENSITIVE_BASE + 0x114)
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CLKRST : R/W ;bitpos:[31:30] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CLKRST    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CLKRST_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CLKRST_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CLKRST_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CLKRST_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CLKRST_S  30
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_BLE_TMR : R/W ;bitpos:[29:28] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_BLE_TMR    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_BLE_TMR_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_BLE_TMR_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_BLE_TMR_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_BLE_TMR_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_BLE_TMR_S  28
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_COEX : R/W ;bitpos:[27:26] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_COEX    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_COEX_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_COEX_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_COEX_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_COEX_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_COEX_S  26
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_ZIGBEEMAC : R/W ;bitpos:[23:22] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_ZIGBEEMAC    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_ZIGBEEMAC_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_ZIGBEEMAC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_ZIGBEEMAC_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_ZIGBEEMAC_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_ZIGBEEMAC_S  22
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BLE_SEC : R/W ;bitpos:[21:20] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BLE_SEC    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BLE_SEC_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BLE_SEC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BLE_SEC_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BLE_SEC_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BLE_SEC_S  20
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP3 : R/W ;bitpos:[19:18] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP3    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP3_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP3_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP3_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP3_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP3_S  18
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_ETM : R/W ;bitpos:[17:16] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_ETM    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_ETM_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_ETM_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_ETM_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_ETM_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_ETM_S  16
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE : R/W ;bitpos:[15:14] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_S  14
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC : R/W ;bitpos:[9:8] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_S  8
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA : R/W ;bitpos:[7:6] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_S  6
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI : R/W ;bitpos:[5:4] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_V  0x3
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_9_REG register
+ *  register description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_9_REG (DR_REG_SENSITIVE_BASE + 0x114)
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI : R/W; bitpos: [5:4];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_V  0x00000003U
 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_S  4
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA : R/W; bitpos: [7:6];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_V  0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_S  6
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC : R/W; bitpos: [9:8]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_V  0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_S  8
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE : R/W; bitpos: [15:14];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_V  0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_S  14
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_ETM : R/W; bitpos: [17:16]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_ETM    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_ETM_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_ETM_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_ETM_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_ETM_V  0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_ETM_S  16
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP3 : R/W; bitpos: [19:18];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP3    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP3_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP3_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP3_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP3_V  0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP3_S  18
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BLE_SEC : R/W; bitpos: [21:20]; default:
+ *  3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BLE_SEC    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BLE_SEC_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BLE_SEC_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BLE_SEC_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BLE_SEC_V  0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BLE_SEC_S  20
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IEEE802154MAC : R/W; bitpos: [23:22];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IEEE802154MAC    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IEEE802154MAC_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IEEE802154MAC_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IEEE802154MAC_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IEEE802154MAC_V  0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IEEE802154MAC_S  22
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_COEX : R/W; bitpos: [27:26]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_COEX    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_COEX_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_COEX_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_COEX_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_COEX_V  0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_COEX_S  26
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_BLE_TMR : R/W; bitpos: [29:28];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_BLE_TMR    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_BLE_TMR_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_BLE_TMR_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_BLE_TMR_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_BLE_TMR_V  0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_BLE_TMR_S  28
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CLKRST : R/W; bitpos: [31:30]; default:
+ *  3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CLKRST    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CLKRST_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CLKRST_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CLKRST_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CLKRST_V  0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CLKRST_S  30
 
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_REG          (DR_REG_SENSITIVE_BASE + 0x118)
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER : R/W ;bitpos:[19:18] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_S  18
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO : R/W ;bitpos:[17:16] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_S  16
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD : R/W ;bitpos:[15:14] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_S  14
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG : R/W ;bitpos:[13:12] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_S  12
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY : R/W ;bitpos:[11:10] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_S  10
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT : R/W ;bitpos:[9:8] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_S  8
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE : R/W ;bitpos:[7:6] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_S  6
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM : R/W ;bitpos:[5:4] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_S  4
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MODEM_WIDGETS : R/W ;bitpos:[3:2] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MODEM_WIDGETS    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MODEM_WIDGETS_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MODEM_WIDGETS_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MODEM_WIDGETS_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MODEM_WIDGETS_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MODEM_WIDGETS_S  2
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PVT : R/W ;bitpos:[1:0] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PVT    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PVT_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PVT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PVT_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PVT_V  0x3
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_REG register
+ *  register description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_REG (DR_REG_SENSITIVE_BASE + 0x118)
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PVT : R/W; bitpos: [1:0]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PVT    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PVT_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PVT_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PVT_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PVT_V  0x00000003U
 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PVT_S  0
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MODEM_WIDGETS : R/W; bitpos: [3:2];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MODEM_WIDGETS    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MODEM_WIDGETS_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MODEM_WIDGETS_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MODEM_WIDGETS_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MODEM_WIDGETS_V  0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MODEM_WIDGETS_S  2
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM : R/W; bitpos: [5:4]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_V  0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_S  4
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE : R/W; bitpos: [7:6]; default:
+ *  3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_V  0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_S  6
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT : R/W; bitpos: [9:8]; default:
+ *  3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_V  0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_S  8
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY : R/W; bitpos: [11:10];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_V  0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_S  10
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG : R/W; bitpos: [13:12];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_V  0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_S  12
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD : R/W; bitpos: [15:14]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_V  0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_S  14
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO : R/W; bitpos: [17:16]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_V  0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_S  16
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER : R/W; bitpos: [19:18];
+ *  default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_V  0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_S  18
 
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_11_REG          (DR_REG_SENSITIVE_BASE + 0x11C)
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1 : R/W ;bitpos:[21:11] ;default: 11'h7ff ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1    0x000007FF
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_V  0x7FF
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_S  11
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0 : R/W ;bitpos:[10:0] ;default: 11'h7ff ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0    0x000007FF
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_V  0x7FF
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_11_REG register
+ *  register description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_11_REG (DR_REG_SENSITIVE_BASE + 0x11c)
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0 : R/W; bitpos: [10:0];
+ *  default: 2047;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0    0x000007FFU
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_V  0x000007FFU
 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_S  0
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1 : R/W; bitpos: [21:11];
+ *  default: 2047;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1    0x000007FFU
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_V  0x000007FFU
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_S  11
 
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_12_REG          (DR_REG_SENSITIVE_BASE + 0x120)
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H : R/W ;bitpos:[11:9] ;default: 3'b111 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H    0x00000007
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_V  0x7
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_S  9
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L : R/W ;bitpos:[8:6] ;default: 3'b111 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L    0x00000007
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_V  0x7
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_S  6
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H : R/W ;bitpos:[5:3] ;default: 3'b111 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H    0x00000007
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_V  0x7
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_S  3
-/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L : R/W ;bitpos:[2:0] ;default: 3'b111 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L    0x00000007
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_S))
-#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_V  0x7
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_12_REG register
+ *  register description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_12_REG (DR_REG_SENSITIVE_BASE + 0x120)
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L : R/W; bitpos: [2:0]; default:
+ *  7;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L    0x00000007U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_V  0x00000007U
 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_S  0
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H : R/W; bitpos: [5:3]; default:
+ *  7;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H    0x00000007U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_V  0x00000007U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_S  3
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L : R/W; bitpos: [8:6]; default:
+ *  7;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L    0x00000007U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_V  0x00000007U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_S  6
+/** SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H : R/W; bitpos: [11:9];
+ *  default: 7;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H    0x00000007U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_M  (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_V << SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_S)
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_V  0x00000007U
+#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_S  9
 
-#define SENSITIVE_REGION_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x124)
-/* SENSITIVE_REGION_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Need add description.*/
+/** SENSITIVE_REGION_PMS_CONSTRAIN_0_REG register
+ *  register description
+ */
+#define SENSITIVE_REGION_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x124)
+/** SENSITIVE_REGION_PMS_CONSTRAIN_LOCK : R/W; bitpos: [0]; default: 0;
+ *  Need add description
+ */
 #define SENSITIVE_REGION_PMS_CONSTRAIN_LOCK    (BIT(0))
-#define SENSITIVE_REGION_PMS_CONSTRAIN_LOCK_M  (BIT(0))
-#define SENSITIVE_REGION_PMS_CONSTRAIN_LOCK_V  0x1
+#define SENSITIVE_REGION_PMS_CONSTRAIN_LOCK_M  (SENSITIVE_REGION_PMS_CONSTRAIN_LOCK_V << SENSITIVE_REGION_PMS_CONSTRAIN_LOCK_S)
+#define SENSITIVE_REGION_PMS_CONSTRAIN_LOCK_V  0x00000001U
 #define SENSITIVE_REGION_PMS_CONSTRAIN_LOCK_S  0
 
-#define SENSITIVE_REGION_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x128)
-/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6 : R/W ;bitpos:[13:12] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6    0x00000003
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_S))
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_V  0x3
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_S  12
-/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5 : R/W ;bitpos:[11:10] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5    0x00000003
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_S))
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_V  0x3
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_S  10
-/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4 : R/W ;bitpos:[9:8] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4    0x00000003
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_S))
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_V  0x3
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_S  8
-/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3 : R/W ;bitpos:[7:6] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3    0x00000003
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_S))
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_V  0x3
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_S  6
-/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2 : R/W ;bitpos:[5:4] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2    0x00000003
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_S))
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_V  0x3
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_S  4
-/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1 : R/W ;bitpos:[3:2] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1    0x00000003
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_S))
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_V  0x3
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_S  2
-/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0 : R/W ;bitpos:[1:0] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0    0x00000003
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_S))
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_V  0x3
+/** SENSITIVE_REGION_PMS_CONSTRAIN_1_REG register
+ *  register description
+ */
+#define SENSITIVE_REGION_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x128)
+/** SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0 : R/W; bitpos: [1:0]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0    0x00000003U
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_M  (SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_V << SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_S)
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_V  0x00000003U
 #define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_S  0
+/** SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1 : R/W; bitpos: [3:2]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1    0x00000003U
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_M  (SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_V << SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_S)
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_V  0x00000003U
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_S  2
+/** SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2 : R/W; bitpos: [5:4]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2    0x00000003U
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_M  (SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_V << SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_S)
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_V  0x00000003U
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_S  4
+/** SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3 : R/W; bitpos: [7:6]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3    0x00000003U
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_M  (SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_V << SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_S)
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_V  0x00000003U
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_S  6
+/** SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4 : R/W; bitpos: [9:8]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4    0x00000003U
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_M  (SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_V << SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_S)
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_V  0x00000003U
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_S  8
+/** SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5 : R/W; bitpos: [11:10]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5    0x00000003U
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_M  (SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_V << SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_S)
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_V  0x00000003U
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_S  10
+/** SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6 : R/W; bitpos: [13:12]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6    0x00000003U
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_M  (SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_V << SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_S)
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_V  0x00000003U
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_S  12
 
-#define SENSITIVE_REGION_PMS_CONSTRAIN_2_REG          (DR_REG_SENSITIVE_BASE + 0x12C)
-/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6 : R/W ;bitpos:[13:12] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6    0x00000003
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_S))
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_V  0x3
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_S  12
-/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5 : R/W ;bitpos:[11:10] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5    0x00000003
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_S))
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_V  0x3
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_S  10
-/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4 : R/W ;bitpos:[9:8] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4    0x00000003
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_S))
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_V  0x3
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_S  8
-/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3 : R/W ;bitpos:[7:6] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3    0x00000003
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_S))
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_V  0x3
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_S  6
-/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2 : R/W ;bitpos:[5:4] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2    0x00000003
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_S))
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_V  0x3
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_S  4
-/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1 : R/W ;bitpos:[3:2] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1    0x00000003
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_S))
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_V  0x3
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_S  2
-/* SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0 : R/W ;bitpos:[1:0] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0    0x00000003
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_S))
-#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_V  0x3
+/** SENSITIVE_REGION_PMS_CONSTRAIN_2_REG register
+ *  register description
+ */
+#define SENSITIVE_REGION_PMS_CONSTRAIN_2_REG (DR_REG_SENSITIVE_BASE + 0x12c)
+/** SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0 : R/W; bitpos: [1:0]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0    0x00000003U
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_M  (SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_V << SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_S)
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_V  0x00000003U
 #define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_S  0
+/** SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1 : R/W; bitpos: [3:2]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1    0x00000003U
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_M  (SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_V << SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_S)
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_V  0x00000003U
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_S  2
+/** SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2 : R/W; bitpos: [5:4]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2    0x00000003U
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_M  (SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_V << SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_S)
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_V  0x00000003U
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_S  4
+/** SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3 : R/W; bitpos: [7:6]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3    0x00000003U
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_M  (SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_V << SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_S)
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_V  0x00000003U
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_S  6
+/** SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4 : R/W; bitpos: [9:8]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4    0x00000003U
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_M  (SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_V << SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_S)
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_V  0x00000003U
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_S  8
+/** SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5 : R/W; bitpos: [11:10]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5    0x00000003U
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_M  (SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_V << SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_S)
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_V  0x00000003U
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_S  10
+/** SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6 : R/W; bitpos: [13:12]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6    0x00000003U
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_M  (SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_V << SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_S)
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_V  0x00000003U
+#define SENSITIVE_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_S  12
 
-#define SENSITIVE_REGION_PMS_CONSTRAIN_3_REG          (DR_REG_SENSITIVE_BASE + 0x130)
-/* SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_0 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
-/*description: Need add description.*/
-#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_0    0x3FFFFFFF
-#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_0_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_0_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_0_S))
-#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_0_V  0x3FFFFFFF
+/** SENSITIVE_REGION_PMS_CONSTRAIN_3_REG register
+ *  register description
+ */
+#define SENSITIVE_REGION_PMS_CONSTRAIN_3_REG (DR_REG_SENSITIVE_BASE + 0x130)
+/** SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_0 : R/W; bitpos: [29:0]; default: 0;
+ *  Need add description
+ */
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_0    0x3FFFFFFFU
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_0_M  (SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_0_V << SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_0_S)
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_0_V  0x3FFFFFFFU
 #define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_0_S  0
 
-#define SENSITIVE_REGION_PMS_CONSTRAIN_4_REG          (DR_REG_SENSITIVE_BASE + 0x134)
-/* SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_1 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
-/*description: Need add description.*/
-#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_1    0x3FFFFFFF
-#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_1_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_1_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_1_S))
-#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_1_V  0x3FFFFFFF
+/** SENSITIVE_REGION_PMS_CONSTRAIN_4_REG register
+ *  register description
+ */
+#define SENSITIVE_REGION_PMS_CONSTRAIN_4_REG (DR_REG_SENSITIVE_BASE + 0x134)
+/** SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_1 : R/W; bitpos: [29:0]; default: 0;
+ *  Need add description
+ */
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_1    0x3FFFFFFFU
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_1_M  (SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_1_V << SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_1_S)
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_1_V  0x3FFFFFFFU
 #define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_1_S  0
 
-#define SENSITIVE_REGION_PMS_CONSTRAIN_5_REG          (DR_REG_SENSITIVE_BASE + 0x138)
-/* SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_2 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
-/*description: Need add description.*/
-#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_2    0x3FFFFFFF
-#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_2_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_2_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_2_S))
-#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_2_V  0x3FFFFFFF
+/** SENSITIVE_REGION_PMS_CONSTRAIN_5_REG register
+ *  register description
+ */
+#define SENSITIVE_REGION_PMS_CONSTRAIN_5_REG (DR_REG_SENSITIVE_BASE + 0x138)
+/** SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_2 : R/W; bitpos: [29:0]; default: 0;
+ *  Need add description
+ */
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_2    0x3FFFFFFFU
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_2_M  (SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_2_V << SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_2_S)
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_2_V  0x3FFFFFFFU
 #define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_2_S  0
 
-#define SENSITIVE_REGION_PMS_CONSTRAIN_6_REG          (DR_REG_SENSITIVE_BASE + 0x13C)
-/* SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_3 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
-/*description: Need add description.*/
-#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_3    0x3FFFFFFF
-#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_3_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_3_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_3_S))
-#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_3_V  0x3FFFFFFF
+/** SENSITIVE_REGION_PMS_CONSTRAIN_6_REG register
+ *  register description
+ */
+#define SENSITIVE_REGION_PMS_CONSTRAIN_6_REG (DR_REG_SENSITIVE_BASE + 0x13c)
+/** SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_3 : R/W; bitpos: [29:0]; default: 0;
+ *  Need add description
+ */
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_3    0x3FFFFFFFU
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_3_M  (SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_3_V << SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_3_S)
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_3_V  0x3FFFFFFFU
 #define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_3_S  0
 
-#define SENSITIVE_REGION_PMS_CONSTRAIN_7_REG          (DR_REG_SENSITIVE_BASE + 0x140)
-/* SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_4 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
-/*description: Need add description.*/
-#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_4    0x3FFFFFFF
-#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_4_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_4_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_4_S))
-#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_4_V  0x3FFFFFFF
+/** SENSITIVE_REGION_PMS_CONSTRAIN_7_REG register
+ *  register description
+ */
+#define SENSITIVE_REGION_PMS_CONSTRAIN_7_REG (DR_REG_SENSITIVE_BASE + 0x140)
+/** SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_4 : R/W; bitpos: [29:0]; default: 0;
+ *  Need add description
+ */
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_4    0x3FFFFFFFU
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_4_M  (SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_4_V << SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_4_S)
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_4_V  0x3FFFFFFFU
 #define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_4_S  0
 
-#define SENSITIVE_REGION_PMS_CONSTRAIN_8_REG          (DR_REG_SENSITIVE_BASE + 0x144)
-/* SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_5 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
-/*description: Need add description.*/
-#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_5    0x3FFFFFFF
-#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_5_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_5_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_5_S))
-#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_5_V  0x3FFFFFFF
+/** SENSITIVE_REGION_PMS_CONSTRAIN_8_REG register
+ *  register description
+ */
+#define SENSITIVE_REGION_PMS_CONSTRAIN_8_REG (DR_REG_SENSITIVE_BASE + 0x144)
+/** SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_5 : R/W; bitpos: [29:0]; default: 0;
+ *  Need add description
+ */
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_5    0x3FFFFFFFU
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_5_M  (SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_5_V << SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_5_S)
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_5_V  0x3FFFFFFFU
 #define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_5_S  0
 
-#define SENSITIVE_REGION_PMS_CONSTRAIN_9_REG          (DR_REG_SENSITIVE_BASE + 0x148)
-/* SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_6 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
-/*description: Need add description.*/
-#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_6    0x3FFFFFFF
-#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_6_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_6_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_6_S))
-#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_6_V  0x3FFFFFFF
+/** SENSITIVE_REGION_PMS_CONSTRAIN_9_REG register
+ *  register description
+ */
+#define SENSITIVE_REGION_PMS_CONSTRAIN_9_REG (DR_REG_SENSITIVE_BASE + 0x148)
+/** SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_6 : R/W; bitpos: [29:0]; default: 0;
+ *  Need add description
+ */
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_6    0x3FFFFFFFU
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_6_M  (SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_6_V << SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_6_S)
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_6_V  0x3FFFFFFFU
 #define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_6_S  0
 
-#define SENSITIVE_REGION_PMS_CONSTRAIN_10_REG          (DR_REG_SENSITIVE_BASE + 0x14C)
-/* SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_7 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
-/*description: Need add description.*/
-#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_7    0x3FFFFFFF
-#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_7_M  ((SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_7_V)<<(SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_7_S))
-#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_7_V  0x3FFFFFFF
+/** SENSITIVE_REGION_PMS_CONSTRAIN_10_REG register
+ *  register description
+ */
+#define SENSITIVE_REGION_PMS_CONSTRAIN_10_REG (DR_REG_SENSITIVE_BASE + 0x14c)
+/** SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_7 : R/W; bitpos: [29:0]; default: 0;
+ *  Need add description
+ */
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_7    0x3FFFFFFFU
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_7_M  (SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_7_V << SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_7_S)
+#define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_7_V  0x3FFFFFFFU
 #define SENSITIVE_REGION_PMS_CONSTRAIN_ADDR_7_S  0
 
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_0_REG          (DR_REG_SENSITIVE_BASE + 0x150)
-/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Need add description.*/
+/** SENSITIVE_CORE_0_PIF_PMS_MONITOR_0_REG register
+ *  register description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_0_REG (DR_REG_SENSITIVE_BASE + 0x150)
+/** SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK : R/W; bitpos: [0]; default: 0;
+ *  Need add description
+ */
 #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK    (BIT(0))
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK_M  (BIT(0))
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK_V  0x1
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK_M  (SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK_V << SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK_S)
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK_V  0x00000001U
 #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK_S  0
 
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG          (DR_REG_SENSITIVE_BASE + 0x154)
-/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN    (BIT(1))
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN_M  (BIT(1))
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN_V  0x1
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN_S  1
-/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: Need add description.*/
+/** SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG register
+ *  register description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG (DR_REG_SENSITIVE_BASE + 0x154)
+/** SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR : R/W; bitpos: [0]; default: 1;
+ *  Need add description
+ */
 #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR    (BIT(0))
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR_M  (BIT(0))
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR_V  0x1
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR_M  (SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR_V << SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR_S)
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR_V  0x00000001U
 #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR_S  0
+/** SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN : R/W; bitpos: [1]; default: 1;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN    (BIT(1))
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN_M  (SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN_V << SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN_S)
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN_V  0x00000001U
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN_S  1
 
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_REG          (DR_REG_SENSITIVE_BASE + 0x158)
-/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD : RO ;bitpos:[7:6] ;default: 2'b0 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_M  ((SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_V)<<(SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_S))
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_S  6
-/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE : RO ;bitpos:[5] ;default: 1'b0 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE    (BIT(5))
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_M  (BIT(5))
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_V  0x1
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_S  5
-/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE : RO ;bitpos:[4:2] ;default: 3'b0 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE    0x00000007
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_M  ((SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_V)<<(SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_S))
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_V  0x7
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_S  2
-/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0 : RO ;bitpos:[1] ;default: 1'b0 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0    (BIT(1))
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_M  (BIT(1))
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_V  0x1
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_S  1
-/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Need add description.*/
+/** SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_REG register
+ *  register description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_REG (DR_REG_SENSITIVE_BASE + 0x158)
+/** SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR : RO; bitpos: [0]; default: 0;
+ *  Need add description
+ */
 #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR    (BIT(0))
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_M  (BIT(0))
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_V  0x1
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_M  (SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_V << SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_S)
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_V  0x00000001U
 #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_S  0
+/** SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0 : RO; bitpos: [1]; default:
+ *  0;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0    (BIT(1))
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_M  (SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_V << SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_S)
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_V  0x00000001U
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_S  1
+/** SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE : RO; bitpos: [4:2]; default:
+ *  0;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE    0x00000007U
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_M  (SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_V << SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_S)
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_V  0x00000007U
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_S  2
+/** SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE : RO; bitpos: [5]; default:
+ *  0;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE    (BIT(5))
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_M  (SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_V << SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_S)
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_V  0x00000001U
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_S  5
+/** SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD : RO; bitpos: [7:6];
+ *  default: 0;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_M  (SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_V << SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_S)
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_V  0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_S  6
 
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_3_REG          (DR_REG_SENSITIVE_BASE + 0x15C)
-/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR    0xFFFFFFFF
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_M  ((SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_V)<<(SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_S))
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_V  0xFFFFFFFF
+/** SENSITIVE_CORE_0_PIF_PMS_MONITOR_3_REG register
+ *  register description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_3_REG (DR_REG_SENSITIVE_BASE + 0x15c)
+/** SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR : RO; bitpos: [31:0];
+ *  default: 0;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR    0xFFFFFFFFU
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_M  (SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_V << SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_S)
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_V  0xFFFFFFFFU
 #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_S  0
 
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_4_REG          (DR_REG_SENSITIVE_BASE + 0x160)
-/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN    (BIT(1))
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_M  (BIT(1))
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_V  0x1
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_S  1
-/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: Need add description.*/
+/** SENSITIVE_CORE_0_PIF_PMS_MONITOR_4_REG register
+ *  register description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_4_REG (DR_REG_SENSITIVE_BASE + 0x160)
+/** SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR : R/W; bitpos: [0]; default: 1;
+ *  Need add description
+ */
 #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR    (BIT(0))
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_M  (BIT(0))
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_V  0x1
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_M  (SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_V << SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_S)
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_V  0x00000001U
 #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_S  0
+/** SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN : R/W; bitpos: [1]; default: 1;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN    (BIT(1))
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_M  (SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_V << SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_S)
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_V  0x00000001U
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_S  1
 
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_5_REG          (DR_REG_SENSITIVE_BASE + 0x164)
-/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD : RO ;bitpos:[4:3] ;default: 2'b0 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_M  ((SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_V)<<(SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_S))
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_S  3
-/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE : RO ;bitpos:[2:1] ;default: 2'b0 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE    0x00000003
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_M  ((SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_V)<<(SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_S))
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_V  0x3
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_S  1
-/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Need add description.*/
+/** SENSITIVE_CORE_0_PIF_PMS_MONITOR_5_REG register
+ *  register description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_5_REG (DR_REG_SENSITIVE_BASE + 0x164)
+/** SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR : RO; bitpos: [0]; default: 0;
+ *  Need add description
+ */
 #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR    (BIT(0))
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_M  (BIT(0))
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_V  0x1
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_M  (SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_V << SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_S)
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_V  0x00000001U
 #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_S  0
+/** SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE : RO; bitpos: [2:1];
+ *  default: 0;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_M  (SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_V << SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_S)
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_V  0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_S  1
+/** SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD : RO; bitpos: [4:3];
+ *  default: 0;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD    0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_M  (SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_V << SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_S)
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_V  0x00000003U
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_S  3
 
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_6_REG          (DR_REG_SENSITIVE_BASE + 0x168)
-/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: Need add description.*/
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR    0xFFFFFFFF
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_M  ((SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_V)<<(SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_S))
-#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_V  0xFFFFFFFF
+/** SENSITIVE_CORE_0_PIF_PMS_MONITOR_6_REG register
+ *  register description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_6_REG (DR_REG_SENSITIVE_BASE + 0x168)
+/** SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR : RO; bitpos: [31:0];
+ *  default: 0;
+ *  Need add description
+ */
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR    0xFFFFFFFFU
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_M  (SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_V << SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_S)
+#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_V  0xFFFFFFFFU
 #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_S  0
 
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x16C)
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Need add description.*/
+/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_0_REG register
+ *  register description
+ */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x16c)
+/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LOCK : R/W; bitpos: [0]; default: 0;
+ *  Need add description
+ */
 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LOCK    (BIT(0))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LOCK_M  (BIT(0))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LOCK_V  0x1
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LOCK_M  (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LOCK_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LOCK_S)
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LOCK_V  0x00000001U
 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LOCK_S  0
 
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x170)
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1 : R/W ;bitpos:[31:30] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1_S  30
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C : R/W ;bitpos:[27:26] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_S  26
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC : R/W ;bitpos:[25:24] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC_S  24
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WDG : R/W ;bitpos:[19:18] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WDG    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WDG_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WDG_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WDG_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WDG_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WDG_S  18
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX : R/W ;bitpos:[17:16] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX_S  16
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC : R/W ;bitpos:[15:14] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_S  14
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE : R/W ;bitpos:[11:10] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE_S  10
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO : R/W ;bitpos:[7:6] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO_S  6
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0 : R/W ;bitpos:[5:4] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_S  4
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1 : R/W ;bitpos:[3:2] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1_S  2
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART : R/W ;bitpos:[1:0] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART_V  0x3
+/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_REG register
+ *  register description
+ */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x170)
+/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART : R/W; bitpos: [1:0]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART    0x00000003U
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART_M  (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART_S)
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART_V  0x00000003U
 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART_S  0
+/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1 : R/W; bitpos: [3:2]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1    0x00000003U
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1_M  (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1_S)
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1_V  0x00000003U
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1_S  2
+/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0 : R/W; bitpos: [5:4]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0    0x00000003U
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_M  (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_S)
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_V  0x00000003U
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_S  4
+/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO : R/W; bitpos: [7:6]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO    0x00000003U
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO_M  (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO_S)
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO_V  0x00000003U
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO_S  6
+/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE : R/W; bitpos: [11:10]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE    0x00000003U
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE_M  (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE_S)
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE_V  0x00000003U
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE_S  10
+/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC : R/W; bitpos: [15:14]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC    0x00000003U
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_M  (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_S)
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_V  0x00000003U
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_S  14
+/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX : R/W; bitpos: [17:16]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX    0x00000003U
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX_M  (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX_S)
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX_V  0x00000003U
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX_S  16
+/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WDG : R/W; bitpos: [19:18]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WDG    0x00000003U
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WDG_M  (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WDG_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WDG_S)
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WDG_V  0x00000003U
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WDG_S  18
+/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC : R/W; bitpos: [25:24]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC    0x00000003U
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC_M  (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC_S)
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC_V  0x00000003U
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC_S  24
+/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C : R/W; bitpos: [27:26]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C    0x00000003U
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_M  (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_S)
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_V  0x00000003U
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_S  26
+/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1 : R/W; bitpos: [31:30]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1    0x00000003U
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1_M  (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1_S)
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1_V  0x00000003U
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1_S  30
 
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_REG          (DR_REG_SENSITIVE_BASE + 0x174)
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER : R/W ;bitpos:[31:30] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_S  30
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1 : R/W ;bitpos:[29:28] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1_S  28
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP : R/W ;bitpos:[27:26] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_S  26
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_EFUSE : R/W ;bitpos:[19:18] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_EFUSE    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_EFUSE_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_EFUSE_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_EFUSE_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_EFUSE_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_EFUSE_S  18
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC : R/W ;bitpos:[17:16] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC_S  16
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT : R/W ;bitpos:[11:10] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT_S  10
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0 : R/W ;bitpos:[7:6] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0_S  6
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0 : R/W ;bitpos:[5:4] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_S  4
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT : R/W ;bitpos:[1:0] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_V  0x3
+/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_REG register
+ *  register description
+ */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_REG (DR_REG_SENSITIVE_BASE + 0x174)
+/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT : R/W; bitpos: [1:0]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT    0x00000003U
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_M  (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_S)
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_V  0x00000003U
 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_S  0
+/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0 : R/W; bitpos: [5:4]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0    0x00000003U
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_M  (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_S)
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_V  0x00000003U
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_S  4
+/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0 : R/W; bitpos: [7:6]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0    0x00000003U
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0_M  (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0_S)
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0_V  0x00000003U
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0_S  6
+/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT : R/W; bitpos: [11:10]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT    0x00000003U
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT_M  (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT_S)
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT_V  0x00000003U
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT_S  10
+/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC : R/W; bitpos: [17:16]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC    0x00000003U
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC_M  (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC_S)
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC_V  0x00000003U
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC_S  16
+/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_EFUSE : R/W; bitpos: [19:18]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_EFUSE    0x00000003U
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_EFUSE_M  (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_EFUSE_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_EFUSE_S)
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_EFUSE_V  0x00000003U
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_EFUSE_S  18
+/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP : R/W; bitpos: [27:26]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP    0x00000003U
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_M  (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_S)
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_V  0x00000003U
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_S  26
+/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1 : R/W; bitpos: [29:28]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1    0x00000003U
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1_M  (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1_S)
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1_V  0x00000003U
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1_S  28
+/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER : R/W; bitpos: [31:30]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER    0x00000003U
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_M  (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_S)
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_V  0x00000003U
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_S  30
 
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_3_REG          (DR_REG_SENSITIVE_BASE + 0x178)
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT : R/W ;bitpos:[23:22] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT_S  22
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1 : R/W ;bitpos:[15:14] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_S  14
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN : R/W ;bitpos:[11:10] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN_S  10
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL : R/W ;bitpos:[5:4] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL_S  4
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2 : R/W ;bitpos:[1:0] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2_V  0x3
+/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_3_REG register
+ *  register description
+ */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_3_REG (DR_REG_SENSITIVE_BASE + 0x178)
+/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2 : R/W; bitpos: [1:0]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2    0x00000003U
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2_M  (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2_S)
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2_V  0x00000003U
 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2_S  0
+/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL : R/W; bitpos: [5:4]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL    0x00000003U
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL_M  (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL_S)
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL_V  0x00000003U
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL_S  4
+/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TWAI : R/W; bitpos: [11:10]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TWAI    0x00000003U
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TWAI_M  (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TWAI_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TWAI_S)
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TWAI_V  0x00000003U
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TWAI_S  10
+/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1 : R/W; bitpos: [15:14]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1    0x00000003U
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_M  (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_S)
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_V  0x00000003U
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_S  14
+/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT : R/W; bitpos: [23:22]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT    0x00000003U
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT_M  (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT_S)
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT_V  0x00000003U
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT_S  22
 
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_REG          (DR_REG_SENSITIVE_BASE + 0x17C)
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CLKRST : R/W ;bitpos:[31:30] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CLKRST    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CLKRST_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CLKRST_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CLKRST_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CLKRST_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CLKRST_S  30
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_BLE_TMR : R/W ;bitpos:[29:28] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_BLE_TMR    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_BLE_TMR_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_BLE_TMR_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_BLE_TMR_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_BLE_TMR_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_BLE_TMR_S  28
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_COEX : R/W ;bitpos:[27:26] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_COEX    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_COEX_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_COEX_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_COEX_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_COEX_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_COEX_S  26
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_ZIGBEEMAC : R/W ;bitpos:[23:22] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_ZIGBEEMAC    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_ZIGBEEMAC_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_ZIGBEEMAC_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_ZIGBEEMAC_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_ZIGBEEMAC_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_ZIGBEEMAC_S  22
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BLE_SEC : R/W ;bitpos:[21:20] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BLE_SEC    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BLE_SEC_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BLE_SEC_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BLE_SEC_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BLE_SEC_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BLE_SEC_S  20
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP3 : R/W ;bitpos:[19:18] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP3    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP3_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP3_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP3_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP3_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP3_S  18
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_ETM : R/W ;bitpos:[17:16] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_ETM    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_ETM_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_ETM_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_ETM_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_ETM_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_ETM_S  16
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE : R/W ;bitpos:[15:14] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_S  14
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC : R/W ;bitpos:[9:8] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC_S  8
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA : R/W ;bitpos:[7:6] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA_S  6
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI : R/W ;bitpos:[5:4] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_V  0x3
+/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_REG register
+ *  register description
+ */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_REG (DR_REG_SENSITIVE_BASE + 0x17c)
+/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI : R/W; bitpos: [5:4]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI    0x00000003U
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_M  (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_S)
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_V  0x00000003U
 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_S  4
+/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA : R/W; bitpos: [7:6]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA    0x00000003U
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA_M  (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA_S)
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA_V  0x00000003U
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA_S  6
+/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC : R/W; bitpos: [9:8]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC    0x00000003U
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC_M  (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC_S)
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC_V  0x00000003U
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC_S  8
+/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE : R/W; bitpos: [15:14]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE    0x00000003U
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_M  (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_S)
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_V  0x00000003U
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_S  14
+/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_ETM : R/W; bitpos: [17:16]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_ETM    0x00000003U
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_ETM_M  (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_ETM_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_ETM_S)
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_ETM_V  0x00000003U
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_ETM_S  16
+/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP3 : R/W; bitpos: [19:18]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP3    0x00000003U
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP3_M  (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP3_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP3_S)
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP3_V  0x00000003U
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP3_S  18
+/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BLE_SEC : R/W; bitpos: [21:20]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BLE_SEC    0x00000003U
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BLE_SEC_M  (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BLE_SEC_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BLE_SEC_S)
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BLE_SEC_V  0x00000003U
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BLE_SEC_S  20
+/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IEEE802154MAC : R/W; bitpos: [23:22]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IEEE802154MAC    0x00000003U
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IEEE802154MAC_M  (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IEEE802154MAC_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IEEE802154MAC_S)
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IEEE802154MAC_V  0x00000003U
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IEEE802154MAC_S  22
+/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_COEX : R/W; bitpos: [27:26]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_COEX    0x00000003U
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_COEX_M  (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_COEX_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_COEX_S)
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_COEX_V  0x00000003U
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_COEX_S  26
+/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_BLE_TMR : R/W; bitpos: [29:28]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_BLE_TMR    0x00000003U
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_BLE_TMR_M  (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_BLE_TMR_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_BLE_TMR_S)
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_BLE_TMR_V  0x00000003U
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_BLE_TMR_S  28
+/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CLKRST : R/W; bitpos: [31:30]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CLKRST    0x00000003U
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CLKRST_M  (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CLKRST_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CLKRST_S)
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CLKRST_V  0x00000003U
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CLKRST_S  30
 
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_5_REG          (DR_REG_SENSITIVE_BASE + 0x180)
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MODEM_WIDGETS : R/W ;bitpos:[3:2] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MODEM_WIDGETS    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MODEM_WIDGETS_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MODEM_WIDGETS_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MODEM_WIDGETS_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MODEM_WIDGETS_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MODEM_WIDGETS_S  2
-/* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PVT : R/W ;bitpos:[1:0] ;default: 2'b11 ; */
-/*description: Need add description.*/
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PVT    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PVT_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PVT_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PVT_S))
-#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PVT_V  0x3
+/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_5_REG register
+ *  register description
+ */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_5_REG (DR_REG_SENSITIVE_BASE + 0x180)
+/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PVT : R/W; bitpos: [1:0]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PVT    0x00000003U
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PVT_M  (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PVT_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PVT_S)
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PVT_V  0x00000003U
 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PVT_S  0
+/** SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MODEM_WIDGETS : R/W; bitpos: [3:2]; default: 3;
+ *  Need add description
+ */
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MODEM_WIDGETS    0x00000003U
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MODEM_WIDGETS_M  (SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MODEM_WIDGETS_V << SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MODEM_WIDGETS_S)
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MODEM_WIDGETS_V  0x00000003U
+#define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MODEM_WIDGETS_S  2
 
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_0_REG          (DR_REG_SENSITIVE_BASE + 0x184)
-/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Need add description.*/
+/** SENSITIVE_BACKUP_BUS_PMS_MONITOR_0_REG register
+ *  register description
+ */
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_0_REG (DR_REG_SENSITIVE_BASE + 0x184)
+/** SENSITIVE_BACKUP_BUS_PMS_MONITOR_LOCK : R/W; bitpos: [0]; default: 0;
+ *  Need add description
+ */
 #define SENSITIVE_BACKUP_BUS_PMS_MONITOR_LOCK    (BIT(0))
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_LOCK_M  (BIT(0))
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_LOCK_V  0x1
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_LOCK_M  (SENSITIVE_BACKUP_BUS_PMS_MONITOR_LOCK_V << SENSITIVE_BACKUP_BUS_PMS_MONITOR_LOCK_S)
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_LOCK_V  0x00000001U
 #define SENSITIVE_BACKUP_BUS_PMS_MONITOR_LOCK_S  0
 
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_1_REG          (DR_REG_SENSITIVE_BASE + 0x188)
-/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
-/*description: Need add description.*/
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN    (BIT(1))
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN_M  (BIT(1))
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN_V  0x1
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN_S  1
-/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: Need add description.*/
+/** SENSITIVE_BACKUP_BUS_PMS_MONITOR_1_REG register
+ *  register description
+ */
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_1_REG (DR_REG_SENSITIVE_BASE + 0x188)
+/** SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR : R/W; bitpos: [0]; default: 1;
+ *  Need add description
+ */
 #define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR    (BIT(0))
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR_M  (BIT(0))
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR_V  0x1
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR_M  (SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR_V << SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR_S)
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR_V  0x00000001U
 #define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR_S  0
+/** SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN : R/W; bitpos: [1]; default: 1;
+ *  Need add description
+ */
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN    (BIT(1))
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN_M  (SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN_V << SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN_S)
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN_V  0x00000001U
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN_S  1
 
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_2_REG          (DR_REG_SENSITIVE_BASE + 0x18C)
-/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE : RO ;bitpos:[6] ;default: 1'b0 ; */
-/*description: Need add description.*/
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE    (BIT(6))
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE_M  (BIT(6))
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE_V  0x1
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE_S  6
-/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE : RO ;bitpos:[5:3] ;default: 3'b0 ; */
-/*description: Need add description.*/
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE    0x00000007
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE_M  ((SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE_V)<<(SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE_S))
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE_V  0x7
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE_S  3
-/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS : RO ;bitpos:[2:1] ;default: 2'b0 ; */
-/*description: Need add description.*/
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS    0x00000003
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS_M  ((SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS_V)<<(SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS_S))
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS_V  0x3
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS_S  1
-/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */
-/*description: Need add description.*/
+/** SENSITIVE_BACKUP_BUS_PMS_MONITOR_2_REG register
+ *  register description
+ */
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_2_REG (DR_REG_SENSITIVE_BASE + 0x18c)
+/** SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR : RO; bitpos: [0]; default: 0;
+ *  Need add description
+ */
 #define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR    (BIT(0))
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR_M  (BIT(0))
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR_V  0x1
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR_M  (SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR_V << SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR_S)
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR_V  0x00000001U
 #define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR_S  0
+/** SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS : RO; bitpos: [2:1];
+ *  default: 0;
+ *  Need add description
+ */
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS    0x00000003U
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS_M  (SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS_V << SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS_S)
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS_V  0x00000003U
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS_S  1
+/** SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE : RO; bitpos: [5:3]; default:
+ *  0;
+ *  Need add description
+ */
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE    0x00000007U
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE_M  (SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE_V << SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE_S)
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE_V  0x00000007U
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE_S  3
+/** SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE : RO; bitpos: [6]; default:
+ *  0;
+ *  Need add description
+ */
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE    (BIT(6))
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE_M  (SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE_V << SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE_S)
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE_V  0x00000001U
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE_S  6
 
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_3_REG          (DR_REG_SENSITIVE_BASE + 0x190)
-/* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
-/*description: Need add description.*/
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR    0xFFFFFFFF
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR_M  ((SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR_V)<<(SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR_S))
-#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR_V  0xFFFFFFFF
+/** SENSITIVE_BACKUP_BUS_PMS_MONITOR_3_REG register
+ *  register description
+ */
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_3_REG (DR_REG_SENSITIVE_BASE + 0x190)
+/** SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR : RO; bitpos: [31:0]; default: 0;
+ *  Need add description
+ */
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR    0xFFFFFFFFU
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR_M  (SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR_V << SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR_S)
+#define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR_V  0xFFFFFFFFU
 #define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR_S  0
 
-#define SENSITIVE_CLOCK_GATE_REG          (DR_REG_SENSITIVE_BASE + 0x194)
-/* SENSITIVE_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
-/*description: Need add description.*/
+/** SENSITIVE_CLOCK_GATE_REG register
+ *  register description
+ */
+#define SENSITIVE_CLOCK_GATE_REG (DR_REG_SENSITIVE_BASE + 0x194)
+/** SENSITIVE_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Need add description
+ */
 #define SENSITIVE_CLK_EN    (BIT(0))
-#define SENSITIVE_CLK_EN_M  (BIT(0))
-#define SENSITIVE_CLK_EN_V  0x1
+#define SENSITIVE_CLK_EN_M  (SENSITIVE_CLK_EN_V << SENSITIVE_CLK_EN_S)
+#define SENSITIVE_CLK_EN_V  0x00000001U
 #define SENSITIVE_CLK_EN_S  0
 
-#define SENSITIVE_DATE_REG          (DR_REG_SENSITIVE_BASE + 0xFFC)
-/* SENSITIVE_DATE : R/W ;bitpos:[27:0] ;default: 28'h2108250 ; */
-/*description: Need add description.*/
-#define SENSITIVE_DATE    0x0FFFFFFF
-#define SENSITIVE_DATE_M  ((SENSITIVE_DATE_V)<<(SENSITIVE_DATE_S))
-#define SENSITIVE_DATE_V  0xFFFFFFF
-#define SENSITIVE_DATE_S  0
-
+/** SENSITIVE_SENSITIVE_REG_DATE_REG register
+ *  register description
+ */
+#define SENSITIVE_SENSITIVE_REG_DATE_REG (DR_REG_SENSITIVE_BASE + 0xffc)
+/** SENSITIVE_SENSITIVE_REG_DATE : R/W; bitpos: [27:0]; default: 34636368;
+ *  Need add description
+ */
+#define SENSITIVE_SENSITIVE_REG_DATE    0x0FFFFFFFU
+#define SENSITIVE_SENSITIVE_REG_DATE_M  (SENSITIVE_SENSITIVE_REG_DATE_V << SENSITIVE_SENSITIVE_REG_DATE_S)
+#define SENSITIVE_SENSITIVE_REG_DATE_V  0x0FFFFFFFU
+#define SENSITIVE_SENSITIVE_REG_DATE_S  0
 
 #ifdef __cplusplus
 }
 #endif
-
-
-
-#endif /*_SOC_SENSITIVE_REG_H_ */

components/soc/esp32h2/include/rev2/soc/sensitive_struct.h

@@ -0,0 +1,2809 @@
+/**
+ * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Configuration Registers */
+/** Type of rom_table_lock register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** rom_table_lock : R/W; bitpos: [0]; default: 0;
+         *  Need add description
+         */
+        uint32_t rom_table_lock:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} sensitive_rom_table_lock_reg_t;
+
+/** Type of rom_table register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** rom_table : R/W; bitpos: [31:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t rom_table:32;
+    };
+    uint32_t val;
+} sensitive_rom_table_reg_t;
+
+/** Type of privilege_mode_sel_lock register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** privilege_mode_sel_lock : R/W; bitpos: [0]; default: 0;
+         *  Need add description
+         */
+        uint32_t privilege_mode_sel_lock:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} sensitive_privilege_mode_sel_lock_reg_t;
+
+/** Type of privilege_mode_sel register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** privilege_mode_sel : R/W; bitpos: [0]; default: 0;
+         *  Need add description
+         */
+        uint32_t privilege_mode_sel:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} sensitive_privilege_mode_sel_reg_t;
+
+/** Type of apb_peripheral_access_0 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** apb_peripheral_access_lock : R/W; bitpos: [0]; default: 0;
+         *  Need add description
+         */
+        uint32_t apb_peripheral_access_lock:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} sensitive_apb_peripheral_access_0_reg_t;
+
+/** Type of apb_peripheral_access_1 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** apb_peripheral_access_split_burst : R/W; bitpos: [0]; default: 1;
+         *  Need add description
+         */
+        uint32_t apb_peripheral_access_split_burst:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} sensitive_apb_peripheral_access_1_reg_t;
+
+/** Type of internal_sram_usage_0 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** internal_sram_usage_lock : R/W; bitpos: [0]; default: 0;
+         *  Need add description
+         */
+        uint32_t internal_sram_usage_lock:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} sensitive_internal_sram_usage_0_reg_t;
+
+/** Type of internal_sram_usage_1 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** internal_sram_usage_cpu_cache : R/W; bitpos: [0]; default: 1;
+         *  Need add description
+         */
+        uint32_t internal_sram_usage_cpu_cache:1;
+        /** internal_sram_usage_cpu_sram : R/W; bitpos: [3:1]; default: 7;
+         *  Need add description
+         */
+        uint32_t internal_sram_usage_cpu_sram:3;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} sensitive_internal_sram_usage_1_reg_t;
+
+/** Type of internal_sram_usage_3 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** internal_sram_usage_mac_dump_sram : R/W; bitpos: [2:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t internal_sram_usage_mac_dump_sram:3;
+        /** internal_sram_alloc_mac_dump : R/W; bitpos: [3]; default: 0;
+         *  Need add description
+         */
+        uint32_t internal_sram_alloc_mac_dump:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} sensitive_internal_sram_usage_3_reg_t;
+
+/** Type of internal_sram_usage_4 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** internal_sram_usage_log_sram : R/W; bitpos: [0]; default: 0;
+         *  Need add description
+         */
+        uint32_t internal_sram_usage_log_sram:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} sensitive_internal_sram_usage_4_reg_t;
+
+/** Type of cache_tag_access_0 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** cache_tag_access_lock : R/W; bitpos: [0]; default: 0;
+         *  Need add description
+         */
+        uint32_t cache_tag_access_lock:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} sensitive_cache_tag_access_0_reg_t;
+
+/** Type of cache_tag_access_1 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** pro_i_tag_rd_acs : R/W; bitpos: [0]; default: 1;
+         *  Need add description
+         */
+        uint32_t pro_i_tag_rd_acs:1;
+        /** pro_i_tag_wr_acs : R/W; bitpos: [1]; default: 1;
+         *  Need add description
+         */
+        uint32_t pro_i_tag_wr_acs:1;
+        /** pro_d_tag_rd_acs : R/W; bitpos: [2]; default: 1;
+         *  Need add description
+         */
+        uint32_t pro_d_tag_rd_acs:1;
+        /** pro_d_tag_wr_acs : R/W; bitpos: [3]; default: 1;
+         *  Need add description
+         */
+        uint32_t pro_d_tag_wr_acs:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} sensitive_cache_tag_access_1_reg_t;
+
+/** Type of cache_mmu_access_0 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** cache_mmu_access_lock : R/W; bitpos: [0]; default: 0;
+         *  Need add description
+         */
+        uint32_t cache_mmu_access_lock:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} sensitive_cache_mmu_access_0_reg_t;
+
+/** Type of cache_mmu_access_1 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** pro_mmu_rd_acs : R/W; bitpos: [0]; default: 1;
+         *  Need add description
+         */
+        uint32_t pro_mmu_rd_acs:1;
+        /** pro_mmu_wr_acs : R/W; bitpos: [1]; default: 1;
+         *  Need add description
+         */
+        uint32_t pro_mmu_wr_acs:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} sensitive_cache_mmu_access_1_reg_t;
+
+/** Type of dma_apbperi_spi2_pms_constrain_0 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** dma_apbperi_spi2_pms_constrain_lock : R/W; bitpos: [0]; default: 0;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_spi2_pms_constrain_lock:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} sensitive_dma_apbperi_spi2_pms_constrain_0_reg_t;
+
+/** Type of dma_apbperi_spi2_pms_constrain_1 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** dma_apbperi_spi2_pms_constrain_sram_world_0_pms_0 : R/W; bitpos: [1:0]; default: 3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_spi2_pms_constrain_sram_world_0_pms_0:2;
+        /** dma_apbperi_spi2_pms_constrain_sram_world_0_pms_1 : R/W; bitpos: [3:2]; default: 3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_spi2_pms_constrain_sram_world_0_pms_1:2;
+        /** dma_apbperi_spi2_pms_constrain_sram_world_0_pms_2 : R/W; bitpos: [5:4]; default: 3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_spi2_pms_constrain_sram_world_0_pms_2:2;
+        /** dma_apbperi_spi2_pms_constrain_sram_world_0_pms_3 : R/W; bitpos: [7:6]; default: 3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_spi2_pms_constrain_sram_world_0_pms_3:2;
+        uint32_t reserved_8:4;
+        /** dma_apbperi_spi2_pms_constrain_sram_world_1_pms_0 : R/W; bitpos: [13:12]; default:
+         *  3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_spi2_pms_constrain_sram_world_1_pms_0:2;
+        /** dma_apbperi_spi2_pms_constrain_sram_world_1_pms_1 : R/W; bitpos: [15:14]; default:
+         *  3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_spi2_pms_constrain_sram_world_1_pms_1:2;
+        /** dma_apbperi_spi2_pms_constrain_sram_world_1_pms_2 : R/W; bitpos: [17:16]; default:
+         *  3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_spi2_pms_constrain_sram_world_1_pms_2:2;
+        /** dma_apbperi_spi2_pms_constrain_sram_world_1_pms_3 : R/W; bitpos: [19:18]; default:
+         *  3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_spi2_pms_constrain_sram_world_1_pms_3:2;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} sensitive_dma_apbperi_spi2_pms_constrain_1_reg_t;
+
+/** Type of dma_apbperi_uchi0_pms_constrain_0 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** dma_apbperi_uchi0_pms_constrain_lock : R/W; bitpos: [0]; default: 0;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_uchi0_pms_constrain_lock:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} sensitive_dma_apbperi_uchi0_pms_constrain_0_reg_t;
+
+/** Type of dma_apbperi_uchi0_pms_constrain_1 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_0 : R/W; bitpos: [1:0]; default: 3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_0:2;
+        /** dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_1 : R/W; bitpos: [3:2]; default: 3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_1:2;
+        /** dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_2 : R/W; bitpos: [5:4]; default: 3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_2:2;
+        /** dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_3 : R/W; bitpos: [7:6]; default: 3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_3:2;
+        uint32_t reserved_8:4;
+        /** dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_0 : R/W; bitpos: [13:12]; default:
+         *  3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_0:2;
+        /** dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_1 : R/W; bitpos: [15:14]; default:
+         *  3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_1:2;
+        /** dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_2 : R/W; bitpos: [17:16]; default:
+         *  3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_2:2;
+        /** dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_3 : R/W; bitpos: [19:18]; default:
+         *  3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_3:2;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} sensitive_dma_apbperi_uchi0_pms_constrain_1_reg_t;
+
+/** Type of dma_apbperi_i2s0_pms_constrain_0 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** dma_apbperi_i2s0_pms_constrain_lock : R/W; bitpos: [0]; default: 0;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_i2s0_pms_constrain_lock:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} sensitive_dma_apbperi_i2s0_pms_constrain_0_reg_t;
+
+/** Type of dma_apbperi_i2s0_pms_constrain_1 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_0 : R/W; bitpos: [1:0]; default: 3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_0:2;
+        /** dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_1 : R/W; bitpos: [3:2]; default: 3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_1:2;
+        /** dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_2 : R/W; bitpos: [5:4]; default: 3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_2:2;
+        /** dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_3 : R/W; bitpos: [7:6]; default: 3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_3:2;
+        uint32_t reserved_8:4;
+        /** dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_0 : R/W; bitpos: [13:12]; default:
+         *  3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_0:2;
+        /** dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_1 : R/W; bitpos: [15:14]; default:
+         *  3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_1:2;
+        /** dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_2 : R/W; bitpos: [17:16]; default:
+         *  3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_2:2;
+        /** dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_3 : R/W; bitpos: [19:18]; default:
+         *  3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_3:2;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} sensitive_dma_apbperi_i2s0_pms_constrain_1_reg_t;
+
+/** Type of dma_apbperi_mac_pms_constrain_0 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** dma_apbperi_mac_pms_constrain_lock : R/W; bitpos: [0]; default: 0;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_mac_pms_constrain_lock:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} sensitive_dma_apbperi_mac_pms_constrain_0_reg_t;
+
+/** Type of dma_apbperi_mac_pms_constrain_1 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** dma_apbperi_mac_pms_constrain_sram_world_0_pms_0 : R/W; bitpos: [1:0]; default: 3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_mac_pms_constrain_sram_world_0_pms_0:2;
+        /** dma_apbperi_mac_pms_constrain_sram_world_0_pms_1 : R/W; bitpos: [3:2]; default: 3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_mac_pms_constrain_sram_world_0_pms_1:2;
+        /** dma_apbperi_mac_pms_constrain_sram_world_0_pms_2 : R/W; bitpos: [5:4]; default: 3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_mac_pms_constrain_sram_world_0_pms_2:2;
+        /** dma_apbperi_mac_pms_constrain_sram_world_0_pms_3 : R/W; bitpos: [7:6]; default: 3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_mac_pms_constrain_sram_world_0_pms_3:2;
+        uint32_t reserved_8:4;
+        /** dma_apbperi_mac_pms_constrain_sram_world_1_pms_0 : R/W; bitpos: [13:12]; default: 3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_mac_pms_constrain_sram_world_1_pms_0:2;
+        /** dma_apbperi_mac_pms_constrain_sram_world_1_pms_1 : R/W; bitpos: [15:14]; default: 3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_mac_pms_constrain_sram_world_1_pms_1:2;
+        /** dma_apbperi_mac_pms_constrain_sram_world_1_pms_2 : R/W; bitpos: [17:16]; default: 3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_mac_pms_constrain_sram_world_1_pms_2:2;
+        /** dma_apbperi_mac_pms_constrain_sram_world_1_pms_3 : R/W; bitpos: [19:18]; default: 3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_mac_pms_constrain_sram_world_1_pms_3:2;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} sensitive_dma_apbperi_mac_pms_constrain_1_reg_t;
+
+/** Type of dma_apbperi_backup_pms_constrain_0 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** dma_apbperi_backup_pms_constrain_lock : R/W; bitpos: [0]; default: 0;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_backup_pms_constrain_lock:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} sensitive_dma_apbperi_backup_pms_constrain_0_reg_t;
+
+/** Type of dma_apbperi_backup_pms_constrain_1 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** dma_apbperi_backup_pms_constrain_sram_world_0_pms_0 : R/W; bitpos: [1:0]; default:
+         *  3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_backup_pms_constrain_sram_world_0_pms_0:2;
+        /** dma_apbperi_backup_pms_constrain_sram_world_0_pms_1 : R/W; bitpos: [3:2]; default:
+         *  3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_backup_pms_constrain_sram_world_0_pms_1:2;
+        /** dma_apbperi_backup_pms_constrain_sram_world_0_pms_2 : R/W; bitpos: [5:4]; default:
+         *  3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_backup_pms_constrain_sram_world_0_pms_2:2;
+        /** dma_apbperi_backup_pms_constrain_sram_world_0_pms_3 : R/W; bitpos: [7:6]; default:
+         *  3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_backup_pms_constrain_sram_world_0_pms_3:2;
+        uint32_t reserved_8:4;
+        /** dma_apbperi_backup_pms_constrain_sram_world_1_pms_0 : R/W; bitpos: [13:12];
+         *  default: 3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_backup_pms_constrain_sram_world_1_pms_0:2;
+        /** dma_apbperi_backup_pms_constrain_sram_world_1_pms_1 : R/W; bitpos: [15:14];
+         *  default: 3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_backup_pms_constrain_sram_world_1_pms_1:2;
+        /** dma_apbperi_backup_pms_constrain_sram_world_1_pms_2 : R/W; bitpos: [17:16];
+         *  default: 3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_backup_pms_constrain_sram_world_1_pms_2:2;
+        /** dma_apbperi_backup_pms_constrain_sram_world_1_pms_3 : R/W; bitpos: [19:18];
+         *  default: 3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_backup_pms_constrain_sram_world_1_pms_3:2;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} sensitive_dma_apbperi_backup_pms_constrain_1_reg_t;
+
+/** Type of dma_apbperi_lc_pms_constrain_0 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** dma_apbperi_lc_pms_constrain_lock : R/W; bitpos: [0]; default: 0;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_lc_pms_constrain_lock:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} sensitive_dma_apbperi_lc_pms_constrain_0_reg_t;
+
+/** Type of dma_apbperi_lc_pms_constrain_1 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** dma_apbperi_lc_pms_constrain_sram_world_0_pms_0 : R/W; bitpos: [1:0]; default: 3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_lc_pms_constrain_sram_world_0_pms_0:2;
+        /** dma_apbperi_lc_pms_constrain_sram_world_0_pms_1 : R/W; bitpos: [3:2]; default: 3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_lc_pms_constrain_sram_world_0_pms_1:2;
+        /** dma_apbperi_lc_pms_constrain_sram_world_0_pms_2 : R/W; bitpos: [5:4]; default: 3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_lc_pms_constrain_sram_world_0_pms_2:2;
+        /** dma_apbperi_lc_pms_constrain_sram_world_0_pms_3 : R/W; bitpos: [7:6]; default: 3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_lc_pms_constrain_sram_world_0_pms_3:2;
+        uint32_t reserved_8:4;
+        /** dma_apbperi_lc_pms_constrain_sram_world_1_pms_0 : R/W; bitpos: [13:12]; default: 3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_lc_pms_constrain_sram_world_1_pms_0:2;
+        /** dma_apbperi_lc_pms_constrain_sram_world_1_pms_1 : R/W; bitpos: [15:14]; default: 3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_lc_pms_constrain_sram_world_1_pms_1:2;
+        /** dma_apbperi_lc_pms_constrain_sram_world_1_pms_2 : R/W; bitpos: [17:16]; default: 3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_lc_pms_constrain_sram_world_1_pms_2:2;
+        /** dma_apbperi_lc_pms_constrain_sram_world_1_pms_3 : R/W; bitpos: [19:18]; default: 3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_lc_pms_constrain_sram_world_1_pms_3:2;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} sensitive_dma_apbperi_lc_pms_constrain_1_reg_t;
+
+/** Type of dma_apbperi_aes_pms_constrain_0 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** dma_apbperi_aes_pms_constrain_lock : R/W; bitpos: [0]; default: 0;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_aes_pms_constrain_lock:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} sensitive_dma_apbperi_aes_pms_constrain_0_reg_t;
+
+/** Type of dma_apbperi_aes_pms_constrain_1 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** dma_apbperi_aes_pms_constrain_sram_world_0_pms_0 : R/W; bitpos: [1:0]; default: 3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_aes_pms_constrain_sram_world_0_pms_0:2;
+        /** dma_apbperi_aes_pms_constrain_sram_world_0_pms_1 : R/W; bitpos: [3:2]; default: 3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_aes_pms_constrain_sram_world_0_pms_1:2;
+        /** dma_apbperi_aes_pms_constrain_sram_world_0_pms_2 : R/W; bitpos: [5:4]; default: 3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_aes_pms_constrain_sram_world_0_pms_2:2;
+        /** dma_apbperi_aes_pms_constrain_sram_world_0_pms_3 : R/W; bitpos: [7:6]; default: 3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_aes_pms_constrain_sram_world_0_pms_3:2;
+        uint32_t reserved_8:4;
+        /** dma_apbperi_aes_pms_constrain_sram_world_1_pms_0 : R/W; bitpos: [13:12]; default: 3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_aes_pms_constrain_sram_world_1_pms_0:2;
+        /** dma_apbperi_aes_pms_constrain_sram_world_1_pms_1 : R/W; bitpos: [15:14]; default: 3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_aes_pms_constrain_sram_world_1_pms_1:2;
+        /** dma_apbperi_aes_pms_constrain_sram_world_1_pms_2 : R/W; bitpos: [17:16]; default: 3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_aes_pms_constrain_sram_world_1_pms_2:2;
+        /** dma_apbperi_aes_pms_constrain_sram_world_1_pms_3 : R/W; bitpos: [19:18]; default: 3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_aes_pms_constrain_sram_world_1_pms_3:2;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} sensitive_dma_apbperi_aes_pms_constrain_1_reg_t;
+
+/** Type of dma_apbperi_sha_pms_constrain_0 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** dma_apbperi_sha_pms_constrain_lock : R/W; bitpos: [0]; default: 0;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_sha_pms_constrain_lock:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} sensitive_dma_apbperi_sha_pms_constrain_0_reg_t;
+
+/** Type of dma_apbperi_sha_pms_constrain_1 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** dma_apbperi_sha_pms_constrain_sram_world_0_pms_0 : R/W; bitpos: [1:0]; default: 3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_sha_pms_constrain_sram_world_0_pms_0:2;
+        /** dma_apbperi_sha_pms_constrain_sram_world_0_pms_1 : R/W; bitpos: [3:2]; default: 3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_sha_pms_constrain_sram_world_0_pms_1:2;
+        /** dma_apbperi_sha_pms_constrain_sram_world_0_pms_2 : R/W; bitpos: [5:4]; default: 3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_sha_pms_constrain_sram_world_0_pms_2:2;
+        /** dma_apbperi_sha_pms_constrain_sram_world_0_pms_3 : R/W; bitpos: [7:6]; default: 3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_sha_pms_constrain_sram_world_0_pms_3:2;
+        uint32_t reserved_8:4;
+        /** dma_apbperi_sha_pms_constrain_sram_world_1_pms_0 : R/W; bitpos: [13:12]; default: 3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_sha_pms_constrain_sram_world_1_pms_0:2;
+        /** dma_apbperi_sha_pms_constrain_sram_world_1_pms_1 : R/W; bitpos: [15:14]; default: 3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_sha_pms_constrain_sram_world_1_pms_1:2;
+        /** dma_apbperi_sha_pms_constrain_sram_world_1_pms_2 : R/W; bitpos: [17:16]; default: 3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_sha_pms_constrain_sram_world_1_pms_2:2;
+        /** dma_apbperi_sha_pms_constrain_sram_world_1_pms_3 : R/W; bitpos: [19:18]; default: 3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_sha_pms_constrain_sram_world_1_pms_3:2;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} sensitive_dma_apbperi_sha_pms_constrain_1_reg_t;
+
+/** Type of dma_apbperi_adc_dac_pms_constrain_0 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** dma_apbperi_adc_dac_pms_constrain_lock : R/W; bitpos: [0]; default: 0;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_adc_dac_pms_constrain_lock:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} sensitive_dma_apbperi_adc_dac_pms_constrain_0_reg_t;
+
+/** Type of dma_apbperi_adc_dac_pms_constrain_1 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_0 : R/W; bitpos: [1:0]; default:
+         *  3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_0:2;
+        /** dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_1 : R/W; bitpos: [3:2]; default:
+         *  3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_1:2;
+        /** dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_2 : R/W; bitpos: [5:4]; default:
+         *  3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_2:2;
+        /** dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_3 : R/W; bitpos: [7:6]; default:
+         *  3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_3:2;
+        uint32_t reserved_8:4;
+        /** dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_0 : R/W; bitpos: [13:12];
+         *  default: 3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_0:2;
+        /** dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_1 : R/W; bitpos: [15:14];
+         *  default: 3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_1:2;
+        /** dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_2 : R/W; bitpos: [17:16];
+         *  default: 3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_2:2;
+        /** dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_3 : R/W; bitpos: [19:18];
+         *  default: 3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_3:2;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} sensitive_dma_apbperi_adc_dac_pms_constrain_1_reg_t;
+
+/** Type of dma_apbperi_ble_sec_pms_constrain_0 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** dma_apbperi_ble_sec_pms_constrain_lock : R/W; bitpos: [0]; default: 0;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_ble_sec_pms_constrain_lock:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} sensitive_dma_apbperi_ble_sec_pms_constrain_0_reg_t;
+
+/** Type of dma_apbperi_ble_sec_pms_constrain_1 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** dma_apbperi_ble_sec_pms_constrain_sram_world_0_pms_0 : R/W; bitpos: [1:0]; default:
+         *  3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_ble_sec_pms_constrain_sram_world_0_pms_0:2;
+        /** dma_apbperi_ble_sec_pms_constrain_sram_world_0_pms_1 : R/W; bitpos: [3:2]; default:
+         *  3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_ble_sec_pms_constrain_sram_world_0_pms_1:2;
+        /** dma_apbperi_ble_sec_pms_constrain_sram_world_0_pms_2 : R/W; bitpos: [5:4]; default:
+         *  3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_ble_sec_pms_constrain_sram_world_0_pms_2:2;
+        /** dma_apbperi_ble_sec_pms_constrain_sram_world_0_pms_3 : R/W; bitpos: [7:6]; default:
+         *  3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_ble_sec_pms_constrain_sram_world_0_pms_3:2;
+        uint32_t reserved_8:4;
+        /** dma_apbperi_ble_sec_pms_constrain_sram_world_1_pms_0 : R/W; bitpos: [13:12];
+         *  default: 3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_ble_sec_pms_constrain_sram_world_1_pms_0:2;
+        /** dma_apbperi_ble_sec_pms_constrain_sram_world_1_pms_1 : R/W; bitpos: [15:14];
+         *  default: 3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_ble_sec_pms_constrain_sram_world_1_pms_1:2;
+        /** dma_apbperi_ble_sec_pms_constrain_sram_world_1_pms_2 : R/W; bitpos: [17:16];
+         *  default: 3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_ble_sec_pms_constrain_sram_world_1_pms_2:2;
+        /** dma_apbperi_ble_sec_pms_constrain_sram_world_1_pms_3 : R/W; bitpos: [19:18];
+         *  default: 3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_ble_sec_pms_constrain_sram_world_1_pms_3:2;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} sensitive_dma_apbperi_ble_sec_pms_constrain_1_reg_t;
+
+/** Type of dma_apbperi_white_list_pms_constrain_0 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** dma_apbperi_white_list_pms_constrain_lock : R/W; bitpos: [0]; default: 0;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_white_list_pms_constrain_lock:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} sensitive_dma_apbperi_white_list_pms_constrain_0_reg_t;
+
+/** Type of dma_apbperi_white_list_pms_constrain_1 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** dma_apbperi_white_list_pms_constrain_sram_world_0_pms_0 : R/W; bitpos: [1:0];
+         *  default: 3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_white_list_pms_constrain_sram_world_0_pms_0:2;
+        /** dma_apbperi_white_list_pms_constrain_sram_world_0_pms_1 : R/W; bitpos: [3:2];
+         *  default: 3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_white_list_pms_constrain_sram_world_0_pms_1:2;
+        /** dma_apbperi_white_list_pms_constrain_sram_world_0_pms_2 : R/W; bitpos: [5:4];
+         *  default: 3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_white_list_pms_constrain_sram_world_0_pms_2:2;
+        /** dma_apbperi_white_list_pms_constrain_sram_world_0_pms_3 : R/W; bitpos: [7:6];
+         *  default: 3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_white_list_pms_constrain_sram_world_0_pms_3:2;
+        uint32_t reserved_8:4;
+        /** dma_apbperi_white_list_pms_constrain_sram_world_1_pms_0 : R/W; bitpos: [13:12];
+         *  default: 3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_white_list_pms_constrain_sram_world_1_pms_0:2;
+        /** dma_apbperi_white_list_pms_constrain_sram_world_1_pms_1 : R/W; bitpos: [15:14];
+         *  default: 3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_white_list_pms_constrain_sram_world_1_pms_1:2;
+        /** dma_apbperi_white_list_pms_constrain_sram_world_1_pms_2 : R/W; bitpos: [17:16];
+         *  default: 3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_white_list_pms_constrain_sram_world_1_pms_2:2;
+        /** dma_apbperi_white_list_pms_constrain_sram_world_1_pms_3 : R/W; bitpos: [19:18];
+         *  default: 3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_white_list_pms_constrain_sram_world_1_pms_3:2;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} sensitive_dma_apbperi_white_list_pms_constrain_1_reg_t;
+
+/** Type of dma_apbperi_sdio_host_pms_constrain_0 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** dma_apbperi_sdio_host_pms_constrain_lock : R/W; bitpos: [0]; default: 0;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_sdio_host_pms_constrain_lock:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} sensitive_dma_apbperi_sdio_host_pms_constrain_0_reg_t;
+
+/** Type of dma_apbperi_sdio_host_pms_constrain_1 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** dma_apbperi_sdio_host_pms_constrain_sram_world_0_pms_0 : R/W; bitpos: [1:0];
+         *  default: 3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_sdio_host_pms_constrain_sram_world_0_pms_0:2;
+        /** dma_apbperi_sdio_host_pms_constrain_sram_world_0_pms_1 : R/W; bitpos: [3:2];
+         *  default: 3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_sdio_host_pms_constrain_sram_world_0_pms_1:2;
+        /** dma_apbperi_sdio_host_pms_constrain_sram_world_0_pms_2 : R/W; bitpos: [5:4];
+         *  default: 3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_sdio_host_pms_constrain_sram_world_0_pms_2:2;
+        /** dma_apbperi_sdio_host_pms_constrain_sram_world_0_pms_3 : R/W; bitpos: [7:6];
+         *  default: 3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_sdio_host_pms_constrain_sram_world_0_pms_3:2;
+        uint32_t reserved_8:4;
+        /** dma_apbperi_sdio_host_pms_constrain_sram_world_1_pms_0 : R/W; bitpos: [13:12];
+         *  default: 3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_sdio_host_pms_constrain_sram_world_1_pms_0:2;
+        /** dma_apbperi_sdio_host_pms_constrain_sram_world_1_pms_1 : R/W; bitpos: [15:14];
+         *  default: 3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_sdio_host_pms_constrain_sram_world_1_pms_1:2;
+        /** dma_apbperi_sdio_host_pms_constrain_sram_world_1_pms_2 : R/W; bitpos: [17:16];
+         *  default: 3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_sdio_host_pms_constrain_sram_world_1_pms_2:2;
+        /** dma_apbperi_sdio_host_pms_constrain_sram_world_1_pms_3 : R/W; bitpos: [19:18];
+         *  default: 3;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_sdio_host_pms_constrain_sram_world_1_pms_3:2;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} sensitive_dma_apbperi_sdio_host_pms_constrain_1_reg_t;
+
+/** Type of dma_apbperi_pms_monitor_0 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** dma_apbperi_pms_monitor_lock : R/W; bitpos: [0]; default: 0;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_pms_monitor_lock:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} sensitive_dma_apbperi_pms_monitor_0_reg_t;
+
+/** Type of dma_apbperi_pms_monitor_1 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** dma_apbperi_pms_monitor_violate_clr : R/W; bitpos: [0]; default: 1;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_pms_monitor_violate_clr:1;
+        /** dma_apbperi_pms_monitor_violate_en : R/W; bitpos: [1]; default: 1;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_pms_monitor_violate_en:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} sensitive_dma_apbperi_pms_monitor_1_reg_t;
+
+/** Type of dma_apbperi_pms_monitor_2 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** dma_apbperi_pms_monitor_violate_intr : RO; bitpos: [0]; default: 0;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_pms_monitor_violate_intr:1;
+        /** dma_apbperi_pms_monitor_violate_status_world : RO; bitpos: [2:1]; default: 0;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_pms_monitor_violate_status_world:2;
+        /** dma_apbperi_pms_monitor_violate_status_addr : RO; bitpos: [26:3]; default: 0;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_pms_monitor_violate_status_addr:24;
+        uint32_t reserved_27:5;
+    };
+    uint32_t val;
+} sensitive_dma_apbperi_pms_monitor_2_reg_t;
+
+/** Type of dma_apbperi_pms_monitor_3 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** dma_apbperi_pms_monitor_violate_status_wr : RO; bitpos: [0]; default: 0;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_pms_monitor_violate_status_wr:1;
+        /** dma_apbperi_pms_monitor_violate_status_byteen : RO; bitpos: [4:1]; default: 0;
+         *  Need add description
+         */
+        uint32_t dma_apbperi_pms_monitor_violate_status_byteen:4;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} sensitive_dma_apbperi_pms_monitor_3_reg_t;
+
+/** Type of core_x_iram0_dram0_dma_split_line_constrain_0 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** core_x_iram0_dram0_dma_split_line_constrain_lock : R/W; bitpos: [0]; default: 0;
+         *  Need add description
+         */
+        uint32_t core_x_iram0_dram0_dma_split_line_constrain_lock:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} sensitive_core_x_iram0_dram0_dma_split_line_constrain_0_reg_t;
+
+/** Type of core_x_iram0_dram0_dma_split_line_constrain_1 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** core_x_iram0_dram0_dma_sram_category_0 : R/W; bitpos: [1:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t core_x_iram0_dram0_dma_sram_category_0:2;
+        /** core_x_iram0_dram0_dma_sram_category_1 : R/W; bitpos: [3:2]; default: 0;
+         *  Need add description
+         */
+        uint32_t core_x_iram0_dram0_dma_sram_category_1:2;
+        /** core_x_iram0_dram0_dma_sram_category_2 : R/W; bitpos: [5:4]; default: 0;
+         *  Need add description
+         */
+        uint32_t core_x_iram0_dram0_dma_sram_category_2:2;
+        uint32_t reserved_6:8;
+        /** core_x_iram0_dram0_dma_sram_splitaddr : R/W; bitpos: [21:14]; default: 0;
+         *  Need add description
+         */
+        uint32_t core_x_iram0_dram0_dma_sram_splitaddr:8;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} sensitive_core_x_iram0_dram0_dma_split_line_constrain_1_reg_t;
+
+/** Type of core_x_iram0_dram0_dma_split_line_constrain_2 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** core_x_iram0_sram_line_0_category_0 : R/W; bitpos: [1:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t core_x_iram0_sram_line_0_category_0:2;
+        /** core_x_iram0_sram_line_0_category_1 : R/W; bitpos: [3:2]; default: 0;
+         *  Need add description
+         */
+        uint32_t core_x_iram0_sram_line_0_category_1:2;
+        /** core_x_iram0_sram_line_0_category_2 : R/W; bitpos: [5:4]; default: 0;
+         *  Need add description
+         */
+        uint32_t core_x_iram0_sram_line_0_category_2:2;
+        uint32_t reserved_6:8;
+        /** core_x_iram0_sram_line_0_splitaddr : R/W; bitpos: [21:14]; default: 0;
+         *  Need add description
+         */
+        uint32_t core_x_iram0_sram_line_0_splitaddr:8;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} sensitive_core_x_iram0_dram0_dma_split_line_constrain_2_reg_t;
+
+/** Type of core_x_iram0_dram0_dma_split_line_constrain_3 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** core_x_iram0_sram_line_1_category_0 : R/W; bitpos: [1:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t core_x_iram0_sram_line_1_category_0:2;
+        /** core_x_iram0_sram_line_1_category_1 : R/W; bitpos: [3:2]; default: 0;
+         *  Need add description
+         */
+        uint32_t core_x_iram0_sram_line_1_category_1:2;
+        /** core_x_iram0_sram_line_1_category_2 : R/W; bitpos: [5:4]; default: 0;
+         *  Need add description
+         */
+        uint32_t core_x_iram0_sram_line_1_category_2:2;
+        uint32_t reserved_6:8;
+        /** core_x_iram0_sram_line_1_splitaddr : R/W; bitpos: [21:14]; default: 0;
+         *  Need add description
+         */
+        uint32_t core_x_iram0_sram_line_1_splitaddr:8;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} sensitive_core_x_iram0_dram0_dma_split_line_constrain_3_reg_t;
+
+/** Type of core_x_iram0_dram0_dma_split_line_constrain_4 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** core_x_dram0_dma_sram_line_0_category_0 : R/W; bitpos: [1:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t core_x_dram0_dma_sram_line_0_category_0:2;
+        /** core_x_dram0_dma_sram_line_0_category_1 : R/W; bitpos: [3:2]; default: 0;
+         *  Need add description
+         */
+        uint32_t core_x_dram0_dma_sram_line_0_category_1:2;
+        /** core_x_dram0_dma_sram_line_0_category_2 : R/W; bitpos: [5:4]; default: 0;
+         *  Need add description
+         */
+        uint32_t core_x_dram0_dma_sram_line_0_category_2:2;
+        uint32_t reserved_6:8;
+        /** core_x_dram0_dma_sram_line_0_splitaddr : R/W; bitpos: [21:14]; default: 0;
+         *  Need add description
+         */
+        uint32_t core_x_dram0_dma_sram_line_0_splitaddr:8;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} sensitive_core_x_iram0_dram0_dma_split_line_constrain_4_reg_t;
+
+/** Type of core_x_iram0_dram0_dma_split_line_constrain_5 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** core_x_dram0_dma_sram_line_1_category_0 : R/W; bitpos: [1:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t core_x_dram0_dma_sram_line_1_category_0:2;
+        /** core_x_dram0_dma_sram_line_1_category_1 : R/W; bitpos: [3:2]; default: 0;
+         *  Need add description
+         */
+        uint32_t core_x_dram0_dma_sram_line_1_category_1:2;
+        /** core_x_dram0_dma_sram_line_1_category_2 : R/W; bitpos: [5:4]; default: 0;
+         *  Need add description
+         */
+        uint32_t core_x_dram0_dma_sram_line_1_category_2:2;
+        uint32_t reserved_6:8;
+        /** core_x_dram0_dma_sram_line_1_splitaddr : R/W; bitpos: [21:14]; default: 0;
+         *  Need add description
+         */
+        uint32_t core_x_dram0_dma_sram_line_1_splitaddr:8;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} sensitive_core_x_iram0_dram0_dma_split_line_constrain_5_reg_t;
+
+/** Type of core_x_iram0_pms_constrain_0 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** core_x_iram0_pms_constrain_lock : R/W; bitpos: [0]; default: 0;
+         *  Need add description
+         */
+        uint32_t core_x_iram0_pms_constrain_lock:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} sensitive_core_x_iram0_pms_constrain_0_reg_t;
+
+/** Type of core_x_iram0_pms_constrain_1 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** core_x_iram0_pms_constrain_sram_world_1_pms_0 : R/W; bitpos: [2:0]; default: 7;
+         *  Need add description
+         */
+        uint32_t core_x_iram0_pms_constrain_sram_world_1_pms_0:3;
+        /** core_x_iram0_pms_constrain_sram_world_1_pms_1 : R/W; bitpos: [5:3]; default: 7;
+         *  Need add description
+         */
+        uint32_t core_x_iram0_pms_constrain_sram_world_1_pms_1:3;
+        /** core_x_iram0_pms_constrain_sram_world_1_pms_2 : R/W; bitpos: [8:6]; default: 7;
+         *  Need add description
+         */
+        uint32_t core_x_iram0_pms_constrain_sram_world_1_pms_2:3;
+        /** core_x_iram0_pms_constrain_sram_world_1_pms_3 : R/W; bitpos: [11:9]; default: 7;
+         *  Need add description
+         */
+        uint32_t core_x_iram0_pms_constrain_sram_world_1_pms_3:3;
+        /** core_x_iram0_pms_constrain_sram_world_1_cachedataarray_pms_0 : R/W; bitpos:
+         *  [14:12]; default: 7;
+         *  Need add description
+         */
+        uint32_t core_x_iram0_pms_constrain_sram_world_1_cachedataarray_pms_0:3;
+        uint32_t reserved_15:3;
+        /** core_x_iram0_pms_constrain_rom_world_1_pms : R/W; bitpos: [20:18]; default: 7;
+         *  Need add description
+         */
+        uint32_t core_x_iram0_pms_constrain_rom_world_1_pms:3;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} sensitive_core_x_iram0_pms_constrain_1_reg_t;
+
+/** Type of core_x_iram0_pms_constrain_2 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** core_x_iram0_pms_constrain_sram_world_0_pms_0 : R/W; bitpos: [2:0]; default: 7;
+         *  Need add description
+         */
+        uint32_t core_x_iram0_pms_constrain_sram_world_0_pms_0:3;
+        /** core_x_iram0_pms_constrain_sram_world_0_pms_1 : R/W; bitpos: [5:3]; default: 7;
+         *  Need add description
+         */
+        uint32_t core_x_iram0_pms_constrain_sram_world_0_pms_1:3;
+        /** core_x_iram0_pms_constrain_sram_world_0_pms_2 : R/W; bitpos: [8:6]; default: 7;
+         *  Need add description
+         */
+        uint32_t core_x_iram0_pms_constrain_sram_world_0_pms_2:3;
+        /** core_x_iram0_pms_constrain_sram_world_0_pms_3 : R/W; bitpos: [11:9]; default: 7;
+         *  Need add description
+         */
+        uint32_t core_x_iram0_pms_constrain_sram_world_0_pms_3:3;
+        /** core_x_iram0_pms_constrain_sram_world_0_cachedataarray_pms_0 : R/W; bitpos:
+         *  [14:12]; default: 7;
+         *  Need add description
+         */
+        uint32_t core_x_iram0_pms_constrain_sram_world_0_cachedataarray_pms_0:3;
+        uint32_t reserved_15:3;
+        /** core_x_iram0_pms_constrain_rom_world_0_pms : R/W; bitpos: [20:18]; default: 7;
+         *  Need add description
+         */
+        uint32_t core_x_iram0_pms_constrain_rom_world_0_pms:3;
+        uint32_t reserved_21:11;
+    };
+    uint32_t val;
+} sensitive_core_x_iram0_pms_constrain_2_reg_t;
+
+/** Type of core_0_iram0_pms_monitor_0 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** core_0_iram0_pms_monitor_lock : R/W; bitpos: [0]; default: 0;
+         *  Need add description
+         */
+        uint32_t core_0_iram0_pms_monitor_lock:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} sensitive_core_0_iram0_pms_monitor_0_reg_t;
+
+/** Type of core_0_iram0_pms_monitor_1 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** core_0_iram0_pms_monitor_violate_clr : R/W; bitpos: [0]; default: 1;
+         *  Need add description
+         */
+        uint32_t core_0_iram0_pms_monitor_violate_clr:1;
+        /** core_0_iram0_pms_monitor_violate_en : R/W; bitpos: [1]; default: 1;
+         *  Need add description
+         */
+        uint32_t core_0_iram0_pms_monitor_violate_en:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} sensitive_core_0_iram0_pms_monitor_1_reg_t;
+
+/** Type of core_0_iram0_pms_monitor_2 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** core_0_iram0_pms_monitor_violate_intr : RO; bitpos: [0]; default: 0;
+         *  Need add description
+         */
+        uint32_t core_0_iram0_pms_monitor_violate_intr:1;
+        /** core_0_iram0_pms_monitor_violate_status_wr : RO; bitpos: [1]; default: 0;
+         *  Need add description
+         */
+        uint32_t core_0_iram0_pms_monitor_violate_status_wr:1;
+        /** core_0_iram0_pms_monitor_violate_status_loadstore : RO; bitpos: [2]; default: 0;
+         *  Need add description
+         */
+        uint32_t core_0_iram0_pms_monitor_violate_status_loadstore:1;
+        /** core_0_iram0_pms_monitor_violate_status_world : RO; bitpos: [4:3]; default: 0;
+         *  Need add description
+         */
+        uint32_t core_0_iram0_pms_monitor_violate_status_world:2;
+        /** core_0_iram0_pms_monitor_violate_status_addr : RO; bitpos: [28:5]; default: 0;
+         *  Need add description
+         */
+        uint32_t core_0_iram0_pms_monitor_violate_status_addr:24;
+        uint32_t reserved_29:3;
+    };
+    uint32_t val;
+} sensitive_core_0_iram0_pms_monitor_2_reg_t;
+
+/** Type of core_x_dram0_pms_constrain_0 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** core_x_dram0_pms_constrain_lock : R/W; bitpos: [0]; default: 0;
+         *  Need add description
+         */
+        uint32_t core_x_dram0_pms_constrain_lock:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} sensitive_core_x_dram0_pms_constrain_0_reg_t;
+
+/** Type of core_x_dram0_pms_constrain_1 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** core_x_dram0_pms_constrain_sram_world_0_pms_0 : R/W; bitpos: [1:0]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_x_dram0_pms_constrain_sram_world_0_pms_0:2;
+        /** core_x_dram0_pms_constrain_sram_world_0_pms_1 : R/W; bitpos: [3:2]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_x_dram0_pms_constrain_sram_world_0_pms_1:2;
+        /** core_x_dram0_pms_constrain_sram_world_0_pms_2 : R/W; bitpos: [5:4]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_x_dram0_pms_constrain_sram_world_0_pms_2:2;
+        /** core_x_dram0_pms_constrain_sram_world_0_pms_3 : R/W; bitpos: [7:6]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_x_dram0_pms_constrain_sram_world_0_pms_3:2;
+        uint32_t reserved_8:4;
+        /** core_x_dram0_pms_constrain_sram_world_1_pms_0 : R/W; bitpos: [13:12]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_x_dram0_pms_constrain_sram_world_1_pms_0:2;
+        /** core_x_dram0_pms_constrain_sram_world_1_pms_1 : R/W; bitpos: [15:14]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_x_dram0_pms_constrain_sram_world_1_pms_1:2;
+        /** core_x_dram0_pms_constrain_sram_world_1_pms_2 : R/W; bitpos: [17:16]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_x_dram0_pms_constrain_sram_world_1_pms_2:2;
+        /** core_x_dram0_pms_constrain_sram_world_1_pms_3 : R/W; bitpos: [19:18]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_x_dram0_pms_constrain_sram_world_1_pms_3:2;
+        uint32_t reserved_20:4;
+        /** core_x_dram0_pms_constrain_rom_world_0_pms : R/W; bitpos: [25:24]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_x_dram0_pms_constrain_rom_world_0_pms:2;
+        /** core_x_dram0_pms_constrain_rom_world_1_pms : R/W; bitpos: [27:26]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_x_dram0_pms_constrain_rom_world_1_pms:2;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} sensitive_core_x_dram0_pms_constrain_1_reg_t;
+
+/** Type of core_0_dram0_pms_monitor_0 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** core_0_dram0_pms_monitor_lock : R/W; bitpos: [0]; default: 0;
+         *  Need add description
+         */
+        uint32_t core_0_dram0_pms_monitor_lock:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} sensitive_core_0_dram0_pms_monitor_0_reg_t;
+
+/** Type of core_0_dram0_pms_monitor_1 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** core_0_dram0_pms_monitor_violate_clr : R/W; bitpos: [0]; default: 1;
+         *  Need add description
+         */
+        uint32_t core_0_dram0_pms_monitor_violate_clr:1;
+        /** core_0_dram0_pms_monitor_violate_en : R/W; bitpos: [1]; default: 1;
+         *  Need add description
+         */
+        uint32_t core_0_dram0_pms_monitor_violate_en:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} sensitive_core_0_dram0_pms_monitor_1_reg_t;
+
+/** Type of core_0_dram0_pms_monitor_2 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** core_0_dram0_pms_monitor_violate_intr : RO; bitpos: [0]; default: 0;
+         *  Need add description
+         */
+        uint32_t core_0_dram0_pms_monitor_violate_intr:1;
+        /** core_0_dram0_pms_monitor_violate_status_lock : RO; bitpos: [1]; default: 0;
+         *  Need add description
+         */
+        uint32_t core_0_dram0_pms_monitor_violate_status_lock:1;
+        /** core_0_dram0_pms_monitor_violate_status_world : RO; bitpos: [3:2]; default: 0;
+         *  Need add description
+         */
+        uint32_t core_0_dram0_pms_monitor_violate_status_world:2;
+        /** core_0_dram0_pms_monitor_violate_status_addr : RO; bitpos: [27:4]; default: 0;
+         *  Need add description
+         */
+        uint32_t core_0_dram0_pms_monitor_violate_status_addr:24;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} sensitive_core_0_dram0_pms_monitor_2_reg_t;
+
+/** Type of core_0_dram0_pms_monitor_3 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** core_0_dram0_pms_monitor_violate_status_wr : RO; bitpos: [0]; default: 0;
+         *  Need add description
+         */
+        uint32_t core_0_dram0_pms_monitor_violate_status_wr:1;
+        /** core_0_dram0_pms_monitor_violate_status_byteen : RO; bitpos: [4:1]; default: 0;
+         *  Need add description
+         */
+        uint32_t core_0_dram0_pms_monitor_violate_status_byteen:4;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} sensitive_core_0_dram0_pms_monitor_3_reg_t;
+
+/** Type of core_0_pif_pms_constrain_0 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** core_0_pif_pms_constrain_lock : R/W; bitpos: [0]; default: 0;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_lock:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} sensitive_core_0_pif_pms_constrain_0_reg_t;
+
+/** Type of core_0_pif_pms_constrain_1 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** core_0_pif_pms_constrain_world_0_uart : R/W; bitpos: [1:0]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_0_uart:2;
+        /** core_0_pif_pms_constrain_world_0_g0spi_1 : R/W; bitpos: [3:2]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_0_g0spi_1:2;
+        /** core_0_pif_pms_constrain_world_0_g0spi_0 : R/W; bitpos: [5:4]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_0_g0spi_0:2;
+        /** core_0_pif_pms_constrain_world_0_gpio : R/W; bitpos: [7:6]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_0_gpio:2;
+        uint32_t reserved_8:2;
+        /** core_0_pif_pms_constrain_world_0_fe : R/W; bitpos: [11:10]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_0_fe:2;
+        uint32_t reserved_12:2;
+        /** core_0_pif_pms_constrain_world_0_rtc : R/W; bitpos: [15:14]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_0_rtc:2;
+        /** core_0_pif_pms_constrain_world_0_io_mux : R/W; bitpos: [17:16]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_0_io_mux:2;
+        /** core_0_pif_pms_constrain_world_0_wdg : R/W; bitpos: [19:18]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_0_wdg:2;
+        uint32_t reserved_20:4;
+        /** core_0_pif_pms_constrain_world_0_misc : R/W; bitpos: [25:24]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_0_misc:2;
+        /** core_0_pif_pms_constrain_world_0_i2c : R/W; bitpos: [27:26]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_0_i2c:2;
+        uint32_t reserved_28:2;
+        /** core_0_pif_pms_constrain_world_0_uart1 : R/W; bitpos: [31:30]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_0_uart1:2;
+    };
+    uint32_t val;
+} sensitive_core_0_pif_pms_constrain_1_reg_t;
+
+/** Type of core_0_pif_pms_constrain_2 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** core_0_pif_pms_constrain_world_0_bt : R/W; bitpos: [1:0]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_0_bt:2;
+        uint32_t reserved_2:2;
+        /** core_0_pif_pms_constrain_world_0_i2c_ext0 : R/W; bitpos: [5:4]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_0_i2c_ext0:2;
+        /** core_0_pif_pms_constrain_world_0_uhci0 : R/W; bitpos: [7:6]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_0_uhci0:2;
+        uint32_t reserved_8:2;
+        /** core_0_pif_pms_constrain_world_0_rmt : R/W; bitpos: [11:10]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_0_rmt:2;
+        uint32_t reserved_12:4;
+        /** core_0_pif_pms_constrain_world_0_ledc : R/W; bitpos: [17:16]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_0_ledc:2;
+        /** core_0_pif_pms_constrain_world_0_efuse : R/W; bitpos: [19:18]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_0_efuse:2;
+        uint32_t reserved_20:6;
+        /** core_0_pif_pms_constrain_world_0_timergroup : R/W; bitpos: [27:26]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_0_timergroup:2;
+        /** core_0_pif_pms_constrain_world_0_timergroup1 : R/W; bitpos: [29:28]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_0_timergroup1:2;
+        /** core_0_pif_pms_constrain_world_0_systimer : R/W; bitpos: [31:30]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_0_systimer:2;
+    };
+    uint32_t val;
+} sensitive_core_0_pif_pms_constrain_2_reg_t;
+
+/** Type of core_0_pif_pms_constrain_3 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** core_0_pif_pms_constrain_world_0_spi_2 : R/W; bitpos: [1:0]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_0_spi_2:2;
+        uint32_t reserved_2:2;
+        /** core_0_pif_pms_constrain_world_0_apb_ctrl : R/W; bitpos: [5:4]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_0_apb_ctrl:2;
+        uint32_t reserved_6:4;
+        /** core_0_pif_pms_constrain_world_0_twai : R/W; bitpos: [11:10]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_0_twai:2;
+        uint32_t reserved_12:2;
+        /** core_0_pif_pms_constrain_world_0_i2s1 : R/W; bitpos: [15:14]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_0_i2s1:2;
+        uint32_t reserved_16:6;
+        /** core_0_pif_pms_constrain_world_0_rwbt : R/W; bitpos: [23:22]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_0_rwbt:2;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} sensitive_core_0_pif_pms_constrain_3_reg_t;
+
+/** Type of core_0_pif_pms_constrain_4 register
+ *  register description
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:4;
+        /** core_0_pif_pms_constrain_world_0_crypto_peri : R/W; bitpos: [5:4]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_0_crypto_peri:2;
+        /** core_0_pif_pms_constrain_world_0_crypto_dma : R/W; bitpos: [7:6]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_0_crypto_dma:2;
+        /** core_0_pif_pms_constrain_world_0_apb_adc : R/W; bitpos: [9:8]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_0_apb_adc:2;
+        uint32_t reserved_10:4;
+        /** core_0_pif_pms_constrain_world_0_usb_device : R/W; bitpos: [15:14]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_0_usb_device:2;
+        /** core_0_pif_pms_constrain_world_0_etm : R/W; bitpos: [17:16]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_0_etm:2;
+        /** core_0_pif_pms_constrain_world_0_timergroup3 : R/W; bitpos: [19:18]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_0_timergroup3:2;
+        /** core_0_pif_pms_constrain_world_0_ble_sec : R/W; bitpos: [21:20]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_0_ble_sec:2;
+        /** core_0_pif_pms_constrain_world_0_ieee802154mac : R/W; bitpos: [23:22]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_0_ieee802154mac:2;
+        uint32_t reserved_24:2;
+        /** core_0_pif_pms_constrain_world_0_coex : R/W; bitpos: [27:26]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_0_coex:2;
+        /** core_0_pif_pms_constrain_world_0_rtc_ble_tmr : R/W; bitpos: [29:28]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_0_rtc_ble_tmr:2;
+        /** core_0_pif_pms_constrain_world_0_clkrst : R/W; bitpos: [31:30]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_0_clkrst:2;
+    };
+    uint32_t val;
+} sensitive_core_0_pif_pms_constrain_4_reg_t;
+
+/** Type of core_0_pif_pms_constrain_5 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** core_0_pif_pms_constrain_world_0_pvt : R/W; bitpos: [1:0]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_0_pvt:2;
+        /** core_0_pif_pms_constrain_world_0_modem_widgets : R/W; bitpos: [3:2]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_0_modem_widgets:2;
+        /** core_0_pif_pms_constrain_world_0_system : R/W; bitpos: [5:4]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_0_system:2;
+        /** core_0_pif_pms_constrain_world_0_sensitive : R/W; bitpos: [7:6]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_0_sensitive:2;
+        /** core_0_pif_pms_constrain_world_0_interrupt : R/W; bitpos: [9:8]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_0_interrupt:2;
+        /** core_0_pif_pms_constrain_world_0_dma_copy : R/W; bitpos: [11:10]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_0_dma_copy:2;
+        /** core_0_pif_pms_constrain_world_0_cache_config : R/W; bitpos: [13:12]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_0_cache_config:2;
+        /** core_0_pif_pms_constrain_world_0_ad : R/W; bitpos: [15:14]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_0_ad:2;
+        /** core_0_pif_pms_constrain_world_0_dio : R/W; bitpos: [17:16]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_0_dio:2;
+        /** core_0_pif_pms_constrain_world_0_world_controller : R/W; bitpos: [19:18]; default:
+         *  3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_0_world_controller:2;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} sensitive_core_0_pif_pms_constrain_5_reg_t;
+
+/** Type of core_0_pif_pms_constrain_6 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** core_0_pif_pms_constrain_world_1_uart : R/W; bitpos: [1:0]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_1_uart:2;
+        /** core_0_pif_pms_constrain_world_1_g0spi_1 : R/W; bitpos: [3:2]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_1_g0spi_1:2;
+        /** core_0_pif_pms_constrain_world_1_g0spi_0 : R/W; bitpos: [5:4]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_1_g0spi_0:2;
+        /** core_0_pif_pms_constrain_world_1_gpio : R/W; bitpos: [7:6]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_1_gpio:2;
+        uint32_t reserved_8:2;
+        /** core_0_pif_pms_constrain_world_1_fe : R/W; bitpos: [11:10]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_1_fe:2;
+        uint32_t reserved_12:2;
+        /** core_0_pif_pms_constrain_world_1_rtc : R/W; bitpos: [15:14]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_1_rtc:2;
+        /** core_0_pif_pms_constrain_world_1_io_mux : R/W; bitpos: [17:16]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_1_io_mux:2;
+        /** core_0_pif_pms_constrain_world_1_wdg : R/W; bitpos: [19:18]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_1_wdg:2;
+        uint32_t reserved_20:4;
+        /** core_0_pif_pms_constrain_world_1_misc : R/W; bitpos: [25:24]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_1_misc:2;
+        /** core_0_pif_pms_constrain_world_1_i2c : R/W; bitpos: [27:26]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_1_i2c:2;
+        uint32_t reserved_28:2;
+        /** core_0_pif_pms_constrain_world_1_uart1 : R/W; bitpos: [31:30]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_1_uart1:2;
+    };
+    uint32_t val;
+} sensitive_core_0_pif_pms_constrain_6_reg_t;
+
+/** Type of core_0_pif_pms_constrain_7 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** core_0_pif_pms_constrain_world_1_bt : R/W; bitpos: [1:0]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_1_bt:2;
+        uint32_t reserved_2:2;
+        /** core_0_pif_pms_constrain_world_1_i2c_ext0 : R/W; bitpos: [5:4]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_1_i2c_ext0:2;
+        /** core_0_pif_pms_constrain_world_1_uhci0 : R/W; bitpos: [7:6]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_1_uhci0:2;
+        uint32_t reserved_8:2;
+        /** core_0_pif_pms_constrain_world_1_rmt : R/W; bitpos: [11:10]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_1_rmt:2;
+        uint32_t reserved_12:4;
+        /** core_0_pif_pms_constrain_world_1_ledc : R/W; bitpos: [17:16]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_1_ledc:2;
+        /** core_0_pif_pms_constrain_world_1_efuse : R/W; bitpos: [19:18]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_1_efuse:2;
+        uint32_t reserved_20:6;
+        /** core_0_pif_pms_constrain_world_1_timergroup : R/W; bitpos: [27:26]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_1_timergroup:2;
+        /** core_0_pif_pms_constrain_world_1_timergroup1 : R/W; bitpos: [29:28]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_1_timergroup1:2;
+        /** core_0_pif_pms_constrain_world_1_systimer : R/W; bitpos: [31:30]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_1_systimer:2;
+    };
+    uint32_t val;
+} sensitive_core_0_pif_pms_constrain_7_reg_t;
+
+/** Type of core_0_pif_pms_constrain_8 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** core_0_pif_pms_constrain_world_1_spi_2 : R/W; bitpos: [1:0]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_1_spi_2:2;
+        uint32_t reserved_2:2;
+        /** core_0_pif_pms_constrain_world_1_apb_ctrl : R/W; bitpos: [5:4]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_1_apb_ctrl:2;
+        uint32_t reserved_6:4;
+        /** core_0_pif_pms_constrain_world_1_twai : R/W; bitpos: [11:10]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_1_twai:2;
+        uint32_t reserved_12:2;
+        /** core_0_pif_pms_constrain_world_1_i2s1 : R/W; bitpos: [15:14]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_1_i2s1:2;
+        uint32_t reserved_16:6;
+        /** core_0_pif_pms_constrain_world_1_rwbt : R/W; bitpos: [23:22]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_1_rwbt:2;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} sensitive_core_0_pif_pms_constrain_8_reg_t;
+
+/** Type of core_0_pif_pms_constrain_9 register
+ *  register description
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:4;
+        /** core_0_pif_pms_constrain_world_1_crypto_peri : R/W; bitpos: [5:4]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_1_crypto_peri:2;
+        /** core_0_pif_pms_constrain_world_1_crypto_dma : R/W; bitpos: [7:6]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_1_crypto_dma:2;
+        /** core_0_pif_pms_constrain_world_1_apb_adc : R/W; bitpos: [9:8]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_1_apb_adc:2;
+        uint32_t reserved_10:4;
+        /** core_0_pif_pms_constrain_world_1_usb_device : R/W; bitpos: [15:14]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_1_usb_device:2;
+        /** core_0_pif_pms_constrain_world_1_etm : R/W; bitpos: [17:16]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_1_etm:2;
+        /** core_0_pif_pms_constrain_world_1_timergroup3 : R/W; bitpos: [19:18]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_1_timergroup3:2;
+        /** core_0_pif_pms_constrain_world_1_ble_sec : R/W; bitpos: [21:20]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_1_ble_sec:2;
+        /** core_0_pif_pms_constrain_world_1_ieee802154mac : R/W; bitpos: [23:22]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_1_ieee802154mac:2;
+        uint32_t reserved_24:2;
+        /** core_0_pif_pms_constrain_world_1_coex : R/W; bitpos: [27:26]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_1_coex:2;
+        /** core_0_pif_pms_constrain_world_1_rtc_ble_tmr : R/W; bitpos: [29:28]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_1_rtc_ble_tmr:2;
+        /** core_0_pif_pms_constrain_world_1_clkrst : R/W; bitpos: [31:30]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_1_clkrst:2;
+    };
+    uint32_t val;
+} sensitive_core_0_pif_pms_constrain_9_reg_t;
+
+/** Type of core_0_pif_pms_constrain_10 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** core_0_pif_pms_constrain_world_1_pvt : R/W; bitpos: [1:0]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_1_pvt:2;
+        /** core_0_pif_pms_constrain_world_1_modem_widgets : R/W; bitpos: [3:2]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_1_modem_widgets:2;
+        /** core_0_pif_pms_constrain_world_1_system : R/W; bitpos: [5:4]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_1_system:2;
+        /** core_0_pif_pms_constrain_world_1_sensitive : R/W; bitpos: [7:6]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_1_sensitive:2;
+        /** core_0_pif_pms_constrain_world_1_interrupt : R/W; bitpos: [9:8]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_1_interrupt:2;
+        /** core_0_pif_pms_constrain_world_1_dma_copy : R/W; bitpos: [11:10]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_1_dma_copy:2;
+        /** core_0_pif_pms_constrain_world_1_cache_config : R/W; bitpos: [13:12]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_1_cache_config:2;
+        /** core_0_pif_pms_constrain_world_1_ad : R/W; bitpos: [15:14]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_1_ad:2;
+        /** core_0_pif_pms_constrain_world_1_dio : R/W; bitpos: [17:16]; default: 3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_1_dio:2;
+        /** core_0_pif_pms_constrain_world_1_world_controller : R/W; bitpos: [19:18]; default:
+         *  3;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_world_1_world_controller:2;
+        uint32_t reserved_20:12;
+    };
+    uint32_t val;
+} sensitive_core_0_pif_pms_constrain_10_reg_t;
+
+/** Type of core_0_pif_pms_constrain_11 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** core_0_pif_pms_constrain_rtcfast_spltaddr_world_0 : R/W; bitpos: [10:0]; default:
+         *  2047;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_rtcfast_spltaddr_world_0:11;
+        /** core_0_pif_pms_constrain_rtcfast_spltaddr_world_1 : R/W; bitpos: [21:11]; default:
+         *  2047;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_rtcfast_spltaddr_world_1:11;
+        uint32_t reserved_22:10;
+    };
+    uint32_t val;
+} sensitive_core_0_pif_pms_constrain_11_reg_t;
+
+/** Type of core_0_pif_pms_constrain_12 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** core_0_pif_pms_constrain_rtcfast_world_0_l : R/W; bitpos: [2:0]; default: 7;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_rtcfast_world_0_l:3;
+        /** core_0_pif_pms_constrain_rtcfast_world_0_h : R/W; bitpos: [5:3]; default: 7;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_rtcfast_world_0_h:3;
+        /** core_0_pif_pms_constrain_rtcfast_world_1_l : R/W; bitpos: [8:6]; default: 7;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_rtcfast_world_1_l:3;
+        /** core_0_pif_pms_constrain_rtcfast_world_1_h : R/W; bitpos: [11:9]; default: 7;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_constrain_rtcfast_world_1_h:3;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} sensitive_core_0_pif_pms_constrain_12_reg_t;
+
+/** Type of region_pms_constrain_0 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** region_pms_constrain_lock : R/W; bitpos: [0]; default: 0;
+         *  Need add description
+         */
+        uint32_t region_pms_constrain_lock:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} sensitive_region_pms_constrain_0_reg_t;
+
+/** Type of region_pms_constrain_1 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** region_pms_constrain_world_0_area_0 : R/W; bitpos: [1:0]; default: 3;
+         *  Need add description
+         */
+        uint32_t region_pms_constrain_world_0_area_0:2;
+        /** region_pms_constrain_world_0_area_1 : R/W; bitpos: [3:2]; default: 3;
+         *  Need add description
+         */
+        uint32_t region_pms_constrain_world_0_area_1:2;
+        /** region_pms_constrain_world_0_area_2 : R/W; bitpos: [5:4]; default: 3;
+         *  Need add description
+         */
+        uint32_t region_pms_constrain_world_0_area_2:2;
+        /** region_pms_constrain_world_0_area_3 : R/W; bitpos: [7:6]; default: 3;
+         *  Need add description
+         */
+        uint32_t region_pms_constrain_world_0_area_3:2;
+        /** region_pms_constrain_world_0_area_4 : R/W; bitpos: [9:8]; default: 3;
+         *  Need add description
+         */
+        uint32_t region_pms_constrain_world_0_area_4:2;
+        /** region_pms_constrain_world_0_area_5 : R/W; bitpos: [11:10]; default: 3;
+         *  Need add description
+         */
+        uint32_t region_pms_constrain_world_0_area_5:2;
+        /** region_pms_constrain_world_0_area_6 : R/W; bitpos: [13:12]; default: 3;
+         *  Need add description
+         */
+        uint32_t region_pms_constrain_world_0_area_6:2;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} sensitive_region_pms_constrain_1_reg_t;
+
+/** Type of region_pms_constrain_2 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** region_pms_constrain_world_1_area_0 : R/W; bitpos: [1:0]; default: 3;
+         *  Need add description
+         */
+        uint32_t region_pms_constrain_world_1_area_0:2;
+        /** region_pms_constrain_world_1_area_1 : R/W; bitpos: [3:2]; default: 3;
+         *  Need add description
+         */
+        uint32_t region_pms_constrain_world_1_area_1:2;
+        /** region_pms_constrain_world_1_area_2 : R/W; bitpos: [5:4]; default: 3;
+         *  Need add description
+         */
+        uint32_t region_pms_constrain_world_1_area_2:2;
+        /** region_pms_constrain_world_1_area_3 : R/W; bitpos: [7:6]; default: 3;
+         *  Need add description
+         */
+        uint32_t region_pms_constrain_world_1_area_3:2;
+        /** region_pms_constrain_world_1_area_4 : R/W; bitpos: [9:8]; default: 3;
+         *  Need add description
+         */
+        uint32_t region_pms_constrain_world_1_area_4:2;
+        /** region_pms_constrain_world_1_area_5 : R/W; bitpos: [11:10]; default: 3;
+         *  Need add description
+         */
+        uint32_t region_pms_constrain_world_1_area_5:2;
+        /** region_pms_constrain_world_1_area_6 : R/W; bitpos: [13:12]; default: 3;
+         *  Need add description
+         */
+        uint32_t region_pms_constrain_world_1_area_6:2;
+        uint32_t reserved_14:18;
+    };
+    uint32_t val;
+} sensitive_region_pms_constrain_2_reg_t;
+
+/** Type of region_pms_constrain_3 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** region_pms_constrain_addr_0 : R/W; bitpos: [29:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t region_pms_constrain_addr_0:30;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} sensitive_region_pms_constrain_3_reg_t;
+
+/** Type of region_pms_constrain_4 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** region_pms_constrain_addr_1 : R/W; bitpos: [29:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t region_pms_constrain_addr_1:30;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} sensitive_region_pms_constrain_4_reg_t;
+
+/** Type of region_pms_constrain_5 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** region_pms_constrain_addr_2 : R/W; bitpos: [29:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t region_pms_constrain_addr_2:30;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} sensitive_region_pms_constrain_5_reg_t;
+
+/** Type of region_pms_constrain_6 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** region_pms_constrain_addr_3 : R/W; bitpos: [29:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t region_pms_constrain_addr_3:30;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} sensitive_region_pms_constrain_6_reg_t;
+
+/** Type of region_pms_constrain_7 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** region_pms_constrain_addr_4 : R/W; bitpos: [29:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t region_pms_constrain_addr_4:30;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} sensitive_region_pms_constrain_7_reg_t;
+
+/** Type of region_pms_constrain_8 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** region_pms_constrain_addr_5 : R/W; bitpos: [29:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t region_pms_constrain_addr_5:30;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} sensitive_region_pms_constrain_8_reg_t;
+
+/** Type of region_pms_constrain_9 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** region_pms_constrain_addr_6 : R/W; bitpos: [29:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t region_pms_constrain_addr_6:30;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} sensitive_region_pms_constrain_9_reg_t;
+
+/** Type of region_pms_constrain_10 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** region_pms_constrain_addr_7 : R/W; bitpos: [29:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t region_pms_constrain_addr_7:30;
+        uint32_t reserved_30:2;
+    };
+    uint32_t val;
+} sensitive_region_pms_constrain_10_reg_t;
+
+/** Type of core_0_pif_pms_monitor_0 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** core_0_pif_pms_monitor_lock : R/W; bitpos: [0]; default: 0;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_monitor_lock:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} sensitive_core_0_pif_pms_monitor_0_reg_t;
+
+/** Type of core_0_pif_pms_monitor_1 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** core_0_pif_pms_monitor_violate_clr : R/W; bitpos: [0]; default: 1;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_monitor_violate_clr:1;
+        /** core_0_pif_pms_monitor_violate_en : R/W; bitpos: [1]; default: 1;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_monitor_violate_en:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} sensitive_core_0_pif_pms_monitor_1_reg_t;
+
+/** Type of core_0_pif_pms_monitor_2 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** core_0_pif_pms_monitor_violate_intr : RO; bitpos: [0]; default: 0;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_monitor_violate_intr:1;
+        /** core_0_pif_pms_monitor_violate_status_hport_0 : RO; bitpos: [1]; default: 0;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_monitor_violate_status_hport_0:1;
+        /** core_0_pif_pms_monitor_violate_status_hsize : RO; bitpos: [4:2]; default: 0;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_monitor_violate_status_hsize:3;
+        /** core_0_pif_pms_monitor_violate_status_hwrite : RO; bitpos: [5]; default: 0;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_monitor_violate_status_hwrite:1;
+        /** core_0_pif_pms_monitor_violate_status_hworld : RO; bitpos: [7:6]; default: 0;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_monitor_violate_status_hworld:2;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} sensitive_core_0_pif_pms_monitor_2_reg_t;
+
+/** Type of core_0_pif_pms_monitor_3 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** core_0_pif_pms_monitor_violate_status_haddr : RO; bitpos: [31:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_monitor_violate_status_haddr:32;
+    };
+    uint32_t val;
+} sensitive_core_0_pif_pms_monitor_3_reg_t;
+
+/** Type of core_0_pif_pms_monitor_4 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** core_0_pif_pms_monitor_nonword_violate_clr : R/W; bitpos: [0]; default: 1;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_monitor_nonword_violate_clr:1;
+        /** core_0_pif_pms_monitor_nonword_violate_en : R/W; bitpos: [1]; default: 1;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_monitor_nonword_violate_en:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} sensitive_core_0_pif_pms_monitor_4_reg_t;
+
+/** Type of core_0_pif_pms_monitor_5 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** core_0_pif_pms_monitor_nonword_violate_intr : RO; bitpos: [0]; default: 0;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_monitor_nonword_violate_intr:1;
+        /** core_0_pif_pms_monitor_nonword_violate_status_hsize : RO; bitpos: [2:1]; default: 0;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_monitor_nonword_violate_status_hsize:2;
+        /** core_0_pif_pms_monitor_nonword_violate_status_hworld : RO; bitpos: [4:3]; default:
+         *  0;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_monitor_nonword_violate_status_hworld:2;
+        uint32_t reserved_5:27;
+    };
+    uint32_t val;
+} sensitive_core_0_pif_pms_monitor_5_reg_t;
+
+/** Type of core_0_pif_pms_monitor_6 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** core_0_pif_pms_monitor_nonword_violate_status_haddr : RO; bitpos: [31:0]; default:
+         *  0;
+         *  Need add description
+         */
+        uint32_t core_0_pif_pms_monitor_nonword_violate_status_haddr:32;
+    };
+    uint32_t val;
+} sensitive_core_0_pif_pms_monitor_6_reg_t;
+
+/** Type of backup_bus_pms_constrain_0 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** backup_bus_pms_constrain_lock : R/W; bitpos: [0]; default: 0;
+         *  Need add description
+         */
+        uint32_t backup_bus_pms_constrain_lock:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} sensitive_backup_bus_pms_constrain_0_reg_t;
+
+/** Type of backup_bus_pms_constrain_1 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** backup_bus_pms_constrain_uart : R/W; bitpos: [1:0]; default: 3;
+         *  Need add description
+         */
+        uint32_t backup_bus_pms_constrain_uart:2;
+        /** backup_bus_pms_constrain_g0spi_1 : R/W; bitpos: [3:2]; default: 3;
+         *  Need add description
+         */
+        uint32_t backup_bus_pms_constrain_g0spi_1:2;
+        /** backup_bus_pms_constrain_g0spi_0 : R/W; bitpos: [5:4]; default: 3;
+         *  Need add description
+         */
+        uint32_t backup_bus_pms_constrain_g0spi_0:2;
+        /** backup_bus_pms_constrain_gpio : R/W; bitpos: [7:6]; default: 3;
+         *  Need add description
+         */
+        uint32_t backup_bus_pms_constrain_gpio:2;
+        uint32_t reserved_8:2;
+        /** backup_bus_pms_constrain_fe : R/W; bitpos: [11:10]; default: 3;
+         *  Need add description
+         */
+        uint32_t backup_bus_pms_constrain_fe:2;
+        uint32_t reserved_12:2;
+        /** backup_bus_pms_constrain_rtc : R/W; bitpos: [15:14]; default: 3;
+         *  Need add description
+         */
+        uint32_t backup_bus_pms_constrain_rtc:2;
+        /** backup_bus_pms_constrain_io_mux : R/W; bitpos: [17:16]; default: 3;
+         *  Need add description
+         */
+        uint32_t backup_bus_pms_constrain_io_mux:2;
+        /** backup_bus_pms_constrain_wdg : R/W; bitpos: [19:18]; default: 3;
+         *  Need add description
+         */
+        uint32_t backup_bus_pms_constrain_wdg:2;
+        uint32_t reserved_20:4;
+        /** backup_bus_pms_constrain_misc : R/W; bitpos: [25:24]; default: 3;
+         *  Need add description
+         */
+        uint32_t backup_bus_pms_constrain_misc:2;
+        /** backup_bus_pms_constrain_i2c : R/W; bitpos: [27:26]; default: 3;
+         *  Need add description
+         */
+        uint32_t backup_bus_pms_constrain_i2c:2;
+        uint32_t reserved_28:2;
+        /** backup_bus_pms_constrain_uart1 : R/W; bitpos: [31:30]; default: 3;
+         *  Need add description
+         */
+        uint32_t backup_bus_pms_constrain_uart1:2;
+    };
+    uint32_t val;
+} sensitive_backup_bus_pms_constrain_1_reg_t;
+
+/** Type of backup_bus_pms_constrain_2 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** backup_bus_pms_constrain_bt : R/W; bitpos: [1:0]; default: 3;
+         *  Need add description
+         */
+        uint32_t backup_bus_pms_constrain_bt:2;
+        uint32_t reserved_2:2;
+        /** backup_bus_pms_constrain_i2c_ext0 : R/W; bitpos: [5:4]; default: 3;
+         *  Need add description
+         */
+        uint32_t backup_bus_pms_constrain_i2c_ext0:2;
+        /** backup_bus_pms_constrain_uhci0 : R/W; bitpos: [7:6]; default: 3;
+         *  Need add description
+         */
+        uint32_t backup_bus_pms_constrain_uhci0:2;
+        uint32_t reserved_8:2;
+        /** backup_bus_pms_constrain_rmt : R/W; bitpos: [11:10]; default: 3;
+         *  Need add description
+         */
+        uint32_t backup_bus_pms_constrain_rmt:2;
+        uint32_t reserved_12:4;
+        /** backup_bus_pms_constrain_ledc : R/W; bitpos: [17:16]; default: 3;
+         *  Need add description
+         */
+        uint32_t backup_bus_pms_constrain_ledc:2;
+        /** backup_bus_pms_constrain_efuse : R/W; bitpos: [19:18]; default: 3;
+         *  Need add description
+         */
+        uint32_t backup_bus_pms_constrain_efuse:2;
+        uint32_t reserved_20:6;
+        /** backup_bus_pms_constrain_timergroup : R/W; bitpos: [27:26]; default: 3;
+         *  Need add description
+         */
+        uint32_t backup_bus_pms_constrain_timergroup:2;
+        /** backup_bus_pms_constrain_timergroup1 : R/W; bitpos: [29:28]; default: 3;
+         *  Need add description
+         */
+        uint32_t backup_bus_pms_constrain_timergroup1:2;
+        /** backup_bus_pms_constrain_systimer : R/W; bitpos: [31:30]; default: 3;
+         *  Need add description
+         */
+        uint32_t backup_bus_pms_constrain_systimer:2;
+    };
+    uint32_t val;
+} sensitive_backup_bus_pms_constrain_2_reg_t;
+
+/** Type of backup_bus_pms_constrain_3 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** backup_bus_pms_constrain_spi_2 : R/W; bitpos: [1:0]; default: 3;
+         *  Need add description
+         */
+        uint32_t backup_bus_pms_constrain_spi_2:2;
+        uint32_t reserved_2:2;
+        /** backup_bus_pms_constrain_apb_ctrl : R/W; bitpos: [5:4]; default: 3;
+         *  Need add description
+         */
+        uint32_t backup_bus_pms_constrain_apb_ctrl:2;
+        uint32_t reserved_6:4;
+        /** backup_bus_pms_constrain_twai : R/W; bitpos: [11:10]; default: 3;
+         *  Need add description
+         */
+        uint32_t backup_bus_pms_constrain_twai:2;
+        uint32_t reserved_12:2;
+        /** backup_bus_pms_constrain_i2s1 : R/W; bitpos: [15:14]; default: 3;
+         *  Need add description
+         */
+        uint32_t backup_bus_pms_constrain_i2s1:2;
+        uint32_t reserved_16:6;
+        /** backup_bus_pms_constrain_rwbt : R/W; bitpos: [23:22]; default: 3;
+         *  Need add description
+         */
+        uint32_t backup_bus_pms_constrain_rwbt:2;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} sensitive_backup_bus_pms_constrain_3_reg_t;
+
+/** Type of backup_bus_pms_constrain_4 register
+ *  register description
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:4;
+        /** backup_bus_pms_constrain_crypto_peri : R/W; bitpos: [5:4]; default: 3;
+         *  Need add description
+         */
+        uint32_t backup_bus_pms_constrain_crypto_peri:2;
+        /** backup_bus_pms_constrain_crypto_dma : R/W; bitpos: [7:6]; default: 3;
+         *  Need add description
+         */
+        uint32_t backup_bus_pms_constrain_crypto_dma:2;
+        /** backup_bus_pms_constrain_apb_adc : R/W; bitpos: [9:8]; default: 3;
+         *  Need add description
+         */
+        uint32_t backup_bus_pms_constrain_apb_adc:2;
+        uint32_t reserved_10:4;
+        /** backup_bus_pms_constrain_usb_device : R/W; bitpos: [15:14]; default: 3;
+         *  Need add description
+         */
+        uint32_t backup_bus_pms_constrain_usb_device:2;
+        /** backup_bus_pms_constrain_etm : R/W; bitpos: [17:16]; default: 3;
+         *  Need add description
+         */
+        uint32_t backup_bus_pms_constrain_etm:2;
+        /** backup_bus_pms_constrain_timergroup3 : R/W; bitpos: [19:18]; default: 3;
+         *  Need add description
+         */
+        uint32_t backup_bus_pms_constrain_timergroup3:2;
+        /** backup_bus_pms_constrain_ble_sec : R/W; bitpos: [21:20]; default: 3;
+         *  Need add description
+         */
+        uint32_t backup_bus_pms_constrain_ble_sec:2;
+        /** backup_bus_pms_constrain_ieee802154mac : R/W; bitpos: [23:22]; default: 3;
+         *  Need add description
+         */
+        uint32_t backup_bus_pms_constrain_ieee802154mac:2;
+        uint32_t reserved_24:2;
+        /** backup_bus_pms_constrain_coex : R/W; bitpos: [27:26]; default: 3;
+         *  Need add description
+         */
+        uint32_t backup_bus_pms_constrain_coex:2;
+        /** backup_bus_pms_constrain_rtc_ble_tmr : R/W; bitpos: [29:28]; default: 3;
+         *  Need add description
+         */
+        uint32_t backup_bus_pms_constrain_rtc_ble_tmr:2;
+        /** backup_bus_pms_constrain_clkrst : R/W; bitpos: [31:30]; default: 3;
+         *  Need add description
+         */
+        uint32_t backup_bus_pms_constrain_clkrst:2;
+    };
+    uint32_t val;
+} sensitive_backup_bus_pms_constrain_4_reg_t;
+
+/** Type of backup_bus_pms_constrain_5 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** backup_bus_pms_constrain_pvt : R/W; bitpos: [1:0]; default: 3;
+         *  Need add description
+         */
+        uint32_t backup_bus_pms_constrain_pvt:2;
+        /** backup_bus_pms_constrain_modem_widgets : R/W; bitpos: [3:2]; default: 3;
+         *  Need add description
+         */
+        uint32_t backup_bus_pms_constrain_modem_widgets:2;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} sensitive_backup_bus_pms_constrain_5_reg_t;
+
+/** Type of backup_bus_pms_monitor_0 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** backup_bus_pms_monitor_lock : R/W; bitpos: [0]; default: 0;
+         *  Need add description
+         */
+        uint32_t backup_bus_pms_monitor_lock:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} sensitive_backup_bus_pms_monitor_0_reg_t;
+
+/** Type of backup_bus_pms_monitor_1 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** backup_bus_pms_monitor_violate_clr : R/W; bitpos: [0]; default: 1;
+         *  Need add description
+         */
+        uint32_t backup_bus_pms_monitor_violate_clr:1;
+        /** backup_bus_pms_monitor_violate_en : R/W; bitpos: [1]; default: 1;
+         *  Need add description
+         */
+        uint32_t backup_bus_pms_monitor_violate_en:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} sensitive_backup_bus_pms_monitor_1_reg_t;
+
+/** Type of backup_bus_pms_monitor_2 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** backup_bus_pms_monitor_violate_intr : RO; bitpos: [0]; default: 0;
+         *  Need add description
+         */
+        uint32_t backup_bus_pms_monitor_violate_intr:1;
+        /** backup_bus_pms_monitor_violate_status_htrans : RO; bitpos: [2:1]; default: 0;
+         *  Need add description
+         */
+        uint32_t backup_bus_pms_monitor_violate_status_htrans:2;
+        /** backup_bus_pms_monitor_violate_status_hsize : RO; bitpos: [5:3]; default: 0;
+         *  Need add description
+         */
+        uint32_t backup_bus_pms_monitor_violate_status_hsize:3;
+        /** backup_bus_pms_monitor_violate_status_hwrite : RO; bitpos: [6]; default: 0;
+         *  Need add description
+         */
+        uint32_t backup_bus_pms_monitor_violate_status_hwrite:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} sensitive_backup_bus_pms_monitor_2_reg_t;
+
+/** Type of backup_bus_pms_monitor_3 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** backup_bus_pms_monitor_violate_haddr : RO; bitpos: [31:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t backup_bus_pms_monitor_violate_haddr:32;
+    };
+    uint32_t val;
+} sensitive_backup_bus_pms_monitor_3_reg_t;
+
+/** Type of clock_gate register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 1;
+         *  Need add description
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} sensitive_clock_gate_reg_t;
+
+/** Type of sensitive_reg_date register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** sensitive_reg_date : R/W; bitpos: [27:0]; default: 34636368;
+         *  Need add description
+         */
+        uint32_t sensitive_reg_date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} sensitive_sensitive_reg_date_reg_t;
+
+
+typedef struct {
+    volatile sensitive_rom_table_lock_reg_t rom_table_lock;
+    volatile sensitive_rom_table_reg_t rom_table;
+    volatile sensitive_privilege_mode_sel_lock_reg_t privilege_mode_sel_lock;
+    volatile sensitive_privilege_mode_sel_reg_t privilege_mode_sel;
+    volatile sensitive_apb_peripheral_access_0_reg_t apb_peripheral_access_0;
+    volatile sensitive_apb_peripheral_access_1_reg_t apb_peripheral_access_1;
+    volatile sensitive_internal_sram_usage_0_reg_t internal_sram_usage_0;
+    volatile sensitive_internal_sram_usage_1_reg_t internal_sram_usage_1;
+    volatile sensitive_internal_sram_usage_3_reg_t internal_sram_usage_3;
+    volatile sensitive_internal_sram_usage_4_reg_t internal_sram_usage_4;
+    volatile sensitive_cache_tag_access_0_reg_t cache_tag_access_0;
+    volatile sensitive_cache_tag_access_1_reg_t cache_tag_access_1;
+    volatile sensitive_cache_mmu_access_0_reg_t cache_mmu_access_0;
+    volatile sensitive_cache_mmu_access_1_reg_t cache_mmu_access_1;
+    volatile sensitive_dma_apbperi_spi2_pms_constrain_0_reg_t dma_apbperi_spi2_pms_constrain_0;
+    volatile sensitive_dma_apbperi_spi2_pms_constrain_1_reg_t dma_apbperi_spi2_pms_constrain_1;
+    volatile sensitive_dma_apbperi_uchi0_pms_constrain_0_reg_t dma_apbperi_uchi0_pms_constrain_0;
+    volatile sensitive_dma_apbperi_uchi0_pms_constrain_1_reg_t dma_apbperi_uchi0_pms_constrain_1;
+    volatile sensitive_dma_apbperi_i2s0_pms_constrain_0_reg_t dma_apbperi_i2s0_pms_constrain_0;
+    volatile sensitive_dma_apbperi_i2s0_pms_constrain_1_reg_t dma_apbperi_i2s0_pms_constrain_1;
+    volatile sensitive_dma_apbperi_mac_pms_constrain_0_reg_t dma_apbperi_mac_pms_constrain_0;
+    volatile sensitive_dma_apbperi_mac_pms_constrain_1_reg_t dma_apbperi_mac_pms_constrain_1;
+    volatile sensitive_dma_apbperi_backup_pms_constrain_0_reg_t dma_apbperi_backup_pms_constrain_0;
+    volatile sensitive_dma_apbperi_backup_pms_constrain_1_reg_t dma_apbperi_backup_pms_constrain_1;
+    volatile sensitive_dma_apbperi_lc_pms_constrain_0_reg_t dma_apbperi_lc_pms_constrain_0;
+    volatile sensitive_dma_apbperi_lc_pms_constrain_1_reg_t dma_apbperi_lc_pms_constrain_1;
+    volatile sensitive_dma_apbperi_aes_pms_constrain_0_reg_t dma_apbperi_aes_pms_constrain_0;
+    volatile sensitive_dma_apbperi_aes_pms_constrain_1_reg_t dma_apbperi_aes_pms_constrain_1;
+    volatile sensitive_dma_apbperi_sha_pms_constrain_0_reg_t dma_apbperi_sha_pms_constrain_0;
+    volatile sensitive_dma_apbperi_sha_pms_constrain_1_reg_t dma_apbperi_sha_pms_constrain_1;
+    volatile sensitive_dma_apbperi_adc_dac_pms_constrain_0_reg_t dma_apbperi_adc_dac_pms_constrain_0;
+    volatile sensitive_dma_apbperi_adc_dac_pms_constrain_1_reg_t dma_apbperi_adc_dac_pms_constrain_1;
+    volatile sensitive_dma_apbperi_ble_sec_pms_constrain_0_reg_t dma_apbperi_ble_sec_pms_constrain_0;
+    volatile sensitive_dma_apbperi_ble_sec_pms_constrain_1_reg_t dma_apbperi_ble_sec_pms_constrain_1;
+    volatile sensitive_dma_apbperi_white_list_pms_constrain_0_reg_t dma_apbperi_white_list_pms_constrain_0;
+    volatile sensitive_dma_apbperi_white_list_pms_constrain_1_reg_t dma_apbperi_white_list_pms_constrain_1;
+    volatile sensitive_dma_apbperi_sdio_host_pms_constrain_0_reg_t dma_apbperi_sdio_host_pms_constrain_0;
+    volatile sensitive_dma_apbperi_sdio_host_pms_constrain_1_reg_t dma_apbperi_sdio_host_pms_constrain_1;
+    volatile sensitive_dma_apbperi_pms_monitor_0_reg_t dma_apbperi_pms_monitor_0;
+    volatile sensitive_dma_apbperi_pms_monitor_1_reg_t dma_apbperi_pms_monitor_1;
+    volatile sensitive_dma_apbperi_pms_monitor_2_reg_t dma_apbperi_pms_monitor_2;
+    volatile sensitive_dma_apbperi_pms_monitor_3_reg_t dma_apbperi_pms_monitor_3;
+    volatile sensitive_core_x_iram0_dram0_dma_split_line_constrain_0_reg_t core_x_iram0_dram0_dma_split_line_constrain_0;
+    volatile sensitive_core_x_iram0_dram0_dma_split_line_constrain_1_reg_t core_x_iram0_dram0_dma_split_line_constrain_1;
+    volatile sensitive_core_x_iram0_dram0_dma_split_line_constrain_2_reg_t core_x_iram0_dram0_dma_split_line_constrain_2;
+    volatile sensitive_core_x_iram0_dram0_dma_split_line_constrain_3_reg_t core_x_iram0_dram0_dma_split_line_constrain_3;
+    volatile sensitive_core_x_iram0_dram0_dma_split_line_constrain_4_reg_t core_x_iram0_dram0_dma_split_line_constrain_4;
+    volatile sensitive_core_x_iram0_dram0_dma_split_line_constrain_5_reg_t core_x_iram0_dram0_dma_split_line_constrain_5;
+    volatile sensitive_core_x_iram0_pms_constrain_0_reg_t core_x_iram0_pms_constrain_0;
+    volatile sensitive_core_x_iram0_pms_constrain_1_reg_t core_x_iram0_pms_constrain_1;
+    volatile sensitive_core_x_iram0_pms_constrain_2_reg_t core_x_iram0_pms_constrain_2;
+    volatile sensitive_core_0_iram0_pms_monitor_0_reg_t core_0_iram0_pms_monitor_0;
+    volatile sensitive_core_0_iram0_pms_monitor_1_reg_t core_0_iram0_pms_monitor_1;
+    volatile sensitive_core_0_iram0_pms_monitor_2_reg_t core_0_iram0_pms_monitor_2;
+    volatile sensitive_core_x_dram0_pms_constrain_0_reg_t core_x_dram0_pms_constrain_0;
+    volatile sensitive_core_x_dram0_pms_constrain_1_reg_t core_x_dram0_pms_constrain_1;
+    volatile sensitive_core_0_dram0_pms_monitor_0_reg_t core_0_dram0_pms_monitor_0;
+    volatile sensitive_core_0_dram0_pms_monitor_1_reg_t core_0_dram0_pms_monitor_1;
+    volatile sensitive_core_0_dram0_pms_monitor_2_reg_t core_0_dram0_pms_monitor_2;
+    volatile sensitive_core_0_dram0_pms_monitor_3_reg_t core_0_dram0_pms_monitor_3;
+    volatile sensitive_core_0_pif_pms_constrain_0_reg_t core_0_pif_pms_constrain_0;
+    volatile sensitive_core_0_pif_pms_constrain_1_reg_t core_0_pif_pms_constrain_1;
+    volatile sensitive_core_0_pif_pms_constrain_2_reg_t core_0_pif_pms_constrain_2;
+    volatile sensitive_core_0_pif_pms_constrain_3_reg_t core_0_pif_pms_constrain_3;
+    volatile sensitive_core_0_pif_pms_constrain_4_reg_t core_0_pif_pms_constrain_4;
+    volatile sensitive_core_0_pif_pms_constrain_5_reg_t core_0_pif_pms_constrain_5;
+    volatile sensitive_core_0_pif_pms_constrain_6_reg_t core_0_pif_pms_constrain_6;
+    volatile sensitive_core_0_pif_pms_constrain_7_reg_t core_0_pif_pms_constrain_7;
+    volatile sensitive_core_0_pif_pms_constrain_8_reg_t core_0_pif_pms_constrain_8;
+    volatile sensitive_core_0_pif_pms_constrain_9_reg_t core_0_pif_pms_constrain_9;
+    volatile sensitive_core_0_pif_pms_constrain_10_reg_t core_0_pif_pms_constrain_10;
+    volatile sensitive_core_0_pif_pms_constrain_11_reg_t core_0_pif_pms_constrain_11;
+    volatile sensitive_core_0_pif_pms_constrain_12_reg_t core_0_pif_pms_constrain_12;
+    volatile sensitive_region_pms_constrain_0_reg_t region_pms_constrain_0;
+    volatile sensitive_region_pms_constrain_1_reg_t region_pms_constrain_1;
+    volatile sensitive_region_pms_constrain_2_reg_t region_pms_constrain_2;
+    volatile sensitive_region_pms_constrain_3_reg_t region_pms_constrain_3;
+    volatile sensitive_region_pms_constrain_4_reg_t region_pms_constrain_4;
+    volatile sensitive_region_pms_constrain_5_reg_t region_pms_constrain_5;
+    volatile sensitive_region_pms_constrain_6_reg_t region_pms_constrain_6;
+    volatile sensitive_region_pms_constrain_7_reg_t region_pms_constrain_7;
+    volatile sensitive_region_pms_constrain_8_reg_t region_pms_constrain_8;
+    volatile sensitive_region_pms_constrain_9_reg_t region_pms_constrain_9;
+    volatile sensitive_region_pms_constrain_10_reg_t region_pms_constrain_10;
+    volatile sensitive_core_0_pif_pms_monitor_0_reg_t core_0_pif_pms_monitor_0;
+    volatile sensitive_core_0_pif_pms_monitor_1_reg_t core_0_pif_pms_monitor_1;
+    volatile sensitive_core_0_pif_pms_monitor_2_reg_t core_0_pif_pms_monitor_2;
+    volatile sensitive_core_0_pif_pms_monitor_3_reg_t core_0_pif_pms_monitor_3;
+    volatile sensitive_core_0_pif_pms_monitor_4_reg_t core_0_pif_pms_monitor_4;
+    volatile sensitive_core_0_pif_pms_monitor_5_reg_t core_0_pif_pms_monitor_5;
+    volatile sensitive_core_0_pif_pms_monitor_6_reg_t core_0_pif_pms_monitor_6;
+    volatile sensitive_backup_bus_pms_constrain_0_reg_t backup_bus_pms_constrain_0;
+    volatile sensitive_backup_bus_pms_constrain_1_reg_t backup_bus_pms_constrain_1;
+    volatile sensitive_backup_bus_pms_constrain_2_reg_t backup_bus_pms_constrain_2;
+    volatile sensitive_backup_bus_pms_constrain_3_reg_t backup_bus_pms_constrain_3;
+    volatile sensitive_backup_bus_pms_constrain_4_reg_t backup_bus_pms_constrain_4;
+    volatile sensitive_backup_bus_pms_constrain_5_reg_t backup_bus_pms_constrain_5;
+    volatile sensitive_backup_bus_pms_monitor_0_reg_t backup_bus_pms_monitor_0;
+    volatile sensitive_backup_bus_pms_monitor_1_reg_t backup_bus_pms_monitor_1;
+    volatile sensitive_backup_bus_pms_monitor_2_reg_t backup_bus_pms_monitor_2;
+    volatile sensitive_backup_bus_pms_monitor_3_reg_t backup_bus_pms_monitor_3;
+    volatile sensitive_clock_gate_reg_t clock_gate;
+    uint32_t reserved_198[921];
+    volatile sensitive_sensitive_reg_date_reg_t sensitive_reg_date;
+} sensitive_dev_t;
+
+extern sensitive_dev_t SENSITIVE;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(sensitive_dev_t) == 0x1000, "Invalid size of sensitive_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32h2/include/rev2/soc/soc_caps.h

@@ -24,6 +24,9 @@
 #define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS   3
 #define SOC_ICACHE_ACCESS_RODATA_SUPPORTED  1
 #define SOC_TEMP_SENSOR_SUPPORTED           1
+#define SOC_RTC_FAST_MEM_SUPPORTED          1
+#define SOC_RTC_SLOW_MEM_SUPPORTED          0
+#define SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY  1
 
 
 /*-------------------------- AES CAPS -----------------------------------------*/

components/soc/esp32h2/include/rev2/soc/syscon_reg.h

@@ -0,0 +1,657 @@
+/**
+ * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** SYSCON_WIFI_BB_CFG_REG register
+ *  register description
+ */
+#define SYSCON_WIFI_BB_CFG_REG (DR_REG_SYSCON_BASE + 0xc)
+/** SYSCON_WIFI_BB_CFG : R/W; bitpos: [31:0]; default: 0;
+ *  Need add description
+ */
+#define SYSCON_WIFI_BB_CFG    0xFFFFFFFFU
+#define SYSCON_WIFI_BB_CFG_M  (SYSCON_WIFI_BB_CFG_V << SYSCON_WIFI_BB_CFG_S)
+#define SYSCON_WIFI_BB_CFG_V  0xFFFFFFFFU
+#define SYSCON_WIFI_BB_CFG_S  0
+
+/** SYSCON_WIFI_BB_CFG_2_REG register
+ *  register description
+ */
+#define SYSCON_WIFI_BB_CFG_2_REG (DR_REG_SYSCON_BASE + 0x10)
+/** SYSCON_WIFI_BB_CFG_2 : R/W; bitpos: [31:0]; default: 0;
+ *  Need add description
+ */
+#define SYSCON_WIFI_BB_CFG_2    0xFFFFFFFFU
+#define SYSCON_WIFI_BB_CFG_2_M  (SYSCON_WIFI_BB_CFG_2_V << SYSCON_WIFI_BB_CFG_2_S)
+#define SYSCON_WIFI_BB_CFG_2_V  0xFFFFFFFFU
+#define SYSCON_WIFI_BB_CFG_2_S  0
+
+/** SYSCON_HOST_INF_SEL_REG register
+ *  register description
+ */
+#define SYSCON_HOST_INF_SEL_REG (DR_REG_SYSCON_BASE + 0x1c)
+/** SYSCON_PERI_IO_SWAP : R/W; bitpos: [7:0]; default: 0;
+ *  Need add description
+ */
+#define SYSCON_PERI_IO_SWAP    0x000000FFU
+#define SYSCON_PERI_IO_SWAP_M  (SYSCON_PERI_IO_SWAP_V << SYSCON_PERI_IO_SWAP_S)
+#define SYSCON_PERI_IO_SWAP_V  0x000000FFU
+#define SYSCON_PERI_IO_SWAP_S  0
+
+/** SYSCON_EXT_MEM_PMS_LOCK_REG register
+ *  register description
+ */
+#define SYSCON_EXT_MEM_PMS_LOCK_REG (DR_REG_SYSCON_BASE + 0x20)
+/** SYSCON_EXT_MEM_PMS_LOCK : R/W; bitpos: [0]; default: 0;
+ *  Need add description
+ */
+#define SYSCON_EXT_MEM_PMS_LOCK    (BIT(0))
+#define SYSCON_EXT_MEM_PMS_LOCK_M  (SYSCON_EXT_MEM_PMS_LOCK_V << SYSCON_EXT_MEM_PMS_LOCK_S)
+#define SYSCON_EXT_MEM_PMS_LOCK_V  0x00000001U
+#define SYSCON_EXT_MEM_PMS_LOCK_S  0
+
+/** SYSCON_FLASH_ACE0_ATTR_REG register
+ *  register description
+ */
+#define SYSCON_FLASH_ACE0_ATTR_REG (DR_REG_SYSCON_BASE + 0x28)
+/** SYSCON_FLASH_ACE0_ATTR : R/W; bitpos: [1:0]; default: 3;
+ *  Need add description
+ */
+#define SYSCON_FLASH_ACE0_ATTR    0x00000003U
+#define SYSCON_FLASH_ACE0_ATTR_M  (SYSCON_FLASH_ACE0_ATTR_V << SYSCON_FLASH_ACE0_ATTR_S)
+#define SYSCON_FLASH_ACE0_ATTR_V  0x00000003U
+#define SYSCON_FLASH_ACE0_ATTR_S  0
+
+/** SYSCON_FLASH_ACE1_ATTR_REG register
+ *  register description
+ */
+#define SYSCON_FLASH_ACE1_ATTR_REG (DR_REG_SYSCON_BASE + 0x2c)
+/** SYSCON_FLASH_ACE1_ATTR : R/W; bitpos: [1:0]; default: 3;
+ *  Need add description
+ */
+#define SYSCON_FLASH_ACE1_ATTR    0x00000003U
+#define SYSCON_FLASH_ACE1_ATTR_M  (SYSCON_FLASH_ACE1_ATTR_V << SYSCON_FLASH_ACE1_ATTR_S)
+#define SYSCON_FLASH_ACE1_ATTR_V  0x00000003U
+#define SYSCON_FLASH_ACE1_ATTR_S  0
+
+/** SYSCON_FLASH_ACE2_ATTR_REG register
+ *  register description
+ */
+#define SYSCON_FLASH_ACE2_ATTR_REG (DR_REG_SYSCON_BASE + 0x30)
+/** SYSCON_FLASH_ACE2_ATTR : R/W; bitpos: [1:0]; default: 3;
+ *  Need add description
+ */
+#define SYSCON_FLASH_ACE2_ATTR    0x00000003U
+#define SYSCON_FLASH_ACE2_ATTR_M  (SYSCON_FLASH_ACE2_ATTR_V << SYSCON_FLASH_ACE2_ATTR_S)
+#define SYSCON_FLASH_ACE2_ATTR_V  0x00000003U
+#define SYSCON_FLASH_ACE2_ATTR_S  0
+
+/** SYSCON_FLASH_ACE3_ATTR_REG register
+ *  register description
+ */
+#define SYSCON_FLASH_ACE3_ATTR_REG (DR_REG_SYSCON_BASE + 0x34)
+/** SYSCON_FLASH_ACE3_ATTR : R/W; bitpos: [1:0]; default: 3;
+ *  Need add description
+ */
+#define SYSCON_FLASH_ACE3_ATTR    0x00000003U
+#define SYSCON_FLASH_ACE3_ATTR_M  (SYSCON_FLASH_ACE3_ATTR_V << SYSCON_FLASH_ACE3_ATTR_S)
+#define SYSCON_FLASH_ACE3_ATTR_V  0x00000003U
+#define SYSCON_FLASH_ACE3_ATTR_S  0
+
+/** SYSCON_FLASH_ACE0_ADDR_REG register
+ *  register description
+ */
+#define SYSCON_FLASH_ACE0_ADDR_REG (DR_REG_SYSCON_BASE + 0x38)
+/** SYSCON_FLASH_ACE0_ADDR_S : R/W; bitpos: [31:0]; default: 0;
+ *  Need add description
+ */
+#define SYSCON_FLASH_ACE0_ADDR_S    0xFFFFFFFFU
+#define SYSCON_FLASH_ACE0_ADDR_S_M  (SYSCON_FLASH_ACE0_ADDR_S_V << SYSCON_FLASH_ACE0_ADDR_S_S)
+#define SYSCON_FLASH_ACE0_ADDR_S_V  0xFFFFFFFFU
+#define SYSCON_FLASH_ACE0_ADDR_S_S  0
+
+/** SYSCON_FLASH_ACE1_ADDR_REG register
+ *  register description
+ */
+#define SYSCON_FLASH_ACE1_ADDR_REG (DR_REG_SYSCON_BASE + 0x3c)
+/** SYSCON_FLASH_ACE1_ADDR_S : R/W; bitpos: [31:0]; default: 4194304;
+ *  Need add description
+ */
+#define SYSCON_FLASH_ACE1_ADDR_S    0xFFFFFFFFU
+#define SYSCON_FLASH_ACE1_ADDR_S_M  (SYSCON_FLASH_ACE1_ADDR_S_V << SYSCON_FLASH_ACE1_ADDR_S_S)
+#define SYSCON_FLASH_ACE1_ADDR_S_V  0xFFFFFFFFU
+#define SYSCON_FLASH_ACE1_ADDR_S_S  0
+
+/** SYSCON_FLASH_ACE2_ADDR_REG register
+ *  register description
+ */
+#define SYSCON_FLASH_ACE2_ADDR_REG (DR_REG_SYSCON_BASE + 0x40)
+/** SYSCON_FLASH_ACE2_ADDR_S : R/W; bitpos: [31:0]; default: 8388608;
+ *  Need add description
+ */
+#define SYSCON_FLASH_ACE2_ADDR_S    0xFFFFFFFFU
+#define SYSCON_FLASH_ACE2_ADDR_S_M  (SYSCON_FLASH_ACE2_ADDR_S_V << SYSCON_FLASH_ACE2_ADDR_S_S)
+#define SYSCON_FLASH_ACE2_ADDR_S_V  0xFFFFFFFFU
+#define SYSCON_FLASH_ACE2_ADDR_S_S  0
+
+/** SYSCON_FLASH_ACE3_ADDR_REG register
+ *  register description
+ */
+#define SYSCON_FLASH_ACE3_ADDR_REG (DR_REG_SYSCON_BASE + 0x44)
+/** SYSCON_FLASH_ACE3_ADDR_S : R/W; bitpos: [31:0]; default: 12582912;
+ *  Need add description
+ */
+#define SYSCON_FLASH_ACE3_ADDR_S    0xFFFFFFFFU
+#define SYSCON_FLASH_ACE3_ADDR_S_M  (SYSCON_FLASH_ACE3_ADDR_S_V << SYSCON_FLASH_ACE3_ADDR_S_S)
+#define SYSCON_FLASH_ACE3_ADDR_S_V  0xFFFFFFFFU
+#define SYSCON_FLASH_ACE3_ADDR_S_S  0
+
+/** SYSCON_FLASH_ACE0_SIZE_REG register
+ *  register description
+ */
+#define SYSCON_FLASH_ACE0_SIZE_REG (DR_REG_SYSCON_BASE + 0x48)
+/** SYSCON_FLASH_ACE0_SIZE : R/W; bitpos: [12:0]; default: 1024;
+ *  Need add description
+ */
+#define SYSCON_FLASH_ACE0_SIZE    0x00001FFFU
+#define SYSCON_FLASH_ACE0_SIZE_M  (SYSCON_FLASH_ACE0_SIZE_V << SYSCON_FLASH_ACE0_SIZE_S)
+#define SYSCON_FLASH_ACE0_SIZE_V  0x00001FFFU
+#define SYSCON_FLASH_ACE0_SIZE_S  0
+
+/** SYSCON_FLASH_ACE1_SIZE_REG register
+ *  register description
+ */
+#define SYSCON_FLASH_ACE1_SIZE_REG (DR_REG_SYSCON_BASE + 0x4c)
+/** SYSCON_FLASH_ACE1_SIZE : R/W; bitpos: [12:0]; default: 1024;
+ *  Need add description
+ */
+#define SYSCON_FLASH_ACE1_SIZE    0x00001FFFU
+#define SYSCON_FLASH_ACE1_SIZE_M  (SYSCON_FLASH_ACE1_SIZE_V << SYSCON_FLASH_ACE1_SIZE_S)
+#define SYSCON_FLASH_ACE1_SIZE_V  0x00001FFFU
+#define SYSCON_FLASH_ACE1_SIZE_S  0
+
+/** SYSCON_FLASH_ACE2_SIZE_REG register
+ *  register description
+ */
+#define SYSCON_FLASH_ACE2_SIZE_REG (DR_REG_SYSCON_BASE + 0x50)
+/** SYSCON_FLASH_ACE2_SIZE : R/W; bitpos: [12:0]; default: 1024;
+ *  Need add description
+ */
+#define SYSCON_FLASH_ACE2_SIZE    0x00001FFFU
+#define SYSCON_FLASH_ACE2_SIZE_M  (SYSCON_FLASH_ACE2_SIZE_V << SYSCON_FLASH_ACE2_SIZE_S)
+#define SYSCON_FLASH_ACE2_SIZE_V  0x00001FFFU
+#define SYSCON_FLASH_ACE2_SIZE_S  0
+
+/** SYSCON_FLASH_ACE3_SIZE_REG register
+ *  register description
+ */
+#define SYSCON_FLASH_ACE3_SIZE_REG (DR_REG_SYSCON_BASE + 0x54)
+/** SYSCON_FLASH_ACE3_SIZE : R/W; bitpos: [12:0]; default: 1024;
+ *  Need add description
+ */
+#define SYSCON_FLASH_ACE3_SIZE    0x00001FFFU
+#define SYSCON_FLASH_ACE3_SIZE_M  (SYSCON_FLASH_ACE3_SIZE_V << SYSCON_FLASH_ACE3_SIZE_S)
+#define SYSCON_FLASH_ACE3_SIZE_V  0x00001FFFU
+#define SYSCON_FLASH_ACE3_SIZE_S  0
+
+/** SYSCON_SPI_MEM_PMS_CTRL_REG register
+ *  register description
+ */
+#define SYSCON_SPI_MEM_PMS_CTRL_REG (DR_REG_SYSCON_BASE + 0x88)
+/** SYSCON_SPI_MEM_REJECT_INT : RO; bitpos: [0]; default: 0;
+ *  Need add description
+ */
+#define SYSCON_SPI_MEM_REJECT_INT    (BIT(0))
+#define SYSCON_SPI_MEM_REJECT_INT_M  (SYSCON_SPI_MEM_REJECT_INT_V << SYSCON_SPI_MEM_REJECT_INT_S)
+#define SYSCON_SPI_MEM_REJECT_INT_V  0x00000001U
+#define SYSCON_SPI_MEM_REJECT_INT_S  0
+/** SYSCON_SPI_MEM_REJECT_CLR : WOD; bitpos: [1]; default: 0;
+ *  Need add description
+ */
+#define SYSCON_SPI_MEM_REJECT_CLR    (BIT(1))
+#define SYSCON_SPI_MEM_REJECT_CLR_M  (SYSCON_SPI_MEM_REJECT_CLR_V << SYSCON_SPI_MEM_REJECT_CLR_S)
+#define SYSCON_SPI_MEM_REJECT_CLR_V  0x00000001U
+#define SYSCON_SPI_MEM_REJECT_CLR_S  1
+/** SYSCON_SPI_MEM_REJECT_CDE : RO; bitpos: [6:2]; default: 0;
+ *  Need add description
+ */
+#define SYSCON_SPI_MEM_REJECT_CDE    0x0000001FU
+#define SYSCON_SPI_MEM_REJECT_CDE_M  (SYSCON_SPI_MEM_REJECT_CDE_V << SYSCON_SPI_MEM_REJECT_CDE_S)
+#define SYSCON_SPI_MEM_REJECT_CDE_V  0x0000001FU
+#define SYSCON_SPI_MEM_REJECT_CDE_S  2
+
+/** SYSCON_SPI_MEM_REJECT_ADDR_REG register
+ *  register description
+ */
+#define SYSCON_SPI_MEM_REJECT_ADDR_REG (DR_REG_SYSCON_BASE + 0x8c)
+/** SYSCON_SPI_MEM_REJECT_ADDR : RO; bitpos: [31:0]; default: 0;
+ *  Need add description
+ */
+#define SYSCON_SPI_MEM_REJECT_ADDR    0xFFFFFFFFU
+#define SYSCON_SPI_MEM_REJECT_ADDR_M  (SYSCON_SPI_MEM_REJECT_ADDR_V << SYSCON_SPI_MEM_REJECT_ADDR_S)
+#define SYSCON_SPI_MEM_REJECT_ADDR_V  0xFFFFFFFFU
+#define SYSCON_SPI_MEM_REJECT_ADDR_S  0
+
+/** SYSCON_SYSCON_SDIO_CTRL_REG register
+ *  register description
+ */
+#define SYSCON_SYSCON_SDIO_CTRL_REG (DR_REG_SYSCON_BASE + 0x90)
+/** SYSCON_SDIO_WIN_ACCESS_EN : R/W; bitpos: [0]; default: 0;
+ *  Need add description
+ */
+#define SYSCON_SDIO_WIN_ACCESS_EN    (BIT(0))
+#define SYSCON_SDIO_WIN_ACCESS_EN_M  (SYSCON_SDIO_WIN_ACCESS_EN_V << SYSCON_SDIO_WIN_ACCESS_EN_S)
+#define SYSCON_SDIO_WIN_ACCESS_EN_V  0x00000001U
+#define SYSCON_SDIO_WIN_ACCESS_EN_S  0
+
+/** SYSCON_REDCY_SIG0_REG register
+ *  register description
+ */
+#define SYSCON_REDCY_SIG0_REG (DR_REG_SYSCON_BASE + 0x94)
+/** SYSCON_REDCY_SIG0 : R/W; bitpos: [30:0]; default: 0;
+ *  Need add description
+ */
+#define SYSCON_REDCY_SIG0    0x7FFFFFFFU
+#define SYSCON_REDCY_SIG0_M  (SYSCON_REDCY_SIG0_V << SYSCON_REDCY_SIG0_S)
+#define SYSCON_REDCY_SIG0_V  0x7FFFFFFFU
+#define SYSCON_REDCY_SIG0_S  0
+/** SYSCON_REDCY_ANDOR : RO; bitpos: [31]; default: 0;
+ *  Need add description
+ */
+#define SYSCON_REDCY_ANDOR    (BIT(31))
+#define SYSCON_REDCY_ANDOR_M  (SYSCON_REDCY_ANDOR_V << SYSCON_REDCY_ANDOR_S)
+#define SYSCON_REDCY_ANDOR_V  0x00000001U
+#define SYSCON_REDCY_ANDOR_S  31
+
+/** SYSCON_REDCY_SIG1_REG register
+ *  register description
+ */
+#define SYSCON_REDCY_SIG1_REG (DR_REG_SYSCON_BASE + 0x98)
+/** SYSCON_REDCY_SIG1 : R/W; bitpos: [30:0]; default: 0;
+ *  Need add description
+ */
+#define SYSCON_REDCY_SIG1    0x7FFFFFFFU
+#define SYSCON_REDCY_SIG1_M  (SYSCON_REDCY_SIG1_V << SYSCON_REDCY_SIG1_S)
+#define SYSCON_REDCY_SIG1_V  0x7FFFFFFFU
+#define SYSCON_REDCY_SIG1_S  0
+/** SYSCON_REDCY_NANDOR : RO; bitpos: [31]; default: 0;
+ *  Need add description
+ */
+#define SYSCON_REDCY_NANDOR    (BIT(31))
+#define SYSCON_REDCY_NANDOR_M  (SYSCON_REDCY_NANDOR_V << SYSCON_REDCY_NANDOR_S)
+#define SYSCON_REDCY_NANDOR_V  0x00000001U
+#define SYSCON_REDCY_NANDOR_S  31
+
+/** SYSCON_FRONT_END_MEM_PD_REG register
+ *  register description
+ */
+#define SYSCON_FRONT_END_MEM_PD_REG (DR_REG_SYSCON_BASE + 0x9c)
+/** SYSCON_AGC_MEM_FORCE_PU : R/W; bitpos: [0]; default: 1;
+ *  Need add description
+ */
+#define SYSCON_AGC_MEM_FORCE_PU    (BIT(0))
+#define SYSCON_AGC_MEM_FORCE_PU_M  (SYSCON_AGC_MEM_FORCE_PU_V << SYSCON_AGC_MEM_FORCE_PU_S)
+#define SYSCON_AGC_MEM_FORCE_PU_V  0x00000001U
+#define SYSCON_AGC_MEM_FORCE_PU_S  0
+/** SYSCON_AGC_MEM_FORCE_PD : R/W; bitpos: [1]; default: 0;
+ *  Need add description
+ */
+#define SYSCON_AGC_MEM_FORCE_PD    (BIT(1))
+#define SYSCON_AGC_MEM_FORCE_PD_M  (SYSCON_AGC_MEM_FORCE_PD_V << SYSCON_AGC_MEM_FORCE_PD_S)
+#define SYSCON_AGC_MEM_FORCE_PD_V  0x00000001U
+#define SYSCON_AGC_MEM_FORCE_PD_S  1
+/** SYSCON_PBUS_MEM_FORCE_PU : R/W; bitpos: [2]; default: 1;
+ *  Need add description
+ */
+#define SYSCON_PBUS_MEM_FORCE_PU    (BIT(2))
+#define SYSCON_PBUS_MEM_FORCE_PU_M  (SYSCON_PBUS_MEM_FORCE_PU_V << SYSCON_PBUS_MEM_FORCE_PU_S)
+#define SYSCON_PBUS_MEM_FORCE_PU_V  0x00000001U
+#define SYSCON_PBUS_MEM_FORCE_PU_S  2
+/** SYSCON_PBUS_MEM_FORCE_PD : R/W; bitpos: [3]; default: 0;
+ *  Need add description
+ */
+#define SYSCON_PBUS_MEM_FORCE_PD    (BIT(3))
+#define SYSCON_PBUS_MEM_FORCE_PD_M  (SYSCON_PBUS_MEM_FORCE_PD_V << SYSCON_PBUS_MEM_FORCE_PD_S)
+#define SYSCON_PBUS_MEM_FORCE_PD_V  0x00000001U
+#define SYSCON_PBUS_MEM_FORCE_PD_S  3
+/** SYSCON_DC_MEM_FORCE_PU : R/W; bitpos: [4]; default: 1;
+ *  Need add description
+ */
+#define SYSCON_DC_MEM_FORCE_PU    (BIT(4))
+#define SYSCON_DC_MEM_FORCE_PU_M  (SYSCON_DC_MEM_FORCE_PU_V << SYSCON_DC_MEM_FORCE_PU_S)
+#define SYSCON_DC_MEM_FORCE_PU_V  0x00000001U
+#define SYSCON_DC_MEM_FORCE_PU_S  4
+/** SYSCON_DC_MEM_FORCE_PD : R/W; bitpos: [5]; default: 0;
+ *  Need add description
+ */
+#define SYSCON_DC_MEM_FORCE_PD    (BIT(5))
+#define SYSCON_DC_MEM_FORCE_PD_M  (SYSCON_DC_MEM_FORCE_PD_V << SYSCON_DC_MEM_FORCE_PD_S)
+#define SYSCON_DC_MEM_FORCE_PD_V  0x00000001U
+#define SYSCON_DC_MEM_FORCE_PD_S  5
+
+/** SYSCON_RETENTION_CTRL_REG register
+ *  register description
+ */
+#define SYSCON_RETENTION_CTRL_REG (DR_REG_SYSCON_BASE + 0xa0)
+/** SYSCON_NOBYPASS_CPU_ISO_RST : R/W; bitpos: [27]; default: 0;
+ *  Need add description
+ */
+#define SYSCON_NOBYPASS_CPU_ISO_RST    (BIT(27))
+#define SYSCON_NOBYPASS_CPU_ISO_RST_M  (SYSCON_NOBYPASS_CPU_ISO_RST_V << SYSCON_NOBYPASS_CPU_ISO_RST_S)
+#define SYSCON_NOBYPASS_CPU_ISO_RST_V  0x00000001U
+#define SYSCON_NOBYPASS_CPU_ISO_RST_S  27
+
+/** SYSCON_CLKGATE_FORCE_ON_REG register
+ *  register description
+ */
+#define SYSCON_CLKGATE_FORCE_ON_REG (DR_REG_SYSCON_BASE + 0xa4)
+/** SYSCON_ROM_CLKGATE_FORCE_ON : R/W; bitpos: [1:0]; default: 3;
+ *  Need add description
+ */
+#define SYSCON_ROM_CLKGATE_FORCE_ON    0x00000003U
+#define SYSCON_ROM_CLKGATE_FORCE_ON_M  (SYSCON_ROM_CLKGATE_FORCE_ON_V << SYSCON_ROM_CLKGATE_FORCE_ON_S)
+#define SYSCON_ROM_CLKGATE_FORCE_ON_V  0x00000003U
+#define SYSCON_ROM_CLKGATE_FORCE_ON_S  0
+/** SYSCON_SRAM_CLKGATE_FORCE_ON : R/W; bitpos: [5:2]; default: 15;
+ *  Need add description
+ */
+#define SYSCON_SRAM_CLKGATE_FORCE_ON    0x0000000FU
+#define SYSCON_SRAM_CLKGATE_FORCE_ON_M  (SYSCON_SRAM_CLKGATE_FORCE_ON_V << SYSCON_SRAM_CLKGATE_FORCE_ON_S)
+#define SYSCON_SRAM_CLKGATE_FORCE_ON_V  0x0000000FU
+#define SYSCON_SRAM_CLKGATE_FORCE_ON_S  2
+
+/** SYSCON_MEM_POWER_DOWN_REG register
+ *  register description
+ */
+#define SYSCON_MEM_POWER_DOWN_REG (DR_REG_SYSCON_BASE + 0xa8)
+/** SYSCON_ROM_POWER_DOWN : R/W; bitpos: [1:0]; default: 0;
+ *  Need add description
+ */
+#define SYSCON_ROM_POWER_DOWN    0x00000003U
+#define SYSCON_ROM_POWER_DOWN_M  (SYSCON_ROM_POWER_DOWN_V << SYSCON_ROM_POWER_DOWN_S)
+#define SYSCON_ROM_POWER_DOWN_V  0x00000003U
+#define SYSCON_ROM_POWER_DOWN_S  0
+/** SYSCON_SRAM_POWER_DOWN : R/W; bitpos: [5:2]; default: 0;
+ *  Need add description
+ */
+#define SYSCON_SRAM_POWER_DOWN    0x0000000FU
+#define SYSCON_SRAM_POWER_DOWN_M  (SYSCON_SRAM_POWER_DOWN_V << SYSCON_SRAM_POWER_DOWN_S)
+#define SYSCON_SRAM_POWER_DOWN_V  0x0000000FU
+#define SYSCON_SRAM_POWER_DOWN_S  2
+
+/** SYSCON_MEM_POWER_UP_REG register
+ *  register description
+ */
+#define SYSCON_MEM_POWER_UP_REG (DR_REG_SYSCON_BASE + 0xac)
+/** SYSCON_ROM_POWER_UP : R/W; bitpos: [1:0]; default: 3;
+ *  Need add description
+ */
+#define SYSCON_ROM_POWER_UP    0x00000003U
+#define SYSCON_ROM_POWER_UP_M  (SYSCON_ROM_POWER_UP_V << SYSCON_ROM_POWER_UP_S)
+#define SYSCON_ROM_POWER_UP_V  0x00000003U
+#define SYSCON_ROM_POWER_UP_S  0
+/** SYSCON_SRAM_POWER_UP : R/W; bitpos: [5:2]; default: 15;
+ *  Need add description
+ */
+#define SYSCON_SRAM_POWER_UP    0x0000000FU
+#define SYSCON_SRAM_POWER_UP_M  (SYSCON_SRAM_POWER_UP_V << SYSCON_SRAM_POWER_UP_S)
+#define SYSCON_SRAM_POWER_UP_V  0x0000000FU
+#define SYSCON_SRAM_POWER_UP_S  2
+
+/** SYSCON_RND_DATA_REG register
+ *  register description
+ */
+#define SYSCON_RND_DATA_REG (DR_REG_SYSCON_BASE + 0xb0)
+/** SYSCON_RND_DATA : RO; bitpos: [31:0]; default: 0;
+ *  Need add description
+ */
+#define SYSCON_RND_DATA    0xFFFFFFFFU
+#define SYSCON_RND_DATA_M  (SYSCON_RND_DATA_V << SYSCON_RND_DATA_S)
+#define SYSCON_RND_DATA_V  0xFFFFFFFFU
+#define SYSCON_RND_DATA_S  0
+
+/** SYSCON_PERI_BACKUP_CONFIG_REG register
+ *  register description
+ */
+#define SYSCON_PERI_BACKUP_CONFIG_REG (DR_REG_SYSCON_BASE + 0xb4)
+/** SYSCON_PERI_BACKUP_FLOW_ERR : RO; bitpos: [2:0]; default: 0;
+ *  Need add description
+ */
+#define SYSCON_PERI_BACKUP_FLOW_ERR    0x00000007U
+#define SYSCON_PERI_BACKUP_FLOW_ERR_M  (SYSCON_PERI_BACKUP_FLOW_ERR_V << SYSCON_PERI_BACKUP_FLOW_ERR_S)
+#define SYSCON_PERI_BACKUP_FLOW_ERR_V  0x00000007U
+#define SYSCON_PERI_BACKUP_FLOW_ERR_S  0
+/** SYSCON_PERI_BACKUP_ADDR_MAP_MODE : R/W; bitpos: [3]; default: 0;
+ *  Need add description
+ */
+#define SYSCON_PERI_BACKUP_ADDR_MAP_MODE    (BIT(3))
+#define SYSCON_PERI_BACKUP_ADDR_MAP_MODE_M  (SYSCON_PERI_BACKUP_ADDR_MAP_MODE_V << SYSCON_PERI_BACKUP_ADDR_MAP_MODE_S)
+#define SYSCON_PERI_BACKUP_ADDR_MAP_MODE_V  0x00000001U
+#define SYSCON_PERI_BACKUP_ADDR_MAP_MODE_S  3
+/** SYSCON_PERI_BACKUP_BURST_LIMIT : R/W; bitpos: [8:4]; default: 8;
+ *  Need add description
+ */
+#define SYSCON_PERI_BACKUP_BURST_LIMIT    0x0000001FU
+#define SYSCON_PERI_BACKUP_BURST_LIMIT_M  (SYSCON_PERI_BACKUP_BURST_LIMIT_V << SYSCON_PERI_BACKUP_BURST_LIMIT_S)
+#define SYSCON_PERI_BACKUP_BURST_LIMIT_V  0x0000001FU
+#define SYSCON_PERI_BACKUP_BURST_LIMIT_S  4
+/** SYSCON_PERI_BACKUP_TOUT_THRES : R/W; bitpos: [18:9]; default: 50;
+ *  Need add description
+ */
+#define SYSCON_PERI_BACKUP_TOUT_THRES    0x000003FFU
+#define SYSCON_PERI_BACKUP_TOUT_THRES_M  (SYSCON_PERI_BACKUP_TOUT_THRES_V << SYSCON_PERI_BACKUP_TOUT_THRES_S)
+#define SYSCON_PERI_BACKUP_TOUT_THRES_V  0x000003FFU
+#define SYSCON_PERI_BACKUP_TOUT_THRES_S  9
+/** SYSCON_PERI_BACKUP_SIZE : R/W; bitpos: [28:19]; default: 0;
+ *  Need add description
+ */
+#define SYSCON_PERI_BACKUP_SIZE    0x000003FFU
+#define SYSCON_PERI_BACKUP_SIZE_M  (SYSCON_PERI_BACKUP_SIZE_V << SYSCON_PERI_BACKUP_SIZE_S)
+#define SYSCON_PERI_BACKUP_SIZE_V  0x000003FFU
+#define SYSCON_PERI_BACKUP_SIZE_S  19
+/** SYSCON_PERI_BACKUP_START : WO; bitpos: [29]; default: 0;
+ *  Need add description
+ */
+#define SYSCON_PERI_BACKUP_START    (BIT(29))
+#define SYSCON_PERI_BACKUP_START_M  (SYSCON_PERI_BACKUP_START_V << SYSCON_PERI_BACKUP_START_S)
+#define SYSCON_PERI_BACKUP_START_V  0x00000001U
+#define SYSCON_PERI_BACKUP_START_S  29
+/** SYSCON_PERI_BACKUP_TO_MEM : R/W; bitpos: [30]; default: 0;
+ *  Need add description
+ */
+#define SYSCON_PERI_BACKUP_TO_MEM    (BIT(30))
+#define SYSCON_PERI_BACKUP_TO_MEM_M  (SYSCON_PERI_BACKUP_TO_MEM_V << SYSCON_PERI_BACKUP_TO_MEM_S)
+#define SYSCON_PERI_BACKUP_TO_MEM_V  0x00000001U
+#define SYSCON_PERI_BACKUP_TO_MEM_S  30
+/** SYSCON_PERI_BACKUP_ENA : R/W; bitpos: [31]; default: 0;
+ *  Need add description
+ */
+#define SYSCON_PERI_BACKUP_ENA    (BIT(31))
+#define SYSCON_PERI_BACKUP_ENA_M  (SYSCON_PERI_BACKUP_ENA_V << SYSCON_PERI_BACKUP_ENA_S)
+#define SYSCON_PERI_BACKUP_ENA_V  0x00000001U
+#define SYSCON_PERI_BACKUP_ENA_S  31
+
+/** SYSCON_PERI_BACKUP_APB_ADDR_REG register
+ *  register description
+ */
+#define SYSCON_PERI_BACKUP_APB_ADDR_REG (DR_REG_SYSCON_BASE + 0xb8)
+/** SYSCON_PERI_BACKUP_APB_START_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Need add description
+ */
+#define SYSCON_PERI_BACKUP_APB_START_ADDR    0xFFFFFFFFU
+#define SYSCON_PERI_BACKUP_APB_START_ADDR_M  (SYSCON_PERI_BACKUP_APB_START_ADDR_V << SYSCON_PERI_BACKUP_APB_START_ADDR_S)
+#define SYSCON_PERI_BACKUP_APB_START_ADDR_V  0xFFFFFFFFU
+#define SYSCON_PERI_BACKUP_APB_START_ADDR_S  0
+
+/** SYSCON_PERI_BACKUP_MEM_ADDR_REG register
+ *  register description
+ */
+#define SYSCON_PERI_BACKUP_MEM_ADDR_REG (DR_REG_SYSCON_BASE + 0xbc)
+/** SYSCON_PERI_BACKUP_MEM_START_ADDR : R/W; bitpos: [31:0]; default: 0;
+ *  Need add description
+ */
+#define SYSCON_PERI_BACKUP_MEM_START_ADDR    0xFFFFFFFFU
+#define SYSCON_PERI_BACKUP_MEM_START_ADDR_M  (SYSCON_PERI_BACKUP_MEM_START_ADDR_V << SYSCON_PERI_BACKUP_MEM_START_ADDR_S)
+#define SYSCON_PERI_BACKUP_MEM_START_ADDR_V  0xFFFFFFFFU
+#define SYSCON_PERI_BACKUP_MEM_START_ADDR_S  0
+
+/** SYSCON_PERI_BACKUP_REG_MAP0_REG register
+ *  register description
+ */
+#define SYSCON_PERI_BACKUP_REG_MAP0_REG (DR_REG_SYSCON_BASE + 0xc0)
+/** SYSCON_PERI_BACKUP_REG_MAP0 : R/W; bitpos: [31:0]; default: 0;
+ *  Need add description
+ */
+#define SYSCON_PERI_BACKUP_REG_MAP0    0xFFFFFFFFU
+#define SYSCON_PERI_BACKUP_REG_MAP0_M  (SYSCON_PERI_BACKUP_REG_MAP0_V << SYSCON_PERI_BACKUP_REG_MAP0_S)
+#define SYSCON_PERI_BACKUP_REG_MAP0_V  0xFFFFFFFFU
+#define SYSCON_PERI_BACKUP_REG_MAP0_S  0
+
+/** SYSCON_PERI_BACKUP_REG_MAP1_REG register
+ *  register description
+ */
+#define SYSCON_PERI_BACKUP_REG_MAP1_REG (DR_REG_SYSCON_BASE + 0xc4)
+/** SYSCON_PERI_BACKUP_REG_MAP1 : R/W; bitpos: [31:0]; default: 0;
+ *  Need add description
+ */
+#define SYSCON_PERI_BACKUP_REG_MAP1    0xFFFFFFFFU
+#define SYSCON_PERI_BACKUP_REG_MAP1_M  (SYSCON_PERI_BACKUP_REG_MAP1_V << SYSCON_PERI_BACKUP_REG_MAP1_S)
+#define SYSCON_PERI_BACKUP_REG_MAP1_V  0xFFFFFFFFU
+#define SYSCON_PERI_BACKUP_REG_MAP1_S  0
+
+/** SYSCON_PERI_BACKUP_REG_MAP2_REG register
+ *  register description
+ */
+#define SYSCON_PERI_BACKUP_REG_MAP2_REG (DR_REG_SYSCON_BASE + 0xc8)
+/** SYSCON_PERI_BACKUP_REG_MAP2 : R/W; bitpos: [31:0]; default: 0;
+ *  Need add description
+ */
+#define SYSCON_PERI_BACKUP_REG_MAP2    0xFFFFFFFFU
+#define SYSCON_PERI_BACKUP_REG_MAP2_M  (SYSCON_PERI_BACKUP_REG_MAP2_V << SYSCON_PERI_BACKUP_REG_MAP2_S)
+#define SYSCON_PERI_BACKUP_REG_MAP2_V  0xFFFFFFFFU
+#define SYSCON_PERI_BACKUP_REG_MAP2_S  0
+
+/** SYSCON_PERI_BACKUP_REG_MAP3_REG register
+ *  register description
+ */
+#define SYSCON_PERI_BACKUP_REG_MAP3_REG (DR_REG_SYSCON_BASE + 0xcc)
+/** SYSCON_PERI_BACKUP_REG_MAP3 : R/W; bitpos: [31:0]; default: 0;
+ *  Need add description
+ */
+#define SYSCON_PERI_BACKUP_REG_MAP3    0xFFFFFFFFU
+#define SYSCON_PERI_BACKUP_REG_MAP3_M  (SYSCON_PERI_BACKUP_REG_MAP3_V << SYSCON_PERI_BACKUP_REG_MAP3_S)
+#define SYSCON_PERI_BACKUP_REG_MAP3_V  0xFFFFFFFFU
+#define SYSCON_PERI_BACKUP_REG_MAP3_S  0
+
+/** SYSCON_PERI_BACKUP_INT_RAW_REG register
+ *  register description
+ */
+#define SYSCON_PERI_BACKUP_INT_RAW_REG (DR_REG_SYSCON_BASE + 0xd0)
+/** SYSCON_PERI_BACKUP_DONE_INT_RAW : RO; bitpos: [0]; default: 0;
+ *  Need add description
+ */
+#define SYSCON_PERI_BACKUP_DONE_INT_RAW    (BIT(0))
+#define SYSCON_PERI_BACKUP_DONE_INT_RAW_M  (SYSCON_PERI_BACKUP_DONE_INT_RAW_V << SYSCON_PERI_BACKUP_DONE_INT_RAW_S)
+#define SYSCON_PERI_BACKUP_DONE_INT_RAW_V  0x00000001U
+#define SYSCON_PERI_BACKUP_DONE_INT_RAW_S  0
+/** SYSCON_PERI_BACKUP_ERR_INT_RAW : RO; bitpos: [1]; default: 0;
+ *  Need add description
+ */
+#define SYSCON_PERI_BACKUP_ERR_INT_RAW    (BIT(1))
+#define SYSCON_PERI_BACKUP_ERR_INT_RAW_M  (SYSCON_PERI_BACKUP_ERR_INT_RAW_V << SYSCON_PERI_BACKUP_ERR_INT_RAW_S)
+#define SYSCON_PERI_BACKUP_ERR_INT_RAW_V  0x00000001U
+#define SYSCON_PERI_BACKUP_ERR_INT_RAW_S  1
+
+/** SYSCON_PERI_BACKUP_INT_ST_REG register
+ *  register description
+ */
+#define SYSCON_PERI_BACKUP_INT_ST_REG (DR_REG_SYSCON_BASE + 0xd4)
+/** SYSCON_PERI_BACKUP_DONE_INT_ST : RO; bitpos: [0]; default: 0;
+ *  Need add description
+ */
+#define SYSCON_PERI_BACKUP_DONE_INT_ST    (BIT(0))
+#define SYSCON_PERI_BACKUP_DONE_INT_ST_M  (SYSCON_PERI_BACKUP_DONE_INT_ST_V << SYSCON_PERI_BACKUP_DONE_INT_ST_S)
+#define SYSCON_PERI_BACKUP_DONE_INT_ST_V  0x00000001U
+#define SYSCON_PERI_BACKUP_DONE_INT_ST_S  0
+/** SYSCON_PERI_BACKUP_ERR_INT_ST : RO; bitpos: [1]; default: 0;
+ *  Need add description
+ */
+#define SYSCON_PERI_BACKUP_ERR_INT_ST    (BIT(1))
+#define SYSCON_PERI_BACKUP_ERR_INT_ST_M  (SYSCON_PERI_BACKUP_ERR_INT_ST_V << SYSCON_PERI_BACKUP_ERR_INT_ST_S)
+#define SYSCON_PERI_BACKUP_ERR_INT_ST_V  0x00000001U
+#define SYSCON_PERI_BACKUP_ERR_INT_ST_S  1
+
+/** SYSCON_PERI_BACKUP_INT_ENA_REG register
+ *  register description
+ */
+#define SYSCON_PERI_BACKUP_INT_ENA_REG (DR_REG_SYSCON_BASE + 0xd8)
+/** SYSCON_PERI_BACKUP_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  Need add description
+ */
+#define SYSCON_PERI_BACKUP_DONE_INT_ENA    (BIT(0))
+#define SYSCON_PERI_BACKUP_DONE_INT_ENA_M  (SYSCON_PERI_BACKUP_DONE_INT_ENA_V << SYSCON_PERI_BACKUP_DONE_INT_ENA_S)
+#define SYSCON_PERI_BACKUP_DONE_INT_ENA_V  0x00000001U
+#define SYSCON_PERI_BACKUP_DONE_INT_ENA_S  0
+/** SYSCON_PERI_BACKUP_ERR_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  Need add description
+ */
+#define SYSCON_PERI_BACKUP_ERR_INT_ENA    (BIT(1))
+#define SYSCON_PERI_BACKUP_ERR_INT_ENA_M  (SYSCON_PERI_BACKUP_ERR_INT_ENA_V << SYSCON_PERI_BACKUP_ERR_INT_ENA_S)
+#define SYSCON_PERI_BACKUP_ERR_INT_ENA_V  0x00000001U
+#define SYSCON_PERI_BACKUP_ERR_INT_ENA_S  1
+
+/** SYSCON_PERI_BACKUP_INT_CLR_REG register
+ *  register description
+ */
+#define SYSCON_PERI_BACKUP_INT_CLR_REG (DR_REG_SYSCON_BASE + 0xdc)
+/** SYSCON_PERI_BACKUP_DONE_INT_CLR : WO; bitpos: [0]; default: 0;
+ *  Need add description
+ */
+#define SYSCON_PERI_BACKUP_DONE_INT_CLR    (BIT(0))
+#define SYSCON_PERI_BACKUP_DONE_INT_CLR_M  (SYSCON_PERI_BACKUP_DONE_INT_CLR_V << SYSCON_PERI_BACKUP_DONE_INT_CLR_S)
+#define SYSCON_PERI_BACKUP_DONE_INT_CLR_V  0x00000001U
+#define SYSCON_PERI_BACKUP_DONE_INT_CLR_S  0
+/** SYSCON_PERI_BACKUP_ERR_INT_CLR : WO; bitpos: [1]; default: 0;
+ *  Need add description
+ */
+#define SYSCON_PERI_BACKUP_ERR_INT_CLR    (BIT(1))
+#define SYSCON_PERI_BACKUP_ERR_INT_CLR_M  (SYSCON_PERI_BACKUP_ERR_INT_CLR_V << SYSCON_PERI_BACKUP_ERR_INT_CLR_S)
+#define SYSCON_PERI_BACKUP_ERR_INT_CLR_V  0x00000001U
+#define SYSCON_PERI_BACKUP_ERR_INT_CLR_S  1
+
+/** SYSCON_SYSCON_REGCLK_CONF_REG register
+ *  register description
+ */
+#define SYSCON_SYSCON_REGCLK_CONF_REG (DR_REG_SYSCON_BASE + 0xe0)
+/** SYSCON_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  Need add description
+ */
+#define SYSCON_CLK_EN    (BIT(0))
+#define SYSCON_CLK_EN_M  (SYSCON_CLK_EN_V << SYSCON_CLK_EN_S)
+#define SYSCON_CLK_EN_V  0x00000001U
+#define SYSCON_CLK_EN_S  0
+
+/** SYSCON_SYSCON_DATE_REG register
+ *  register description
+ */
+#define SYSCON_SYSCON_DATE_REG (DR_REG_SYSCON_BASE + 0x3fc)
+/** SYSCON_SYSCON_DATE : R/W; bitpos: [31:0]; default: 34607184;
+ *  Version control
+ */
+#define SYSCON_SYSCON_DATE    0xFFFFFFFFU
+#define SYSCON_SYSCON_DATE_M  (SYSCON_SYSCON_DATE_V << SYSCON_SYSCON_DATE_S)
+#define SYSCON_SYSCON_DATE_V  0xFFFFFFFFU
+#define SYSCON_SYSCON_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32h2/include/rev2/soc/syscon_struct.h

@@ -0,0 +1,706 @@
+/**
+ * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Configuration Registers */
+/** Type of wifi_bb_cfg register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** wifi_bb_cfg : R/W; bitpos: [31:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t wifi_bb_cfg:32;
+    };
+    uint32_t val;
+} syscon_wifi_bb_cfg_reg_t;
+
+/** Type of wifi_bb_cfg_2 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** wifi_bb_cfg_2 : R/W; bitpos: [31:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t wifi_bb_cfg_2:32;
+    };
+    uint32_t val;
+} syscon_wifi_bb_cfg_2_reg_t;
+
+/** Type of host_inf_sel register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** peri_io_swap : R/W; bitpos: [7:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t peri_io_swap:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} syscon_host_inf_sel_reg_t;
+
+/** Type of ext_mem_pms_lock register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** ext_mem_pms_lock : R/W; bitpos: [0]; default: 0;
+         *  Need add description
+         */
+        uint32_t ext_mem_pms_lock:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} syscon_ext_mem_pms_lock_reg_t;
+
+/** Type of flash_ace0_attr register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** flash_ace0_attr : R/W; bitpos: [1:0]; default: 3;
+         *  Need add description
+         */
+        uint32_t flash_ace0_attr:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} syscon_flash_ace0_attr_reg_t;
+
+/** Type of flash_ace1_attr register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** flash_ace1_attr : R/W; bitpos: [1:0]; default: 3;
+         *  Need add description
+         */
+        uint32_t flash_ace1_attr:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} syscon_flash_ace1_attr_reg_t;
+
+/** Type of flash_ace2_attr register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** flash_ace2_attr : R/W; bitpos: [1:0]; default: 3;
+         *  Need add description
+         */
+        uint32_t flash_ace2_attr:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} syscon_flash_ace2_attr_reg_t;
+
+/** Type of flash_ace3_attr register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** flash_ace3_attr : R/W; bitpos: [1:0]; default: 3;
+         *  Need add description
+         */
+        uint32_t flash_ace3_attr:2;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} syscon_flash_ace3_attr_reg_t;
+
+/** Type of flash_ace0_addr register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** flash_ace0_addr_s : R/W; bitpos: [31:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t flash_ace0_addr_s:32;
+    };
+    uint32_t val;
+} syscon_flash_ace0_addr_reg_t;
+
+/** Type of flash_ace1_addr register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** flash_ace1_addr_s : R/W; bitpos: [31:0]; default: 4194304;
+         *  Need add description
+         */
+        uint32_t flash_ace1_addr_s:32;
+    };
+    uint32_t val;
+} syscon_flash_ace1_addr_reg_t;
+
+/** Type of flash_ace2_addr register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** flash_ace2_addr_s : R/W; bitpos: [31:0]; default: 8388608;
+         *  Need add description
+         */
+        uint32_t flash_ace2_addr_s:32;
+    };
+    uint32_t val;
+} syscon_flash_ace2_addr_reg_t;
+
+/** Type of flash_ace3_addr register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** flash_ace3_addr_s : R/W; bitpos: [31:0]; default: 12582912;
+         *  Need add description
+         */
+        uint32_t flash_ace3_addr_s:32;
+    };
+    uint32_t val;
+} syscon_flash_ace3_addr_reg_t;
+
+/** Type of flash_ace0_size register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** flash_ace0_size : R/W; bitpos: [12:0]; default: 1024;
+         *  Need add description
+         */
+        uint32_t flash_ace0_size:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} syscon_flash_ace0_size_reg_t;
+
+/** Type of flash_ace1_size register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** flash_ace1_size : R/W; bitpos: [12:0]; default: 1024;
+         *  Need add description
+         */
+        uint32_t flash_ace1_size:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} syscon_flash_ace1_size_reg_t;
+
+/** Type of flash_ace2_size register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** flash_ace2_size : R/W; bitpos: [12:0]; default: 1024;
+         *  Need add description
+         */
+        uint32_t flash_ace2_size:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} syscon_flash_ace2_size_reg_t;
+
+/** Type of flash_ace3_size register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** flash_ace3_size : R/W; bitpos: [12:0]; default: 1024;
+         *  Need add description
+         */
+        uint32_t flash_ace3_size:13;
+        uint32_t reserved_13:19;
+    };
+    uint32_t val;
+} syscon_flash_ace3_size_reg_t;
+
+/** Type of spi_mem_pms_ctrl register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** spi_mem_reject_int : RO; bitpos: [0]; default: 0;
+         *  Need add description
+         */
+        uint32_t spi_mem_reject_int:1;
+        /** spi_mem_reject_clr : WOD; bitpos: [1]; default: 0;
+         *  Need add description
+         */
+        uint32_t spi_mem_reject_clr:1;
+        /** spi_mem_reject_cde : RO; bitpos: [6:2]; default: 0;
+         *  Need add description
+         */
+        uint32_t spi_mem_reject_cde:5;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} syscon_spi_mem_pms_ctrl_reg_t;
+
+/** Type of spi_mem_reject_addr register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** spi_mem_reject_addr : RO; bitpos: [31:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t spi_mem_reject_addr:32;
+    };
+    uint32_t val;
+} syscon_spi_mem_reject_addr_reg_t;
+
+/** Type of syscon_sdio_ctrl register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** sdio_win_access_en : R/W; bitpos: [0]; default: 0;
+         *  Need add description
+         */
+        uint32_t sdio_win_access_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} syscon_syscon_sdio_ctrl_reg_t;
+
+/** Type of redcy_sig0 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** redcy_sig0 : R/W; bitpos: [30:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t redcy_sig0:31;
+        /** redcy_andor : RO; bitpos: [31]; default: 0;
+         *  Need add description
+         */
+        uint32_t redcy_andor:1;
+    };
+    uint32_t val;
+} syscon_redcy_sig0_reg_t;
+
+/** Type of redcy_sig1 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** redcy_sig1 : R/W; bitpos: [30:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t redcy_sig1:31;
+        /** redcy_nandor : RO; bitpos: [31]; default: 0;
+         *  Need add description
+         */
+        uint32_t redcy_nandor:1;
+    };
+    uint32_t val;
+} syscon_redcy_sig1_reg_t;
+
+/** Type of front_end_mem_pd register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** agc_mem_force_pu : R/W; bitpos: [0]; default: 1;
+         *  Need add description
+         */
+        uint32_t agc_mem_force_pu:1;
+        /** agc_mem_force_pd : R/W; bitpos: [1]; default: 0;
+         *  Need add description
+         */
+        uint32_t agc_mem_force_pd:1;
+        /** pbus_mem_force_pu : R/W; bitpos: [2]; default: 1;
+         *  Need add description
+         */
+        uint32_t pbus_mem_force_pu:1;
+        /** pbus_mem_force_pd : R/W; bitpos: [3]; default: 0;
+         *  Need add description
+         */
+        uint32_t pbus_mem_force_pd:1;
+        /** dc_mem_force_pu : R/W; bitpos: [4]; default: 1;
+         *  Need add description
+         */
+        uint32_t dc_mem_force_pu:1;
+        /** dc_mem_force_pd : R/W; bitpos: [5]; default: 0;
+         *  Need add description
+         */
+        uint32_t dc_mem_force_pd:1;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} syscon_front_end_mem_pd_reg_t;
+
+/** Type of retention_ctrl register
+ *  register description
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:27;
+        /** nobypass_cpu_iso_rst : R/W; bitpos: [27]; default: 0;
+         *  Need add description
+         */
+        uint32_t nobypass_cpu_iso_rst:1;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} syscon_retention_ctrl_reg_t;
+
+/** Type of clkgate_force_on register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** rom_clkgate_force_on : R/W; bitpos: [1:0]; default: 3;
+         *  Need add description
+         */
+        uint32_t rom_clkgate_force_on:2;
+        /** sram_clkgate_force_on : R/W; bitpos: [5:2]; default: 15;
+         *  Need add description
+         */
+        uint32_t sram_clkgate_force_on:4;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} syscon_clkgate_force_on_reg_t;
+
+/** Type of mem_power_down register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** rom_power_down : R/W; bitpos: [1:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t rom_power_down:2;
+        /** sram_power_down : R/W; bitpos: [5:2]; default: 0;
+         *  Need add description
+         */
+        uint32_t sram_power_down:4;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} syscon_mem_power_down_reg_t;
+
+/** Type of mem_power_up register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** rom_power_up : R/W; bitpos: [1:0]; default: 3;
+         *  Need add description
+         */
+        uint32_t rom_power_up:2;
+        /** sram_power_up : R/W; bitpos: [5:2]; default: 15;
+         *  Need add description
+         */
+        uint32_t sram_power_up:4;
+        uint32_t reserved_6:26;
+    };
+    uint32_t val;
+} syscon_mem_power_up_reg_t;
+
+/** Type of rnd_data register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** rnd_data : RO; bitpos: [31:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t rnd_data:32;
+    };
+    uint32_t val;
+} syscon_rnd_data_reg_t;
+
+/** Type of peri_backup_config register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** peri_backup_flow_err : RO; bitpos: [2:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t peri_backup_flow_err:3;
+        /** peri_backup_addr_map_mode : R/W; bitpos: [3]; default: 0;
+         *  Need add description
+         */
+        uint32_t peri_backup_addr_map_mode:1;
+        /** peri_backup_burst_limit : R/W; bitpos: [8:4]; default: 8;
+         *  Need add description
+         */
+        uint32_t peri_backup_burst_limit:5;
+        /** peri_backup_tout_thres : R/W; bitpos: [18:9]; default: 50;
+         *  Need add description
+         */
+        uint32_t peri_backup_tout_thres:10;
+        /** peri_backup_size : R/W; bitpos: [28:19]; default: 0;
+         *  Need add description
+         */
+        uint32_t peri_backup_size:10;
+        /** peri_backup_start : WO; bitpos: [29]; default: 0;
+         *  Need add description
+         */
+        uint32_t peri_backup_start:1;
+        /** peri_backup_to_mem : R/W; bitpos: [30]; default: 0;
+         *  Need add description
+         */
+        uint32_t peri_backup_to_mem:1;
+        /** peri_backup_ena : R/W; bitpos: [31]; default: 0;
+         *  Need add description
+         */
+        uint32_t peri_backup_ena:1;
+    };
+    uint32_t val;
+} syscon_peri_backup_config_reg_t;
+
+/** Type of peri_backup_apb_addr register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** peri_backup_apb_start_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t peri_backup_apb_start_addr:32;
+    };
+    uint32_t val;
+} syscon_peri_backup_apb_addr_reg_t;
+
+/** Type of peri_backup_mem_addr register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** peri_backup_mem_start_addr : R/W; bitpos: [31:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t peri_backup_mem_start_addr:32;
+    };
+    uint32_t val;
+} syscon_peri_backup_mem_addr_reg_t;
+
+/** Type of peri_backup_reg_map0 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** peri_backup_reg_map0 : R/W; bitpos: [31:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t peri_backup_reg_map0:32;
+    };
+    uint32_t val;
+} syscon_peri_backup_reg_map0_reg_t;
+
+/** Type of peri_backup_reg_map1 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** peri_backup_reg_map1 : R/W; bitpos: [31:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t peri_backup_reg_map1:32;
+    };
+    uint32_t val;
+} syscon_peri_backup_reg_map1_reg_t;
+
+/** Type of peri_backup_reg_map2 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** peri_backup_reg_map2 : R/W; bitpos: [31:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t peri_backup_reg_map2:32;
+    };
+    uint32_t val;
+} syscon_peri_backup_reg_map2_reg_t;
+
+/** Type of peri_backup_reg_map3 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** peri_backup_reg_map3 : R/W; bitpos: [31:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t peri_backup_reg_map3:32;
+    };
+    uint32_t val;
+} syscon_peri_backup_reg_map3_reg_t;
+
+/** Type of peri_backup_int_raw register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** peri_backup_done_int_raw : RO; bitpos: [0]; default: 0;
+         *  Need add description
+         */
+        uint32_t peri_backup_done_int_raw:1;
+        /** peri_backup_err_int_raw : RO; bitpos: [1]; default: 0;
+         *  Need add description
+         */
+        uint32_t peri_backup_err_int_raw:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} syscon_peri_backup_int_raw_reg_t;
+
+/** Type of peri_backup_int_st register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** peri_backup_done_int_st : RO; bitpos: [0]; default: 0;
+         *  Need add description
+         */
+        uint32_t peri_backup_done_int_st:1;
+        /** peri_backup_err_int_st : RO; bitpos: [1]; default: 0;
+         *  Need add description
+         */
+        uint32_t peri_backup_err_int_st:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} syscon_peri_backup_int_st_reg_t;
+
+/** Type of peri_backup_int_ena register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** peri_backup_done_int_ena : R/W; bitpos: [0]; default: 0;
+         *  Need add description
+         */
+        uint32_t peri_backup_done_int_ena:1;
+        /** peri_backup_err_int_ena : R/W; bitpos: [1]; default: 0;
+         *  Need add description
+         */
+        uint32_t peri_backup_err_int_ena:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} syscon_peri_backup_int_ena_reg_t;
+
+/** Type of peri_backup_int_clr register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** peri_backup_done_int_clr : WO; bitpos: [0]; default: 0;
+         *  Need add description
+         */
+        uint32_t peri_backup_done_int_clr:1;
+        /** peri_backup_err_int_clr : WO; bitpos: [1]; default: 0;
+         *  Need add description
+         */
+        uint32_t peri_backup_err_int_clr:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} syscon_peri_backup_int_clr_reg_t;
+
+/** Type of syscon_regclk_conf register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 0;
+         *  Need add description
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} syscon_syscon_regclk_conf_reg_t;
+
+/** Type of syscon_date register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** syscon_date : R/W; bitpos: [31:0]; default: 34607184;
+         *  Version control
+         */
+        uint32_t syscon_date:32;
+    };
+    uint32_t val;
+} syscon_syscon_date_reg_t;
+
+
+typedef struct {
+    uint32_t reserved_000[3];
+    volatile syscon_wifi_bb_cfg_reg_t wifi_bb_cfg;
+    volatile syscon_wifi_bb_cfg_2_reg_t wifi_bb_cfg_2;
+    uint32_t reserved_014[2];
+    volatile syscon_host_inf_sel_reg_t host_inf_sel;
+    volatile syscon_ext_mem_pms_lock_reg_t ext_mem_pms_lock;
+    uint32_t reserved_024;
+    volatile syscon_flash_ace0_attr_reg_t flash_ace0_attr;
+    volatile syscon_flash_ace1_attr_reg_t flash_ace1_attr;
+    volatile syscon_flash_ace2_attr_reg_t flash_ace2_attr;
+    volatile syscon_flash_ace3_attr_reg_t flash_ace3_attr;
+    volatile syscon_flash_ace0_addr_reg_t flash_ace0_addr;
+    volatile syscon_flash_ace1_addr_reg_t flash_ace1_addr;
+    volatile syscon_flash_ace2_addr_reg_t flash_ace2_addr;
+    volatile syscon_flash_ace3_addr_reg_t flash_ace3_addr;
+    volatile syscon_flash_ace0_size_reg_t flash_ace0_size;
+    volatile syscon_flash_ace1_size_reg_t flash_ace1_size;
+    volatile syscon_flash_ace2_size_reg_t flash_ace2_size;
+    volatile syscon_flash_ace3_size_reg_t flash_ace3_size;
+    uint32_t reserved_058[12];
+    volatile syscon_spi_mem_pms_ctrl_reg_t spi_mem_pms_ctrl;
+    volatile syscon_spi_mem_reject_addr_reg_t spi_mem_reject_addr;
+    volatile syscon_syscon_sdio_ctrl_reg_t syscon_sdio_ctrl;
+    volatile syscon_redcy_sig0_reg_t redcy_sig0;
+    volatile syscon_redcy_sig1_reg_t redcy_sig1;
+    volatile syscon_front_end_mem_pd_reg_t front_end_mem_pd;
+    volatile syscon_retention_ctrl_reg_t retention_ctrl;
+    volatile syscon_clkgate_force_on_reg_t clkgate_force_on;
+    volatile syscon_mem_power_down_reg_t mem_power_down;
+    volatile syscon_mem_power_up_reg_t mem_power_up;
+    volatile syscon_rnd_data_reg_t rnd_data;
+    volatile syscon_peri_backup_config_reg_t peri_backup_config;
+    volatile syscon_peri_backup_apb_addr_reg_t peri_backup_apb_addr;
+    volatile syscon_peri_backup_mem_addr_reg_t peri_backup_mem_addr;
+    volatile syscon_peri_backup_reg_map0_reg_t peri_backup_reg_map0;
+    volatile syscon_peri_backup_reg_map1_reg_t peri_backup_reg_map1;
+    volatile syscon_peri_backup_reg_map2_reg_t peri_backup_reg_map2;
+    volatile syscon_peri_backup_reg_map3_reg_t peri_backup_reg_map3;
+    volatile syscon_peri_backup_int_raw_reg_t peri_backup_int_raw;
+    volatile syscon_peri_backup_int_st_reg_t peri_backup_int_st;
+    volatile syscon_peri_backup_int_ena_reg_t peri_backup_int_ena;
+    volatile syscon_peri_backup_int_clr_reg_t peri_backup_int_clr;
+    volatile syscon_syscon_regclk_conf_reg_t syscon_regclk_conf;
+    uint32_t reserved_0e4[198];
+    volatile syscon_syscon_date_reg_t syscon_date;
+} syscon_dev_t;
+
+extern syscon_dev_t SYSCON;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(syscon_dev_t) == 0x400, "Invalid size of syscon_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32h2/include/rev2/soc/system_reg.h

@@ -0,0 +1,373 @@
+/**
+ * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#include "soc/clkrst_reg.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** SYSTEM_CPU_PERI_CLK_EN_REG register
+ *  register description
+ */
+#define SYSTEM_CPU_PERI_CLK_EN_REG (DR_REG_SYSTEM_BASE + 0x0)
+/** SYSTEM_CLK_EN_ASSIST_DEBUG : R/W; bitpos: [6]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_CLK_EN_ASSIST_DEBUG    (BIT(6))
+#define SYSTEM_CLK_EN_ASSIST_DEBUG_M  (SYSTEM_CLK_EN_ASSIST_DEBUG_V << SYSTEM_CLK_EN_ASSIST_DEBUG_S)
+#define SYSTEM_CLK_EN_ASSIST_DEBUG_V  0x00000001U
+#define SYSTEM_CLK_EN_ASSIST_DEBUG_S  6
+/** SYSTEM_CLK_EN_DEDICATED_GPIO : R/W; bitpos: [7]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_CLK_EN_DEDICATED_GPIO    (BIT(7))
+#define SYSTEM_CLK_EN_DEDICATED_GPIO_M  (SYSTEM_CLK_EN_DEDICATED_GPIO_V << SYSTEM_CLK_EN_DEDICATED_GPIO_S)
+#define SYSTEM_CLK_EN_DEDICATED_GPIO_V  0x00000001U
+#define SYSTEM_CLK_EN_DEDICATED_GPIO_S  7
+
+/** SYSTEM_CPU_PERI_RST_EN_REG register
+ *  register description
+ */
+#define SYSTEM_CPU_PERI_RST_EN_REG (DR_REG_SYSTEM_BASE + 0x4)
+/** SYSTEM_RST_EN_ASSIST_DEBUG : R/W; bitpos: [6]; default: 1;
+ *  Need add description
+ */
+#define SYSTEM_RST_EN_ASSIST_DEBUG    (BIT(6))
+#define SYSTEM_RST_EN_ASSIST_DEBUG_M  (SYSTEM_RST_EN_ASSIST_DEBUG_V << SYSTEM_RST_EN_ASSIST_DEBUG_S)
+#define SYSTEM_RST_EN_ASSIST_DEBUG_V  0x00000001U
+#define SYSTEM_RST_EN_ASSIST_DEBUG_S  6
+/** SYSTEM_RST_EN_DEDICATED_GPIO : R/W; bitpos: [7]; default: 1;
+ *  Need add description
+ */
+#define SYSTEM_RST_EN_DEDICATED_GPIO    (BIT(7))
+#define SYSTEM_RST_EN_DEDICATED_GPIO_M  (SYSTEM_RST_EN_DEDICATED_GPIO_V << SYSTEM_RST_EN_DEDICATED_GPIO_S)
+#define SYSTEM_RST_EN_DEDICATED_GPIO_V  0x00000001U
+#define SYSTEM_RST_EN_DEDICATED_GPIO_S  7
+
+/** SYSTEM_CPU_PER_CONF_REG register
+ *  register description
+ */
+#define SYSTEM_CPU_PER_CONF_REG (DR_REG_SYSTEM_BASE + 0x8)
+/** SYSTEM_CPU_WAIT_MODE_FORCE_ON : R/W; bitpos: [3]; default: 1;
+ *  Need add description
+ */
+#define SYSTEM_CPU_WAIT_MODE_FORCE_ON    (BIT(3))
+#define SYSTEM_CPU_WAIT_MODE_FORCE_ON_M  (SYSTEM_CPU_WAIT_MODE_FORCE_ON_V << SYSTEM_CPU_WAIT_MODE_FORCE_ON_S)
+#define SYSTEM_CPU_WAIT_MODE_FORCE_ON_V  0x00000001U
+#define SYSTEM_CPU_WAIT_MODE_FORCE_ON_S  3
+/** SYSTEM_CPU_WAITI_DELAY_NUM : R/W; bitpos: [7:4]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_CPU_WAITI_DELAY_NUM    0x0000000FU
+#define SYSTEM_CPU_WAITI_DELAY_NUM_M  (SYSTEM_CPU_WAITI_DELAY_NUM_V << SYSTEM_CPU_WAITI_DELAY_NUM_S)
+#define SYSTEM_CPU_WAITI_DELAY_NUM_V  0x0000000FU
+#define SYSTEM_CPU_WAITI_DELAY_NUM_S  4
+
+/** SYSTEM_MEM_PD_MASK_REG register
+ *  register description
+ */
+#define SYSTEM_MEM_PD_MASK_REG (DR_REG_SYSTEM_BASE + 0xc)
+/** SYSTEM_LSLP_MEM_PD_MASK : R/W; bitpos: [0]; default: 1;
+ *  Need add description
+ */
+#define SYSTEM_LSLP_MEM_PD_MASK    (BIT(0))
+#define SYSTEM_LSLP_MEM_PD_MASK_M  (SYSTEM_LSLP_MEM_PD_MASK_V << SYSTEM_LSLP_MEM_PD_MASK_S)
+#define SYSTEM_LSLP_MEM_PD_MASK_V  0x00000001U
+#define SYSTEM_LSLP_MEM_PD_MASK_S  0
+
+/** SYSTEM_CPU_INTR_FROM_CPU_0_REG register
+ *  register description
+ */
+#define SYSTEM_CPU_INTR_FROM_CPU_0_REG (DR_REG_SYSTEM_BASE + 0x10)
+/** SYSTEM_CPU_INTR_FROM_CPU_0 : R/W; bitpos: [0]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_CPU_INTR_FROM_CPU_0    (BIT(0))
+#define SYSTEM_CPU_INTR_FROM_CPU_0_M  (SYSTEM_CPU_INTR_FROM_CPU_0_V << SYSTEM_CPU_INTR_FROM_CPU_0_S)
+#define SYSTEM_CPU_INTR_FROM_CPU_0_V  0x00000001U
+#define SYSTEM_CPU_INTR_FROM_CPU_0_S  0
+
+/** SYSTEM_CPU_INTR_FROM_CPU_1_REG register
+ *  register description
+ */
+#define SYSTEM_CPU_INTR_FROM_CPU_1_REG (DR_REG_SYSTEM_BASE + 0x14)
+/** SYSTEM_CPU_INTR_FROM_CPU_1 : R/W; bitpos: [0]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_CPU_INTR_FROM_CPU_1    (BIT(0))
+#define SYSTEM_CPU_INTR_FROM_CPU_1_M  (SYSTEM_CPU_INTR_FROM_CPU_1_V << SYSTEM_CPU_INTR_FROM_CPU_1_S)
+#define SYSTEM_CPU_INTR_FROM_CPU_1_V  0x00000001U
+#define SYSTEM_CPU_INTR_FROM_CPU_1_S  0
+
+/** SYSTEM_CPU_INTR_FROM_CPU_2_REG register
+ *  register description
+ */
+#define SYSTEM_CPU_INTR_FROM_CPU_2_REG (DR_REG_SYSTEM_BASE + 0x18)
+/** SYSTEM_CPU_INTR_FROM_CPU_2 : R/W; bitpos: [0]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_CPU_INTR_FROM_CPU_2    (BIT(0))
+#define SYSTEM_CPU_INTR_FROM_CPU_2_M  (SYSTEM_CPU_INTR_FROM_CPU_2_V << SYSTEM_CPU_INTR_FROM_CPU_2_S)
+#define SYSTEM_CPU_INTR_FROM_CPU_2_V  0x00000001U
+#define SYSTEM_CPU_INTR_FROM_CPU_2_S  0
+
+/** SYSTEM_CPU_INTR_FROM_CPU_3_REG register
+ *  register description
+ */
+#define SYSTEM_CPU_INTR_FROM_CPU_3_REG (DR_REG_SYSTEM_BASE + 0x1c)
+/** SYSTEM_CPU_INTR_FROM_CPU_3 : R/W; bitpos: [0]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_CPU_INTR_FROM_CPU_3    (BIT(0))
+#define SYSTEM_CPU_INTR_FROM_CPU_3_M  (SYSTEM_CPU_INTR_FROM_CPU_3_V << SYSTEM_CPU_INTR_FROM_CPU_3_S)
+#define SYSTEM_CPU_INTR_FROM_CPU_3_V  0x00000001U
+#define SYSTEM_CPU_INTR_FROM_CPU_3_S  0
+
+/** SYSTEM_RSA_PD_CTRL_REG register
+ *  register description
+ */
+#define SYSTEM_RSA_PD_CTRL_REG (DR_REG_SYSTEM_BASE + 0x20)
+/** SYSTEM_RSA_MEM_PD : R/W; bitpos: [0]; default: 1;
+ *  Need add description
+ */
+#define SYSTEM_RSA_MEM_PD    (BIT(0))
+#define SYSTEM_RSA_MEM_PD_M  (SYSTEM_RSA_MEM_PD_V << SYSTEM_RSA_MEM_PD_S)
+#define SYSTEM_RSA_MEM_PD_V  0x00000001U
+#define SYSTEM_RSA_MEM_PD_S  0
+/** SYSTEM_RSA_MEM_FORCE_PU : R/W; bitpos: [1]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_RSA_MEM_FORCE_PU    (BIT(1))
+#define SYSTEM_RSA_MEM_FORCE_PU_M  (SYSTEM_RSA_MEM_FORCE_PU_V << SYSTEM_RSA_MEM_FORCE_PU_S)
+#define SYSTEM_RSA_MEM_FORCE_PU_V  0x00000001U
+#define SYSTEM_RSA_MEM_FORCE_PU_S  1
+/** SYSTEM_RSA_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_RSA_MEM_FORCE_PD    (BIT(2))
+#define SYSTEM_RSA_MEM_FORCE_PD_M  (SYSTEM_RSA_MEM_FORCE_PD_V << SYSTEM_RSA_MEM_FORCE_PD_S)
+#define SYSTEM_RSA_MEM_FORCE_PD_V  0x00000001U
+#define SYSTEM_RSA_MEM_FORCE_PD_S  2
+
+/** SYSTEM_EDMA_CTRL_REG register
+ *  register description
+ */
+#define SYSTEM_EDMA_CTRL_REG (DR_REG_SYSTEM_BASE + 0x24)
+/** SYSTEM_EDMA_CLK_ON : R/W; bitpos: [0]; default: 1;
+ *  Need add description
+ */
+#define SYSTEM_EDMA_CLK_ON    (BIT(0))
+#define SYSTEM_EDMA_CLK_ON_M  (SYSTEM_EDMA_CLK_ON_V << SYSTEM_EDMA_CLK_ON_S)
+#define SYSTEM_EDMA_CLK_ON_V  0x00000001U
+#define SYSTEM_EDMA_CLK_ON_S  0
+/** SYSTEM_EDMA_RESET : R/W; bitpos: [1]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_EDMA_RESET    (BIT(1))
+#define SYSTEM_EDMA_RESET_M  (SYSTEM_EDMA_RESET_V << SYSTEM_EDMA_RESET_S)
+#define SYSTEM_EDMA_RESET_V  0x00000001U
+#define SYSTEM_EDMA_RESET_S  1
+
+/** SYSTEM_CACHE_CONTROL_REG register
+ *  register description
+ */
+#define SYSTEM_CACHE_CONTROL_REG (DR_REG_SYSTEM_BASE + 0x28)
+/** SYSTEM_ICACHE_CLK_ON : R/W; bitpos: [0]; default: 1;
+ *  Need add description
+ */
+#define SYSTEM_ICACHE_CLK_ON    (BIT(0))
+#define SYSTEM_ICACHE_CLK_ON_M  (SYSTEM_ICACHE_CLK_ON_V << SYSTEM_ICACHE_CLK_ON_S)
+#define SYSTEM_ICACHE_CLK_ON_V  0x00000001U
+#define SYSTEM_ICACHE_CLK_ON_S  0
+/** SYSTEM_ICACHE_RESET : R/W; bitpos: [1]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_ICACHE_RESET    (BIT(1))
+#define SYSTEM_ICACHE_RESET_M  (SYSTEM_ICACHE_RESET_V << SYSTEM_ICACHE_RESET_S)
+#define SYSTEM_ICACHE_RESET_V  0x00000001U
+#define SYSTEM_ICACHE_RESET_S  1
+/** SYSTEM_DCACHE_CLK_ON : R/W; bitpos: [2]; default: 1;
+ *  Need add description
+ */
+#define SYSTEM_DCACHE_CLK_ON    (BIT(2))
+#define SYSTEM_DCACHE_CLK_ON_M  (SYSTEM_DCACHE_CLK_ON_V << SYSTEM_DCACHE_CLK_ON_S)
+#define SYSTEM_DCACHE_CLK_ON_V  0x00000001U
+#define SYSTEM_DCACHE_CLK_ON_S  2
+/** SYSTEM_DCACHE_RESET : R/W; bitpos: [3]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_DCACHE_RESET    (BIT(3))
+#define SYSTEM_DCACHE_RESET_M  (SYSTEM_DCACHE_RESET_V << SYSTEM_DCACHE_RESET_S)
+#define SYSTEM_DCACHE_RESET_V  0x00000001U
+#define SYSTEM_DCACHE_RESET_S  3
+
+/** SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG register
+ *  register description
+ */
+#define SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG (DR_REG_SYSTEM_BASE + 0x2c)
+/** SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT : R/W; bitpos: [0]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT    (BIT(0))
+#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_M  (SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_V << SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_S)
+#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_V  0x00000001U
+#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_S  0
+/** SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT : R/W; bitpos: [1]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT    (BIT(1))
+#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_M  (SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_V << SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_S)
+#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_V  0x00000001U
+#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_S  1
+/** SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT : R/W; bitpos: [2]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT    (BIT(2))
+#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_M  (SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_V << SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_S)
+#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_V  0x00000001U
+#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_S  2
+/** SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT : R/W; bitpos: [3]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT    (BIT(3))
+#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_M  (SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V << SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S)
+#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V  0x00000001U
+#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S  3
+
+/** SYSTEM_RTC_FASTMEM_CONFIG_REG register
+ *  register description
+ */
+#define SYSTEM_RTC_FASTMEM_CONFIG_REG (DR_REG_SYSTEM_BASE + 0x30)
+/** SYSTEM_RTC_MEM_CRC_START : R/W; bitpos: [8]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_RTC_MEM_CRC_START    (BIT(8))
+#define SYSTEM_RTC_MEM_CRC_START_M  (SYSTEM_RTC_MEM_CRC_START_V << SYSTEM_RTC_MEM_CRC_START_S)
+#define SYSTEM_RTC_MEM_CRC_START_V  0x00000001U
+#define SYSTEM_RTC_MEM_CRC_START_S  8
+/** SYSTEM_RTC_MEM_CRC_ADDR : R/W; bitpos: [19:9]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_RTC_MEM_CRC_ADDR    0x000007FFU
+#define SYSTEM_RTC_MEM_CRC_ADDR_M  (SYSTEM_RTC_MEM_CRC_ADDR_V << SYSTEM_RTC_MEM_CRC_ADDR_S)
+#define SYSTEM_RTC_MEM_CRC_ADDR_V  0x000007FFU
+#define SYSTEM_RTC_MEM_CRC_ADDR_S  9
+/** SYSTEM_RTC_MEM_CRC_LEN : R/W; bitpos: [30:20]; default: 2047;
+ *  Need add description
+ */
+#define SYSTEM_RTC_MEM_CRC_LEN    0x000007FFU
+#define SYSTEM_RTC_MEM_CRC_LEN_M  (SYSTEM_RTC_MEM_CRC_LEN_V << SYSTEM_RTC_MEM_CRC_LEN_S)
+#define SYSTEM_RTC_MEM_CRC_LEN_V  0x000007FFU
+#define SYSTEM_RTC_MEM_CRC_LEN_S  20
+/** SYSTEM_RTC_MEM_CRC_FINISH : RO; bitpos: [31]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_RTC_MEM_CRC_FINISH    (BIT(31))
+#define SYSTEM_RTC_MEM_CRC_FINISH_M  (SYSTEM_RTC_MEM_CRC_FINISH_V << SYSTEM_RTC_MEM_CRC_FINISH_S)
+#define SYSTEM_RTC_MEM_CRC_FINISH_V  0x00000001U
+#define SYSTEM_RTC_MEM_CRC_FINISH_S  31
+
+/** SYSTEM_RTC_FASTMEM_CRC_REG register
+ *  register description
+ */
+#define SYSTEM_RTC_FASTMEM_CRC_REG (DR_REG_SYSTEM_BASE + 0x34)
+/** SYSTEM_RTC_MEM_CRC_RES : RO; bitpos: [31:0]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_RTC_MEM_CRC_RES    0xFFFFFFFFU
+#define SYSTEM_RTC_MEM_CRC_RES_M  (SYSTEM_RTC_MEM_CRC_RES_V << SYSTEM_RTC_MEM_CRC_RES_S)
+#define SYSTEM_RTC_MEM_CRC_RES_V  0xFFFFFFFFU
+#define SYSTEM_RTC_MEM_CRC_RES_S  0
+
+/** SYSTEM_REDUNDANT_ECO_CTRL_REG register
+ *  register description
+ */
+#define SYSTEM_REDUNDANT_ECO_CTRL_REG (DR_REG_SYSTEM_BASE + 0x38)
+/** SYSTEM_REDUNDANT_ECO_DRIVE : R/W; bitpos: [0]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_REDUNDANT_ECO_DRIVE    (BIT(0))
+#define SYSTEM_REDUNDANT_ECO_DRIVE_M  (SYSTEM_REDUNDANT_ECO_DRIVE_V << SYSTEM_REDUNDANT_ECO_DRIVE_S)
+#define SYSTEM_REDUNDANT_ECO_DRIVE_V  0x00000001U
+#define SYSTEM_REDUNDANT_ECO_DRIVE_S  0
+/** SYSTEM_REDUNDANT_ECO_RESULT : RO; bitpos: [1]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_REDUNDANT_ECO_RESULT    (BIT(1))
+#define SYSTEM_REDUNDANT_ECO_RESULT_M  (SYSTEM_REDUNDANT_ECO_RESULT_V << SYSTEM_REDUNDANT_ECO_RESULT_S)
+#define SYSTEM_REDUNDANT_ECO_RESULT_V  0x00000001U
+#define SYSTEM_REDUNDANT_ECO_RESULT_S  1
+
+/** SYSTEM_CLOCK_GATE_REG register
+ *  register description
+ */
+#define SYSTEM_CLOCK_GATE_REG (DR_REG_SYSTEM_BASE + 0x3c)
+/** SYSTEM_CLK_EN : R/W; bitpos: [0]; default: 1;
+ *  Need add description
+ */
+#define SYSTEM_CLK_EN    (BIT(0))
+#define SYSTEM_CLK_EN_M  (SYSTEM_CLK_EN_V << SYSTEM_CLK_EN_S)
+#define SYSTEM_CLK_EN_V  0x00000001U
+#define SYSTEM_CLK_EN_S  0
+
+/** SYSTEM_MEM_PVT_REG register
+ *  register description
+ */
+#define SYSTEM_MEM_PVT_REG (DR_REG_SYSTEM_BASE + 0x40)
+/** SYSTEM_MEM_PATH_LEN : R/W; bitpos: [3:0]; default: 3;
+ *  Need add description
+ */
+#define SYSTEM_MEM_PATH_LEN    0x0000000FU
+#define SYSTEM_MEM_PATH_LEN_M  (SYSTEM_MEM_PATH_LEN_V << SYSTEM_MEM_PATH_LEN_S)
+#define SYSTEM_MEM_PATH_LEN_V  0x0000000FU
+#define SYSTEM_MEM_PATH_LEN_S  0
+/** SYSTEM_MEM_ERR_CNT_CLR : WO; bitpos: [4]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_MEM_ERR_CNT_CLR    (BIT(4))
+#define SYSTEM_MEM_ERR_CNT_CLR_M  (SYSTEM_MEM_ERR_CNT_CLR_V << SYSTEM_MEM_ERR_CNT_CLR_S)
+#define SYSTEM_MEM_ERR_CNT_CLR_V  0x00000001U
+#define SYSTEM_MEM_ERR_CNT_CLR_S  4
+/** SYSTEM_MEM_PVT_MONITOR_EN : R/W; bitpos: [5]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_MEM_PVT_MONITOR_EN    (BIT(5))
+#define SYSTEM_MEM_PVT_MONITOR_EN_M  (SYSTEM_MEM_PVT_MONITOR_EN_V << SYSTEM_MEM_PVT_MONITOR_EN_S)
+#define SYSTEM_MEM_PVT_MONITOR_EN_V  0x00000001U
+#define SYSTEM_MEM_PVT_MONITOR_EN_S  5
+/** SYSTEM_MEM_TIMING_ERR_CNT : RO; bitpos: [21:6]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_MEM_TIMING_ERR_CNT    0x0000FFFFU
+#define SYSTEM_MEM_TIMING_ERR_CNT_M  (SYSTEM_MEM_TIMING_ERR_CNT_V << SYSTEM_MEM_TIMING_ERR_CNT_S)
+#define SYSTEM_MEM_TIMING_ERR_CNT_V  0x0000FFFFU
+#define SYSTEM_MEM_TIMING_ERR_CNT_S  6
+/** SYSTEM_MEM_VT_SEL : R/W; bitpos: [23:22]; default: 0;
+ *  Need add description
+ */
+#define SYSTEM_MEM_VT_SEL    0x00000003U
+#define SYSTEM_MEM_VT_SEL_M  (SYSTEM_MEM_VT_SEL_V << SYSTEM_MEM_VT_SEL_S)
+#define SYSTEM_MEM_VT_SEL_V  0x00000003U
+#define SYSTEM_MEM_VT_SEL_S  22
+
+/** SYSTEM_SYSTEM_REG_DATE_REG register
+ *  register description
+ */
+#define SYSTEM_SYSTEM_REG_DATE_REG (DR_REG_SYSTEM_BASE + 0xffc)
+/** SYSTEM_SYSTEM_REG_DATE : R/W; bitpos: [27:0]; default: 34615872;
+ *  Need add description
+ */
+#define SYSTEM_SYSTEM_REG_DATE    0x0FFFFFFFU
+#define SYSTEM_SYSTEM_REG_DATE_M  (SYSTEM_SYSTEM_REG_DATE_V << SYSTEM_SYSTEM_REG_DATE_S)
+#define SYSTEM_SYSTEM_REG_DATE_V  0x0FFFFFFFU
+#define SYSTEM_SYSTEM_REG_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32h2/include/rev2/soc/system_struct.h

@@ -0,0 +1,379 @@
+/**
+ * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Configuration Registers */
+/** Type of cpu_peri_clk_en register
+ *  register description
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:6;
+        /** clk_en_assist_debug : R/W; bitpos: [6]; default: 0;
+         *  Need add description
+         */
+        uint32_t clk_en_assist_debug:1;
+        /** clk_en_dedicated_gpio : R/W; bitpos: [7]; default: 0;
+         *  Need add description
+         */
+        uint32_t clk_en_dedicated_gpio:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} system_cpu_peri_clk_en_reg_t;
+
+/** Type of cpu_peri_rst_en register
+ *  register description
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:6;
+        /** rst_en_assist_debug : R/W; bitpos: [6]; default: 1;
+         *  Need add description
+         */
+        uint32_t rst_en_assist_debug:1;
+        /** rst_en_dedicated_gpio : R/W; bitpos: [7]; default: 1;
+         *  Need add description
+         */
+        uint32_t rst_en_dedicated_gpio:1;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} system_cpu_peri_rst_en_reg_t;
+
+/** Type of cpu_per_conf register
+ *  register description
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:3;
+        /** cpu_wait_mode_force_on : R/W; bitpos: [3]; default: 1;
+         *  Need add description
+         */
+        uint32_t cpu_wait_mode_force_on:1;
+        /** cpu_waiti_delay_num : R/W; bitpos: [7:4]; default: 0;
+         *  Need add description
+         */
+        uint32_t cpu_waiti_delay_num:4;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} system_cpu_per_conf_reg_t;
+
+/** Type of mem_pd_mask register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** lslp_mem_pd_mask : R/W; bitpos: [0]; default: 1;
+         *  Need add description
+         */
+        uint32_t lslp_mem_pd_mask:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} system_mem_pd_mask_reg_t;
+
+/** Type of cpu_intr_from_cpu_0 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** cpu_intr_from_cpu_0 : R/W; bitpos: [0]; default: 0;
+         *  Need add description
+         */
+        uint32_t cpu_intr_from_cpu_0:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} system_cpu_intr_from_cpu_0_reg_t;
+
+/** Type of cpu_intr_from_cpu_1 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** cpu_intr_from_cpu_1 : R/W; bitpos: [0]; default: 0;
+         *  Need add description
+         */
+        uint32_t cpu_intr_from_cpu_1:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} system_cpu_intr_from_cpu_1_reg_t;
+
+/** Type of cpu_intr_from_cpu_2 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** cpu_intr_from_cpu_2 : R/W; bitpos: [0]; default: 0;
+         *  Need add description
+         */
+        uint32_t cpu_intr_from_cpu_2:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} system_cpu_intr_from_cpu_2_reg_t;
+
+/** Type of cpu_intr_from_cpu_3 register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** cpu_intr_from_cpu_3 : R/W; bitpos: [0]; default: 0;
+         *  Need add description
+         */
+        uint32_t cpu_intr_from_cpu_3:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} system_cpu_intr_from_cpu_3_reg_t;
+
+/** Type of rsa_pd_ctrl register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** rsa_mem_pd : R/W; bitpos: [0]; default: 1;
+         *  Need add description
+         */
+        uint32_t rsa_mem_pd:1;
+        /** rsa_mem_force_pu : R/W; bitpos: [1]; default: 0;
+         *  Need add description
+         */
+        uint32_t rsa_mem_force_pu:1;
+        /** rsa_mem_force_pd : R/W; bitpos: [2]; default: 0;
+         *  Need add description
+         */
+        uint32_t rsa_mem_force_pd:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} system_rsa_pd_ctrl_reg_t;
+
+/** Type of edma_ctrl register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** edma_clk_on : R/W; bitpos: [0]; default: 1;
+         *  Need add description
+         */
+        uint32_t edma_clk_on:1;
+        /** edma_reset : R/W; bitpos: [1]; default: 0;
+         *  Need add description
+         */
+        uint32_t edma_reset:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} system_edma_ctrl_reg_t;
+
+/** Type of cache_control register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** icache_clk_on : R/W; bitpos: [0]; default: 1;
+         *  Need add description
+         */
+        uint32_t icache_clk_on:1;
+        /** icache_reset : R/W; bitpos: [1]; default: 0;
+         *  Need add description
+         */
+        uint32_t icache_reset:1;
+        /** dcache_clk_on : R/W; bitpos: [2]; default: 1;
+         *  Need add description
+         */
+        uint32_t dcache_clk_on:1;
+        /** dcache_reset : R/W; bitpos: [3]; default: 0;
+         *  Need add description
+         */
+        uint32_t dcache_reset:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} system_cache_control_reg_t;
+
+/** Type of external_device_encrypt_decrypt_control register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** enable_spi_manual_encrypt : R/W; bitpos: [0]; default: 0;
+         *  Need add description
+         */
+        uint32_t enable_spi_manual_encrypt:1;
+        /** enable_download_db_encrypt : R/W; bitpos: [1]; default: 0;
+         *  Need add description
+         */
+        uint32_t enable_download_db_encrypt:1;
+        /** enable_download_g0cb_decrypt : R/W; bitpos: [2]; default: 0;
+         *  Need add description
+         */
+        uint32_t enable_download_g0cb_decrypt:1;
+        /** enable_download_manual_encrypt : R/W; bitpos: [3]; default: 0;
+         *  Need add description
+         */
+        uint32_t enable_download_manual_encrypt:1;
+        uint32_t reserved_4:28;
+    };
+    uint32_t val;
+} system_external_device_encrypt_decrypt_control_reg_t;
+
+/** Type of rtc_fastmem_config register
+ *  register description
+ */
+typedef union {
+    struct {
+        uint32_t reserved_0:8;
+        /** rtc_mem_crc_start : R/W; bitpos: [8]; default: 0;
+         *  Need add description
+         */
+        uint32_t rtc_mem_crc_start:1;
+        /** rtc_mem_crc_addr : R/W; bitpos: [19:9]; default: 0;
+         *  Need add description
+         */
+        uint32_t rtc_mem_crc_addr:11;
+        /** rtc_mem_crc_len : R/W; bitpos: [30:20]; default: 2047;
+         *  Need add description
+         */
+        uint32_t rtc_mem_crc_len:11;
+        /** rtc_mem_crc_finish : RO; bitpos: [31]; default: 0;
+         *  Need add description
+         */
+        uint32_t rtc_mem_crc_finish:1;
+    };
+    uint32_t val;
+} system_rtc_fastmem_config_reg_t;
+
+/** Type of rtc_fastmem_crc register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** rtc_mem_crc_res : RO; bitpos: [31:0]; default: 0;
+         *  Need add description
+         */
+        uint32_t rtc_mem_crc_res:32;
+    };
+    uint32_t val;
+} system_rtc_fastmem_crc_reg_t;
+
+/** Type of redundant_eco_ctrl register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** redundant_eco_drive : R/W; bitpos: [0]; default: 0;
+         *  Need add description
+         */
+        uint32_t redundant_eco_drive:1;
+        /** redundant_eco_result : RO; bitpos: [1]; default: 0;
+         *  Need add description
+         */
+        uint32_t redundant_eco_result:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} system_redundant_eco_ctrl_reg_t;
+
+/** Type of clock_gate register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 1;
+         *  Need add description
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} system_clock_gate_reg_t;
+
+/** Type of mem_pvt register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** mem_path_len : R/W; bitpos: [3:0]; default: 3;
+         *  Need add description
+         */
+        uint32_t mem_path_len:4;
+        /** mem_err_cnt_clr : WO; bitpos: [4]; default: 0;
+         *  Need add description
+         */
+        uint32_t mem_err_cnt_clr:1;
+        /** mem_pvt_monitor_en : R/W; bitpos: [5]; default: 0;
+         *  Need add description
+         */
+        uint32_t mem_pvt_monitor_en:1;
+        /** mem_timing_err_cnt : RO; bitpos: [21:6]; default: 0;
+         *  Need add description
+         */
+        uint32_t mem_timing_err_cnt:16;
+        /** mem_vt_sel : R/W; bitpos: [23:22]; default: 0;
+         *  Need add description
+         */
+        uint32_t mem_vt_sel:2;
+        uint32_t reserved_24:8;
+    };
+    uint32_t val;
+} system_mem_pvt_reg_t;
+
+/** Type of system_reg_date register
+ *  register description
+ */
+typedef union {
+    struct {
+        /** system_reg_date : R/W; bitpos: [27:0]; default: 34615872;
+         *  Need add description
+         */
+        uint32_t system_reg_date:28;
+        uint32_t reserved_28:4;
+    };
+    uint32_t val;
+} system_system_reg_date_reg_t;
+
+
+typedef struct {
+    volatile system_cpu_peri_clk_en_reg_t cpu_peri_clk_en;
+    volatile system_cpu_peri_rst_en_reg_t cpu_peri_rst_en;
+    volatile system_cpu_per_conf_reg_t cpu_per_conf;
+    volatile system_mem_pd_mask_reg_t mem_pd_mask;
+    volatile system_cpu_intr_from_cpu_0_reg_t cpu_intr_from_cpu_0;
+    volatile system_cpu_intr_from_cpu_1_reg_t cpu_intr_from_cpu_1;
+    volatile system_cpu_intr_from_cpu_2_reg_t cpu_intr_from_cpu_2;
+    volatile system_cpu_intr_from_cpu_3_reg_t cpu_intr_from_cpu_3;
+    volatile system_rsa_pd_ctrl_reg_t rsa_pd_ctrl;
+    volatile system_edma_ctrl_reg_t edma_ctrl;
+    volatile system_cache_control_reg_t cache_control;
+    volatile system_external_device_encrypt_decrypt_control_reg_t external_device_encrypt_decrypt_control;
+    volatile system_rtc_fastmem_config_reg_t rtc_fastmem_config;
+    volatile system_rtc_fastmem_crc_reg_t rtc_fastmem_crc;
+    volatile system_redundant_eco_ctrl_reg_t redundant_eco_ctrl;
+    volatile system_clock_gate_reg_t clock_gate;
+    volatile system_mem_pvt_reg_t mem_pvt;
+    uint32_t reserved_044[1006];
+    volatile system_system_reg_date_reg_t system_reg_date;
+} system_dev_t;
+
+extern system_dev_t SYSTEM;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(system_dev_t) == 0x1000, "Invalid size of system_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32h2/include/rev2/soc/usb_serial_jtag_reg.h

@@ -0,0 +1,899 @@
+/**
+ * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include "soc/soc.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** USB_SERIAL_JTAG_EP1_REG register
+ *  FIFO access for the CDC-ACM data IN and OUT endpoints.
+ */
+#define USB_SERIAL_JTAG_EP1_REG (DR_REG_USB_DEVICE_BASE + 0x0)
+/** USB_SERIAL_JTAG_RDWR_BYTE : R/W; bitpos: [7:0]; default: 0;
+ *  Write and read byte data to/from UART Tx/Rx FIFO through this field. When
+ *  USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64
+ *  bytes) into UART Tx FIFO. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is set, user
+ *  can check USB_SERIAL_JTAG_OUT_EP1_WR_ADDR USB_SERIAL_JTAG_OUT_EP0_RD_ADDR to know
+ *  how many data is received, then read data from UART Rx FIFO.
+ */
+#define USB_SERIAL_JTAG_RDWR_BYTE    0x000000FFU
+#define USB_SERIAL_JTAG_RDWR_BYTE_M  (USB_SERIAL_JTAG_RDWR_BYTE_V << USB_SERIAL_JTAG_RDWR_BYTE_S)
+#define USB_SERIAL_JTAG_RDWR_BYTE_V  0x000000FFU
+#define USB_SERIAL_JTAG_RDWR_BYTE_S  0
+
+/** USB_SERIAL_JTAG_EP1_CONF_REG register
+ *  Configuration and control registers for the CDC-ACM FIFOs.
+ */
+#define USB_SERIAL_JTAG_EP1_CONF_REG (DR_REG_USB_DEVICE_BASE + 0x4)
+/** USB_SERIAL_JTAG_WR_DONE : WT; bitpos: [0]; default: 0;
+ *  Set this bit to indicate writing byte data to UART Tx FIFO is done.
+ */
+#define USB_SERIAL_JTAG_WR_DONE    (BIT(0))
+#define USB_SERIAL_JTAG_WR_DONE_M  (USB_SERIAL_JTAG_WR_DONE_V << USB_SERIAL_JTAG_WR_DONE_S)
+#define USB_SERIAL_JTAG_WR_DONE_V  0x00000001U
+#define USB_SERIAL_JTAG_WR_DONE_S  0
+/** USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE : RO; bitpos: [1]; default: 1;
+ *  1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing
+ *  USB_SERIAL_JTAG_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by
+ *  USB Host.
+ */
+#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE    (BIT(1))
+#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_M  (USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V << USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S)
+#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S  1
+/** USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL : RO; bitpos: [2]; default: 0;
+ *  1'b1: Indicate there is data in UART Rx FIFO.
+ */
+#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL    (BIT(2))
+#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_M  (USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V << USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S)
+#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S  2
+
+/** USB_SERIAL_JTAG_INT_RAW_REG register
+ *  Interrupt raw status register.
+ */
+#define USB_SERIAL_JTAG_INT_RAW_REG (DR_REG_USB_DEVICE_BASE + 0x8)
+/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ *  The raw interrupt bit turns to high level when flush cmd is received for IN
+ *  endpoint 2 of JTAG.
+ */
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW    (BIT(0))
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_M  (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S)
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S  0
+/** USB_SERIAL_JTAG_SOF_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ *  The raw interrupt bit turns to high level when SOF frame is received.
+ */
+#define USB_SERIAL_JTAG_SOF_INT_RAW    (BIT(1))
+#define USB_SERIAL_JTAG_SOF_INT_RAW_M  (USB_SERIAL_JTAG_SOF_INT_RAW_V << USB_SERIAL_JTAG_SOF_INT_RAW_S)
+#define USB_SERIAL_JTAG_SOF_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_SOF_INT_RAW_S  1
+/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
+ *  The raw interrupt bit turns to high level when Serial Port OUT Endpoint received
+ *  one packet.
+ */
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW    (BIT(2))
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_M  (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S)
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S  2
+/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW : R/WTC/SS; bitpos: [3]; default: 1;
+ *  The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty.
+ */
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW    (BIT(3))
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_M  (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S)
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S  3
+/** USB_SERIAL_JTAG_PID_ERR_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ *  The raw interrupt bit turns to high level when pid error is detected.
+ */
+#define USB_SERIAL_JTAG_PID_ERR_INT_RAW    (BIT(4))
+#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_M  (USB_SERIAL_JTAG_PID_ERR_INT_RAW_V << USB_SERIAL_JTAG_PID_ERR_INT_RAW_S)
+#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_S  4
+/** USB_SERIAL_JTAG_CRC5_ERR_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ *  The raw interrupt bit turns to high level when CRC5 error is detected.
+ */
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW    (BIT(5))
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_M  (USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_V << USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_S)
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_S  5
+/** USB_SERIAL_JTAG_CRC16_ERR_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ *  The raw interrupt bit turns to high level when CRC16 error is detected.
+ */
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW    (BIT(6))
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_M  (USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_V << USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_S)
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_S  6
+/** USB_SERIAL_JTAG_STUFF_ERR_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ *  The raw interrupt bit turns to high level when stuff error is detected.
+ */
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW    (BIT(7))
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_M  (USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_V << USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_S)
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_S  7
+/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
+ *  The raw interrupt bit turns to high level when IN token for IN endpoint 1 is
+ *  received.
+ */
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW    (BIT(8))
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_M  (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S)
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S  8
+/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ *  The raw interrupt bit turns to high level when usb bus reset is detected.
+ */
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW    (BIT(9))
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_M  (USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S)
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S  9
+/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
+ *  The raw interrupt bit turns to high level when OUT endpoint 1 received packet with
+ *  zero palyload.
+ */
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW    (BIT(10))
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_M  (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S)
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S  10
+/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
+ *  The raw interrupt bit turns to high level when OUT endpoint 2 received packet with
+ *  zero palyload.
+ */
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW    (BIT(11))
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_M  (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S)
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S  11
+
+/** USB_SERIAL_JTAG_INT_ST_REG register
+ *  Interrupt status register.
+ */
+#define USB_SERIAL_JTAG_INT_ST_REG (DR_REG_USB_DEVICE_BASE + 0xc)
+/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST : RO; bitpos: [0]; default: 0;
+ *  The raw interrupt status bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST    (BIT(0))
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_M  (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S)
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S  0
+/** USB_SERIAL_JTAG_SOF_INT_ST : RO; bitpos: [1]; default: 0;
+ *  The raw interrupt status bit for the USB_SERIAL_JTAG_SOF_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SOF_INT_ST    (BIT(1))
+#define USB_SERIAL_JTAG_SOF_INT_ST_M  (USB_SERIAL_JTAG_SOF_INT_ST_V << USB_SERIAL_JTAG_SOF_INT_ST_S)
+#define USB_SERIAL_JTAG_SOF_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_SOF_INT_ST_S  1
+/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST : RO; bitpos: [2]; default: 0;
+ *  The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
+ *  interrupt.
+ */
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST    (BIT(2))
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_M  (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S)
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S  2
+/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST : RO; bitpos: [3]; default: 0;
+ *  The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST    (BIT(3))
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_M  (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S)
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S  3
+/** USB_SERIAL_JTAG_PID_ERR_INT_ST : RO; bitpos: [4]; default: 0;
+ *  The raw interrupt status bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_PID_ERR_INT_ST    (BIT(4))
+#define USB_SERIAL_JTAG_PID_ERR_INT_ST_M  (USB_SERIAL_JTAG_PID_ERR_INT_ST_V << USB_SERIAL_JTAG_PID_ERR_INT_ST_S)
+#define USB_SERIAL_JTAG_PID_ERR_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_PID_ERR_INT_ST_S  4
+/** USB_SERIAL_JTAG_CRC5_ERR_INT_ST : RO; bitpos: [5]; default: 0;
+ *  The raw interrupt status bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST    (BIT(5))
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_M  (USB_SERIAL_JTAG_CRC5_ERR_INT_ST_V << USB_SERIAL_JTAG_CRC5_ERR_INT_ST_S)
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_S  5
+/** USB_SERIAL_JTAG_CRC16_ERR_INT_ST : RO; bitpos: [6]; default: 0;
+ *  The raw interrupt status bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST    (BIT(6))
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_M  (USB_SERIAL_JTAG_CRC16_ERR_INT_ST_V << USB_SERIAL_JTAG_CRC16_ERR_INT_ST_S)
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_S  6
+/** USB_SERIAL_JTAG_STUFF_ERR_INT_ST : RO; bitpos: [7]; default: 0;
+ *  The raw interrupt status bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST    (BIT(7))
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_M  (USB_SERIAL_JTAG_STUFF_ERR_INT_ST_V << USB_SERIAL_JTAG_STUFF_ERR_INT_ST_S)
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_S  7
+/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST : RO; bitpos: [8]; default: 0;
+ *  The raw interrupt status bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT
+ *  interrupt.
+ */
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST    (BIT(8))
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_M  (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S)
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S  8
+/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST : RO; bitpos: [9]; default: 0;
+ *  The raw interrupt status bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST    (BIT(9))
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_M  (USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S)
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S  9
+/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST : RO; bitpos: [10]; default: 0;
+ *  The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT
+ *  interrupt.
+ */
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST    (BIT(10))
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_M  (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S)
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S  10
+/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST : RO; bitpos: [11]; default: 0;
+ *  The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT
+ *  interrupt.
+ */
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST    (BIT(11))
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_M  (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S)
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S  11
+
+/** USB_SERIAL_JTAG_INT_ENA_REG register
+ *  Interrupt enable status register.
+ */
+#define USB_SERIAL_JTAG_INT_ENA_REG (DR_REG_USB_DEVICE_BASE + 0x10)
+/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA : R/W; bitpos: [0]; default: 0;
+ *  The interrupt enable bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA    (BIT(0))
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_M  (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S)
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S  0
+/** USB_SERIAL_JTAG_SOF_INT_ENA : R/W; bitpos: [1]; default: 0;
+ *  The interrupt enable bit for the USB_SERIAL_JTAG_SOF_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SOF_INT_ENA    (BIT(1))
+#define USB_SERIAL_JTAG_SOF_INT_ENA_M  (USB_SERIAL_JTAG_SOF_INT_ENA_V << USB_SERIAL_JTAG_SOF_INT_ENA_S)
+#define USB_SERIAL_JTAG_SOF_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_SOF_INT_ENA_S  1
+/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA : R/W; bitpos: [2]; default: 0;
+ *  The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA    (BIT(2))
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_M  (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S)
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S  2
+/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA : R/W; bitpos: [3]; default: 0;
+ *  The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA    (BIT(3))
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_M  (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S)
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S  3
+/** USB_SERIAL_JTAG_PID_ERR_INT_ENA : R/W; bitpos: [4]; default: 0;
+ *  The interrupt enable bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_PID_ERR_INT_ENA    (BIT(4))
+#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_M  (USB_SERIAL_JTAG_PID_ERR_INT_ENA_V << USB_SERIAL_JTAG_PID_ERR_INT_ENA_S)
+#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_S  4
+/** USB_SERIAL_JTAG_CRC5_ERR_INT_ENA : R/W; bitpos: [5]; default: 0;
+ *  The interrupt enable bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA    (BIT(5))
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_M  (USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_V << USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_S)
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_S  5
+/** USB_SERIAL_JTAG_CRC16_ERR_INT_ENA : R/W; bitpos: [6]; default: 0;
+ *  The interrupt enable bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA    (BIT(6))
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_M  (USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_V << USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_S)
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_S  6
+/** USB_SERIAL_JTAG_STUFF_ERR_INT_ENA : R/W; bitpos: [7]; default: 0;
+ *  The interrupt enable bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA    (BIT(7))
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_M  (USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_V << USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_S)
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_S  7
+/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA : R/W; bitpos: [8]; default: 0;
+ *  The interrupt enable bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA    (BIT(8))
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_M  (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S)
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S  8
+/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA : R/W; bitpos: [9]; default: 0;
+ *  The interrupt enable bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA    (BIT(9))
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_M  (USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S)
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S  9
+/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA : R/W; bitpos: [10]; default: 0;
+ *  The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA    (BIT(10))
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_M  (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S)
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S  10
+/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA : R/W; bitpos: [11]; default: 0;
+ *  The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA    (BIT(11))
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_M  (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S)
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S  11
+
+/** USB_SERIAL_JTAG_INT_CLR_REG register
+ *  Interrupt clear status register.
+ */
+#define USB_SERIAL_JTAG_INT_CLR_REG (DR_REG_USB_DEVICE_BASE + 0x14)
+/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR : WT; bitpos: [0]; default: 0;
+ *  Set this bit to clear the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR    (BIT(0))
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_M  (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S)
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S  0
+/** USB_SERIAL_JTAG_SOF_INT_CLR : WT; bitpos: [1]; default: 0;
+ *  Set this bit to clear the USB_SERIAL_JTAG_JTAG_SOF_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SOF_INT_CLR    (BIT(1))
+#define USB_SERIAL_JTAG_SOF_INT_CLR_M  (USB_SERIAL_JTAG_SOF_INT_CLR_V << USB_SERIAL_JTAG_SOF_INT_CLR_S)
+#define USB_SERIAL_JTAG_SOF_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_SOF_INT_CLR_S  1
+/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR : WT; bitpos: [2]; default: 0;
+ *  Set this bit to clear the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR    (BIT(2))
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_M  (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S)
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S  2
+/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR : WT; bitpos: [3]; default: 0;
+ *  Set this bit to clear the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR    (BIT(3))
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_M  (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S)
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S  3
+/** USB_SERIAL_JTAG_PID_ERR_INT_CLR : WT; bitpos: [4]; default: 0;
+ *  Set this bit to clear the USB_SERIAL_JTAG_PID_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_PID_ERR_INT_CLR    (BIT(4))
+#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_M  (USB_SERIAL_JTAG_PID_ERR_INT_CLR_V << USB_SERIAL_JTAG_PID_ERR_INT_CLR_S)
+#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_S  4
+/** USB_SERIAL_JTAG_CRC5_ERR_INT_CLR : WT; bitpos: [5]; default: 0;
+ *  Set this bit to clear the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR    (BIT(5))
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_M  (USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_V << USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_S)
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_S  5
+/** USB_SERIAL_JTAG_CRC16_ERR_INT_CLR : WT; bitpos: [6]; default: 0;
+ *  Set this bit to clear the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR    (BIT(6))
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_M  (USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_V << USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_S)
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_S  6
+/** USB_SERIAL_JTAG_STUFF_ERR_INT_CLR : WT; bitpos: [7]; default: 0;
+ *  Set this bit to clear the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR    (BIT(7))
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_M  (USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_V << USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_S)
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_S  7
+/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR : WT; bitpos: [8]; default: 0;
+ *  Set this bit to clear the USB_SERIAL_JTAG_IN_TOKEN_IN_EP1_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR    (BIT(8))
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_M  (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S)
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S  8
+/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR : WT; bitpos: [9]; default: 0;
+ *  Set this bit to clear the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR    (BIT(9))
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_M  (USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S)
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S  9
+/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR : WT; bitpos: [10]; default: 0;
+ *  Set this bit to clear the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR    (BIT(10))
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_M  (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S)
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S  10
+/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR : WT; bitpos: [11]; default: 0;
+ *  Set this bit to clear the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
+ */
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR    (BIT(11))
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_M  (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S)
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S  11
+
+/** USB_SERIAL_JTAG_CONF0_REG register
+ *  PHY hardware configuration.
+ */
+#define USB_SERIAL_JTAG_CONF0_REG (DR_REG_USB_DEVICE_BASE + 0x18)
+/** USB_SERIAL_JTAG_PHY_SEL : R/W; bitpos: [0]; default: 0;
+ *  Select internal/external PHY
+ */
+#define USB_SERIAL_JTAG_PHY_SEL    (BIT(0))
+#define USB_SERIAL_JTAG_PHY_SEL_M  (USB_SERIAL_JTAG_PHY_SEL_V << USB_SERIAL_JTAG_PHY_SEL_S)
+#define USB_SERIAL_JTAG_PHY_SEL_V  0x00000001U
+#define USB_SERIAL_JTAG_PHY_SEL_S  0
+/** USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE : R/W; bitpos: [1]; default: 0;
+ *  Enable software control USB D+ D- exchange
+ */
+#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE    (BIT(1))
+#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_M  (USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V << USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S)
+#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V  0x00000001U
+#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S  1
+/** USB_SERIAL_JTAG_EXCHG_PINS : R/W; bitpos: [2]; default: 0;
+ *  USB D+ D- exchange
+ */
+#define USB_SERIAL_JTAG_EXCHG_PINS    (BIT(2))
+#define USB_SERIAL_JTAG_EXCHG_PINS_M  (USB_SERIAL_JTAG_EXCHG_PINS_V << USB_SERIAL_JTAG_EXCHG_PINS_S)
+#define USB_SERIAL_JTAG_EXCHG_PINS_V  0x00000001U
+#define USB_SERIAL_JTAG_EXCHG_PINS_S  2
+/** USB_SERIAL_JTAG_VREFH : R/W; bitpos: [4:3]; default: 0;
+ *  Control single-end input high threshold,1.76V to 2V, step 80mV
+ */
+#define USB_SERIAL_JTAG_VREFH    0x00000003U
+#define USB_SERIAL_JTAG_VREFH_M  (USB_SERIAL_JTAG_VREFH_V << USB_SERIAL_JTAG_VREFH_S)
+#define USB_SERIAL_JTAG_VREFH_V  0x00000003U
+#define USB_SERIAL_JTAG_VREFH_S  3
+/** USB_SERIAL_JTAG_VREFL : R/W; bitpos: [6:5]; default: 0;
+ *  Control single-end input low threshold,0.8V to 1.04V, step 80mV
+ */
+#define USB_SERIAL_JTAG_VREFL    0x00000003U
+#define USB_SERIAL_JTAG_VREFL_M  (USB_SERIAL_JTAG_VREFL_V << USB_SERIAL_JTAG_VREFL_S)
+#define USB_SERIAL_JTAG_VREFL_V  0x00000003U
+#define USB_SERIAL_JTAG_VREFL_S  5
+/** USB_SERIAL_JTAG_VREF_OVERRIDE : R/W; bitpos: [7]; default: 0;
+ *  Enable software control input  threshold
+ */
+#define USB_SERIAL_JTAG_VREF_OVERRIDE    (BIT(7))
+#define USB_SERIAL_JTAG_VREF_OVERRIDE_M  (USB_SERIAL_JTAG_VREF_OVERRIDE_V << USB_SERIAL_JTAG_VREF_OVERRIDE_S)
+#define USB_SERIAL_JTAG_VREF_OVERRIDE_V  0x00000001U
+#define USB_SERIAL_JTAG_VREF_OVERRIDE_S  7
+/** USB_SERIAL_JTAG_PAD_PULL_OVERRIDE : R/W; bitpos: [8]; default: 0;
+ *  Enable software control USB D+ D- pullup pulldown
+ */
+#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE    (BIT(8))
+#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_M  (USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_V << USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_S)
+#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_V  0x00000001U
+#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_S  8
+/** USB_SERIAL_JTAG_DP_PULLUP : R/W; bitpos: [9]; default: 1;
+ *  Control USB D+ pull up.
+ */
+#define USB_SERIAL_JTAG_DP_PULLUP    (BIT(9))
+#define USB_SERIAL_JTAG_DP_PULLUP_M  (USB_SERIAL_JTAG_DP_PULLUP_V << USB_SERIAL_JTAG_DP_PULLUP_S)
+#define USB_SERIAL_JTAG_DP_PULLUP_V  0x00000001U
+#define USB_SERIAL_JTAG_DP_PULLUP_S  9
+/** USB_SERIAL_JTAG_DP_PULLDOWN : R/W; bitpos: [10]; default: 0;
+ *  Control USB D+ pull down.
+ */
+#define USB_SERIAL_JTAG_DP_PULLDOWN    (BIT(10))
+#define USB_SERIAL_JTAG_DP_PULLDOWN_M  (USB_SERIAL_JTAG_DP_PULLDOWN_V << USB_SERIAL_JTAG_DP_PULLDOWN_S)
+#define USB_SERIAL_JTAG_DP_PULLDOWN_V  0x00000001U
+#define USB_SERIAL_JTAG_DP_PULLDOWN_S  10
+/** USB_SERIAL_JTAG_DM_PULLUP : R/W; bitpos: [11]; default: 0;
+ *  Control USB D- pull up.
+ */
+#define USB_SERIAL_JTAG_DM_PULLUP    (BIT(11))
+#define USB_SERIAL_JTAG_DM_PULLUP_M  (USB_SERIAL_JTAG_DM_PULLUP_V << USB_SERIAL_JTAG_DM_PULLUP_S)
+#define USB_SERIAL_JTAG_DM_PULLUP_V  0x00000001U
+#define USB_SERIAL_JTAG_DM_PULLUP_S  11
+/** USB_SERIAL_JTAG_DM_PULLDOWN : R/W; bitpos: [12]; default: 0;
+ *  Control USB D- pull down.
+ */
+#define USB_SERIAL_JTAG_DM_PULLDOWN    (BIT(12))
+#define USB_SERIAL_JTAG_DM_PULLDOWN_M  (USB_SERIAL_JTAG_DM_PULLDOWN_V << USB_SERIAL_JTAG_DM_PULLDOWN_S)
+#define USB_SERIAL_JTAG_DM_PULLDOWN_V  0x00000001U
+#define USB_SERIAL_JTAG_DM_PULLDOWN_S  12
+/** USB_SERIAL_JTAG_PULLUP_VALUE : R/W; bitpos: [13]; default: 0;
+ *  Control pull up value.
+ */
+#define USB_SERIAL_JTAG_PULLUP_VALUE    (BIT(13))
+#define USB_SERIAL_JTAG_PULLUP_VALUE_M  (USB_SERIAL_JTAG_PULLUP_VALUE_V << USB_SERIAL_JTAG_PULLUP_VALUE_S)
+#define USB_SERIAL_JTAG_PULLUP_VALUE_V  0x00000001U
+#define USB_SERIAL_JTAG_PULLUP_VALUE_S  13
+/** USB_SERIAL_JTAG_USB_PAD_ENABLE : R/W; bitpos: [14]; default: 1;
+ *  Enable USB pad function.
+ */
+#define USB_SERIAL_JTAG_USB_PAD_ENABLE    (BIT(14))
+#define USB_SERIAL_JTAG_USB_PAD_ENABLE_M  (USB_SERIAL_JTAG_USB_PAD_ENABLE_V << USB_SERIAL_JTAG_USB_PAD_ENABLE_S)
+#define USB_SERIAL_JTAG_USB_PAD_ENABLE_V  0x00000001U
+#define USB_SERIAL_JTAG_USB_PAD_ENABLE_S  14
+/** USB_SERIAL_JTAG_PHY_TX_EDGE_SEL : R/W; bitpos: [15]; default: 0;
+ *  0: TX output at clock negedge. 1: Tx output at clock posedge.
+ */
+#define USB_SERIAL_JTAG_PHY_TX_EDGE_SEL    (BIT(15))
+#define USB_SERIAL_JTAG_PHY_TX_EDGE_SEL_M  (USB_SERIAL_JTAG_PHY_TX_EDGE_SEL_V << USB_SERIAL_JTAG_PHY_TX_EDGE_SEL_S)
+#define USB_SERIAL_JTAG_PHY_TX_EDGE_SEL_V  0x00000001U
+#define USB_SERIAL_JTAG_PHY_TX_EDGE_SEL_S  15
+/** USB_SERIAL_JTAG_PLL_DIV2_EN : R/W; bitpos: [16]; default: 1;
+ *  This bit is used to set divider coefficient of PLL. 0: PLL divider coefficient is
+ *  0. 1: PLL divider coefficient is 1.
+ */
+#define USB_SERIAL_JTAG_PLL_DIV2_EN    (BIT(16))
+#define USB_SERIAL_JTAG_PLL_DIV2_EN_M  (USB_SERIAL_JTAG_PLL_DIV2_EN_V << USB_SERIAL_JTAG_PLL_DIV2_EN_S)
+#define USB_SERIAL_JTAG_PLL_DIV2_EN_V  0x00000001U
+#define USB_SERIAL_JTAG_PLL_DIV2_EN_S  16
+
+/** USB_SERIAL_JTAG_TEST_REG register
+ *  Registers used for debugging the PHY.
+ */
+#define USB_SERIAL_JTAG_TEST_REG (DR_REG_USB_DEVICE_BASE + 0x1c)
+/** USB_SERIAL_JTAG_TEST_ENABLE : R/W; bitpos: [0]; default: 0;
+ *  Enable test of the USB pad
+ */
+#define USB_SERIAL_JTAG_TEST_ENABLE    (BIT(0))
+#define USB_SERIAL_JTAG_TEST_ENABLE_M  (USB_SERIAL_JTAG_TEST_ENABLE_V << USB_SERIAL_JTAG_TEST_ENABLE_S)
+#define USB_SERIAL_JTAG_TEST_ENABLE_V  0x00000001U
+#define USB_SERIAL_JTAG_TEST_ENABLE_S  0
+/** USB_SERIAL_JTAG_TEST_USB_OE : R/W; bitpos: [1]; default: 0;
+ *  USB pad oen in test
+ */
+#define USB_SERIAL_JTAG_TEST_USB_OE    (BIT(1))
+#define USB_SERIAL_JTAG_TEST_USB_OE_M  (USB_SERIAL_JTAG_TEST_USB_OE_V << USB_SERIAL_JTAG_TEST_USB_OE_S)
+#define USB_SERIAL_JTAG_TEST_USB_OE_V  0x00000001U
+#define USB_SERIAL_JTAG_TEST_USB_OE_S  1
+/** USB_SERIAL_JTAG_TEST_TX_DP : R/W; bitpos: [2]; default: 0;
+ *  USB D+ tx value in test
+ */
+#define USB_SERIAL_JTAG_TEST_TX_DP    (BIT(2))
+#define USB_SERIAL_JTAG_TEST_TX_DP_M  (USB_SERIAL_JTAG_TEST_TX_DP_V << USB_SERIAL_JTAG_TEST_TX_DP_S)
+#define USB_SERIAL_JTAG_TEST_TX_DP_V  0x00000001U
+#define USB_SERIAL_JTAG_TEST_TX_DP_S  2
+/** USB_SERIAL_JTAG_TEST_TX_DM : R/W; bitpos: [3]; default: 0;
+ *  USB D- tx value in test
+ */
+#define USB_SERIAL_JTAG_TEST_TX_DM    (BIT(3))
+#define USB_SERIAL_JTAG_TEST_TX_DM_M  (USB_SERIAL_JTAG_TEST_TX_DM_V << USB_SERIAL_JTAG_TEST_TX_DM_S)
+#define USB_SERIAL_JTAG_TEST_TX_DM_V  0x00000001U
+#define USB_SERIAL_JTAG_TEST_TX_DM_S  3
+/** USB_SERIAL_JTAG_TEST_RX_RCV : RO; bitpos: [4]; default: 0;
+ *  USB differential rx value in test
+ */
+#define USB_SERIAL_JTAG_TEST_RX_RCV    (BIT(4))
+#define USB_SERIAL_JTAG_TEST_RX_RCV_M  (USB_SERIAL_JTAG_TEST_RX_RCV_V << USB_SERIAL_JTAG_TEST_RX_RCV_S)
+#define USB_SERIAL_JTAG_TEST_RX_RCV_V  0x00000001U
+#define USB_SERIAL_JTAG_TEST_RX_RCV_S  4
+/** USB_SERIAL_JTAG_TEST_RX_DP : RO; bitpos: [5]; default: 0;
+ *  USB D+ rx value in test
+ */
+#define USB_SERIAL_JTAG_TEST_RX_DP    (BIT(5))
+#define USB_SERIAL_JTAG_TEST_RX_DP_M  (USB_SERIAL_JTAG_TEST_RX_DP_V << USB_SERIAL_JTAG_TEST_RX_DP_S)
+#define USB_SERIAL_JTAG_TEST_RX_DP_V  0x00000001U
+#define USB_SERIAL_JTAG_TEST_RX_DP_S  5
+/** USB_SERIAL_JTAG_TEST_RX_DM : RO; bitpos: [6]; default: 0;
+ *  USB D- rx value in test
+ */
+#define USB_SERIAL_JTAG_TEST_RX_DM    (BIT(6))
+#define USB_SERIAL_JTAG_TEST_RX_DM_M  (USB_SERIAL_JTAG_TEST_RX_DM_V << USB_SERIAL_JTAG_TEST_RX_DM_S)
+#define USB_SERIAL_JTAG_TEST_RX_DM_V  0x00000001U
+#define USB_SERIAL_JTAG_TEST_RX_DM_S  6
+
+/** USB_SERIAL_JTAG_JFIFO_ST_REG register
+ *  JTAG FIFO status and control registers.
+ */
+#define USB_SERIAL_JTAG_JFIFO_ST_REG (DR_REG_USB_DEVICE_BASE + 0x20)
+/** USB_SERIAL_JTAG_IN_FIFO_CNT : RO; bitpos: [1:0]; default: 0;
+ *  JTAT in fifo counter.
+ */
+#define USB_SERIAL_JTAG_IN_FIFO_CNT    0x00000003U
+#define USB_SERIAL_JTAG_IN_FIFO_CNT_M  (USB_SERIAL_JTAG_IN_FIFO_CNT_V << USB_SERIAL_JTAG_IN_FIFO_CNT_S)
+#define USB_SERIAL_JTAG_IN_FIFO_CNT_V  0x00000003U
+#define USB_SERIAL_JTAG_IN_FIFO_CNT_S  0
+/** USB_SERIAL_JTAG_IN_FIFO_EMPTY : RO; bitpos: [2]; default: 1;
+ *  1: JTAG in fifo is empty.
+ */
+#define USB_SERIAL_JTAG_IN_FIFO_EMPTY    (BIT(2))
+#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_M  (USB_SERIAL_JTAG_IN_FIFO_EMPTY_V << USB_SERIAL_JTAG_IN_FIFO_EMPTY_S)
+#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_V  0x00000001U
+#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_S  2
+/** USB_SERIAL_JTAG_IN_FIFO_FULL : RO; bitpos: [3]; default: 0;
+ *  1: JTAG in fifo is full.
+ */
+#define USB_SERIAL_JTAG_IN_FIFO_FULL    (BIT(3))
+#define USB_SERIAL_JTAG_IN_FIFO_FULL_M  (USB_SERIAL_JTAG_IN_FIFO_FULL_V << USB_SERIAL_JTAG_IN_FIFO_FULL_S)
+#define USB_SERIAL_JTAG_IN_FIFO_FULL_V  0x00000001U
+#define USB_SERIAL_JTAG_IN_FIFO_FULL_S  3
+/** USB_SERIAL_JTAG_OUT_FIFO_CNT : RO; bitpos: [5:4]; default: 0;
+ *  JTAT out fifo counter.
+ */
+#define USB_SERIAL_JTAG_OUT_FIFO_CNT    0x00000003U
+#define USB_SERIAL_JTAG_OUT_FIFO_CNT_M  (USB_SERIAL_JTAG_OUT_FIFO_CNT_V << USB_SERIAL_JTAG_OUT_FIFO_CNT_S)
+#define USB_SERIAL_JTAG_OUT_FIFO_CNT_V  0x00000003U
+#define USB_SERIAL_JTAG_OUT_FIFO_CNT_S  4
+/** USB_SERIAL_JTAG_OUT_FIFO_EMPTY : RO; bitpos: [6]; default: 1;
+ *  1: JTAG out fifo is empty.
+ */
+#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY    (BIT(6))
+#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_M  (USB_SERIAL_JTAG_OUT_FIFO_EMPTY_V << USB_SERIAL_JTAG_OUT_FIFO_EMPTY_S)
+#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_S  6
+/** USB_SERIAL_JTAG_OUT_FIFO_FULL : RO; bitpos: [7]; default: 0;
+ *  1: JTAG out fifo is full.
+ */
+#define USB_SERIAL_JTAG_OUT_FIFO_FULL    (BIT(7))
+#define USB_SERIAL_JTAG_OUT_FIFO_FULL_M  (USB_SERIAL_JTAG_OUT_FIFO_FULL_V << USB_SERIAL_JTAG_OUT_FIFO_FULL_S)
+#define USB_SERIAL_JTAG_OUT_FIFO_FULL_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_FIFO_FULL_S  7
+/** USB_SERIAL_JTAG_IN_FIFO_RESET : R/W; bitpos: [8]; default: 0;
+ *  Write 1 to reset JTAG in fifo.
+ */
+#define USB_SERIAL_JTAG_IN_FIFO_RESET    (BIT(8))
+#define USB_SERIAL_JTAG_IN_FIFO_RESET_M  (USB_SERIAL_JTAG_IN_FIFO_RESET_V << USB_SERIAL_JTAG_IN_FIFO_RESET_S)
+#define USB_SERIAL_JTAG_IN_FIFO_RESET_V  0x00000001U
+#define USB_SERIAL_JTAG_IN_FIFO_RESET_S  8
+/** USB_SERIAL_JTAG_OUT_FIFO_RESET : R/W; bitpos: [9]; default: 0;
+ *  Write 1 to reset JTAG out fifo.
+ */
+#define USB_SERIAL_JTAG_OUT_FIFO_RESET    (BIT(9))
+#define USB_SERIAL_JTAG_OUT_FIFO_RESET_M  (USB_SERIAL_JTAG_OUT_FIFO_RESET_V << USB_SERIAL_JTAG_OUT_FIFO_RESET_S)
+#define USB_SERIAL_JTAG_OUT_FIFO_RESET_V  0x00000001U
+#define USB_SERIAL_JTAG_OUT_FIFO_RESET_S  9
+
+/** USB_SERIAL_JTAG_FRAM_NUM_REG register
+ *  Last received SOF frame index register.
+ */
+#define USB_SERIAL_JTAG_FRAM_NUM_REG (DR_REG_USB_DEVICE_BASE + 0x24)
+/** USB_SERIAL_JTAG_SOF_FRAME_INDEX : RO; bitpos: [10:0]; default: 0;
+ *  Frame index of received SOF frame.
+ */
+#define USB_SERIAL_JTAG_SOF_FRAME_INDEX    0x000007FFU
+#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_M  (USB_SERIAL_JTAG_SOF_FRAME_INDEX_V << USB_SERIAL_JTAG_SOF_FRAME_INDEX_S)
+#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_V  0x000007FFU
+#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_S  0
+
+/** USB_SERIAL_JTAG_IN_EP0_ST_REG register
+ *  Control IN endpoint status information.
+ */
+#define USB_SERIAL_JTAG_IN_EP0_ST_REG (DR_REG_USB_DEVICE_BASE + 0x28)
+/** USB_SERIAL_JTAG_IN_EP0_STATE : RO; bitpos: [1:0]; default: 1;
+ *  State of IN Endpoint 0.
+ */
+#define USB_SERIAL_JTAG_IN_EP0_STATE    0x00000003U
+#define USB_SERIAL_JTAG_IN_EP0_STATE_M  (USB_SERIAL_JTAG_IN_EP0_STATE_V << USB_SERIAL_JTAG_IN_EP0_STATE_S)
+#define USB_SERIAL_JTAG_IN_EP0_STATE_V  0x00000003U
+#define USB_SERIAL_JTAG_IN_EP0_STATE_S  0
+/** USB_SERIAL_JTAG_IN_EP0_WR_ADDR : RO; bitpos: [8:2]; default: 0;
+ *  Write data address of IN endpoint 0.
+ */
+#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_M  (USB_SERIAL_JTAG_IN_EP0_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP0_WR_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_S  2
+/** USB_SERIAL_JTAG_IN_EP0_RD_ADDR : RO; bitpos: [15:9]; default: 0;
+ *  Read data address of IN endpoint 0.
+ */
+#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_M  (USB_SERIAL_JTAG_IN_EP0_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP0_RD_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_S  9
+
+/** USB_SERIAL_JTAG_IN_EP1_ST_REG register
+ *  CDC-ACM IN endpoint status information.
+ */
+#define USB_SERIAL_JTAG_IN_EP1_ST_REG (DR_REG_USB_DEVICE_BASE + 0x2c)
+/** USB_SERIAL_JTAG_IN_EP1_STATE : RO; bitpos: [1:0]; default: 1;
+ *  State of IN Endpoint 1.
+ */
+#define USB_SERIAL_JTAG_IN_EP1_STATE    0x00000003U
+#define USB_SERIAL_JTAG_IN_EP1_STATE_M  (USB_SERIAL_JTAG_IN_EP1_STATE_V << USB_SERIAL_JTAG_IN_EP1_STATE_S)
+#define USB_SERIAL_JTAG_IN_EP1_STATE_V  0x00000003U
+#define USB_SERIAL_JTAG_IN_EP1_STATE_S  0
+/** USB_SERIAL_JTAG_IN_EP1_WR_ADDR : RO; bitpos: [8:2]; default: 0;
+ *  Write data address of IN endpoint 1.
+ */
+#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_M  (USB_SERIAL_JTAG_IN_EP1_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP1_WR_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_S  2
+/** USB_SERIAL_JTAG_IN_EP1_RD_ADDR : RO; bitpos: [15:9]; default: 0;
+ *  Read data address of IN endpoint 1.
+ */
+#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_M  (USB_SERIAL_JTAG_IN_EP1_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP1_RD_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_S  9
+
+/** USB_SERIAL_JTAG_IN_EP2_ST_REG register
+ *  CDC-ACM interrupt IN endpoint status information.
+ */
+#define USB_SERIAL_JTAG_IN_EP2_ST_REG (DR_REG_USB_DEVICE_BASE + 0x30)
+/** USB_SERIAL_JTAG_IN_EP2_STATE : RO; bitpos: [1:0]; default: 1;
+ *  State of IN Endpoint 2.
+ */
+#define USB_SERIAL_JTAG_IN_EP2_STATE    0x00000003U
+#define USB_SERIAL_JTAG_IN_EP2_STATE_M  (USB_SERIAL_JTAG_IN_EP2_STATE_V << USB_SERIAL_JTAG_IN_EP2_STATE_S)
+#define USB_SERIAL_JTAG_IN_EP2_STATE_V  0x00000003U
+#define USB_SERIAL_JTAG_IN_EP2_STATE_S  0
+/** USB_SERIAL_JTAG_IN_EP2_WR_ADDR : RO; bitpos: [8:2]; default: 0;
+ *  Write data address of IN endpoint 2.
+ */
+#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_M  (USB_SERIAL_JTAG_IN_EP2_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP2_WR_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_S  2
+/** USB_SERIAL_JTAG_IN_EP2_RD_ADDR : RO; bitpos: [15:9]; default: 0;
+ *  Read data address of IN endpoint 2.
+ */
+#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_M  (USB_SERIAL_JTAG_IN_EP2_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP2_RD_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_S  9
+
+/** USB_SERIAL_JTAG_IN_EP3_ST_REG register
+ *  JTAG IN endpoint status information.
+ */
+#define USB_SERIAL_JTAG_IN_EP3_ST_REG (DR_REG_USB_DEVICE_BASE + 0x34)
+/** USB_SERIAL_JTAG_IN_EP3_STATE : RO; bitpos: [1:0]; default: 1;
+ *  State of IN Endpoint 3.
+ */
+#define USB_SERIAL_JTAG_IN_EP3_STATE    0x00000003U
+#define USB_SERIAL_JTAG_IN_EP3_STATE_M  (USB_SERIAL_JTAG_IN_EP3_STATE_V << USB_SERIAL_JTAG_IN_EP3_STATE_S)
+#define USB_SERIAL_JTAG_IN_EP3_STATE_V  0x00000003U
+#define USB_SERIAL_JTAG_IN_EP3_STATE_S  0
+/** USB_SERIAL_JTAG_IN_EP3_WR_ADDR : RO; bitpos: [8:2]; default: 0;
+ *  Write data address of IN endpoint 3.
+ */
+#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_M  (USB_SERIAL_JTAG_IN_EP3_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP3_WR_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_S  2
+/** USB_SERIAL_JTAG_IN_EP3_RD_ADDR : RO; bitpos: [15:9]; default: 0;
+ *  Read data address of IN endpoint 3.
+ */
+#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_M  (USB_SERIAL_JTAG_IN_EP3_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP3_RD_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_S  9
+
+/** USB_SERIAL_JTAG_OUT_EP0_ST_REG register
+ *  Control OUT endpoint status information.
+ */
+#define USB_SERIAL_JTAG_OUT_EP0_ST_REG (DR_REG_USB_DEVICE_BASE + 0x38)
+/** USB_SERIAL_JTAG_OUT_EP0_STATE : RO; bitpos: [1:0]; default: 0;
+ *  State of OUT Endpoint 0.
+ */
+#define USB_SERIAL_JTAG_OUT_EP0_STATE    0x00000003U
+#define USB_SERIAL_JTAG_OUT_EP0_STATE_M  (USB_SERIAL_JTAG_OUT_EP0_STATE_V << USB_SERIAL_JTAG_OUT_EP0_STATE_S)
+#define USB_SERIAL_JTAG_OUT_EP0_STATE_V  0x00000003U
+#define USB_SERIAL_JTAG_OUT_EP0_STATE_S  0
+/** USB_SERIAL_JTAG_OUT_EP0_WR_ADDR : RO; bitpos: [8:2]; default: 0;
+ *  Write data address of OUT endpoint 0. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
+ *  is detected, there are USB_SERIAL_JTAG_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0.
+ */
+#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_M  (USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_S)
+#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_S  2
+/** USB_SERIAL_JTAG_OUT_EP0_RD_ADDR : RO; bitpos: [15:9]; default: 0;
+ *  Read data address of OUT endpoint 0.
+ */
+#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_M  (USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_S)
+#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_S  9
+
+/** USB_SERIAL_JTAG_OUT_EP1_ST_REG register
+ *  CDC-ACM OUT endpoint status information.
+ */
+#define USB_SERIAL_JTAG_OUT_EP1_ST_REG (DR_REG_USB_DEVICE_BASE + 0x3c)
+/** USB_SERIAL_JTAG_OUT_EP1_STATE : RO; bitpos: [1:0]; default: 0;
+ *  State of OUT Endpoint 1.
+ */
+#define USB_SERIAL_JTAG_OUT_EP1_STATE    0x00000003U
+#define USB_SERIAL_JTAG_OUT_EP1_STATE_M  (USB_SERIAL_JTAG_OUT_EP1_STATE_V << USB_SERIAL_JTAG_OUT_EP1_STATE_S)
+#define USB_SERIAL_JTAG_OUT_EP1_STATE_V  0x00000003U
+#define USB_SERIAL_JTAG_OUT_EP1_STATE_S  0
+/** USB_SERIAL_JTAG_OUT_EP1_WR_ADDR : RO; bitpos: [8:2]; default: 0;
+ *  Write data address of OUT endpoint 1. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
+ *  is detected, there are USB_SERIAL_JTAG_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1.
+ */
+#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_M  (USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_S)
+#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_S  2
+/** USB_SERIAL_JTAG_OUT_EP1_RD_ADDR : RO; bitpos: [15:9]; default: 0;
+ *  Read data address of OUT endpoint 1.
+ */
+#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_M  (USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_S)
+#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_S  9
+/** USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT : RO; bitpos: [22:16]; default: 0;
+ *  Data count in OUT endpoint 1 when one packet is received.
+ */
+#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT    0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_M  (USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V << USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S)
+#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V  0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S  16
+
+/** USB_SERIAL_JTAG_OUT_EP2_ST_REG register
+ *  JTAG OUT endpoint status information.
+ */
+#define USB_SERIAL_JTAG_OUT_EP2_ST_REG (DR_REG_USB_DEVICE_BASE + 0x40)
+/** USB_SERIAL_JTAG_OUT_EP2_STATE : RO; bitpos: [1:0]; default: 0;
+ *  State of OUT Endpoint 2.
+ */
+#define USB_SERIAL_JTAG_OUT_EP2_STATE    0x00000003U
+#define USB_SERIAL_JTAG_OUT_EP2_STATE_M  (USB_SERIAL_JTAG_OUT_EP2_STATE_V << USB_SERIAL_JTAG_OUT_EP2_STATE_S)
+#define USB_SERIAL_JTAG_OUT_EP2_STATE_V  0x00000003U
+#define USB_SERIAL_JTAG_OUT_EP2_STATE_S  0
+/** USB_SERIAL_JTAG_OUT_EP2_WR_ADDR : RO; bitpos: [8:2]; default: 0;
+ *  Write data address of OUT endpoint 2. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
+ *  is detected, there are USB_SERIAL_JTAG_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2.
+ */
+#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_M  (USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_S)
+#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_S  2
+/** USB_SERIAL_JTAG_OUT_EP2_RD_ADDR : RO; bitpos: [15:9]; default: 0;
+ *  Read data address of OUT endpoint 2.
+ */
+#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR    0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_M  (USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_S)
+#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_V  0x0000007FU
+#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_S  9
+
+/** USB_SERIAL_JTAG_MISC_CONF_REG register
+ *  Clock enable control
+ */
+#define USB_SERIAL_JTAG_MISC_CONF_REG (DR_REG_USB_DEVICE_BASE + 0x44)
+/** USB_SERIAL_JTAG_CLK_EN : R/W; bitpos: [0]; default: 0;
+ *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
+ *  registers.
+ */
+#define USB_SERIAL_JTAG_CLK_EN    (BIT(0))
+#define USB_SERIAL_JTAG_CLK_EN_M  (USB_SERIAL_JTAG_CLK_EN_V << USB_SERIAL_JTAG_CLK_EN_S)
+#define USB_SERIAL_JTAG_CLK_EN_V  0x00000001U
+#define USB_SERIAL_JTAG_CLK_EN_S  0
+
+/** USB_SERIAL_JTAG_MEM_CONF_REG register
+ *  Memory power control
+ */
+#define USB_SERIAL_JTAG_MEM_CONF_REG (DR_REG_USB_DEVICE_BASE + 0x48)
+/** USB_SERIAL_JTAG_USB_MEM_PD : R/W; bitpos: [0]; default: 0;
+ *  1: power down usb memory.
+ */
+#define USB_SERIAL_JTAG_USB_MEM_PD    (BIT(0))
+#define USB_SERIAL_JTAG_USB_MEM_PD_M  (USB_SERIAL_JTAG_USB_MEM_PD_V << USB_SERIAL_JTAG_USB_MEM_PD_S)
+#define USB_SERIAL_JTAG_USB_MEM_PD_V  0x00000001U
+#define USB_SERIAL_JTAG_USB_MEM_PD_S  0
+/** USB_SERIAL_JTAG_USB_MEM_CLK_EN : R/W; bitpos: [1]; default: 1;
+ *  1: Force clock on for usb memory.
+ */
+#define USB_SERIAL_JTAG_USB_MEM_CLK_EN    (BIT(1))
+#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_M  (USB_SERIAL_JTAG_USB_MEM_CLK_EN_V << USB_SERIAL_JTAG_USB_MEM_CLK_EN_S)
+#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_V  0x00000001U
+#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_S  1
+
+/** USB_SERIAL_JTAG_DATE_REG register
+ *  Date register
+ */
+#define USB_SERIAL_JTAG_DATE_REG (DR_REG_USB_DEVICE_BASE + 0x80)
+/** USB_SERIAL_JTAG_DATE : R/W; bitpos: [31:0]; default: 34607505;
+ *  register version.
+ */
+#define USB_SERIAL_JTAG_DATE    0xFFFFFFFFU
+#define USB_SERIAL_JTAG_DATE_M  (USB_SERIAL_JTAG_DATE_V << USB_SERIAL_JTAG_DATE_S)
+#define USB_SERIAL_JTAG_DATE_V  0xFFFFFFFFU
+#define USB_SERIAL_JTAG_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32h2/include/rev2/soc/usb_serial_jtag_struct.h

@@ -0,0 +1,708 @@
+/**
+ * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Group: Configuration Registers */
+/** Type of ep1 register
+ *  FIFO access for the CDC-ACM data IN and OUT endpoints.
+ */
+typedef union {
+    struct {
+        /** rdwr_byte : R/W; bitpos: [7:0]; default: 0;
+         *  Write and read byte data to/from UART Tx/Rx FIFO through this field. When
+         *  USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64
+         *  bytes) into UART Tx FIFO. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is set, user
+         *  can check USB_SERIAL_JTAG_OUT_EP1_WR_ADDR USB_SERIAL_JTAG_OUT_EP0_RD_ADDR to know
+         *  how many data is received, then read data from UART Rx FIFO.
+         */
+        uint32_t rdwr_byte:8;
+        uint32_t reserved_8:24;
+    };
+    uint32_t val;
+} usb_serial_jtag_ep1_reg_t;
+
+/** Type of ep1_conf register
+ *  Configuration and control registers for the CDC-ACM FIFOs.
+ */
+typedef union {
+    struct {
+        /** wr_done : WT; bitpos: [0]; default: 0;
+         *  Set this bit to indicate writing byte data to UART Tx FIFO is done.
+         */
+        uint32_t wr_done:1;
+        /** serial_in_ep_data_free : RO; bitpos: [1]; default: 1;
+         *  1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing
+         *  USB_SERIAL_JTAG_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by
+         *  USB Host.
+         */
+        uint32_t serial_in_ep_data_free:1;
+        /** serial_out_ep_data_avail : RO; bitpos: [2]; default: 0;
+         *  1'b1: Indicate there is data in UART Rx FIFO.
+         */
+        uint32_t serial_out_ep_data_avail:1;
+        uint32_t reserved_3:29;
+    };
+    uint32_t val;
+} usb_serial_jtag_ep1_conf_reg_t;
+
+/** Type of conf0 register
+ *  PHY hardware configuration.
+ */
+typedef union {
+    struct {
+        /** phy_sel : R/W; bitpos: [0]; default: 0;
+         *  Select internal/external PHY
+         */
+        uint32_t phy_sel:1;
+        /** exchg_pins_override : R/W; bitpos: [1]; default: 0;
+         *  Enable software control USB D+ D- exchange
+         */
+        uint32_t exchg_pins_override:1;
+        /** exchg_pins : R/W; bitpos: [2]; default: 0;
+         *  USB D+ D- exchange
+         */
+        uint32_t exchg_pins:1;
+        /** vrefh : R/W; bitpos: [4:3]; default: 0;
+         *  Control single-end input high threshold,1.76V to 2V, step 80mV
+         */
+        uint32_t vrefh:2;
+        /** vrefl : R/W; bitpos: [6:5]; default: 0;
+         *  Control single-end input low threshold,0.8V to 1.04V, step 80mV
+         */
+        uint32_t vrefl:2;
+        /** vref_override : R/W; bitpos: [7]; default: 0;
+         *  Enable software control input  threshold
+         */
+        uint32_t vref_override:1;
+        /** pad_pull_override : R/W; bitpos: [8]; default: 0;
+         *  Enable software control USB D+ D- pullup pulldown
+         */
+        uint32_t pad_pull_override:1;
+        /** dp_pullup : R/W; bitpos: [9]; default: 1;
+         *  Control USB D+ pull up.
+         */
+        uint32_t dp_pullup:1;
+        /** dp_pulldown : R/W; bitpos: [10]; default: 0;
+         *  Control USB D+ pull down.
+         */
+        uint32_t dp_pulldown:1;
+        /** dm_pullup : R/W; bitpos: [11]; default: 0;
+         *  Control USB D- pull up.
+         */
+        uint32_t dm_pullup:1;
+        /** dm_pulldown : R/W; bitpos: [12]; default: 0;
+         *  Control USB D- pull down.
+         */
+        uint32_t dm_pulldown:1;
+        /** pullup_value : R/W; bitpos: [13]; default: 0;
+         *  Control pull up value.
+         */
+        uint32_t pullup_value:1;
+        /** usb_pad_enable : R/W; bitpos: [14]; default: 1;
+         *  Enable USB pad function.
+         */
+        uint32_t usb_pad_enable:1;
+        /** phy_tx_edge_sel : R/W; bitpos: [15]; default: 0;
+         *  0: TX output at clock negedge. 1: Tx output at clock posedge.
+         */
+        uint32_t phy_tx_edge_sel:1;
+        /** pll_div2_en : R/W; bitpos: [16]; default: 1;
+         *  This bit is used to set divider coefficient of PLL. 0: PLL divider coefficient is
+         *  0. 1: PLL divider coefficient is 1.
+         */
+        uint32_t pll_div2_en:1;
+        uint32_t reserved_17:15;
+    };
+    uint32_t val;
+} usb_serial_jtag_conf0_reg_t;
+
+/** Type of test register
+ *  Registers used for debugging the PHY.
+ */
+typedef union {
+    struct {
+        /** test_enable : R/W; bitpos: [0]; default: 0;
+         *  Enable test of the USB pad
+         */
+        uint32_t test_enable:1;
+        /** test_usb_oe : R/W; bitpos: [1]; default: 0;
+         *  USB pad oen in test
+         */
+        uint32_t test_usb_oe:1;
+        /** test_tx_dp : R/W; bitpos: [2]; default: 0;
+         *  USB D+ tx value in test
+         */
+        uint32_t test_tx_dp:1;
+        /** test_tx_dm : R/W; bitpos: [3]; default: 0;
+         *  USB D- tx value in test
+         */
+        uint32_t test_tx_dm:1;
+        /** test_rx_rcv : RO; bitpos: [4]; default: 0;
+         *  USB differential rx value in test
+         */
+        uint32_t test_rx_rcv:1;
+        /** test_rx_dp : RO; bitpos: [5]; default: 0;
+         *  USB D+ rx value in test
+         */
+        uint32_t test_rx_dp:1;
+        /** test_rx_dm : RO; bitpos: [6]; default: 0;
+         *  USB D- rx value in test
+         */
+        uint32_t test_rx_dm:1;
+        uint32_t reserved_7:25;
+    };
+    uint32_t val;
+} usb_serial_jtag_test_reg_t;
+
+/** Type of misc_conf register
+ *  Clock enable control
+ */
+typedef union {
+    struct {
+        /** clk_en : R/W; bitpos: [0]; default: 0;
+         *  1'h1: Force clock on for register. 1'h0: Support clock only when application writes
+         *  registers.
+         */
+        uint32_t clk_en:1;
+        uint32_t reserved_1:31;
+    };
+    uint32_t val;
+} usb_serial_jtag_misc_conf_reg_t;
+
+/** Type of mem_conf register
+ *  Memory power control
+ */
+typedef union {
+    struct {
+        /** usb_mem_pd : R/W; bitpos: [0]; default: 0;
+         *  1: power down usb memory.
+         */
+        uint32_t usb_mem_pd:1;
+        /** usb_mem_clk_en : R/W; bitpos: [1]; default: 1;
+         *  1: Force clock on for usb memory.
+         */
+        uint32_t usb_mem_clk_en:1;
+        uint32_t reserved_2:30;
+    };
+    uint32_t val;
+} usb_serial_jtag_mem_conf_reg_t;
+
+
+/** Group: Interrupt Registers */
+/** Type of int_raw register
+ *  Interrupt raw status register.
+ */
+typedef union {
+    struct {
+        /** jtag_in_flush_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
+         *  The raw interrupt bit turns to high level when flush cmd is received for IN
+         *  endpoint 2 of JTAG.
+         */
+        uint32_t jtag_in_flush_int_raw:1;
+        /** sof_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
+         *  The raw interrupt bit turns to high level when SOF frame is received.
+         */
+        uint32_t sof_int_raw:1;
+        /** serial_out_recv_pkt_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
+         *  The raw interrupt bit turns to high level when Serial Port OUT Endpoint received
+         *  one packet.
+         */
+        uint32_t serial_out_recv_pkt_int_raw:1;
+        /** serial_in_empty_int_raw : R/WTC/SS; bitpos: [3]; default: 1;
+         *  The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty.
+         */
+        uint32_t serial_in_empty_int_raw:1;
+        /** pid_err_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw interrupt bit turns to high level when pid error is detected.
+         */
+        uint32_t pid_err_int_raw:1;
+        /** crc5_err_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
+         *  The raw interrupt bit turns to high level when CRC5 error is detected.
+         */
+        uint32_t crc5_err_int_raw:1;
+        /** crc16_err_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
+         *  The raw interrupt bit turns to high level when CRC16 error is detected.
+         */
+        uint32_t crc16_err_int_raw:1;
+        /** stuff_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
+         *  The raw interrupt bit turns to high level when stuff error is detected.
+         */
+        uint32_t stuff_err_int_raw:1;
+        /** in_token_rec_in_ep1_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
+         *  The raw interrupt bit turns to high level when IN token for IN endpoint 1 is
+         *  received.
+         */
+        uint32_t in_token_rec_in_ep1_int_raw:1;
+        /** usb_bus_reset_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
+         *  The raw interrupt bit turns to high level when usb bus reset is detected.
+         */
+        uint32_t usb_bus_reset_int_raw:1;
+        /** out_ep1_zero_payload_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
+         *  The raw interrupt bit turns to high level when OUT endpoint 1 received packet with
+         *  zero palyload.
+         */
+        uint32_t out_ep1_zero_payload_int_raw:1;
+        /** out_ep2_zero_payload_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
+         *  The raw interrupt bit turns to high level when OUT endpoint 2 received packet with
+         *  zero palyload.
+         */
+        uint32_t out_ep2_zero_payload_int_raw:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} usb_serial_jtag_int_raw_reg_t;
+
+/** Type of int_st register
+ *  Interrupt status register.
+ */
+typedef union {
+    struct {
+        /** jtag_in_flush_int_st : RO; bitpos: [0]; default: 0;
+         *  The raw interrupt status bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt.
+         */
+        uint32_t jtag_in_flush_int_st:1;
+        /** sof_int_st : RO; bitpos: [1]; default: 0;
+         *  The raw interrupt status bit for the USB_SERIAL_JTAG_SOF_INT interrupt.
+         */
+        uint32_t sof_int_st:1;
+        /** serial_out_recv_pkt_int_st : RO; bitpos: [2]; default: 0;
+         *  The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
+         *  interrupt.
+         */
+        uint32_t serial_out_recv_pkt_int_st:1;
+        /** serial_in_empty_int_st : RO; bitpos: [3]; default: 0;
+         *  The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt.
+         */
+        uint32_t serial_in_empty_int_st:1;
+        /** pid_err_int_st : RO; bitpos: [4]; default: 0;
+         *  The raw interrupt status bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt.
+         */
+        uint32_t pid_err_int_st:1;
+        /** crc5_err_int_st : RO; bitpos: [5]; default: 0;
+         *  The raw interrupt status bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt.
+         */
+        uint32_t crc5_err_int_st:1;
+        /** crc16_err_int_st : RO; bitpos: [6]; default: 0;
+         *  The raw interrupt status bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt.
+         */
+        uint32_t crc16_err_int_st:1;
+        /** stuff_err_int_st : RO; bitpos: [7]; default: 0;
+         *  The raw interrupt status bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt.
+         */
+        uint32_t stuff_err_int_st:1;
+        /** in_token_rec_in_ep1_int_st : RO; bitpos: [8]; default: 0;
+         *  The raw interrupt status bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT
+         *  interrupt.
+         */
+        uint32_t in_token_rec_in_ep1_int_st:1;
+        /** usb_bus_reset_int_st : RO; bitpos: [9]; default: 0;
+         *  The raw interrupt status bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt.
+         */
+        uint32_t usb_bus_reset_int_st:1;
+        /** out_ep1_zero_payload_int_st : RO; bitpos: [10]; default: 0;
+         *  The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT
+         *  interrupt.
+         */
+        uint32_t out_ep1_zero_payload_int_st:1;
+        /** out_ep2_zero_payload_int_st : RO; bitpos: [11]; default: 0;
+         *  The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT
+         *  interrupt.
+         */
+        uint32_t out_ep2_zero_payload_int_st:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} usb_serial_jtag_int_st_reg_t;
+
+/** Type of int_ena register
+ *  Interrupt enable status register.
+ */
+typedef union {
+    struct {
+        /** jtag_in_flush_int_ena : R/W; bitpos: [0]; default: 0;
+         *  The interrupt enable bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt.
+         */
+        uint32_t jtag_in_flush_int_ena:1;
+        /** sof_int_ena : R/W; bitpos: [1]; default: 0;
+         *  The interrupt enable bit for the USB_SERIAL_JTAG_SOF_INT interrupt.
+         */
+        uint32_t sof_int_ena:1;
+        /** serial_out_recv_pkt_int_ena : R/W; bitpos: [2]; default: 0;
+         *  The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt.
+         */
+        uint32_t serial_out_recv_pkt_int_ena:1;
+        /** serial_in_empty_int_ena : R/W; bitpos: [3]; default: 0;
+         *  The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt.
+         */
+        uint32_t serial_in_empty_int_ena:1;
+        /** pid_err_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The interrupt enable bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt.
+         */
+        uint32_t pid_err_int_ena:1;
+        /** crc5_err_int_ena : R/W; bitpos: [5]; default: 0;
+         *  The interrupt enable bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt.
+         */
+        uint32_t crc5_err_int_ena:1;
+        /** crc16_err_int_ena : R/W; bitpos: [6]; default: 0;
+         *  The interrupt enable bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt.
+         */
+        uint32_t crc16_err_int_ena:1;
+        /** stuff_err_int_ena : R/W; bitpos: [7]; default: 0;
+         *  The interrupt enable bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt.
+         */
+        uint32_t stuff_err_int_ena:1;
+        /** in_token_rec_in_ep1_int_ena : R/W; bitpos: [8]; default: 0;
+         *  The interrupt enable bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT interrupt.
+         */
+        uint32_t in_token_rec_in_ep1_int_ena:1;
+        /** usb_bus_reset_int_ena : R/W; bitpos: [9]; default: 0;
+         *  The interrupt enable bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt.
+         */
+        uint32_t usb_bus_reset_int_ena:1;
+        /** out_ep1_zero_payload_int_ena : R/W; bitpos: [10]; default: 0;
+         *  The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
+         */
+        uint32_t out_ep1_zero_payload_int_ena:1;
+        /** out_ep2_zero_payload_int_ena : R/W; bitpos: [11]; default: 0;
+         *  The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
+         */
+        uint32_t out_ep2_zero_payload_int_ena:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} usb_serial_jtag_int_ena_reg_t;
+
+/** Type of int_clr register
+ *  Interrupt clear status register.
+ */
+typedef union {
+    struct {
+        /** jtag_in_flush_int_clr : WT; bitpos: [0]; default: 0;
+         *  Set this bit to clear the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt.
+         */
+        uint32_t jtag_in_flush_int_clr:1;
+        /** sof_int_clr : WT; bitpos: [1]; default: 0;
+         *  Set this bit to clear the USB_SERIAL_JTAG_JTAG_SOF_INT interrupt.
+         */
+        uint32_t sof_int_clr:1;
+        /** serial_out_recv_pkt_int_clr : WT; bitpos: [2]; default: 0;
+         *  Set this bit to clear the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt.
+         */
+        uint32_t serial_out_recv_pkt_int_clr:1;
+        /** serial_in_empty_int_clr : WT; bitpos: [3]; default: 0;
+         *  Set this bit to clear the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt.
+         */
+        uint32_t serial_in_empty_int_clr:1;
+        /** pid_err_int_clr : WT; bitpos: [4]; default: 0;
+         *  Set this bit to clear the USB_SERIAL_JTAG_PID_ERR_INT interrupt.
+         */
+        uint32_t pid_err_int_clr:1;
+        /** crc5_err_int_clr : WT; bitpos: [5]; default: 0;
+         *  Set this bit to clear the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt.
+         */
+        uint32_t crc5_err_int_clr:1;
+        /** crc16_err_int_clr : WT; bitpos: [6]; default: 0;
+         *  Set this bit to clear the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt.
+         */
+        uint32_t crc16_err_int_clr:1;
+        /** stuff_err_int_clr : WT; bitpos: [7]; default: 0;
+         *  Set this bit to clear the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt.
+         */
+        uint32_t stuff_err_int_clr:1;
+        /** in_token_rec_in_ep1_int_clr : WT; bitpos: [8]; default: 0;
+         *  Set this bit to clear the USB_SERIAL_JTAG_IN_TOKEN_IN_EP1_INT interrupt.
+         */
+        uint32_t in_token_rec_in_ep1_int_clr:1;
+        /** usb_bus_reset_int_clr : WT; bitpos: [9]; default: 0;
+         *  Set this bit to clear the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt.
+         */
+        uint32_t usb_bus_reset_int_clr:1;
+        /** out_ep1_zero_payload_int_clr : WT; bitpos: [10]; default: 0;
+         *  Set this bit to clear the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
+         */
+        uint32_t out_ep1_zero_payload_int_clr:1;
+        /** out_ep2_zero_payload_int_clr : WT; bitpos: [11]; default: 0;
+         *  Set this bit to clear the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
+         */
+        uint32_t out_ep2_zero_payload_int_clr:1;
+        uint32_t reserved_12:20;
+    };
+    uint32_t val;
+} usb_serial_jtag_int_clr_reg_t;
+
+
+/** Group: Status Registers */
+/** Type of jfifo_st register
+ *  JTAG FIFO status and control registers.
+ */
+typedef union {
+    struct {
+        /** in_fifo_cnt : RO; bitpos: [1:0]; default: 0;
+         *  JTAT in fifo counter.
+         */
+        uint32_t in_fifo_cnt:2;
+        /** in_fifo_empty : RO; bitpos: [2]; default: 1;
+         *  1: JTAG in fifo is empty.
+         */
+        uint32_t in_fifo_empty:1;
+        /** in_fifo_full : RO; bitpos: [3]; default: 0;
+         *  1: JTAG in fifo is full.
+         */
+        uint32_t in_fifo_full:1;
+        /** out_fifo_cnt : RO; bitpos: [5:4]; default: 0;
+         *  JTAT out fifo counter.
+         */
+        uint32_t out_fifo_cnt:2;
+        /** out_fifo_empty : RO; bitpos: [6]; default: 1;
+         *  1: JTAG out fifo is empty.
+         */
+        uint32_t out_fifo_empty:1;
+        /** out_fifo_full : RO; bitpos: [7]; default: 0;
+         *  1: JTAG out fifo is full.
+         */
+        uint32_t out_fifo_full:1;
+        /** in_fifo_reset : R/W; bitpos: [8]; default: 0;
+         *  Write 1 to reset JTAG in fifo.
+         */
+        uint32_t in_fifo_reset:1;
+        /** out_fifo_reset : R/W; bitpos: [9]; default: 0;
+         *  Write 1 to reset JTAG out fifo.
+         */
+        uint32_t out_fifo_reset:1;
+        uint32_t reserved_10:22;
+    };
+    uint32_t val;
+} usb_serial_jtag_jfifo_st_reg_t;
+
+/** Type of fram_num register
+ *  Last received SOF frame index register.
+ */
+typedef union {
+    struct {
+        /** sof_frame_index : RO; bitpos: [10:0]; default: 0;
+         *  Frame index of received SOF frame.
+         */
+        uint32_t sof_frame_index:11;
+        uint32_t reserved_11:21;
+    };
+    uint32_t val;
+} usb_serial_jtag_fram_num_reg_t;
+
+/** Type of in_ep0_st register
+ *  Control IN endpoint status information.
+ */
+typedef union {
+    struct {
+        /** in_ep0_state : RO; bitpos: [1:0]; default: 1;
+         *  State of IN Endpoint 0.
+         */
+        uint32_t in_ep0_state:2;
+        /** in_ep0_wr_addr : RO; bitpos: [8:2]; default: 0;
+         *  Write data address of IN endpoint 0.
+         */
+        uint32_t in_ep0_wr_addr:7;
+        /** in_ep0_rd_addr : RO; bitpos: [15:9]; default: 0;
+         *  Read data address of IN endpoint 0.
+         */
+        uint32_t in_ep0_rd_addr:7;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} usb_serial_jtag_in_ep0_st_reg_t;
+
+/** Type of in_ep1_st register
+ *  CDC-ACM IN endpoint status information.
+ */
+typedef union {
+    struct {
+        /** in_ep1_state : RO; bitpos: [1:0]; default: 1;
+         *  State of IN Endpoint 1.
+         */
+        uint32_t in_ep1_state:2;
+        /** in_ep1_wr_addr : RO; bitpos: [8:2]; default: 0;
+         *  Write data address of IN endpoint 1.
+         */
+        uint32_t in_ep1_wr_addr:7;
+        /** in_ep1_rd_addr : RO; bitpos: [15:9]; default: 0;
+         *  Read data address of IN endpoint 1.
+         */
+        uint32_t in_ep1_rd_addr:7;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} usb_serial_jtag_in_ep1_st_reg_t;
+
+/** Type of in_ep2_st register
+ *  CDC-ACM interrupt IN endpoint status information.
+ */
+typedef union {
+    struct {
+        /** in_ep2_state : RO; bitpos: [1:0]; default: 1;
+         *  State of IN Endpoint 2.
+         */
+        uint32_t in_ep2_state:2;
+        /** in_ep2_wr_addr : RO; bitpos: [8:2]; default: 0;
+         *  Write data address of IN endpoint 2.
+         */
+        uint32_t in_ep2_wr_addr:7;
+        /** in_ep2_rd_addr : RO; bitpos: [15:9]; default: 0;
+         *  Read data address of IN endpoint 2.
+         */
+        uint32_t in_ep2_rd_addr:7;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} usb_serial_jtag_in_ep2_st_reg_t;
+
+/** Type of in_ep3_st register
+ *  JTAG IN endpoint status information.
+ */
+typedef union {
+    struct {
+        /** in_ep3_state : RO; bitpos: [1:0]; default: 1;
+         *  State of IN Endpoint 3.
+         */
+        uint32_t in_ep3_state:2;
+        /** in_ep3_wr_addr : RO; bitpos: [8:2]; default: 0;
+         *  Write data address of IN endpoint 3.
+         */
+        uint32_t in_ep3_wr_addr:7;
+        /** in_ep3_rd_addr : RO; bitpos: [15:9]; default: 0;
+         *  Read data address of IN endpoint 3.
+         */
+        uint32_t in_ep3_rd_addr:7;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} usb_serial_jtag_in_ep3_st_reg_t;
+
+/** Type of out_ep0_st register
+ *  Control OUT endpoint status information.
+ */
+typedef union {
+    struct {
+        /** out_ep0_state : RO; bitpos: [1:0]; default: 0;
+         *  State of OUT Endpoint 0.
+         */
+        uint32_t out_ep0_state:2;
+        /** out_ep0_wr_addr : RO; bitpos: [8:2]; default: 0;
+         *  Write data address of OUT endpoint 0. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
+         *  is detected, there are USB_SERIAL_JTAG_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0.
+         */
+        uint32_t out_ep0_wr_addr:7;
+        /** out_ep0_rd_addr : RO; bitpos: [15:9]; default: 0;
+         *  Read data address of OUT endpoint 0.
+         */
+        uint32_t out_ep0_rd_addr:7;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} usb_serial_jtag_out_ep0_st_reg_t;
+
+/** Type of out_ep1_st register
+ *  CDC-ACM OUT endpoint status information.
+ */
+typedef union {
+    struct {
+        /** out_ep1_state : RO; bitpos: [1:0]; default: 0;
+         *  State of OUT Endpoint 1.
+         */
+        uint32_t out_ep1_state:2;
+        /** out_ep1_wr_addr : RO; bitpos: [8:2]; default: 0;
+         *  Write data address of OUT endpoint 1. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
+         *  is detected, there are USB_SERIAL_JTAG_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1.
+         */
+        uint32_t out_ep1_wr_addr:7;
+        /** out_ep1_rd_addr : RO; bitpos: [15:9]; default: 0;
+         *  Read data address of OUT endpoint 1.
+         */
+        uint32_t out_ep1_rd_addr:7;
+        /** out_ep1_rec_data_cnt : RO; bitpos: [22:16]; default: 0;
+         *  Data count in OUT endpoint 1 when one packet is received.
+         */
+        uint32_t out_ep1_rec_data_cnt:7;
+        uint32_t reserved_23:9;
+    };
+    uint32_t val;
+} usb_serial_jtag_out_ep1_st_reg_t;
+
+/** Type of out_ep2_st register
+ *  JTAG OUT endpoint status information.
+ */
+typedef union {
+    struct {
+        /** out_ep2_state : RO; bitpos: [1:0]; default: 0;
+         *  State of OUT Endpoint 2.
+         */
+        uint32_t out_ep2_state:2;
+        /** out_ep2_wr_addr : RO; bitpos: [8:2]; default: 0;
+         *  Write data address of OUT endpoint 2. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
+         *  is detected, there are USB_SERIAL_JTAG_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2.
+         */
+        uint32_t out_ep2_wr_addr:7;
+        /** out_ep2_rd_addr : RO; bitpos: [15:9]; default: 0;
+         *  Read data address of OUT endpoint 2.
+         */
+        uint32_t out_ep2_rd_addr:7;
+        uint32_t reserved_16:16;
+    };
+    uint32_t val;
+} usb_serial_jtag_out_ep2_st_reg_t;
+
+
+/** Group: Version Registers */
+/** Type of date register
+ *  Date register
+ */
+typedef union {
+    struct {
+        /** date : R/W; bitpos: [31:0]; default: 34607505;
+         *  register version.
+         */
+        uint32_t date:32;
+    };
+    uint32_t val;
+} usb_serial_jtag_date_reg_t;
+
+
+typedef struct {
+    volatile usb_serial_jtag_ep1_reg_t ep1;
+    volatile usb_serial_jtag_ep1_conf_reg_t ep1_conf;
+    volatile usb_serial_jtag_int_raw_reg_t int_raw;
+    volatile usb_serial_jtag_int_st_reg_t int_st;
+    volatile usb_serial_jtag_int_ena_reg_t int_ena;
+    volatile usb_serial_jtag_int_clr_reg_t int_clr;
+    volatile usb_serial_jtag_conf0_reg_t conf0;
+    volatile usb_serial_jtag_test_reg_t test;
+    volatile usb_serial_jtag_jfifo_st_reg_t jfifo_st;
+    volatile usb_serial_jtag_fram_num_reg_t fram_num;
+    volatile usb_serial_jtag_in_ep0_st_reg_t in_ep0_st;
+    volatile usb_serial_jtag_in_ep1_st_reg_t in_ep1_st;
+    volatile usb_serial_jtag_in_ep2_st_reg_t in_ep2_st;
+    volatile usb_serial_jtag_in_ep3_st_reg_t in_ep3_st;
+    volatile usb_serial_jtag_out_ep0_st_reg_t out_ep0_st;
+    volatile usb_serial_jtag_out_ep1_st_reg_t out_ep1_st;
+    volatile usb_serial_jtag_out_ep2_st_reg_t out_ep2_st;
+    volatile usb_serial_jtag_misc_conf_reg_t misc_conf;
+    volatile usb_serial_jtag_mem_conf_reg_t mem_conf;
+    uint32_t reserved_04c[13];
+    volatile usb_serial_jtag_date_reg_t date;
+} usb_serial_jtag_dev_t;
+
+extern usb_serial_jtag_dev_t USB_SERIAL_JTAG;
+
+#ifndef __cplusplus
+_Static_assert(sizeof(usb_serial_jtag_dev_t) == 0x84, "Invalid size of usb_serial_jtag_dev_t structure");
+#endif
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32h2/include/soc/dport_access.h

@@ -1,16 +1,8 @@
-// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 
 #ifndef _DPORT_ACCESS_H_
 #define _DPORT_ACCESS_H_
@@ -20,7 +12,7 @@
 #include "esp_attr.h"
 #include "esp32h2/dport_access.h"
 #include "soc.h"
-#include "uart_reg.h"
+#include "soc/uart_reg.h"
 
 #ifdef __cplusplus
 extern "C" {

components/soc/esp32h2/include/soc/i2c_reg.h

@@ -1,24 +1,16 @@
-// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 #ifndef _SOC_I2C_REG_H_
 #define _SOC_I2C_REG_H_
 
+#include "soc/soc.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc.h"
 
 #define I2C_SCL_LOW_PERIOD_REG(i)          (REG_I2C_BASE(i) + 0x0)
 /* I2C_SCL_LOW_PERIOD : R/W ;bitpos:[8:0] ;default: 9'b0 ; */

components/soc/esp32h2/include/soc/i2c_struct.h

@@ -1,24 +1,16 @@
-// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 #ifndef _SOC_I2C_STRUCT_H_
 #define _SOC_I2C_STRUCT_H_
 
+#include "soc/soc.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc.h"
 
 typedef volatile struct i2c_dev_s {
     union {

components/soc/esp32h2/include/soc/i2s_reg.h

@@ -1,24 +1,16 @@
-// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 #ifndef _SOC_I2S_REG_H_
 #define _SOC_I2S_REG_H_
 
+#include "soc/soc.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc.h"
 #define I2S_INT_RAW_REG(i)          (REG_I2S_BASE(i) + 0x000c)
 /* I2S_TX_HUNG_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
 /*description: The raw interrupt status bit  for the i2s_tx_hung_int interrupt*/

components/soc/esp32h2/include/soc/i2s_struct.h

@@ -1,16 +1,8 @@
-// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 #ifndef _SOC_I2S_STRUCT_H_
 #define _SOC_I2S_STRUCT_H_
 #ifdef __cplusplus

components/soc/esp32h2/include/soc/interrupt_reg.h

@@ -1 +1 @@
-#include "interrupt_core0_reg.h"
+#include "soc/interrupt_core0_reg.h"

components/soc/esp32h2/include/soc/periph_defs.h

@@ -1,16 +1,8 @@
-// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 
 #pragma once
 
@@ -75,7 +67,7 @@ typedef enum {
     ETS_UART1_INTR_SOURCE,                      /**< interrupt of UART1, level*/
     ETS_LEDC_INTR_SOURCE,                       /**< interrupt of LED PWM, level*/
     ETS_EFUSE_INTR_SOURCE,                      /**< interrupt of efuse, level, not likely to use*/
-    ETS_TWAI_INTR_SOURCE,                        /**< interrupt of can, level*/
+    ETS_TWAI_INTR_SOURCE,                        /**< interrupt of twai, level*/
     ETS_USB_INTR_SOURCE,                        /**< interrupt of USB, level*/
     ETS_RTC_CORE_INTR_SOURCE,                   /**< interrupt of rtc core, level, include rtc watchdog*/
     ETS_RMT_INTR_SOURCE,                        /**< interrupt of remote controller, level*/

components/soc/esp32h2/include/soc/rmt_reg.h

@@ -1,24 +1,16 @@
-// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 #ifndef _SOC_RMT_REG_H_
 #define _SOC_RMT_REG_H_
 
+#include "soc/soc.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc.h"
 #define RMT_CH0DATA_REG          (DR_REG_RMT_BASE + 0x0000)
 
 #define RMT_CH1DATA_REG          (DR_REG_RMT_BASE + 0x0004)

components/soc/esp32h2/include/soc/rmt_struct.h

@@ -1,16 +1,8 @@
-// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 #ifndef _SOC_RMT_STRUCT_H_
 #define _SOC_RMT_STRUCT_H_
 

components/soc/esp32h2/include/soc/soc.h

@@ -1,16 +1,8 @@
-// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 
 #pragma once
 
@@ -81,7 +73,7 @@
 #define DR_REG_SYSCON_BASE                      0x60026000
 #define DR_REG_I2C1_EXT_BASE                    0x60027000
 #define DR_REG_SDMMC_BASE                       0x60028000
-#define DR_REG_CAN_BASE                         0x6002B000
+#define DR_REG_TWAI_BASE                         0x6002B000
 #define DR_REG_PWM1_BASE                        0x6002C000
 #define DR_REG_I2S1_BASE                        0x6002D000
 #define DR_REG_UART2_BASE                       0x6002E000

components/soc/esp32h2/include/soc/systimer_reg.h

@@ -1,24 +1,16 @@
-// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 #ifndef _SOC_SYS_TIMER_REG_H_
 #define _SOC_SYS_TIMER_REG_H_
 
+#include "soc/soc.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc.h"
 #define SYS_TIMER_SYSTIMER_CONF_REG          (DR_REG_SYS_TIMER_BASE + 0x0000)
 /* SYS_TIMER_CLK_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
 /*description: register file clk gating*/

components/soc/esp32h2/include/soc/systimer_struct.h

@@ -1,16 +1,7 @@
-/** Copyright 2021 Espressif Systems (Shanghai) PTE LTD
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
  *
- *  Licensed under the Apache License, Version 2.0 (the "License");
- *  you may not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *      http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS,
- *  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
  */
 #pragma once
 

components/soc/esp32h2/include/soc/timer_group_reg.h

@@ -1,5 +1,5 @@
 /**
- *  SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
  *
  *  SPDX-License-Identifier: Apache-2.0
  */

components/soc/esp32h2/include/soc/uart_reg.h

@@ -1,24 +1,16 @@
-// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 #ifndef _SOC_UART_REG_H_
 #define _SOC_UART_REG_H_
 
+#include "soc/soc.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc.h"
 #define UART_FIFO_REG(i)          (REG_UART_BASE(i) + 0x0)
 /* UART_RXFIFO_RD_BYTE : RO ;bitpos:[7:0] ;default: 8'b0 ; */
 /*description: UART $n accesses FIFO via this register.*/

components/soc/esp32h2/include/soc/uart_struct.h

@@ -1,16 +1,8 @@
-// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 #ifndef _SOC_UART_STRUCT_H_
 #define _SOC_UART_STRUCT_H_
 #ifdef __cplusplus

components/soc/esp32h2/include/soc/uhci_reg.h

@@ -1,24 +1,16 @@
-// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 #ifndef _SOC_UHCI_REG_H_
 #define _SOC_UHCI_REG_H_
 
+#include "soc/soc.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
-#include "soc.h"
 #define UHCI_CONF0_REG(i)          (REG_UHCI_BASE(i) + 0x0)
 /* UHCI_UART_RX_BRK_EOF_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */
 /*description: If this bit is set to 1  UHCI will end payload receive process

components/soc/esp32h2/include/soc/uhci_struct.h

@@ -1,16 +1,8 @@
-// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 #ifndef _SOC_UHCI_STRUCT_H_
 #define _SOC_UHCI_STRUCT_H_
 #ifdef __cplusplus

components/soc/esp32h2/interrupts.c

@@ -1,16 +1,8 @@
-// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 
 #include "soc/interrupts.h"
 
@@ -40,7 +32,7 @@ const char *const esp_isr_names[ETS_MAX_INTR_SOURCE] = {
     [22] = "UART1",
     [23] = "LEDC",
     [24] = "EFUSE",
-    [25] = "CAN",
+    [25] = "TWAI",
     [26] = "USB",
     [27] = "RTC_CORE",
     [28] = "RMT",

tools/ci/check_copyright_ignore.txt

@@ -1199,12 +1199,10 @@ components/hal/esp32h2/include/hal/ds_ll.h
 components/hal/esp32h2/include/hal/gpspi_flash_ll.h
 components/hal/esp32h2/include/hal/hmac_hal.h
 components/hal/esp32h2/include/hal/hmac_ll.h
-components/hal/esp32h2/include/hal/i2c_ll.h
 components/hal/esp32h2/include/hal/interrupt_controller_ll.h
 components/hal/esp32h2/include/hal/memprot_ll.h
 components/hal/esp32h2/include/hal/mpu_ll.h
 components/hal/esp32h2/include/hal/rtc_cntl_ll.h
-components/hal/esp32h2/include/hal/rwdt_ll.h
 components/hal/esp32h2/include/hal/sha_ll.h
 components/hal/esp32h2/include/hal/sigmadelta_ll.h
 components/hal/esp32h2/include/hal/soc_ll.h
@@ -1212,9 +1210,7 @@ components/hal/esp32h2/include/hal/spi_flash_encrypted_ll.h
 components/hal/esp32h2/include/hal/spi_flash_ll.h
 components/hal/esp32h2/include/hal/spi_ll.h
 components/hal/esp32h2/include/hal/spimem_flash_ll.h
-components/hal/esp32h2/include/hal/systimer_ll.h
 components/hal/esp32h2/include/hal/twai_ll.h
-components/hal/esp32h2/include/hal/uart_ll.h
 components/hal/esp32h2/include/hal/uhci_ll.h
 components/hal/esp32h2/include/hal/uhci_types.h
 components/hal/esp32h2/include/hal/usb_serial_jtag_ll.h
@@ -1959,7 +1955,6 @@ components/soc/esp32h2/include/soc/bb_reg.h
 components/soc/esp32h2/include/soc/boot_mode.h
 components/soc/esp32h2/include/soc/clkout_channel.h
 components/soc/esp32h2/include/soc/clkrst_reg.h
-components/soc/esp32h2/include/soc/dport_access.h
 components/soc/esp32h2/include/soc/efuse_reg.h
 components/soc/esp32h2/include/soc/efuse_struct.h
 components/soc/esp32h2/include/soc/extmem_reg.h
@@ -1969,25 +1964,17 @@ components/soc/esp32h2/include/soc/gpio_sd_reg.h
 components/soc/esp32h2/include/soc/gpio_sd_struct.h
 components/soc/esp32h2/include/soc/gpio_struct.h
 components/soc/esp32h2/include/soc/hwcrypto_reg.h
-components/soc/esp32h2/include/soc/i2c_reg.h
-components/soc/esp32h2/include/soc/i2c_struct.h
-components/soc/esp32h2/include/soc/i2s_reg.h
-components/soc/esp32h2/include/soc/i2s_struct.h
 components/soc/esp32h2/include/soc/interrupt_reg.h
 components/soc/esp32h2/include/soc/io_mux_reg.h
 components/soc/esp32h2/include/soc/ledc_reg.h
 components/soc/esp32h2/include/soc/mmu.h
 components/soc/esp32h2/include/soc/nrx_reg.h
-components/soc/esp32h2/include/soc/periph_defs.h
 components/soc/esp32h2/include/soc/reset_reasons.h
-components/soc/esp32h2/include/soc/rmt_reg.h
-components/soc/esp32h2/include/soc/rmt_struct.h
 components/soc/esp32h2/include/soc/rtc_caps.h
 components/soc/esp32h2/include/soc/rtc_i2c_reg.h
 components/soc/esp32h2/include/soc/rtc_i2c_struct.h
 components/soc/esp32h2/include/soc/rtc_io_caps.h
 components/soc/esp32h2/include/soc/sensitive_struct.h
-components/soc/esp32h2/include/soc/soc.h
 components/soc/esp32h2/include/soc/soc_caps.h
 components/soc/esp32h2/include/soc/soc_pins.h
 components/soc/esp32h2/include/soc/spi_caps.h
@@ -2000,19 +1987,12 @@ components/soc/esp32h2/include/soc/syscon_reg.h
 components/soc/esp32h2/include/soc/syscon_struct.h
 components/soc/esp32h2/include/soc/system_reg.h
 components/soc/esp32h2/include/soc/system_struct.h
-components/soc/esp32h2/include/soc/systimer_reg.h
-components/soc/esp32h2/include/soc/systimer_struct.h
 components/soc/esp32h2/include/soc/twai_struct.h
 components/soc/esp32h2/include/soc/uart_channel.h
 components/soc/esp32h2/include/soc/uart_pins.h
-components/soc/esp32h2/include/soc/uart_reg.h
-components/soc/esp32h2/include/soc/uart_struct.h
-components/soc/esp32h2/include/soc/uhci_reg.h
-components/soc/esp32h2/include/soc/uhci_struct.h
 components/soc/esp32h2/include/soc/usb_serial_jtag_reg.h
 components/soc/esp32h2/include/soc/usb_serial_jtag_struct.h
 components/soc/esp32h2/include/soc/wdev_reg.h
-components/soc/esp32h2/interrupts.c
 components/soc/esp32h2/ld/esp32h2.peripherals.ld
 components/soc/esp32h2/ledc_periph.c
 components/soc/esp32h2/rmt_periph.c

tools/ci/check_copyright_permanent_ignore.txt

@@ -8,4 +8,3 @@ components/bt/host/bluedroid/main/*
 components/bt/host/bluedroid/stack/*
 components/bt/host/nimble/nimble/*
 components/wpa_supplicant/src/*
-components/esp_rom/esp32h2/ld/*