clk_tree: added default clock source for peripheral

components/app_trace/sys_view/Sample/Config/SEGGER_SYSVIEW_Config_FreeRTOS.c

@@ -197,7 +197,7 @@ static void SEGGER_SYSVIEW_TS_Init(void)
      */
 #if TS_USE_TIMERGROUP
     gptimer_config_t config = {
-        .clk_src = GPTIMER_CLK_SRC_APB,
+        .clk_src = GPTIMER_CLK_SRC_DEFAULT,
         .direction = GPTIMER_COUNT_UP,
         .resolution_hz = SYSVIEW_TIMESTAMP_FREQ,
     };

components/app_trace/test/test_trace.c

@@ -156,7 +156,7 @@ static void esp_apptrace_dummy_task(void *p)
 
     for (int i = 0; i < arg->timers_num; i++) {
         gptimer_config_t timer_config = {
-            .clk_src = GPTIMER_CLK_SRC_APB,
+            .clk_src = GPTIMER_CLK_SRC_DEFAULT,
             .direction = GPTIMER_COUNT_UP,
             .resolution_hz = 1000000,
         };
@@ -203,7 +203,7 @@ static void esp_apptrace_test_task(void *p)
 
     for (int i = 0; i < arg->timers_num; i++) {
         gptimer_config_t timer_config = {
-            .clk_src = GPTIMER_CLK_SRC_APB,
+            .clk_src = GPTIMER_CLK_SRC_DEFAULT,
             .direction = GPTIMER_COUNT_UP,
             .resolution_hz = 1000000,
         };
@@ -305,7 +305,7 @@ static uint64_t esp_apptrace_test_ts_get(void)
 static void esp_apptrace_test_ts_init(void)
 {
     gptimer_config_t timer_config = {
-        .clk_src = GPTIMER_CLK_SRC_APB,
+        .clk_src = GPTIMER_CLK_SRC_DEFAULT,
         .direction = GPTIMER_COUNT_UP,
         .resolution_hz = 10000000,
     };
@@ -791,7 +791,7 @@ TEST_CASE("SysView trace test 1", "[trace][ignore]")
     };
 
     gptimer_config_t timer_config = {
-        .clk_src = GPTIMER_CLK_SRC_APB,
+        .clk_src = GPTIMER_CLK_SRC_DEFAULT,
         .direction = GPTIMER_COUNT_UP,
         .resolution_hz = 1000000,
     };
@@ -870,7 +870,7 @@ TEST_CASE("SysView trace test 2", "[trace][ignore]")
     };
 
     gptimer_config_t timer_config = {
-        .clk_src = GPTIMER_CLK_SRC_APB,
+        .clk_src = GPTIMER_CLK_SRC_DEFAULT,
         .direction = GPTIMER_COUNT_UP,
         .resolution_hz = 1000000,
     };

components/driver/deprecated/driver/timer_types_legacy.h

@@ -7,6 +7,7 @@
 #pragma once
 
 #include "soc/soc_caps.h"
+#include "soc/clk_tree_defs.h"
 #include "hal/timer_types.h"
 #include "esp_intr_alloc.h"
 #include "esp_attr.h"
@@ -105,12 +106,7 @@ typedef enum {
 /**
  * @brief Timer group clock source
  */
-typedef enum {
-    TIMER_SRC_CLK_APB = GPTIMER_CLK_SRC_APB,   /*!< Select APB as the source clock*/
-#if SOC_TIMER_GROUP_SUPPORT_XTAL
-    TIMER_SRC_CLK_XTAL = GPTIMER_CLK_SRC_XTAL, /*!< Select XTAL as the source clock*/
-#endif
-} timer_src_clk_t;
+typedef soc_periph_tg_clk_src_legacy_t timer_src_clk_t;
 
 /**
  * @brief Interrupt handler callback function

components/driver/deprecated/pcnt_legacy.c

@@ -555,7 +555,7 @@ static void check_pcnt_driver_conflict(void)
     // This function was declared as weak here. pulse_cnt driver has one implementation.
     // So if pulse_cnt driver is not linked in, then `pcnt_new_unit` should be NULL at runtime.
     extern __attribute__((weak)) esp_err_t pcnt_new_unit(const void *config, void **ret_unit);
-    if (pcnt_new_unit != NULL) {
+    if ((void *)pcnt_new_unit != NULL) {
         ESP_EARLY_LOGE(TAG, "CONFLICT! driver_ng is not allowed to be used with the legacy driver");
         abort();
     }

components/driver/deprecated/timer_legacy.c

@@ -44,7 +44,7 @@ typedef struct {
 typedef struct {
     timer_hal_context_t hal;
     timer_isr_func_t timer_isr_fun;
-    gptimer_clock_source_t clk_src;
+    timer_src_clk_t clk_src;
     gptimer_count_direction_t direction;
     uint32_t divider;
     uint64_t alarm_value;
@@ -76,14 +76,27 @@ esp_err_t timer_get_counter_time_sec(timer_group_t group_num, timer_idx_t timer_
     ESP_RETURN_ON_FALSE(p_timer_obj[group_num][timer_num] != NULL, ESP_ERR_INVALID_ARG, TIMER_TAG,  TIMER_NEVER_INIT_ERROR);
     uint64_t timer_val = timer_ll_get_counter_value(p_timer_obj[group_num][timer_num]->hal.dev, timer_num);
     uint32_t div = p_timer_obj[group_num][timer_num]->divider;
+    // [clk_tree] TODO: replace the following switch table by clk_tree API
     switch (p_timer_obj[group_num][timer_num]->clk_src) {
-    case GPTIMER_CLK_SRC_APB:
+#if SOC_TIMER_GROUP_SUPPORT_APB
+    case TIMER_SRC_CLK_APB:
         *time = (double)timer_val * div / esp_clk_apb_freq();
         break;
+#endif
 #if SOC_TIMER_GROUP_SUPPORT_XTAL
-    case GPTIMER_CLK_SRC_XTAL:
+    case TIMER_SRC_CLK_XTAL:
         *time = (double)timer_val * div / esp_clk_xtal_freq();
         break;
+#endif
+#if SOC_TIMER_GROUP_SUPPORT_AHB
+    case TIMER_SRC_CLK_AHB:
+        *time = (double)timer_val * div / 48 * 1000 * 1000;
+        break;
+#endif
+#if SOC_TIMER_GROUP_SUPPORT_PLL_F40M
+    case TIMER_SRC_CLK_PLL_F40M:
+        *time = (double)timer_val * div / 40 * 1000 * 1000;
+        break;
 #endif
     default:
         ESP_RETURN_ON_FALSE(false, ESP_ERR_INVALID_ARG, TIMER_TAG, "invalid clock source");
@@ -315,7 +328,9 @@ esp_err_t timer_init(timer_group_t group_num, timer_idx_t timer_num, const timer
     TIMER_ENTER_CRITICAL(&timer_spinlock[group_num]);
     timer_hal_init(hal, group_num, timer_num);
     timer_hal_set_counter_value(hal, 0);
-    timer_ll_set_clock_source(p_timer_obj[group_num][timer_num]->hal.dev, timer_num, config->clk_src);
+    // although `clk_src` is of `timer_src_clk_t` type, but it's binary compatible with `gptimer_clock_source_t`,
+    // as the underlying enum entries come from the same `soc_module_clk_t`
+    timer_ll_set_clock_source(p_timer_obj[group_num][timer_num]->hal.dev, timer_num, (gptimer_clock_source_t)config->clk_src);
     timer_ll_set_clock_prescale(hal->dev, timer_num, config->divider);
     timer_ll_set_count_direction(p_timer_obj[group_num][timer_num]->hal.dev, timer_num, config->counter_dir);
     timer_ll_enable_intr(hal->dev, TIMER_LL_EVENT_ALARM(timer_num), false);
@@ -483,7 +498,7 @@ static void check_legacy_timer_driver_conflict(void)
     // This function was declared as weak here. gptimer driver has one implementation.
     // So if gptimer driver is not linked in, then `gptimer_new_timer()` should be NULL at runtime.
     extern __attribute__((weak)) esp_err_t gptimer_new_timer(const void *config, void **ret_timer);
-    if (gptimer_new_timer != NULL) {
+    if ((void *)gptimer_new_timer != NULL) {
         ESP_EARLY_LOGE(TIMER_TAG, "CONFLICT! driver_ng is not allowed to be used with the legacy driver");
         abort();
     }

components/driver/gptimer.c

@@ -422,7 +422,9 @@ static esp_err_t gptimer_select_periph_clock(gptimer_t *timer, gptimer_clock_sou
     unsigned int counter_src_hz = 0;
     esp_err_t ret = ESP_OK;
     int timer_id = timer->timer_id;
+    // [clk_tree] TODO: replace the following switch table by clk_tree API
     switch (src_clk) {
+#if SOC_TIMER_GROUP_SUPPORT_APB
     case GPTIMER_CLK_SRC_APB:
         counter_src_hz = esp_clk_apb_freq();
 #if CONFIG_PM_ENABLE
@@ -432,11 +434,24 @@ static esp_err_t gptimer_select_periph_clock(gptimer_t *timer, gptimer_clock_sou
         ESP_LOGD(TAG, "install APB_FREQ_MAX lock for timer (%d,%d)", timer->group->group_id, timer_id);
 #endif
         break;
+#endif // SOC_TIMER_GROUP_SUPPORT_APB
+#if SOC_TIMER_GROUP_SUPPORT_PLL_F40M
+    case GPTIMER_CLK_SRC_PLL_F40M:
+        // TODO: decide which kind of PM lock we should use for such clock
+        counter_src_hz = 40 * 1000 * 1000;
+        break;
+#endif // SOC_TIMER_GROUP_SUPPORT_PLL_F40M
+#if SOC_TIMER_GROUP_SUPPORT_AHB
+    case GPTIMER_CLK_SRC_AHB:
+        // TODO: decide which kind of PM lock we should use for such clock
+        counter_src_hz = 48 * 1000 * 1000;
+        break;
+#endif // SOC_TIMER_GROUP_SUPPORT_AHB
 #if SOC_TIMER_GROUP_SUPPORT_XTAL
     case GPTIMER_CLK_SRC_XTAL:
         counter_src_hz = esp_clk_xtal_freq();
         break;
-#endif
+#endif // SOC_TIMER_GROUP_SUPPORT_XTAL
     default:
         ESP_RETURN_ON_FALSE(false, ESP_ERR_NOT_SUPPORTED, TAG, "clock source %d is not support", src_clk);
         break;

components/driver/include/driver/rmt.h

@@ -10,6 +10,7 @@
 #include <stdint.h>
 #include "esp_err.h"
 #include "soc/soc_caps.h"
+#include "soc/clk_tree_defs.h"
 #include "driver/gpio.h"
 #include "freertos/FreeRTOS.h"
 #include "freertos/ringbuf.h"
@@ -88,16 +89,7 @@ typedef enum {
  * @brief Clock Source of RMT Channel
  *
  */
-typedef enum {
-#if SOC_RMT_SUPPORT_REF_TICK
-    RMT_BASECLK_REF = 0, /*!< RMT source clock is REF_TICK, 1MHz by default */
-#endif
-    RMT_BASECLK_APB = 1, /*!< RMT source clock is APB CLK, 80Mhz by default */
-#if SOC_RMT_SUPPORT_XTAL
-    RMT_BASECLK_XTAL = 3, /*!< RMT source clock is XTAL clock, 40Mhz by default */
-#endif
-    RMT_BASECLK_MAX,
-} rmt_source_clk_t;
+typedef soc_periph_rmt_clk_src_legacy_t rmt_source_clk_t;
 
 /**
  * @brief RMT Data Mode

components/driver/rmt.c

@@ -413,28 +413,9 @@ esp_err_t rmt_set_rx_filter(rmt_channel_t channel, bool rx_filter_en, uint8_t th
 esp_err_t rmt_set_source_clk(rmt_channel_t channel, rmt_source_clk_t base_clk)
 {
     ESP_RETURN_ON_FALSE(channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
-    ESP_RETURN_ON_FALSE(base_clk < RMT_BASECLK_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_BASECLK_ERROR_STR);
-    rmt_clock_source_t rmt_clk_src = RMT_CLK_SRC_APB;
     RMT_ENTER_CRITICAL();
-    // the clock type might be different to the one used in LL driver, so simply do a translation here
-    switch (base_clk) {
-    case RMT_BASECLK_APB:
-        rmt_clk_src = RMT_CLK_SRC_APB;
-        break;
-#if SOC_RMT_SUPPORT_REF_TICK
-    case RMT_BASECLK_REF:
-        rmt_clk_src = RMT_CLK_SRC_REFTICK;
-        break;
-#endif
-#if SOC_RMT_SUPPORT_XTAL
-    case RMT_BASECLK_XTAL:
-        rmt_clk_src = RMT_CLK_SRC_XTAL;
-        break;
-#endif
-    default:
-        break;
-    }
-    rmt_ll_set_group_clock_src(rmt_contex.hal.regs, channel, rmt_clk_src, 1, 0, 0);
+    // `rmt_clock_source_t` and `rmt_source_clk_t` are binary competible, as the underlying enum entries come from the same `soc_module_clk_t`
+    rmt_ll_set_group_clock_src(rmt_contex.hal.regs, channel, (rmt_clock_source_t)base_clk, 1, 0, 0);
     RMT_EXIT_CRITICAL();
     return ESP_OK;
 }
@@ -443,24 +424,8 @@ esp_err_t rmt_get_source_clk(rmt_channel_t channel, rmt_source_clk_t *src_clk)
 {
     ESP_RETURN_ON_FALSE(channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
     RMT_ENTER_CRITICAL();
+    // `rmt_clock_source_t` and `rmt_source_clk_t` are binary competible, as the underlying enum entries come from the same `soc_module_clk_t`
     *src_clk = (rmt_source_clk_t)rmt_ll_get_group_clock_src(rmt_contex.hal.regs, channel);
-    switch (rmt_ll_get_group_clock_src(rmt_contex.hal.regs, channel)) {
-    case RMT_CLK_SRC_APB:
-        *src_clk = RMT_BASECLK_APB;
-        break;
-#if SOC_RMT_SUPPORT_REF_TICK
-    case RMT_CLK_SRC_REFTICK:
-        *src_clk = RMT_BASECLK_REF;
-        break;
-#endif
-#if SOC_RMT_SUPPORT_XTAL
-    case RMT_CLK_SRC_XTAL:
-        *src_clk = RMT_BASECLK_XTAL;
-        break;
-#endif
-    default:
-        break;
-    }
     RMT_EXIT_CRITICAL();
     return ESP_OK;
 }
@@ -600,19 +565,20 @@ static esp_err_t rmt_internal_config(rmt_dev_t *dev, const rmt_config_t *rmt_par
     rmt_ll_enable_mem_access_nonfifo(dev, true);
 
     if (rmt_param->flags & RMT_CHANNEL_FLAGS_AWARE_DFS) {
+        // [clk_tree] TODO: refactor the following code by clk_tree API
 #if SOC_RMT_SUPPORT_XTAL
         // clock src: XTAL_CLK
         rmt_source_clk_hz = esp_clk_xtal_freq();
-        rmt_ll_set_group_clock_src(dev, channel, RMT_CLK_SRC_XTAL, 1, 0, 0);
+        rmt_ll_set_group_clock_src(dev, channel, (rmt_clock_source_t)RMT_BASECLK_XTAL, 1, 0, 0);
 #elif SOC_RMT_SUPPORT_REF_TICK
         // clock src: REF_CLK
         rmt_source_clk_hz = REF_CLK_FREQ;
-        rmt_ll_set_group_clock_src(dev, channel, RMT_CLK_SRC_REFTICK, 1, 0, 0);
+        rmt_ll_set_group_clock_src(dev, channel, (rmt_clock_source_t)RMT_BASECLK_REF, 1, 0, 0);
 #endif
     } else {
-        // clock src: APB_CLK
+        // fallback to use default clock source
         rmt_source_clk_hz = APB_CLK_FREQ;
-        rmt_ll_set_group_clock_src(dev, channel, RMT_CLK_SRC_APB, 1, 0, 0);
+        rmt_ll_set_group_clock_src(dev, channel, (rmt_clock_source_t)RMT_BASECLK_DEFAULT, 1, 0, 0);
     }
     RMT_EXIT_CRITICAL();
 

components/driver/test_apps/gptimer/main/test_gptimer.c

@@ -22,7 +22,7 @@
 TEST_CASE("gptimer_set_get_raw_count", "[gptimer]")
 {
     gptimer_config_t config = {
-        .clk_src = GPTIMER_CLK_SRC_APB,
+        .clk_src = GPTIMER_CLK_SRC_DEFAULT,
         .direction = GPTIMER_COUNT_UP,
         .resolution_hz = 1 * 1000 * 1000,
     };
@@ -59,12 +59,7 @@ TEST_CASE("gptimer_set_get_raw_count", "[gptimer]")
 
 TEST_CASE("gptimer_wallclock_with_various_clock_sources", "[gptimer]")
 {
-    gptimer_clock_source_t test_clk_srcs[] = {
-        GPTIMER_CLK_SRC_APB,
-#if SOC_TIMER_GROUP_SUPPORT_XTAL
-        GPTIMER_CLK_SRC_XTAL,
-#endif // SOC_TIMER_GROUP_SUPPORT_XTAL
-    };
+    gptimer_clock_source_t test_clk_srcs[] = SOC_GPTIMER_CLKS;
 
     // test with various clock sources
     for (size_t i = 0; i < sizeof(test_clk_srcs) / sizeof(test_clk_srcs[0]); i++) {
@@ -136,7 +131,7 @@ TEST_CASE("gptimer_stop_on_alarm", "[gptimer]")
 
     gptimer_config_t timer_config = {
         .resolution_hz = 1 * 1000 * 1000,
-        .clk_src = GPTIMER_CLK_SRC_APB,
+        .clk_src = GPTIMER_CLK_SRC_DEFAULT,
         .direction = GPTIMER_COUNT_UP,
     };
     gptimer_handle_t timers[SOC_TIMER_GROUP_TOTAL_TIMERS];
@@ -210,7 +205,7 @@ TEST_CASE("gptimer_auto_reload_on_alarm", "[gptimer]")
 
     gptimer_config_t timer_config = {
         .resolution_hz = 1 * 1000 * 1000,
-        .clk_src = GPTIMER_CLK_SRC_APB,
+        .clk_src = GPTIMER_CLK_SRC_DEFAULT,
         .direction = GPTIMER_COUNT_UP,
     };
     gptimer_handle_t timers[SOC_TIMER_GROUP_TOTAL_TIMERS];
@@ -261,7 +256,7 @@ TEST_CASE("gptimer_one_shot_alarm", "[gptimer]")
 
     gptimer_config_t timer_config = {
         .resolution_hz = 1 * 1000 * 1000,
-        .clk_src = GPTIMER_CLK_SRC_APB,
+        .clk_src = GPTIMER_CLK_SRC_DEFAULT,
         .direction = GPTIMER_COUNT_UP,
     };
     gptimer_handle_t timers[SOC_TIMER_GROUP_TOTAL_TIMERS];
@@ -324,7 +319,7 @@ TEST_CASE("gptimer_update_alarm_dynamically", "[gptimer]")
 
     gptimer_config_t timer_config = {
         .resolution_hz = 1 * 1000 * 1000,
-        .clk_src = GPTIMER_CLK_SRC_APB,
+        .clk_src = GPTIMER_CLK_SRC_DEFAULT,
         .direction = GPTIMER_COUNT_UP,
     };
     gptimer_handle_t timers[SOC_TIMER_GROUP_TOTAL_TIMERS];
@@ -386,7 +381,7 @@ TEST_CASE("gptimer_count_down_reload", "[gptimer]")
 
     gptimer_config_t timer_config = {
         .resolution_hz = 1 * 1000 * 1000,
-        .clk_src = GPTIMER_CLK_SRC_APB,
+        .clk_src = GPTIMER_CLK_SRC_DEFAULT,
         .direction = GPTIMER_COUNT_DOWN,
     };
     gptimer_handle_t timers[SOC_TIMER_GROUP_TOTAL_TIMERS];
@@ -444,7 +439,7 @@ TEST_CASE("gptimer_overflow", "[gptimer]")
 
     gptimer_config_t timer_config = {
         .resolution_hz = 1 * 1000 * 1000,
-        .clk_src = GPTIMER_CLK_SRC_APB,
+        .clk_src = GPTIMER_CLK_SRC_DEFAULT,
         .direction = GPTIMER_COUNT_UP,
     };
     gptimer_handle_t timers[SOC_TIMER_GROUP_TOTAL_TIMERS];

components/driver/test_apps/gptimer/main/test_gptimer_iram.c

@@ -69,7 +69,7 @@ TEST_CASE("gptimer_iram_interrupt_safe", "[gptimer]")
     };
 
     gptimer_config_t timer_config = {
-        .clk_src = GPTIMER_CLK_SRC_APB,
+        .clk_src = GPTIMER_CLK_SRC_DEFAULT,
         .direction = GPTIMER_COUNT_UP,
         .resolution_hz = 1 * 1000 * 1000,
     };

components/driver/test_apps/legacy_timer_driver/main/test_legacy_timer.c

@@ -298,7 +298,7 @@ TEST_CASE("Timer_init", "[hw_timer]")
 
     // lack one parameter
     timer_config_t config2 = {
-        .clk_src = TIMER_SRC_CLK_APB,
+        .clk_src = TIMER_SRC_CLK_DEFAULT,
         .divider = APB_CLK_FREQ / TEST_TIMER_RESOLUTION_HZ,
         .auto_reload = TIMER_AUTORELOAD_EN,
         .counter_dir = TIMER_COUNT_UP,
@@ -313,7 +313,7 @@ TEST_CASE("Timer_init", "[hw_timer]")
     // Test init 2:  init
     uint64_t set_timer_val = 0x0;
     timer_config_t config = {
-        .clk_src = TIMER_SRC_CLK_APB,
+        .clk_src = TIMER_SRC_CLK_DEFAULT,
         .divider = APB_CLK_FREQ / TEST_TIMER_RESOLUTION_HZ,
         .alarm_en = TIMER_ALARM_DIS,
         .auto_reload = TIMER_AUTORELOAD_EN,
@@ -355,7 +355,7 @@ TEST_CASE("Timer_init", "[hw_timer]")
 TEST_CASE("Timer_read_counter_value", "[hw_timer]")
 {
     timer_config_t config = {
-        .clk_src = TIMER_SRC_CLK_APB,
+        .clk_src = TIMER_SRC_CLK_DEFAULT,
         .divider = APB_CLK_FREQ / TEST_TIMER_RESOLUTION_HZ,
         .alarm_en = TIMER_ALARM_EN,
         .auto_reload = TIMER_AUTORELOAD_EN,
@@ -395,7 +395,7 @@ TEST_CASE("Timer_read_counter_value", "[hw_timer]")
 TEST_CASE("Timer_start", "[hw_timer]")
 {
     timer_config_t config = {
-        .clk_src = TIMER_SRC_CLK_APB,
+        .clk_src = TIMER_SRC_CLK_DEFAULT,
         .divider = APB_CLK_FREQ / TEST_TIMER_RESOLUTION_HZ,
         .alarm_en = TIMER_ALARM_EN,
         .auto_reload = TIMER_AUTORELOAD_EN,
@@ -427,7 +427,7 @@ TEST_CASE("Timer_start", "[hw_timer]")
 TEST_CASE("Timer_pause", "[hw_timer]")
 {
     timer_config_t config = {
-        .clk_src = TIMER_SRC_CLK_APB,
+        .clk_src = TIMER_SRC_CLK_DEFAULT,
         .divider = APB_CLK_FREQ / TEST_TIMER_RESOLUTION_HZ,
         .alarm_en = TIMER_ALARM_EN,
         .auto_reload = TIMER_AUTORELOAD_EN,
@@ -455,7 +455,7 @@ TEST_CASE("Timer_pause", "[hw_timer]")
 TEST_CASE("Timer_counter_direction", "[hw_timer]")
 {
     timer_config_t config = {
-        .clk_src = TIMER_SRC_CLK_APB,
+        .clk_src = TIMER_SRC_CLK_DEFAULT,
         .divider = APB_CLK_FREQ / TEST_TIMER_RESOLUTION_HZ,
         .alarm_en = TIMER_ALARM_EN,
         .auto_reload = TIMER_AUTORELOAD_EN,
@@ -492,7 +492,7 @@ TEST_CASE("Timer_counter_direction", "[hw_timer]")
 TEST_CASE("Timer_divider", "[hw_timer]")
 {
     timer_config_t config = {
-        .clk_src = TIMER_SRC_CLK_APB,
+        .clk_src = TIMER_SRC_CLK_DEFAULT,
         .divider = APB_CLK_FREQ / TEST_TIMER_RESOLUTION_HZ,
         .alarm_en = TIMER_ALARM_EN,
         .auto_reload = TIMER_AUTORELOAD_EN,
@@ -568,7 +568,7 @@ TEST_CASE("Timer_divider", "[hw_timer]")
 TEST_CASE("Timer_enable_alarm", "[hw_timer]")
 {
     timer_config_t config_test = {
-        .clk_src = TIMER_SRC_CLK_APB,
+        .clk_src = TIMER_SRC_CLK_DEFAULT,
         .divider = APB_CLK_FREQ / TEST_TIMER_RESOLUTION_HZ,
         .alarm_en = TIMER_ALARM_DIS,
         .auto_reload = TIMER_AUTORELOAD_DIS,
@@ -621,7 +621,7 @@ TEST_CASE("Timer_set_alarm_value", "[hw_timer]")
 {
     uint64_t alarm_val[SOC_TIMER_GROUP_TOTAL_TIMERS];
     timer_config_t config = {
-        .clk_src = TIMER_SRC_CLK_APB,
+        .clk_src = TIMER_SRC_CLK_DEFAULT,
         .divider = APB_CLK_FREQ / TEST_TIMER_RESOLUTION_HZ,
         .alarm_en = TIMER_ALARM_EN,
         .auto_reload = TIMER_AUTORELOAD_DIS,
@@ -658,7 +658,7 @@ TEST_CASE("Timer_set_alarm_value", "[hw_timer]")
 TEST_CASE("Timer_auto_reload", "[hw_timer]")
 {
     timer_config_t config = {
-        .clk_src = TIMER_SRC_CLK_APB,
+        .clk_src = TIMER_SRC_CLK_DEFAULT,
         .divider = APB_CLK_FREQ / TEST_TIMER_RESOLUTION_HZ,
         .alarm_en = TIMER_ALARM_EN,
         .auto_reload = TIMER_AUTORELOAD_DIS,
@@ -698,7 +698,7 @@ TEST_CASE("Timer_auto_reload", "[hw_timer]")
 TEST_CASE("Timer_enable_timer_interrupt", "[hw_timer]")
 {
     timer_config_t config = {
-        .clk_src = TIMER_SRC_CLK_APB,
+        .clk_src = TIMER_SRC_CLK_DEFAULT,
         .divider = APB_CLK_FREQ / TEST_TIMER_RESOLUTION_HZ,
         .alarm_en = TIMER_ALARM_DIS,
         .counter_dir = TIMER_COUNT_UP,
@@ -740,7 +740,7 @@ TEST_CASE("Timer_enable_timer_group_interrupt", "[hw_timer][ignore]")
     intr_handle_t isr_handle = NULL;
     alarm_flag = false;
     timer_config_t config = {
-        .clk_src = TIMER_SRC_CLK_APB,
+        .clk_src = TIMER_SRC_CLK_DEFAULT,
         .divider = APB_CLK_FREQ / TEST_TIMER_RESOLUTION_HZ,
         .alarm_en = TIMER_ALARM_EN,
         .auto_reload = TIMER_AUTORELOAD_DIS,
@@ -779,7 +779,7 @@ TEST_CASE("Timer_enable_timer_group_interrupt", "[hw_timer][ignore]")
 TEST_CASE("Timer_interrupt_register", "[hw_timer]")
 {
     timer_config_t config = {
-        .clk_src = TIMER_SRC_CLK_APB,
+        .clk_src = TIMER_SRC_CLK_DEFAULT,
         .divider = APB_CLK_FREQ / TEST_TIMER_RESOLUTION_HZ,
         .alarm_en = TIMER_ALARM_DIS,
         .auto_reload = TIMER_AUTORELOAD_DIS,
@@ -835,7 +835,7 @@ TEST_CASE("Timer_clock_source", "[hw_timer]")
 {
     // configure clock source as APB clock
     timer_config_t config = {
-        .clk_src = TIMER_SRC_CLK_APB,
+        .clk_src = TIMER_SRC_CLK_DEFAULT,
         .divider = APB_CLK_FREQ / TEST_TIMER_RESOLUTION_HZ,
         .alarm_en = TIMER_ALARM_DIS,
         .auto_reload = TIMER_AUTORELOAD_DIS,
@@ -878,7 +878,7 @@ TEST_CASE("Timer_ISR_callback", "[hw_timer]")
 {
     alarm_flag = false;
     timer_config_t config = {
-        .clk_src = TIMER_SRC_CLK_APB,
+        .clk_src = TIMER_SRC_CLK_DEFAULT,
         .divider = APB_CLK_FREQ / TEST_TIMER_RESOLUTION_HZ,
         .alarm_en = TIMER_ALARM_EN,
         .auto_reload = TIMER_AUTORELOAD_DIS,
@@ -938,7 +938,7 @@ TEST_CASE("Timer_ISR_callback", "[hw_timer]")
 TEST_CASE("Timer_init_deinit_stress_test", "[hw_timer]")
 {
     timer_config_t config = {
-        .clk_src = TIMER_SRC_CLK_APB,
+        .clk_src = TIMER_SRC_CLK_DEFAULT,
         .divider = APB_CLK_FREQ / TEST_TIMER_RESOLUTION_HZ,
         .alarm_en = TIMER_ALARM_EN,
         .auto_reload = TIMER_AUTORELOAD_EN,
@@ -961,7 +961,7 @@ static void timer_group_test_init(void)
     static const uint32_t time_ms = 100;  // Alarm value 100ms.
     static const uint32_t ste_val = time_ms * TEST_TIMER_RESOLUTION_HZ / 1000;
     timer_config_t config = {
-        .clk_src = TIMER_SRC_CLK_APB,
+        .clk_src = TIMER_SRC_CLK_DEFAULT,
         .divider = APB_CLK_FREQ / TEST_TIMER_RESOLUTION_HZ,
         .counter_dir = TIMER_COUNT_UP,
         .counter_en = TIMER_PAUSE,
@@ -991,7 +991,7 @@ TEST_CASE("Timer_check_reinitialization_sequence", "[hw_timer]")
     // 3 - deinit timer driver
     TEST_ESP_OK(timer_deinit(TIMER_GROUP_0, TIMER_0));
     timer_config_t config = {
-        .clk_src = TIMER_SRC_CLK_APB,
+        .clk_src = TIMER_SRC_CLK_DEFAULT,
         .divider = APB_CLK_FREQ / TEST_TIMER_RESOLUTION_HZ,
         .counter_dir = TIMER_COUNT_UP,
         .counter_en = TIMER_START,

components/esp_event/test/test_event.c

@@ -1987,7 +1987,7 @@ TEST_CASE("can post events from interrupt handler", "[event]")
     gptimer_handle_t gptimer = NULL;
     /* Select and initialize basic parameters of the timer */
     gptimer_config_t config = {
-        .clk_src = GPTIMER_CLK_SRC_APB,
+        .clk_src = GPTIMER_CLK_SRC_DEFAULT,
         .direction = GPTIMER_COUNT_UP,
         .resolution_hz = 1000000, // 1MHz, 1 tick = 1us
     };

components/esp_hw_support/test/test_intr_alloc.c

@@ -38,7 +38,7 @@ static void timer_test(int flags)
     intr_handle_t inth[SOC_TIMER_GROUP_TOTAL_TIMERS];
 
     gptimer_config_t config = {
-        .clk_src = GPTIMER_CLK_SRC_APB,
+        .clk_src = GPTIMER_CLK_SRC_DEFAULT,
         .direction = GPTIMER_COUNT_UP,
         .resolution_hz = 1000000,
         .flags.intr_shared = (flags & ESP_INTR_FLAG_SHARED) == ESP_INTR_FLAG_SHARED,

components/esp_lcd/test_apps/i80_lcd/main/test_i80_lcd_panel.c

@@ -26,7 +26,7 @@ TEST_CASE("i80_and_i2s_driver_co-existence", "[lcd][i2s]")
     esp_lcd_i80_bus_config_t bus_config = {
         .dc_gpio_num = TEST_LCD_DC_GPIO,
         .wr_gpio_num = TEST_LCD_PCLK_GPIO,
-        .clk_src = LCD_CLK_SRC_PLL160M,
+        .clk_src = LCD_CLK_SRC_DEFAULT,
         .data_gpio_nums = {
             TEST_LCD_DATA0_GPIO,
             TEST_LCD_DATA1_GPIO,
@@ -64,7 +64,7 @@ TEST_CASE("lcd_i80_device_swap_color_bytes", "[lcd]")
     esp_lcd_i80_bus_config_t bus_config = {
         .dc_gpio_num = TEST_LCD_DC_GPIO,
         .wr_gpio_num = TEST_LCD_PCLK_GPIO,
-        .clk_src = LCD_CLK_SRC_PLL160M,
+        .clk_src = LCD_CLK_SRC_DEFAULT,
         .data_gpio_nums = {
             TEST_LCD_DATA0_GPIO,
             TEST_LCD_DATA1_GPIO,
@@ -127,7 +127,7 @@ TEST_CASE("lcd_i80_device_clock_mode", "[lcd]")
     esp_lcd_i80_bus_config_t bus_config = {
         .dc_gpio_num = TEST_LCD_DC_GPIO,
         .wr_gpio_num = TEST_LCD_PCLK_GPIO,
-        .clk_src = LCD_CLK_SRC_PLL160M,
+        .clk_src = LCD_CLK_SRC_DEFAULT,
         .data_gpio_nums = {
             TEST_LCD_DATA0_GPIO,
             TEST_LCD_DATA1_GPIO,
@@ -187,7 +187,7 @@ TEST_CASE("lcd_i80_bus_and_device_allocation", "[lcd]")
     esp_lcd_i80_bus_config_t bus_config = {
         .dc_gpio_num = TEST_LCD_DC_GPIO,
         .wr_gpio_num = TEST_LCD_PCLK_GPIO,
-        .clk_src = LCD_CLK_SRC_PLL160M,
+        .clk_src = LCD_CLK_SRC_DEFAULT,
         .data_gpio_nums = {
             TEST_LCD_DATA0_GPIO,
             TEST_LCD_DATA1_GPIO,
@@ -232,7 +232,7 @@ TEST_CASE("lcd_i80_bus_exclusively_owned_by_one_device", "[lcd]")
     esp_lcd_i80_bus_config_t bus_config = {
         .dc_gpio_num = TEST_LCD_DC_GPIO,
         .wr_gpio_num = TEST_LCD_PCLK_GPIO,
-        .clk_src = LCD_CLK_SRC_PLL160M,
+        .clk_src = LCD_CLK_SRC_DEFAULT,
         .data_gpio_nums = {
             TEST_LCD_DATA0_GPIO,
             TEST_LCD_DATA1_GPIO,
@@ -268,7 +268,7 @@ TEST_CASE("lcd_panel_i80_io_test", "[lcd]")
     esp_lcd_i80_bus_config_t bus_config = {
         .dc_gpio_num = TEST_LCD_DC_GPIO,
         .wr_gpio_num = TEST_LCD_PCLK_GPIO,
-        .clk_src = LCD_CLK_SRC_PLL160M,
+        .clk_src = LCD_CLK_SRC_DEFAULT,
         .data_gpio_nums = {
             TEST_LCD_DATA0_GPIO,
             TEST_LCD_DATA1_GPIO,
@@ -391,7 +391,7 @@ TEST_CASE("lcd_panel_with_i80_interface_(st7789, 8bits)", "[lcd]")
     esp_lcd_i80_bus_config_t bus_config = {
         .dc_gpio_num = TEST_LCD_DC_GPIO,
         .wr_gpio_num = TEST_LCD_PCLK_GPIO,
-        .clk_src = LCD_CLK_SRC_PLL160M,
+        .clk_src = LCD_CLK_SRC_DEFAULT,
         .data_gpio_nums = {
             TEST_LCD_DATA0_GPIO,
             TEST_LCD_DATA1_GPIO,

components/esp_lcd/test_apps/rgb_lcd/main/test_rgb_panel.c

@@ -29,7 +29,7 @@ static esp_lcd_panel_handle_t test_rgb_panel_initialization(bool stream_mode, es
     esp_lcd_rgb_panel_config_t panel_config = {
         .data_width = 16,
         .psram_trans_align = 64,
-        .clk_src = LCD_CLK_SRC_PLL160M,
+        .clk_src = LCD_CLK_SRC_DEFAULT,
         .disp_gpio_num = TEST_LCD_DISP_EN_GPIO,
         .pclk_gpio_num = TEST_LCD_PCLK_GPIO,
         .vsync_gpio_num = TEST_LCD_VSYNC_GPIO,

components/esp_pm/test/test_pm.c

@@ -134,7 +134,7 @@ TEST_CASE("Automatic light occurs when tasks are suspended", "[pm]")
      * It will stop working while in light sleep.
      */
     gptimer_config_t config = {
-        .clk_src = GPTIMER_CLK_SRC_APB,
+        .clk_src = GPTIMER_CLK_SRC_DEFAULT,
         .direction = GPTIMER_COUNT_UP,
         .resolution_hz = 1000000, /* 1 us per tick */
     };

components/esp_ringbuf/test/test_ringbuf.c

@@ -764,7 +764,7 @@ TEST_CASE("Test ring buffer ISR", "[esp_ringbuf]")
 
     //Setup timer for ISR
     gptimer_config_t config = {
-        .clk_src = GPTIMER_CLK_SRC_APB,
+        .clk_src = GPTIMER_CLK_SRC_DEFAULT,
         .direction = GPTIMER_COUNT_UP,
         .resolution_hz = 1000000,
     };

components/freertos/test/test_freertos_eventgroups.c

@@ -1,3 +1,8 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 #include <stdio.h>
 
 #include "freertos/FreeRTOS.h"
@@ -157,7 +162,7 @@ TEST_CASE("FreeRTOS Event Group ISR", "[freertos]")
     test_clear_bits = false;
     //Setup timer for ISR
     gptimer_config_t config = {
-        .clk_src = GPTIMER_CLK_SRC_APB,
+        .clk_src = GPTIMER_CLK_SRC_DEFAULT,
         .direction = GPTIMER_COUNT_UP,
         .resolution_hz = 1000000,
     };

components/freertos/test/test_freertos_task_notify.c

@@ -1,3 +1,8 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 /*
  Test of FreeRTOS task notifications. This test creates a sender and receiver
  task under different core permutations. For each permutation, the sender task
@@ -133,7 +138,7 @@ static void install_gptimer_on_core(void *arg)
 {
     int core_id = (int)arg;
     gptimer_config_t timer_config = {
-        .clk_src = GPTIMER_CLK_SRC_APB,
+        .clk_src = GPTIMER_CLK_SRC_DEFAULT,
         .direction = GPTIMER_COUNT_UP,
         .resolution_hz = 1000000, // 1MHz, 1 tick = 1us
     };

components/freertos/test/test_suspend_scheduler.c

@@ -71,7 +71,7 @@ TEST_CASE("Scheduler disabled can handle a pending context switch on resume", "[
                             &counter_task, UNITY_FREERTOS_CPU);
 
     gptimer_config_t timer_config = {
-        .clk_src = GPTIMER_CLK_SRC_APB,
+        .clk_src = GPTIMER_CLK_SRC_DEFAULT,
         .direction = GPTIMER_COUNT_UP,
         .resolution_hz = 1000000, // 1MHz, 1 tick=1us
     };

components/freertos/test/test_task_suspend_resume.c

@@ -155,7 +155,7 @@ static void test_resume_task_from_isr(int target_core)
 
     /* Configure timer ISR */
     gptimer_config_t timer_config = {
-        .clk_src = GPTIMER_CLK_SRC_APB,
+        .clk_src = GPTIMER_CLK_SRC_DEFAULT,
         .direction = GPTIMER_COUNT_UP,
         .resolution_hz = 1000000, // 1MHz, 1 tick = 1us
     };

components/hal/esp32/include/hal/rmt_ll.h

@@ -90,7 +90,7 @@ static inline void rmt_ll_set_group_clock_src(rmt_dev_t *dev, uint32_t channel,
     case RMT_CLK_SRC_APB:
         dev->conf_ch[channel].conf1.ref_always_on = 1;
         break;
-    case RMT_CLK_SRC_REFTICK:
+    case RMT_CLK_SRC_APB_F1M:
         dev->conf_ch[channel].conf1.ref_always_on = 0;
         break;
     default:
@@ -526,7 +526,7 @@ static inline rmt_clock_source_t rmt_ll_get_group_clock_src(rmt_dev_t *dev, uint
     if (dev->conf_ch[channel].conf1.ref_always_on) {
         return RMT_CLK_SRC_APB;
     }
-    return RMT_CLK_SRC_REFTICK;
+    return RMT_CLK_SRC_APB_F1M;
 }
 
 static inline bool rmt_ll_tx_is_idle_enabled(rmt_dev_t *dev, uint32_t channel)

components/hal/esp32c2/include/hal/timer_ll.h

@@ -32,7 +32,7 @@ extern "C" {
 static inline void timer_ll_set_clock_source(timg_dev_t *hw, uint32_t timer_num, gptimer_clock_source_t clk_src)
 {
     switch (clk_src) {
-    case GPTIMER_CLK_SRC_APB:
+    case GPTIMER_CLK_SRC_PLL_F40M:
         hw->hw_timer[timer_num].config.tx_use_xtal = 0;
         break;
     case GPTIMER_CLK_SRC_XTAL:

components/hal/esp32c3/include/hal/temperature_sensor_ll.h

@@ -22,6 +22,8 @@
 #include "soc/soc.h"
 #include "soc/soc_caps.h"
 #include "hal/temperature_sensor_types.h"
+#include "hal/assert.h"
+
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -77,7 +79,6 @@ static inline void temperature_sensor_ll_clk_sel(temperature_sensor_clk_src_t cl
 {
     uint8_t clk_sel = 0;
     switch (clk_src) {
-        case TEMPERATURE_SENSOR_CLK_SRC_DEFAULT:
         case TEMPERATURE_SENSOR_CLK_SRC_XTAL:
             clk_sel = 1;
             break;
@@ -85,7 +86,7 @@ static inline void temperature_sensor_ll_clk_sel(temperature_sensor_clk_src_t cl
             clk_sel = 0;
             break;
         default:
-            abort();
+            HAL_ASSERT(false);
             break;
     }
     APB_SARADC.apb_tsens_ctrl2.tsens_clk_sel = clk_sel;

components/hal/esp32h2/include/hal/rmt_ll.h

@@ -95,7 +95,7 @@ static inline void rmt_ll_set_group_clock_src(rmt_dev_t *dev, uint32_t channel,
     dev->sys_conf.sclk_div_a = divider_numerator;
     dev->sys_conf.sclk_div_b = divider_denominator;
     switch (src) {
-    case RMT_CLK_SRC_APB:
+    case RMT_CLK_SRC_AHB:
         dev->sys_conf.sclk_sel = 1;
         break;
     case RMT_CLK_SRC_RC_FAST:
@@ -701,10 +701,10 @@ static inline bool rmt_ll_tx_is_loop_enabled(rmt_dev_t *dev, uint32_t channel)
 
 static inline rmt_clock_source_t rmt_ll_get_group_clock_src(rmt_dev_t *dev, uint32_t channel)
 {
-    rmt_clock_source_t clk_src = RMT_CLK_SRC_APB;
+    rmt_clock_source_t clk_src = RMT_CLK_SRC_AHB;
     switch (dev->sys_conf.sclk_sel) {
     case 1:
-        clk_src = RMT_CLK_SRC_APB;
+        clk_src = RMT_CLK_SRC_AHB;
         break;
     case 2:
         clk_src = RMT_CLK_SRC_RC_FAST;

components/hal/esp32h2/include/hal/temperature_sensor_ll.h

@@ -22,6 +22,7 @@
 #include "soc/soc.h"
 #include "soc/soc_caps.h"
 #include "hal/temperature_sensor_types.h"
+#include "hal/assert.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -78,7 +79,6 @@ static inline void temperature_sensor_ll_clk_sel(temperature_sensor_clk_src_t cl
 {
     uint8_t clk_sel = 0;
     switch (clk_src) {
-        case TEMPERATURE_SENSOR_CLK_SRC_DEFAULT:
         case TEMPERATURE_SENSOR_CLK_SRC_XTAL:
             clk_sel = 1;
             break;
@@ -86,7 +86,7 @@ static inline void temperature_sensor_ll_clk_sel(temperature_sensor_clk_src_t cl
             clk_sel = 0;
             break;
         default:
-            abort();
+            HAL_ASSERT(false);
             break;
     }
     APB_SARADC.apb_tsens_ctrl2.tsens_clk_sel = clk_sel;

components/hal/esp32h2/include/hal/timer_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -32,7 +32,7 @@ extern "C" {
 static inline void timer_ll_set_clock_source(timg_dev_t *hw, uint32_t timer_num, gptimer_clock_source_t clk_src)
 {
     switch (clk_src) {
-    case GPTIMER_CLK_SRC_APB:
+    case GPTIMER_CLK_SRC_AHB:
         hw->hw_timer[timer_num].config.tx_use_xtal = 0;
         break;
     case GPTIMER_CLK_SRC_XTAL:

components/hal/esp32s2/include/hal/rmt_ll.h

@@ -95,7 +95,7 @@ static inline void rmt_ll_set_group_clock_src(rmt_dev_t *dev, uint32_t channel,
     case RMT_CLK_SRC_APB:
         dev->conf_ch[channel].conf1.ref_always_on = 1;
         break;
-    case RMT_CLK_SRC_REFTICK:
+    case RMT_CLK_SRC_APB_F1M:
         dev->conf_ch[channel].conf1.ref_always_on = 0;
         break;
     default:
@@ -667,7 +667,7 @@ static inline rmt_clock_source_t rmt_ll_get_group_clock_src(rmt_dev_t *dev, uint
     if (dev->conf_ch[channel].conf1.ref_always_on) {
         return RMT_CLK_SRC_APB;
     }
-    return RMT_CLK_SRC_REFTICK;
+    return RMT_CLK_SRC_APB_F1M;
 }
 
 static inline bool rmt_ll_tx_is_idle_enabled(rmt_dev_t *dev, uint32_t channel)

components/hal/include/hal/timer_types.h

@@ -14,6 +14,7 @@ extern "C" {
 
 /**
  * @brief GPTimer clock source
+ * @note User should select the clock source based on the power and resolution requirement
  */
 typedef soc_periph_gptimer_clk_src_t gptimer_clock_source_t;
 

components/soc/esp32/include/soc/Kconfig.soc_caps.in

@@ -495,6 +495,10 @@ config SOC_TIMER_GROUP_TOTAL_TIMERS
     int
     default 4
 
+config SOC_TIMER_GROUP_SUPPORT_APB
+    bool
+    default y
+
 config SOC_TOUCH_VERSION_1
     bool
     default y

components/soc/esp32/include/soc/clk_tree_defs.h

@@ -89,6 +89,7 @@ typedef enum {
  * Naming convention: SOC_MOD_CLK_{<upstream>clock_name}_<attr>
  * {<upstream>clock_name}: APB, APLL, (BB)PLL, etc.
  * <attr> - optional: FAST, SLOW, D<divider>, F<freq>
+ * @note enum starts from 1, to save 0 for special purpose
  */
 typedef enum {
     // For CPU domain
@@ -108,26 +109,86 @@ typedef enum {
 } soc_module_clk_t;
 
 
-// List clock sources available to each peripherial
-// soc_module_clk_src_t enum starts from 1 to save enum = 0 for AUTO selection
+//////////////////////////////////////////////////GPTimer///////////////////////////////////////////////////////////////
 
+/**
+ * @brief Array initializer for all supported clock sources of GPTimer
+ * The following code can be used to iterate all possible clocks:
+ * @code{c}
+ * soc_periph_gptimer_clk_src_t gptimer_clks[] = (soc_periph_gptimer_clk_src_t)SOC_GPTIMER_CLKS;
+ * for (size_t i = 0; i< sizeof(gptimer_clks) / sizeof(gptimer_clks[0]); i++) {
+ *     soc_periph_gptimer_clk_src_t clk = gptimer_clks[i];
+ *     // Test GPTimer with the clock `clk`
+ * }
+ * @endcode
+ */
+#define SOC_GPTIMER_CLKS {SOC_MOD_CLK_APB}
+
+/**
+ * @brief Type of GPTimer clock source
+ */
 typedef enum {
-    GPTIMER_CLK_SRC_APB = SOC_MOD_CLK_APB,                      /*!< Select APB as the source clock */
+    GPTIMER_CLK_SRC_APB = SOC_MOD_CLK_APB,     /*!< Select APB as the source clock */
+    GPTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB as the default choice */
 } soc_periph_gptimer_clk_src_t;
 
+/**
+ * @brief Type of Timer Group clock source, reserved for the legacy timer group driver
+ */
+typedef enum {
+    TIMER_SRC_CLK_APB = SOC_MOD_CLK_APB,     /*!< Timer group source clock is APB */
+    TIMER_SRC_CLK_DEFAULT = SOC_MOD_CLK_APB, /*!< Timer group source clock default choice is APB */
+} soc_periph_tg_clk_src_legacy_t;
+
+//////////////////////////////////////////////////LCD///////////////////////////////////////////////////////////////////
+
+/**
+ * @brief Array initializer for all supported clock sources of LCD
+ */
+#define SOC_LCD_CLKS {SOC_MOD_CLK_PLL_D2, SOC_MOD_CLK_APLL, SOC_MOD_CLK_XTAL}
+
+/**
+ * @brief Type of LCD clock source
+ */
 typedef enum {
-    LCD_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_D2,                   /*!< Select PLL_D2 (160MHz) as the source clock */
-    LCD_CLK_SRC_APLL = SOC_MOD_CLK_APLL,                        /*!< Select APLL as the source clock */
-    LCD_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,                        /*!< Select XTAL as the source clock */
+    LCD_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_D2, /*!< Select PLL_D2 (default to 160MHz) as the source clock */
+    LCD_CLK_SRC_APLL = SOC_MOD_CLK_APLL,      /*!< Select APLL as the source clock */
+    LCD_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,      /*!< Select XTAL as the source clock */
+    LCD_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_D2, /*!< Select PLL_D2 (default to 160MHz) as the default choice */
 } soc_periph_lcd_clk_src_t;
 
+//////////////////////////////////////////////////RMT///////////////////////////////////////////////////////////////////
+
+/**
+ * @brief Array initializer for all supported clock sources of RMT
+ */
+#define SOC_RMT_CLKS {SOC_MOD_CLK_APB, SOC_MOD_CLK_APB_F1M}
+
+/**
+ * @brief Type of RMT clock source
+ */
 typedef enum {
-    RMT_CLK_SRC_NONE = 0,                                       /*!< No clock source is selected */
-    RMT_CLK_SRC_REFTICK = SOC_MOD_CLK_APB_F1M,                  /*!< Select REF_TICK (1MHz) as the source clock */
-    RMT_CLK_SRC_APB = SOC_MOD_CLK_APB,                          /*!< Select APB as the source clock */
+    RMT_CLK_SRC_NONE = 0,                      /*!< No clock source is selected */
+    RMT_CLK_SRC_APB = SOC_MOD_CLK_APB,         /*!< Select APB as the source clock */
+    RMT_CLK_SRC_APB_F1M = SOC_MOD_CLK_APB_F1M, /*!< Select APB_F1M (a.k.a REF_TICK) as the source clock */
+    RMT_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB,     /*!< Select APB as the default choice */
 } soc_periph_rmt_clk_src_t;
 
-// ESP32 does not support temperature sensor, it is only to pass ci check_public_headers
+/**
+ * @brief Type of RMT clock source, reserved for the legacy RMT driver
+ */
+typedef enum {
+    RMT_BASECLK_APB = SOC_MOD_CLK_APB,     /*!< RMT source clock is APB CLK */
+    RMT_BASECLK_REF = SOC_MOD_CLK_APB_F1M, /*!< RMT source clock is APB_F1M */
+    RMT_BASECLK_DEFAULT = SOC_MOD_CLK_APB, /*!< RMT source clock default choice is APB */
+} soc_periph_rmt_clk_src_legacy_t;
+
+//////////////////////////////////////////////////Temp Sensor///////////////////////////////////////////////////////////
+
+/**
+ * @brief Type of Temp Sensor clock source
+ * @note ESP32 does not support temperature sensor
+ */
 typedef enum {
     TEMPERATURE_SENSOR_SRC_NA,
 } soc_periph_temperature_sensor_clk_src_t;

components/soc/esp32/include/soc/soc_caps.h

@@ -270,6 +270,7 @@
 #define SOC_TIMER_GROUP_TIMERS_PER_GROUP  (2)
 #define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (64)
 #define SOC_TIMER_GROUP_TOTAL_TIMERS      (4)
+#define SOC_TIMER_GROUP_SUPPORT_APB       (1)
 
 /*-------------------------- TOUCH SENSOR CAPS -------------------------------*/
 #define SOC_TOUCH_VERSION_1                 (1)     /*!<Hardware version of touch sensor */

components/soc/esp32c2/include/soc/Kconfig.soc_caps.in

@@ -415,6 +415,10 @@ config SOC_TIMER_GROUP_SUPPORT_XTAL
     bool
     default y
 
+config SOC_TIMER_GROUP_SUPPORT_PLL_F40M
+    bool
+    default y
+
 config SOC_TIMER_GROUP_TOTAL_TIMERS
     int
     default 1

components/soc/esp32c2/include/soc/clk_tree_defs.h

@@ -87,6 +87,7 @@ typedef enum {
  * Naming convention: SOC_MOD_CLK_{<upstream>clock_name}_<attr>
  * {<upstream>clock_name}: (BB)PLL etc.
  * <attr> - optional: FAST, SLOW, D<divider>, F<freq>
+ * @note enum starts from 1, to save 0 for special purpose
  */
 typedef enum {
     // For CPU domain
@@ -105,18 +106,53 @@ typedef enum {
 } soc_module_clk_t;
 
 
-// List clock sources available to each peripherial
-// soc_module_clk_src_t enum starts from 1 to save enum = 0 for AUTO selection
+//////////////////////////////////////////////////GPTimer///////////////////////////////////////////////////////////////
 
+/**
+ * @brief Array initializer for all supported clock sources of GPTimer
+ * The following code can be used to iterate all possible clocks:
+ * @code{c}
+ * soc_periph_gptimer_clk_src_t gptimer_clks[] = (soc_periph_gptimer_clk_src_t)SOC_GPTIMER_CLKS;
+ * for (size_t i = 0; i< sizeof(gptimer_clks) / sizeof(gptimer_clks[0]); i++) {
+ *     soc_periph_gptimer_clk_src_t clk = gptimer_clks[i];
+ *     // Test GPTimer with the clock `clk`
+ * }
+ * @endcode
+ */
+#define SOC_GPTIMER_CLKS {SOC_MOD_CLK_PLL_F40M, SOC_MOD_CLK_XTAL}
+
+/**
+ * @brief Type of GPTimer clock source
+ */
 typedef enum {
-    GPTIMER_CLK_SRC_APB = SOC_MOD_CLK_PLL_F40M,                      /*!< Select APB as the source clock */
-    GPTIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,                         /*!< Select XTAL as the source clock */
+    GPTIMER_CLK_SRC_PLL_F40M = SOC_MOD_CLK_PLL_F40M, /*!< Select PLL_F40M as the source clock */
+    GPTIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,         /*!< Select XTAL as the source clock */
+    GPTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F40M,  /*!< Select PLL_F40M as the default choice */
 } soc_periph_gptimer_clk_src_t;
 
+/**
+ * @brief Type of Timer Group clock source, reserved for the legacy timer group driver
+ */
+typedef enum {
+    TIMER_SRC_CLK_PLL_F40M = SOC_MOD_CLK_PLL_F40M, /*!< Timer group clock source is PLL_F40M */
+    TIMER_SRC_CLK_XTAL = SOC_MOD_CLK_XTAL,         /*!< Timer group clock source is XTAL */
+    TIMER_SRC_CLK_DEFAULT = SOC_MOD_CLK_PLL_F40M,  /*!< Timer group clock source default choice is PLL_F40M */
+} soc_periph_tg_clk_src_legacy_t;
+
+//////////////////////////////////////////////////Temp Sensor///////////////////////////////////////////////////////////
+
+/**
+ * @brief Array initializer for all supported clock sources of Temperature Sensor
+ */
+#define SOC_TEMP_SENSOR_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST}
+
+/**
+ * @brief Type of Temp Sensor clock source
+ */
 typedef enum {
-    TEMPERATURE_SENSOR_CLK_SRC_DEFAULT = 0,                          /*!< Use default clock selection */
-    TEMPERATURE_SENSOR_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,              /*!< Select XTAL as the source clock */
-    TEMPERATURE_SENSOR_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST,        /*!< Select RC_FAST as the source clock */
+    TEMPERATURE_SENSOR_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,       /*!< Select XTAL as the source clock */
+    TEMPERATURE_SENSOR_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
+    TEMPERATURE_SENSOR_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL,    /*!< Select XTAL as the default choice */
 } soc_periph_temperature_sensor_clk_src_t;
 
 #ifdef __cplusplus

components/soc/esp32c2/include/soc/soc_caps.h

@@ -218,6 +218,7 @@
 #define SOC_TIMER_GROUP_TIMERS_PER_GROUP  (1U)
 #define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (54)
 #define SOC_TIMER_GROUP_SUPPORT_XTAL      (1)
+#define SOC_TIMER_GROUP_SUPPORT_PLL_F40M  (1)
 #define SOC_TIMER_GROUP_TOTAL_TIMERS      (1U)
 
 /*-------------------------- TOUCH SENSOR CAPS -------------------------------*/

components/soc/esp32c3/include/soc/Kconfig.soc_caps.in

@@ -579,6 +579,10 @@ config SOC_TIMER_GROUP_SUPPORT_XTAL
     bool
     default y
 
+config SOC_TIMER_GROUP_SUPPORT_APB
+    bool
+    default y
+
 config SOC_TIMER_GROUP_TOTAL_TIMERS
     int
     default 2

components/soc/esp32c3/include/soc/clk_tree_defs.h

@@ -88,6 +88,7 @@ typedef enum {
  * Naming convention: SOC_MOD_CLK_{<upstream>clock_name}_<attr>
  * {<upstream>clock_name}: APB, (BB)PLL, etc.
  * <attr> - optional: FAST, SLOW, D<divider>, F<freq>
+ * @note enum starts from 1, to save 0 for special purpose
  */
 typedef enum {
     // For CPU domain
@@ -106,28 +107,82 @@ typedef enum {
     SOC_MOD_CLK_XTAL = 11,                     /*< XTAL_CLK comes from the external 40MHz crystal */
 } soc_module_clk_t;
 
+//////////////////////////////////////////////////GPTimer///////////////////////////////////////////////////////////////
 
-// List clock sources available to each peripherial
-// soc_module_clk_src_t enum starts from 1 to save enum = 0 for AUTO selection
+/**
+ * @brief Array initializer for all supported clock sources of GPTimer
+ * The following code can be used to iterate all possible clocks:
+ * @code{c}
+ * soc_periph_gptimer_clk_src_t gptimer_clks[] = (soc_periph_gptimer_clk_src_t)SOC_GPTIMER_CLKS;
+ * for (size_t i = 0; i< sizeof(gptimer_clks) / sizeof(gptimer_clks[0]); i++) {
+ *     soc_periph_gptimer_clk_src_t clk = gptimer_clks[i];
+ *     // Test GPTimer with the clock `clk`
+ * }
+ * @endcode
+ */
+#define SOC_GPTIMER_CLKS {SOC_MOD_CLK_APB, SOC_MOD_CLK_XTAL}
 
+/**
+ * @brief Type of GPTimer clock source
+ */
 typedef enum {
-    GPTIMER_CLK_SRC_APB = SOC_MOD_CLK_APB,                      /*!< Select APB as the source clock */
-    GPTIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,                    /*!< Select XTAL as the source clock */
+    GPTIMER_CLK_SRC_APB = SOC_MOD_CLK_APB,     /*!< Select APB as the source clock */
+    GPTIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,   /*!< Select XTAL as the source clock */
+    GPTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB as the default choice */
 } soc_periph_gptimer_clk_src_t;
 
+/**
+ * @brief Type of Timer Group clock source, reserved for the legacy timer group driver
+ */
 typedef enum {
-    TEMPERATURE_SENSOR_CLK_SRC_DEFAULT = 0,                     /*!< Use default clock selection */
-    TEMPERATURE_SENSOR_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,         /*!< Select XTAL as the source clock */
-    TEMPERATURE_SENSOR_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST,   /*!< Select RC_FAST as the source clock */
-} soc_periph_temperature_sensor_clk_src_t;
+    TIMER_SRC_CLK_APB = SOC_MOD_CLK_APB,     /*!< Timer group clock source is APB */
+    TIMER_SRC_CLK_XTAL = SOC_MOD_CLK_XTAL,   /*!< Timer group clock source is XTAL */
+    TIMER_SRC_CLK_DEFAULT = SOC_MOD_CLK_APB, /*!< Timer group clock source default choice is APB */
+} soc_periph_tg_clk_src_legacy_t;
 
+//////////////////////////////////////////////////RMT///////////////////////////////////////////////////////////////////
+
+/**
+ * @brief Array initializer for all supported clock sources of RMT
+ */
+#define SOC_RMT_CLKS {SOC_MOD_CLK_APB, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL}
+
+/**
+ * @brief Type of RMT clock source
+ */
 typedef enum {
-    RMT_CLK_SRC_NONE = 0,                                       /*!< No clock source is selected */
-    RMT_CLK_SRC_APB = SOC_MOD_CLK_APB,                          /*!< Select APB as the source clock */
-    RMT_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST,                  /*!< Select RC_FAST as the source clock */
-    RMT_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,                        /*!< Select XTAL as the source clock */
+    RMT_CLK_SRC_NONE = 0,                      /*!< No clock source is selected */
+    RMT_CLK_SRC_APB = SOC_MOD_CLK_APB,         /*!< Select APB as the source clock */
+    RMT_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
+    RMT_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,       /*!< Select XTAL as the source clock */
+    RMT_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB,     /*!< Select APB as the default choice */
 } soc_periph_rmt_clk_src_t;
 
+/**
+ * @brief Type of RMT clock source, reserved for the legacy RMT driver
+ */
+typedef enum {
+    RMT_BASECLK_APB = SOC_MOD_CLK_APB,     /*!< RMT source clock is APB */
+    RMT_BASECLK_XTAL = SOC_MOD_CLK_XTAL,   /*!< RMT source clock is XTAL */
+    RMT_BASECLK_DEFAULT = SOC_MOD_CLK_APB, /*!< RMT source clock default choice is APB */
+} soc_periph_rmt_clk_src_legacy_t;
+
+//////////////////////////////////////////////////Temp Sensor///////////////////////////////////////////////////////////
+
+/**
+ * @brief Array initializer for all supported clock sources of Temperature Sensor
+ */
+#define SOC_TEMP_SENSOR_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST}
+
+/**
+ * @brief Type of Temp Sensor clock source
+ */
+typedef enum {
+    TEMPERATURE_SENSOR_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,       /*!< Select XTAL as the source clock */
+    TEMPERATURE_SENSOR_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
+    TEMPERATURE_SENSOR_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL,    /*!< Select XTAL as the default choice */
+} soc_periph_temperature_sensor_clk_src_t;
+
 #ifdef __cplusplus
 }
 #endif

components/soc/esp32c3/include/soc/soc_caps.h

@@ -282,6 +282,7 @@
 #define SOC_TIMER_GROUP_TIMERS_PER_GROUP  (1U)
 #define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (54)
 #define SOC_TIMER_GROUP_SUPPORT_XTAL      (1)
+#define SOC_TIMER_GROUP_SUPPORT_APB       (1)
 #define SOC_TIMER_GROUP_TOTAL_TIMERS      (2)
 
 /*-------------------------- TOUCH SENSOR CAPS -------------------------------*/

components/soc/esp32h2/include/soc/Kconfig.soc_caps.in

@@ -571,6 +571,10 @@ config SOC_TIMER_GROUP_SUPPORT_XTAL
     bool
     default y
 
+config SOC_TIMER_GROUP_SUPPORT_AHB
+    bool
+    default y
+
 config SOC_TIMER_GROUP_TOTAL_TIMERS
     int
     default 2

components/soc/esp32h2/include/soc/clk_tree_defs.h

@@ -96,6 +96,7 @@ typedef enum {
  * Naming convention: SOC_MOD_CLK_{<upstream>clock_name}_<attr>
  * {<upstream>clock_name}: AHB etc.
  * <attr> - optional: FAST, SLOW, D<divider>, F<freq>
+ * @note enum starts from 1, to save 0 for special purpose
  */
 typedef enum {
     // For CPU domain
@@ -111,27 +112,82 @@ typedef enum {
 } soc_module_clk_t;
 
 
-// List clock sources available to each peripherial
-// soc_module_clk_src_t enum starts from 1 to save enum = 0 for AUTO selection
+//////////////////////////////////////////////////GPTimer///////////////////////////////////////////////////////////////
 
+/**
+ * @brief Array initializer for all supported clock sources of GPTimer
+ * The following code can be used to iterate all possible clocks:
+ * @code{c}
+ * soc_periph_gptimer_clk_src_t gptimer_clks[] = (soc_periph_gptimer_clk_src_t)SOC_GPTIMER_CLKS;
+ * for (size_t i = 0; i< sizeof(gptimer_clks) / sizeof(gptimer_clks[0]); i++) {
+ *     soc_periph_gptimer_clk_src_t clk = gptimer_clks[i];
+ *     // Test GPTimer with the clock `clk`
+ * }
+ * @endcode
+ */
+#define SOC_GPTIMER_CLKS {SOC_MOD_CLK_AHB, SOC_MOD_CLK_XTAL}
+
+/**
+ * @brief Type of GPTimer clock source
+ */
 typedef enum {
-    GPTIMER_CLK_SRC_APB = SOC_MOD_CLK_AHB,                      /*!< Select AHB as the source clock */
-    GPTIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,                    /*!< Select XTAL as the source clock */
+    GPTIMER_CLK_SRC_AHB = SOC_MOD_CLK_AHB,     /*!< Select AHB as the source clock */
+    GPTIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,   /*!< Select XTAL as the source clock */
+    GPTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_AHB, /*!< Select AHB as the default choice */
 } soc_periph_gptimer_clk_src_t;
 
+/**
+ * @brief Type of Timer Group clock source, reserved for the legacy timer group driver
+ */
 typedef enum {
-    TEMPERATURE_SENSOR_CLK_SRC_DEFAULT = 0,                     /*!< Use default clock selection */
-    TEMPERATURE_SENSOR_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,         /*!< Select XTAL as the source clock */
-    TEMPERATURE_SENSOR_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST,   /*!< Select RC_FAST as the source clock */
-} soc_periph_temperature_sensor_clk_src_t;
+    TIMER_SRC_CLK_AHB = SOC_MOD_CLK_AHB,     /*!< Timer group clock source is AHB */
+    TIMER_SRC_CLK_XTAL = SOC_MOD_CLK_XTAL,   /*!< Timer group clock source is XTAL */
+    TIMER_SRC_CLK_DEFAULT = SOC_MOD_CLK_AHB, /*!< Timer group clock source default choice is AHB */
+} soc_periph_tg_clk_src_legacy_t;
+
+//////////////////////////////////////////////////RMT///////////////////////////////////////////////////////////////////
 
+/**
+ * @brief Array initializer for all supported clock sources of RMT
+ */
+#define SOC_RMT_CLKS {SOC_MOD_CLK_AHB, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL}
+
+/**
+ * @brief Type of RMT clock source
+ */
 typedef enum {
-    RMT_CLK_SRC_NONE = 0,                                       /*!< No clock source is selected */
-    RMT_CLK_SRC_APB = SOC_MOD_CLK_AHB,                          /*!< Select AHB as the source clock */
-    RMT_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST,                  /*!< Select RC_FAST as the source clock */
-    RMT_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,                        /*!< Select XTAL as the source clock */
+    RMT_CLK_SRC_NONE = 0,                      /*!< No clock source is selected */
+    RMT_CLK_SRC_AHB = SOC_MOD_CLK_AHB,         /*!< Select AHB clock as the source clock */
+    RMT_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
+    RMT_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,       /*!< Select XTAL as the source clock */
+    RMT_CLK_SRC_DEFAULT = SOC_MOD_CLK_AHB,     /*!< Select AHB as the default choice */
 } soc_periph_rmt_clk_src_t;
 
+/**
+ * @brief Type of RMT clock source, reserved for the legacy RMT driver
+ */
+typedef enum {
+    RMT_BASECLK_AHB = SOC_MOD_CLK_AHB,     /*!< RMT source clock is AHB */
+    RMT_BASECLK_XTAL = SOC_MOD_CLK_XTAL,   /*!< RMT source clock is XTAL */
+    RMT_BASECLK_DEFAULT = SOC_MOD_CLK_AHB, /*!< RMT source clock default choice is AHB */
+} soc_periph_rmt_clk_src_legacy_t;
+
+//////////////////////////////////////////////////Temp Sensor///////////////////////////////////////////////////////////
+
+/**
+ * @brief Array initializer for all supported clock sources of Temperature Sensor
+ */
+#define SOC_TEMP_SENSOR_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST}
+
+/**
+ * @brief Type of Temp Sensor clock source
+ */
+typedef enum {
+    TEMPERATURE_SENSOR_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,       /*!< Select XTAL as the source clock */
+    TEMPERATURE_SENSOR_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
+    TEMPERATURE_SENSOR_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL,    /*!< Select XTAL as the default choice */
+} soc_periph_temperature_sensor_clk_src_t;
+
 #ifdef __cplusplus
 }
 #endif

components/soc/esp32h2/include/soc/soc_caps.h

@@ -293,6 +293,7 @@
 #define SOC_TIMER_GROUP_TIMERS_PER_GROUP  (1U)
 #define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (54)
 #define SOC_TIMER_GROUP_SUPPORT_XTAL      (1)
+#define SOC_TIMER_GROUP_SUPPORT_AHB       (1)
 #define SOC_TIMER_GROUP_TOTAL_TIMERS      (2)
 
 /*-------------------------- TOUCH SENSOR CAPS -------------------------------*/

components/soc/esp32s2/include/soc/Kconfig.soc_caps.in

@@ -571,6 +571,10 @@ config SOC_TIMER_GROUP_SUPPORT_XTAL
     bool
     default y
 
+config SOC_TIMER_GROUP_SUPPORT_APB
+    bool
+    default y
+
 config SOC_TIMER_GROUP_TOTAL_TIMERS
     int
     default 4

components/soc/esp32s2/include/soc/clk_tree_defs.h

@@ -89,6 +89,7 @@ typedef enum {
  * Naming convention: SOC_MOD_CLK_{<upstream>clock_name}_<attr>
  * {<upstream>clock_name}: APB, APLL, (BB)PLL, etc.
  * <attr> - optional: FAST, SLOW, D<divider>, F<freq>
+ * @note enum starts from 1, to save 0 for special purpose
  */
 typedef enum {
     // For CPU domain
@@ -109,31 +110,97 @@ typedef enum {
 } soc_module_clk_t;
 
 
-// List clock sources available to each peripherial
-// soc_module_clk_src_t enum starts from 1 to save enum = 0 for AUTO selection
+//////////////////////////////////////////////////GPTimer///////////////////////////////////////////////////////////////
 
+/**
+ * @brief Array initializer for all supported clock sources of GPTimer
+ * The following code can be used to iterate all possible clocks:
+ * @code{c}
+ * soc_periph_gptimer_clk_src_t gptimer_clks[] = (soc_periph_gptimer_clk_src_t)SOC_GPTIMER_CLKS;
+ * for (size_t i = 0; i< sizeof(gptimer_clks) / sizeof(gptimer_clks[0]); i++) {
+ *     soc_periph_gptimer_clk_src_t clk = gptimer_clks[i];
+ *     // Test GPTimer with the clock `clk`
+ * }
+ * @endcode
+ */
+#define SOC_GPTIMER_CLKS {SOC_MOD_CLK_APB, SOC_MOD_CLK_XTAL}
+
+/**
+ * @brief Type of GPTimer clock source
+ */
 typedef enum {
-    GPTIMER_CLK_SRC_APB = SOC_MOD_CLK_APB,                          /*!< Select APB as the source clock */
-    GPTIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,                        /*!< Select XTAL as the source clock */
+    GPTIMER_CLK_SRC_APB = SOC_MOD_CLK_APB,     /*!< Select APB as the source clock */
+    GPTIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,   /*!< Select XTAL as the source clock */
+    GPTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB as the default choice */
 } soc_periph_gptimer_clk_src_t;
 
+/**
+ * @brief Type of Timer Group clock source, reserved for the legacy timer group driver
+ */
 typedef enum {
-    TEMPERATURE_SENSOR_CLK_SRC_DEFAULT = 0,                         /*!< Use default clock selection */
-    TEMPERATURE_SENSOR_CLK_SRC_RC_FAST = SOC_MOD_CLK_TEMP_SENSOR,   /*!< Select RC_FAST as the source clock */
-} soc_periph_temperature_sensor_clk_src_t;
+    TIMER_SRC_CLK_APB = SOC_MOD_CLK_APB,     /*!< Timer group source clock is APB */
+    TIMER_SRC_CLK_XTAL = SOC_MOD_CLK_XTAL,   /*!< Timer group source clock is XTAL */
+    TIMER_SRC_CLK_DEFAULT = SOC_MOD_CLK_APB, /*!< Timer group source clock default choice is APB */
+} soc_periph_tg_clk_src_legacy_t;
+
+//////////////////////////////////////////////////LCD///////////////////////////////////////////////////////////////////
 
+/**
+ * @brief Array initializer for all supported clock sources of LCD
+ */
+#define SOC_LCD_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_APLL, SOC_MOD_CLK_XTAL}
+
+/**
+ * @brief Type of LCD clock source
+ */
 typedef enum {
-    LCD_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_F160M,                    /*!< Select PLL_F160M as the source clock */
-    LCD_CLK_SRC_APLL = SOC_MOD_CLK_APLL,                            /*!< Select APLL as the source clock */
-    LCD_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,                            /*!< Select XTAL as the source clock */
+    LCD_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */
+    LCD_CLK_SRC_APLL = SOC_MOD_CLK_APLL,         /*!< Select APLL as the source clock */
+    LCD_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,         /*!< Select XTAL as the source clock */
+    LCD_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default choice */
 } soc_periph_lcd_clk_src_t;
 
+//////////////////////////////////////////////////RMT///////////////////////////////////////////////////////////////////
+
+/**
+ * @brief Array initializer for all supported clock sources of RMT
+ */
+#define SOC_RMT_CLKS {SOC_MOD_CLK_APB, SOC_MOD_CLK_APB_F1M}
+
+/**
+ * @brief Type of RMT clock source
+ */
 typedef enum {
-    RMT_CLK_SRC_NONE = 0,                                           /*!< No clock source is selected */
-    RMT_CLK_SRC_REFTICK = SOC_MOD_CLK_APB_F1M,                      /*!< Select REF_TICK (1MHz) as the source clock */
-    RMT_CLK_SRC_APB = SOC_MOD_CLK_APB,                              /*!< Select APB as the source clock */
+    RMT_CLK_SRC_NONE = 0,                      /*!< No clock source is selected */
+    RMT_CLK_SRC_APB = SOC_MOD_CLK_APB,         /*!< Select APB as the source clock */
+    RMT_CLK_SRC_APB_F1M = SOC_MOD_CLK_APB_F1M, /*!< Select APB_F1M (a.k.a REF_TICK) as the source clock */
+    RMT_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB,     /*!< Select APB as the default choice */
 } soc_periph_rmt_clk_src_t;
 
+/**
+ * @brief Type of RMT clock source, reserved for the legacy RMT driver
+ */
+typedef enum {
+    RMT_BASECLK_APB = SOC_MOD_CLK_APB,     /*!< RMT source clock is APB CLK */
+    RMT_BASECLK_REF = SOC_MOD_CLK_APB_F1M, /*!< RMT source clock is APB_F1M */
+    RMT_BASECLK_DEFAULT = SOC_MOD_CLK_APB, /*!< RMT source clock default choice is APB */
+} soc_periph_rmt_clk_src_legacy_t;
+
+//////////////////////////////////////////////////Temp Sensor///////////////////////////////////////////////////////////
+
+/**
+ * @brief Array initializer for all supported clock sources of Temperature Sensor
+ */
+#define SOC_TEMP_SENSOR_CLKS {SOC_MOD_CLK_TEMP_SENSOR}
+
+/**
+ * @brief Type of Temp Sensor clock source
+ */
+typedef enum {
+    TEMPERATURE_SENSOR_CLK_SRC_RC_FAST = SOC_MOD_CLK_TEMP_SENSOR, /*!< Select RC_FAST as the source clock */
+    TEMPERATURE_SENSOR_CLK_SRC_DEFAULT = SOC_MOD_CLK_TEMP_SENSOR, /*!< Select RC_FAST as the default choice */
+} soc_periph_temperature_sensor_clk_src_t;
+
 #ifdef __cplusplus
 }
 #endif

components/soc/esp32s2/include/soc/soc_caps.h

@@ -266,6 +266,7 @@
 #define SOC_TIMER_GROUP_TIMERS_PER_GROUP  (2)
 #define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (64)
 #define SOC_TIMER_GROUP_SUPPORT_XTAL      (1)
+#define SOC_TIMER_GROUP_SUPPORT_APB       (1)
 #define SOC_TIMER_GROUP_TOTAL_TIMERS      (4)
 
 /*-------------------------- TOUCH SENSOR CAPS -------------------------------*/

components/soc/esp32s3/include/soc/Kconfig.soc_caps.in

@@ -671,6 +671,10 @@ config SOC_TIMER_GROUP_SUPPORT_XTAL
     bool
     default y
 
+config SOC_TIMER_GROUP_SUPPORT_APB
+    bool
+    default y
+
 config SOC_TIMER_GROUP_TOTAL_TIMERS
     int
     default 4

components/soc/esp32s3/include/soc/clk_tree_defs.h

@@ -88,6 +88,7 @@ typedef enum {
  * Naming convention: SOC_MOD_CLK_{<upstream>clock_name}_<attr>
  * {<upstream>clock_name}: APB, (BB)PLL, etc.
  * <attr> - optional: FAST, SLOW, D<divider>, F<freq>
+ * @note enum starts from 1, to save 0 for special purpose
  */
 typedef enum {
     // For CPU domain
@@ -108,32 +109,98 @@ typedef enum {
 } soc_module_clk_t;
 
 
-// List clock sources available to each peripherial
-// soc_module_clk_src_t enum starts from 1 to save enum = 0 for AUTO selection
+//////////////////////////////////////////////////GPTimer///////////////////////////////////////////////////////////////
 
+/**
+ * @brief Array initializer for all supported clock sources of GPTimer
+ * The following code can be used to iterate all possible clocks:
+ * @code{c}
+ * soc_periph_gptimer_clk_src_t gptimer_clks[] = (soc_periph_gptimer_clk_src_t)SOC_GPTIMER_CLKS;
+ * for (size_t i = 0; i< sizeof(gptimer_clks) / sizeof(gptimer_clks[0]); i++) {
+ *     soc_periph_gptimer_clk_src_t clk = gptimer_clks[i];
+ *     // Test GPTimer with the clock `clk`
+ * }
+ * @endcode
+ */
+#define SOC_GPTIMER_CLKS {SOC_MOD_CLK_APB, SOC_MOD_CLK_XTAL}
+
+/**
+ * @brief Type of GPTimer clock source
+ */
 typedef enum {
-    GPTIMER_CLK_SRC_APB = SOC_MOD_CLK_APB,                          /*!< Select APB as the source clock */
-    GPTIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,                        /*!< Select XTAL as the source clock */
+    GPTIMER_CLK_SRC_APB = SOC_MOD_CLK_APB,     /*!< Select APB as the source clock */
+    GPTIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,   /*!< Select XTAL as the source clock */
+    GPTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB as the default choice */
 } soc_periph_gptimer_clk_src_t;
 
+/**
+ * @brief Type of Timer Group clock source, reserved for the legacy timer group driver
+ */
 typedef enum {
-    TEMPERATURE_SENSOR_CLK_SRC_DEFAULT = 0,                         /*!< Use default clock selection */
-    TEMPERATURE_SENSOR_CLK_SRC_RC_FAST = SOC_MOD_CLK_TEMP_SENSOR,   /*!< Select RC_FAST as the source clock */
-} soc_periph_temperature_sensor_clk_src_t;
+    TIMER_SRC_CLK_APB = SOC_MOD_CLK_APB,     /*!< Timer group source clock is APB */
+    TIMER_SRC_CLK_XTAL = SOC_MOD_CLK_XTAL,   /*!< Timer group source clock is XTAL */
+    TIMER_SRC_CLK_DEFAULT = SOC_MOD_CLK_APB, /*!< Timer group source clock default choice is APB */
+} soc_periph_tg_clk_src_legacy_t;
 
+//////////////////////////////////////////////////LCD///////////////////////////////////////////////////////////////////
+
+/**
+ * @brief Array initializer for all supported clock sources of LCD
+ */
+#define SOC_LCD_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_PLL_D2, SOC_MOD_CLK_XTAL}
+
+/**
+ * @brief Type of LCD clock source
+ */
 typedef enum {
-    LCD_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_F160M,                    /*!< Select PLL_F160M as the source clock */
-    LCD_CLK_SRC_PLL240M = SOC_MOD_CLK_PLL_D2,                       /*!< Select PLL_D2 as the source clock */
-    LCD_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,                            /*!< Select XTAL as the source clock */
+    LCD_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */
+    LCD_CLK_SRC_PLL240M = SOC_MOD_CLK_PLL_D2,    /*!< Select PLL_D2 as the source clock */
+    LCD_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,         /*!< Select XTAL as the source clock */
+    LCD_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default choice */
 } soc_periph_lcd_clk_src_t;
 
+//////////////////////////////////////////////////RMT///////////////////////////////////////////////////////////////////
+
+/**
+ * @brief Array initializer for all supported clock sources of RMT
+ */
+#define SOC_RMT_CLKS {SOC_MOD_CLK_APB, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL}
+
+/**
+ * @brief Type of RMT clock source
+ */
 typedef enum {
-    RMT_CLK_SRC_NONE = 0,                                           /*!< No clock source is selected */
-    RMT_CLK_SRC_APB = SOC_MOD_CLK_APB,                              /*!< Select APB as the source clock */
-    RMT_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST,                      /*!< Select RC_FAST as the source clock */
-    RMT_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,                            /*!< Select XTAL as the source clock */
+    RMT_CLK_SRC_NONE = 0,                      /*!< No clock source is selected */
+    RMT_CLK_SRC_APB = SOC_MOD_CLK_APB,         /*!< Select APB as the source clock */
+    RMT_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
+    RMT_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,       /*!< Select XTAL as the source clock */
+    RMT_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB,     /*!< Select APB as the default choice */
 } soc_periph_rmt_clk_src_t;
 
+/**
+ * @brief Type of RMT clock source, reserved for the legacy RMT driver
+ */
+typedef enum {
+    RMT_BASECLK_APB = SOC_MOD_CLK_APB,     /*!< RMT source clock is APB */
+    RMT_BASECLK_XTAL = SOC_MOD_CLK_XTAL,   /*!< RMT source clock is XTAL */
+    RMT_BASECLK_DEFAULT = SOC_MOD_CLK_APB, /*!< RMT source clock default choice is APB */
+} soc_periph_rmt_clk_src_legacy_t;
+
+//////////////////////////////////////////////////Temp Sensor///////////////////////////////////////////////////////////
+
+/**
+ * @brief Array initializer for all supported clock sources of Temperature Sensor
+ */
+#define SOC_TEMP_SENSOR_CLKS {SOC_MOD_CLK_TEMP_SENSOR}
+
+/**
+ * @brief Type of Temp Sensor clock source
+ */
+typedef enum {
+    TEMPERATURE_SENSOR_CLK_SRC_RC_FAST = SOC_MOD_CLK_TEMP_SENSOR,   /*!< Select RC_FAST as the source clock */
+    TEMPERATURE_SENSOR_CLK_SRC_DEFAULT = SOC_MOD_CLK_TEMP_SENSOR,   /*!< Select RC_FAST as the default choice */
+} soc_periph_temperature_sensor_clk_src_t;
+
 #ifdef __cplusplus
 }
 #endif

components/soc/esp32s3/include/soc/soc_caps.h

@@ -278,6 +278,7 @@
 #define SOC_TIMER_GROUP_TIMERS_PER_GROUP  (2)
 #define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (54)
 #define SOC_TIMER_GROUP_SUPPORT_XTAL      (1)
+#define SOC_TIMER_GROUP_SUPPORT_APB       (1)
 #define SOC_TIMER_GROUP_TOTAL_TIMERS      (4)
 
 /*-------------------------- TOUCH SENSOR CAPS -------------------------------*/

components/vfs/test/test_vfs_eventfd.c

@@ -227,7 +227,7 @@ TEST_CASE("eventfd signal from ISR", "[vfs][eventfd]")
 
     gptimer_handle_t gptimer = NULL;
     gptimer_config_t timer_config = {
-        .clk_src = GPTIMER_CLK_SRC_APB,
+        .clk_src = GPTIMER_CLK_SRC_DEFAULT,
         .direction = GPTIMER_COUNT_UP,
         .resolution_hz = 1000000,
     };

docs/en/api-reference/peripherals/gptimer.rst

@@ -59,7 +59,7 @@ Creating a GPTimer Handle with Resolution of 1MHz
 
    gptimer_handle_t gptimer = NULL;
    gptimer_config_t timer_config = {
-       .clk_src = GPTIMER_CLK_SRC_APB,
+       .clk_src = GPTIMER_CLK_SRC_DEFAULT,
        .direction = GPTIMER_COUNT_UP,
        .resolution_hz = 1 * 1000 * 1000, // 1MHz, 1 tick = 1us
    };

examples/bluetooth/esp_ble_mesh/common_components/light_driver/iot_led.c

@@ -331,7 +331,7 @@ esp_err_t iot_led_init(ledc_timer_t timer_num, ledc_mode_t speed_mode, uint32_t
         g_light_config->speed_mode = speed_mode;
 
         gptimer_config_t timer_config = {
-            .clk_src = GPTIMER_CLK_SRC_APB,
+            .clk_src = GPTIMER_CLK_SRC_DEFAULT,
             .direction = GPTIMER_COUNT_UP,
             .resolution_hz = GPTIMER_RESOLUTION_HZ,
         };

examples/bluetooth/esp_ble_mesh/common_components/light_driver/iot_light.c

@@ -223,7 +223,7 @@ light_handle_t iot_light_create(ledc_timer_t timer, ledc_mode_t speed_mode, uint
 
     if (g_hw_timer_started == false) {
         gptimer_config_t timer_config = {
-            .clk_src = GPTIMER_CLK_SRC_APB,
+            .clk_src = GPTIMER_CLK_SRC_DEFAULT,
             .direction = GPTIMER_COUNT_UP,
             .resolution_hz = GPTIMER_RESOLUTION_HZ,
         };

examples/peripherals/lcd/i80_controller/main/i80_controller_example_main.c

@@ -113,7 +113,7 @@ void app_main(void)
     ESP_LOGI(TAG, "Initialize Intel 8080 bus");
     esp_lcd_i80_bus_handle_t i80_bus = NULL;
     esp_lcd_i80_bus_config_t bus_config = {
-        .clk_src = LCD_CLK_SRC_PLL160M,
+        .clk_src = LCD_CLK_SRC_DEFAULT,
         .dc_gpio_num = EXAMPLE_PIN_NUM_DC,
         .wr_gpio_num = EXAMPLE_PIN_NUM_PCLK,
         .data_gpio_nums = {

examples/peripherals/lcd/rgb_panel/main/rgb_lcd_example_main.c

@@ -89,7 +89,7 @@ void app_main(void)
     esp_lcd_rgb_panel_config_t panel_config = {
         .data_width = 16, // RGB565 in parallel mode, thus 16bit in width
         .psram_trans_align = 64,
-        .clk_src = LCD_CLK_SRC_PLL160M,
+        .clk_src = LCD_CLK_SRC_DEFAULT,
         .disp_gpio_num = EXAMPLE_PIN_NUM_DISP_EN,
         .pclk_gpio_num = EXAMPLE_PIN_NUM_PCLK,
         .vsync_gpio_num = EXAMPLE_PIN_NUM_VSYNC,

examples/peripherals/mcpwm/mcpwm_bdc_speed_control/main/mcpwm_bdc_control_example_main.c

@@ -220,7 +220,7 @@ void app_main(void)
     printf("init motor control timer\r\n");
     gptimer_handle_t gptimer;
     gptimer_config_t timer_config = {
-        .clk_src = GPTIMER_CLK_SRC_APB,
+        .clk_src = GPTIMER_CLK_SRC_DEFAULT,
         .direction = GPTIMER_COUNT_UP,
         .resolution_hz = 1000000, // 1MHz, 1 tick = 1us
     };

examples/peripherals/timer_group/gptimer/main/gptimer_example_main.c

@@ -75,7 +75,7 @@ void app_main(void)
     ESP_LOGI(TAG, "Create timer handle");
     gptimer_handle_t gptimer = NULL;
     gptimer_config_t timer_config = {
-        .clk_src = GPTIMER_CLK_SRC_APB,
+        .clk_src = GPTIMER_CLK_SRC_DEFAULT,
         .direction = GPTIMER_COUNT_UP,
         .resolution_hz = 1000000, // 1MHz, 1 tick=1us
     };

examples/peripherals/timer_group/legacy_driver/main/timer_group_example_main.c

@@ -62,7 +62,7 @@ static void example_tg_timer_init(example_timer_user_data_t *user_data)
     int timer = user_data->timer_idx;
 
     timer_config_t config = {
-        .clk_src = TIMER_SRC_CLK_APB,
+        .clk_src = TIMER_SRC_CLK_DEFAULT,
         .divider = APB_CLK_FREQ / TIMER_RESOLUTION_HZ,
         .counter_dir = TIMER_COUNT_UP,
         .counter_en = TIMER_PAUSE,

examples/peripherals/wave_gen/main/wave_gen_example_main.c

@@ -96,7 +96,7 @@ void app_main(void)
     g_index = 0;
     gptimer_handle_t gptimer = NULL;
     gptimer_config_t timer_config = {
-        .clk_src = GPTIMER_CLK_SRC_APB,
+        .clk_src = GPTIMER_CLK_SRC_DEFAULT,
         .direction = GPTIMER_COUNT_UP,
         .resolution_hz = 1000000, // 1MHz, 1 tick = 1us
     };

examples/system/eventfd/main/eventfd_example.c

@@ -46,7 +46,7 @@ static bool eventfd_timer_isr_callback(gptimer_handle_t timer, const gptimer_ala
 static void eventfd_timer_init(void)
 {
     gptimer_config_t timer_config = {
-        .clk_src = GPTIMER_CLK_SRC_APB,
+        .clk_src = GPTIMER_CLK_SRC_DEFAULT,
         .direction = GPTIMER_COUNT_UP,
         .resolution_hz = TIMER_RESOLUTION,
     };

examples/system/flash_suspend/main/app_main.c

@@ -101,7 +101,7 @@ void app_main(void)
 
     gptimer_handle_t gptimer = NULL;
     gptimer_config_t timer_config = {
-        .clk_src = GPTIMER_CLK_SRC_APB,
+        .clk_src = GPTIMER_CLK_SRC_DEFAULT,
         .direction = GPTIMER_COUNT_UP,
         .resolution_hz = TIMER_RESOLUTION_HZ,
     };

examples/system/sysview_tracing/main/sysview_tracing.c

@@ -146,7 +146,7 @@ void app_main(void)
 
     for (int i = 0; i < portNUM_PROCESSORS; i++) {
         gptimer_config_t timer_config = {
-            .clk_src = GPTIMER_CLK_SRC_APB,
+            .clk_src = GPTIMER_CLK_SRC_DEFAULT,
             .direction = GPTIMER_COUNT_UP,
             .resolution_hz = 1000000,
         };

tools/unit-test-app/components/test_utils/ref_clock_impl_rmt_pcnt.c

@@ -101,7 +101,7 @@ void ref_clock_init(void)
     };
 
     rmt_ll_enable_periph_clock(s_rmt_hal.regs, true);
-    rmt_ll_set_group_clock_src(s_rmt_hal.regs, REF_CLOCK_RMT_CHANNEL, RMT_CLK_SRC_REFTICK, 1, 1, 0); // select REF_TICK (1MHz)
+    rmt_ll_set_group_clock_src(s_rmt_hal.regs, REF_CLOCK_RMT_CHANNEL, RMT_CLK_SRC_APB_F1M, 1, 1, 0); // select REF_TICK (1MHz)
     rmt_ll_tx_set_channel_clock_div(s_rmt_hal.regs, REF_CLOCK_RMT_CHANNEL, 1); // channel clock = REF_TICK / 1 = 1MHz
     rmt_ll_tx_fix_idle_level(s_rmt_hal.regs, REF_CLOCK_RMT_CHANNEL, 1, true); // enable idle output, idle level: 1
     rmt_ll_tx_enable_carrier_modulation(s_rmt_hal.regs, REF_CLOCK_RMT_CHANNEL, true);