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@@ -1,16 +1,8 @@
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-// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
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-//
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-// Licensed under the Apache License, Version 2.0 (the "License");
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-// you may not use this file except in compliance with the License.
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-// You may obtain a copy of the License at
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-//
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-// http://www.apache.org/licenses/LICENSE-2.0
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-//
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-// Unless required by applicable law or agreed to in writing, software
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-// distributed under the License is distributed on an "AS IS" BASIS,
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-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-// See the License for the specific language governing permissions and
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-// limitations under the License.
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+/*
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+ * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
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+ *
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+ * SPDX-License-Identifier: Apache-2.0
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+ */
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// The HAL layer for I2S (common part)
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// The HAL layer for I2S (common part)
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@@ -104,6 +96,13 @@ void i2s_hal_tx_set_pdm_mode_default(i2s_hal_context_t *hal, uint32_t sample_rat
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{
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{
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/* enable pdm tx mode */
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/* enable pdm tx mode */
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i2s_ll_tx_enable_pdm(hal->dev, true);
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i2s_ll_tx_enable_pdm(hal->dev, true);
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+#if SOC_I2S_SUPPORTS_TDM
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+ i2s_ll_tx_enable_clock(hal->dev);
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+ i2s_ll_tx_clk_set_src(hal->dev, I2S_CLK_D2CLK); // Set I2S_CLK_D2CLK as default
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+ i2s_ll_mclk_use_tx_clk(hal->dev);
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+#else
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+ i2s_ll_tx_force_enable_fifo_mod(hal->dev, true);
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+#endif
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/* set pdm tx default presacle */
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/* set pdm tx default presacle */
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i2s_ll_tx_set_pdm_prescale(hal->dev, 0);
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i2s_ll_tx_set_pdm_prescale(hal->dev, 0);
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/* set pdm tx default sacle of high pass filter */
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/* set pdm tx default sacle of high pass filter */
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@@ -140,6 +139,16 @@ void i2s_hal_rx_set_pdm_mode_default(i2s_hal_context_t *hal)
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i2s_ll_rx_enable_pdm(hal->dev, true);
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i2s_ll_rx_enable_pdm(hal->dev, true);
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/* set pdm rx downsample number */
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/* set pdm rx downsample number */
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i2s_ll_rx_set_pdm_dsr(hal->dev, I2S_PDM_DSR_8S);
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i2s_ll_rx_set_pdm_dsr(hal->dev, I2S_PDM_DSR_8S);
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+#if !SOC_I2S_SUPPORTS_TDM
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+ i2s_ll_rx_force_enable_fifo_mod(hal->dev, true);
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+#endif
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+#if SOC_I2S_SUPPORTS_TDM
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+ i2s_ll_rx_enable_clock(hal->dev);
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+ i2s_ll_rx_clk_set_src(hal->dev, I2S_CLK_D2CLK); // Set I2S_CLK_D2CLK as default
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+ i2s_ll_mclk_use_rx_clk(hal->dev);
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+#else
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+ i2s_ll_rx_force_enable_fifo_mod(hal->dev, true);
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+#endif
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}
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}
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#endif // SOC_I2S_SUPPORTS_PDM_RX
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#endif // SOC_I2S_SUPPORTS_PDM_RX
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@@ -286,8 +295,8 @@ void i2s_hal_config_param(i2s_hal_context_t *hal, const i2s_hal_config_t *hal_cf
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{
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{
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/* Set tx common mode */
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/* Set tx common mode */
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i2s_hal_tx_set_common_mode(hal, hal_cfg);
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i2s_hal_tx_set_common_mode(hal, hal_cfg);
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- i2s_hal_tx_set_channel_style(hal, hal_cfg);
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}
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}
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+ i2s_hal_tx_set_channel_style(hal, hal_cfg);
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}
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}
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/* Set configurations for RX mode */
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/* Set configurations for RX mode */
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@@ -304,8 +313,8 @@ void i2s_hal_config_param(i2s_hal_context_t *hal, const i2s_hal_config_t *hal_cf
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{
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{
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/* Set rx common mode */
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/* Set rx common mode */
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i2s_hal_rx_set_common_mode(hal, hal_cfg);
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i2s_hal_rx_set_common_mode(hal, hal_cfg);
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- i2s_hal_rx_set_channel_style(hal, hal_cfg);
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}
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}
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+ i2s_hal_rx_set_channel_style(hal, hal_cfg);
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}
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}
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/* Set configurations for full-duplex mode */
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/* Set configurations for full-duplex mode */
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