Merge branch 'bugfix/esp32c6_h2_clk_gate_periph_rst' into 'master'

clk_gate_ll: fix issue with DS peripheral clk reset

Closes IDF-6740

See merge request espressif/esp-idf!22301

components/hal/esp32c6/include/hal/clk_gate_ll.h

@@ -10,7 +10,7 @@
 #include <stdbool.h>
 #include "soc/periph_defs.h"
 #include "soc/pcr_reg.h"
-#include "soc/dport_access.h"
+#include "soc/soc.h"
 #include "esp_attr.h"
 
 #ifdef __cplusplus
@@ -139,29 +139,24 @@ static inline uint32_t periph_ll_get_rst_en_mask(periph_module_t periph, bool en
         case PERIPH_TEMPSENSOR_MODULE:
             return PCR_TSENS_RST_EN;
         case PERIPH_AES_MODULE:
-        if (enable == true) {
-            // Clear reset on digital signature, otherwise AES unit is held in reset also.
-                return (PCR_AES_RST_EN | PCR_DS_RST_EN);
-        } else {
-                //Don't return other units to reset, as this pulls reset on RSA & SHA units, respectively.
-                return PCR_AES_RST_EN;
-        }
+            if (enable == true) {
+                // Clear reset on digital signature, otherwise AES unit is held in reset
+                CLEAR_PERI_REG_MASK(PCR_DS_CONF_REG, PCR_DS_RST_EN);
+            }
+            return PCR_AES_RST_EN;
         case PERIPH_SHA_MODULE:
-        if (enable == true) {
-            // Clear reset on digital signature and HMAC, otherwise SHA is held in reset
-                return (PCR_SHA_RST_EN | PCR_DS_RST_EN | PCR_HMAC_RST_EN);
-        } else {
-            // Don't assert reset on secure boot, otherwise AES is held in reset
-                return PCR_SHA_RST_EN;
-        }
+            if (enable == true) {
+                // Clear reset on digital signature and HMAC, otherwise SHA is held in reset
+                CLEAR_PERI_REG_MASK(PCR_DS_CONF_REG, PCR_DS_RST_EN);
+                CLEAR_PERI_REG_MASK(PCR_HMAC_CONF_REG, PCR_HMAC_RST_EN);
+            }
+            return PCR_SHA_RST_EN;
         case PERIPH_RSA_MODULE:
-        if (enable == true) {
-            /* also clear reset on digital signature, otherwise RSA is held in reset */
-                return (PCR_RSA_RST_EN | PCR_DS_RST_EN);
-        } else {
-            /* don't reset digital signature unit, as this resets AES also */
-                return PCR_RSA_RST_EN;
-        }
+            if (enable == true) {
+                // Clear reset on digital signature, otherwise RSA is held in reset
+                CLEAR_PERI_REG_MASK(PCR_DS_CONF_REG, PCR_DS_RST_EN);
+            }
+            return PCR_RSA_RST_EN;
         case PERIPH_HMAC_MODULE:
             return PCR_HMAC_RST_EN;
         case PERIPH_DS_MODULE:
@@ -319,26 +314,26 @@ static uint32_t periph_ll_get_rst_en_reg(periph_module_t periph)
 
 static inline void periph_ll_enable_clk_clear_rst(periph_module_t periph)
 {
-    DPORT_SET_PERI_REG_MASK(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph));
-    DPORT_CLEAR_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, true));
+    SET_PERI_REG_MASK(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph));
+    CLEAR_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, true));
 }
 
 static inline void periph_ll_disable_clk_set_rst(periph_module_t periph)
 {
-    DPORT_CLEAR_PERI_REG_MASK(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph));
-    DPORT_SET_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false));
+    CLEAR_PERI_REG_MASK(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph));
+    SET_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false));
 }
 
 static inline void periph_ll_reset(periph_module_t periph)
 {
-    DPORT_SET_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false));
-    DPORT_CLEAR_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false));
+    SET_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false));
+    CLEAR_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false));
 }
 
 static inline bool IRAM_ATTR periph_ll_periph_enabled(periph_module_t periph)
 {
-    return DPORT_REG_GET_BIT(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false)) == 0 &&
-           DPORT_REG_GET_BIT(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph)) != 0;
+    return REG_GET_BIT(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false)) == 0 &&
+           REG_GET_BIT(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph)) != 0;
 }
 
 #ifdef __cplusplus

components/hal/esp32h2/include/hal/clk_gate_ll.h

@@ -10,7 +10,7 @@
 #include <stdbool.h>
 #include "soc/periph_defs.h"
 #include "soc/pcr_reg.h"
-#include "soc/dport_access.h"
+#include "soc/soc.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -133,29 +133,24 @@ static inline uint32_t periph_ll_get_rst_en_mask(periph_module_t periph, bool en
         case PERIPH_TEMPSENSOR_MODULE:
             return PCR_TSENS_RST_EN;
         case PERIPH_AES_MODULE:
-        if (enable == true) {
-            // Clear reset on digital signature, otherwise AES unit is held in reset also.
-                return (PCR_AES_RST_EN | PCR_DS_RST_EN);
-        } else {
-                //Don't return other units to reset, as this pulls reset on RSA & SHA units, respectively.
-                return PCR_AES_RST_EN;
-        }
+            if (enable == true) {
+                // Clear reset on digital signature, otherwise AES unit is held in reset
+                CLEAR_PERI_REG_MASK(PCR_DS_CONF_REG, PCR_DS_RST_EN);
+            }
+            return PCR_AES_RST_EN;
         case PERIPH_SHA_MODULE:
-        if (enable == true) {
-            // Clear reset on digital signature and HMAC, otherwise SHA is held in reset
-                return (PCR_SHA_RST_EN | PCR_DS_RST_EN | PCR_HMAC_RST_EN);
-        } else {
-            // Don't assert reset on secure boot, otherwise AES is held in reset
-                return PCR_SHA_RST_EN;
-        }
+            if (enable == true) {
+                // Clear reset on digital signature and HMAC, otherwise SHA is held in reset
+                CLEAR_PERI_REG_MASK(PCR_DS_CONF_REG, PCR_DS_RST_EN);
+                CLEAR_PERI_REG_MASK(PCR_HMAC_CONF_REG, PCR_HMAC_RST_EN);
+            }
+            return PCR_SHA_RST_EN;
         case PERIPH_RSA_MODULE:
-        if (enable == true) {
-            /* also clear reset on digital signature, otherwise RSA is held in reset */
-                return (PCR_RSA_RST_EN | PCR_DS_RST_EN);
-        } else {
-            /* don't reset digital signature unit, as this resets AES also */
-                return PCR_RSA_RST_EN;
-        }
+            if (enable == true) {
+                // Clear reset on digital signature, otherwise RSA is held in reset
+                CLEAR_PERI_REG_MASK(PCR_DS_CONF_REG, PCR_DS_RST_EN);
+            }
+            return PCR_RSA_RST_EN;
         case PERIPH_HMAC_MODULE:
             return PCR_HMAC_RST_EN;
         case PERIPH_DS_MODULE:
@@ -304,14 +299,14 @@ static uint32_t periph_ll_get_rst_en_reg(periph_module_t periph)
 
 static inline void periph_ll_enable_clk_clear_rst(periph_module_t periph)
 {
-    DPORT_SET_PERI_REG_MASK(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph));
-    DPORT_CLEAR_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, true));
+    SET_PERI_REG_MASK(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph));
+    CLEAR_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, true));
 }
 
 static inline void periph_ll_disable_clk_set_rst(periph_module_t periph)
 {
-    DPORT_CLEAR_PERI_REG_MASK(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph));
-    DPORT_SET_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false));
+    CLEAR_PERI_REG_MASK(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph));
+    SET_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false));
 }
 
 static inline void periph_ll_wifi_bt_module_enable_clk_clear_rst(void)
@@ -328,14 +323,14 @@ static inline void periph_ll_wifi_bt_module_disable_clk_set_rst(void)
 
 static inline void periph_ll_reset(periph_module_t periph)
 {
-    DPORT_SET_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false));
-    DPORT_CLEAR_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false));
+    SET_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false));
+    CLEAR_PERI_REG_MASK(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false));
 }
 
 static inline bool periph_ll_periph_enabled(periph_module_t periph)
 {
-    return DPORT_REG_GET_BIT(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false)) == 0 &&
-           DPORT_REG_GET_BIT(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph)) != 0;
+    return REG_GET_BIT(periph_ll_get_rst_en_reg(periph), periph_ll_get_rst_en_mask(periph, false)) == 0 &&
+           REG_GET_BIT(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph)) != 0;
 }
 
 static inline void periph_ll_wifi_module_enable_clk_clear_rst(void)