Merge branch 'feature/esp32s2beta' into feature/esp32s2beta_merge

components/app_trace/sys_view/Sample/Config/SEGGER_SYSVIEW_Config_FreeRTOS.c

@@ -63,12 +63,19 @@ Revision: $Rev: 3734 $
 */
 #include "freertos/FreeRTOS.h"
 #include "SEGGER_SYSVIEW.h"
-#include "esp32/rom/ets_sys.h"
 #include "esp_app_trace.h"
 #include "esp_app_trace_util.h"
 #include "esp_intr_alloc.h"
-#include "esp32/clk.h"
 #include "soc/soc.h"
+#include "soc/interrupts.h"
+#if CONFIG_IDF_TARGET_ESP32
+#include "esp32/rom/ets_sys.h"
+#include "esp32/clk.h"
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
+#include "esp32s2beta/rom/ets_sys.h"
+#include "esp32s2beta/clk.h"
+#endif
+
 
 extern const SEGGER_SYSVIEW_OS_API SYSVIEW_X_OS_TraceAPI;
 
@@ -82,7 +89,7 @@ extern const SEGGER_SYSVIEW_OS_API SYSVIEW_X_OS_TraceAPI;
 #define SYSVIEW_APP_NAME        "FreeRTOS Application"
 
 // The target device name
-#define SYSVIEW_DEVICE_NAME     "ESP32"
+#define SYSVIEW_DEVICE_NAME     CONFIG_IDF_TARGET
 
 // Determine which timer to use as timestamp source
 #if CONFIG_SYSVIEW_TS_SOURCE_CCOUNT
@@ -124,7 +131,12 @@ extern const SEGGER_SYSVIEW_OS_API SYSVIEW_X_OS_TraceAPI;
 
 #if TS_USE_CCOUNT
 // CCOUNT is incremented at CPU frequency
+#if CONFIG_IDF_TARGET_ESP32
 #define SYSVIEW_TIMESTAMP_FREQ  (CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ * 1000000)
+#elif CONFIG_IDF_TARGET_ESP32S2BETA
+#define SYSVIEW_TIMESTAMP_FREQ  (CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ * 1000000)
+#endif
+
 #endif // TS_USE_CCOUNT
 
 // System Frequency.
@@ -148,78 +160,6 @@ extern const SEGGER_SYSVIEW_OS_API SYSVIEW_X_OS_TraceAPI;
 
 static esp_apptrace_lock_t s_sys_view_lock = {.mux = portMUX_INITIALIZER_UNLOCKED, .int_state = 0};
 
-static const char * const s_isr_names[] = {
-    [0] = "WIFI_MAC",
-    [1] = "WIFI_NMI",
-    [2] = "WIFI_BB",
-    [3] = "BT_MAC",
-    [4] = "BT_BB",
-    [5] = "BT_BB_NMI",
-    [6] = "RWBT",
-    [7] = "RWBLE",
-    [8] = "RWBT_NMI",
-    [9] = "RWBLE_NMI",
-    [10] = "SLC0",
-    [11] = "SLC1",
-    [12] = "UHCI0",
-    [13] = "UHCI1",
-    [14] = "TG0_T0_LEVEL",
-    [15] = "TG0_T1_LEVEL",
-    [16] = "TG0_WDT_LEVEL",
-    [17] = "TG0_LACT_LEVEL",
-    [18] = "TG1_T0_LEVEL",
-    [19] = "TG1_T1_LEVEL",
-    [20] = "TG1_WDT_LEVEL",
-    [21] = "TG1_LACT_LEVEL",
-    [22] = "GPIO",
-    [23] = "GPIO_NMI",
-    [24] = "FROM_CPU0",
-    [25] = "FROM_CPU1",
-    [26] = "FROM_CPU2",
-    [27] = "FROM_CPU3",
-    [28] = "SPI0",
-    [29] = "SPI1",
-    [30] = "SPI2",
-    [31] = "SPI3",
-    [32] = "I2S0",
-    [33] = "I2S1",
-    [34] = "UART0",
-    [35] = "UART1",
-    [36] = "UART2",
-    [37] = "SDIO_HOST",
-    [38] = "ETH_MAC",
-    [39] = "PWM0",
-    [40] = "PWM1",
-    [41] = "PWM2",
-    [42] = "PWM3",
-    [43] = "LEDC",
-    [44] = "EFUSE",
-    [45] = "CAN",
-    [46] = "RTC_CORE",
-    [47] = "RMT",
-    [48] = "PCNT",
-    [49] = "I2C_EXT0",
-    [50] = "I2C_EXT1",
-    [51] = "RSA",
-    [52] = "SPI1_DMA",
-    [53] = "SPI2_DMA",
-    [54] = "SPI3_DMA",
-    [55] = "WDT",
-    [56] = "TIMER1",
-    [57] = "TIMER2",
-    [58] = "TG0_T0_EDGE",
-    [59] = "TG0_T1_EDGE",
-    [60] = "TG0_WDT_EDGE",
-    [61] = "TG0_LACT_EDGE",
-    [62] = "TG1_T0_EDGE",
-    [63] = "TG1_T1_EDGE",
-    [64] = "TG1_WDT_EDGE",
-    [65] = "TG1_LACT_EDGE",
-    [66] = "MMU_IA",
-    [67] = "MPU_IA",
-    [68] = "CACHE_IA",
-};
-
 /*********************************************************************
 *
 *       _cbSendSystemDesc()
@@ -232,9 +172,9 @@ static void _cbSendSystemDesc(void) {
     SEGGER_SYSVIEW_SendSysDesc("N="SYSVIEW_APP_NAME",D="SYSVIEW_DEVICE_NAME",C=Xtensa,O=FreeRTOS");
     snprintf(irq_str, sizeof(irq_str), "I#%d=SysTick", SYSTICK_INTR_ID);
     SEGGER_SYSVIEW_SendSysDesc(irq_str);
-    size_t isr_count = sizeof(s_isr_names)/sizeof(s_isr_names[0]);
+    size_t isr_count = sizeof(esp_isr_names)/sizeof(esp_isr_names[0]);
     for (size_t i = 0; i < isr_count; ++i) {
-        snprintf(irq_str, sizeof(irq_str), "I#%d=%s", ETS_INTERNAL_INTR_SOURCE_OFF + i, s_isr_names[i]);
+        snprintf(irq_str, sizeof(irq_str), "I#%d=%s", ETS_INTERNAL_INTR_SOURCE_OFF + i, esp_isr_names[i]);
         SEGGER_SYSVIEW_SendSysDesc(irq_str);
     }
 }

components/bootloader/subproject/main/ld/esp32s2beta/bootloader.ld

@@ -15,8 +15,8 @@ MEMORY
   dport0_seg (RW) :                 org = 0x3FF00000, len = 0x10
   iram_loader_seg (RWX) :           org = 0x40062000, len = 0x4000  /* 16KB, IRAM */
   iram_seg (RWX) :                  org = 0x40066000, len = 0x4000  /* 16KB, IRAM */
-  /* 16k at the end of DRAM, before ROM data & stack */
-  dram_seg (RW) :                   org = 0x3FFF8000, len = 0x4000
+  /* 8k at the end of DRAM, before ROM data & stack */
+  dram_seg (RW) :                   org = 0x3FFFA000, len = 0x2000
 }
 
 /*  Default entry point:  */

components/esp32s2beta/clk.c

@@ -66,10 +66,10 @@ void esp_clk_init(void)
 
 #ifdef CONFIG_BOOTLOADER_WDT_ENABLE
     // WDT uses a SLOW_CLK clock source. After a function select_rtc_slow_clk a frequency of this source can changed.
-    // If the frequency changes from 150kHz to 32kHz, then the timeout set for the WDT will increase 4.6 times.
+    // If the frequency changes from 90kHz to 32kHz, then the timeout set for the WDT will increase 2.8 times.
     // Therefore, for the time of frequency change, set a new lower timeout value (1.6 sec).
     // This prevents excessive delay before resetting in case the supply voltage is drawdown.
-    // (If frequency is changed from 150kHz to 32kHz then WDT timeout will increased to 1.6sec * 150/32 = 7.5 sec).
+    // (If frequency is changed from 90kHz to 32kHz then WDT timeout will increased to 1.6sec * 90/32 = 4.5 sec).
     rtc_wdt_protect_off();
     rtc_wdt_feed();
     rtc_wdt_set_time(RTC_WDT_STAGE0, 1600);

components/newlib/test/test_time.c

@@ -316,11 +316,11 @@ TEST_CASE("test time adjustment happens linearly", "[newlib][timeout=35]")
 }
 #endif
 
-#if defined( CONFIG_ESP32_TIME_SYSCALL_USE_RTC ) || defined( CONFIG_ESP32_TIME_SYSCALL_USE_RTC_FRC1 )
+#if defined( CONFIG_ESP32_TIME_SYSCALL_USE_RTC ) || defined( CONFIG_ESP32_TIME_SYSCALL_USE_RTC_FRC1 ) || defined( CONFIG_ESP32S2_TIME_SYSCALL_USE_RTC ) || defined( CONFIG_ESP32S2_TIME_SYSCALL_USE_RTC_FRC1 )
 #define WITH_RTC 1
 #endif
 
-#if defined( CONFIG_ESP32_TIME_SYSCALL_USE_FRC1 ) || defined( CONFIG_ESP32_TIME_SYSCALL_USE_RTC_FRC1 )
+#if defined( CONFIG_ESP32_TIME_SYSCALL_USE_FRC1 ) || defined( CONFIG_ESP32_TIME_SYSCALL_USE_RTC_FRC1 ) || defined( CONFIG_ESP32S2_TIME_SYSCALL_USE_FRC1 ) || defined( CONFIG_ESP32S2_TIME_SYSCALL_USE_RTC_FRC1 )
 #define WITH_FRC 1
 #endif
 void test_posix_timers_clock (void)
@@ -416,7 +416,7 @@ void test_posix_timers_clock (void)
 #endif // defined( WITH_FRC ) || defined( WITH_RTC )
 }
 
-TEST_CASE_ESP32("test posix_timers clock_... functions", "[newlib]")
+TEST_CASE("test posix_timers clock_... functions", "[newlib]")
 {
     test_posix_timers_clock();
 }

components/soc/esp32/interrupts.c

@@ -0,0 +1,87 @@
+// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include "soc/interrupts.h"
+
+const char * const esp_isr_names[ETS_MAX_INTR_SOURCE] = {
+    [0] = "WIFI_MAC",
+    [1] = "WIFI_NMI",
+    [2] = "WIFI_BB",
+    [3] = "BT_MAC",
+    [4] = "BT_BB",
+    [5] = "BT_BB_NMI",
+    [6] = "RWBT",
+    [7] = "RWBLE",
+    [8] = "RWBT_NMI",
+    [9] = "RWBLE_NMI",
+    [10] = "SLC0",
+    [11] = "SLC1",
+    [12] = "UHCI0",
+    [13] = "UHCI1",
+    [14] = "TG0_T0_LEVEL",
+    [15] = "TG0_T1_LEVEL",
+    [16] = "TG0_WDT_LEVEL",
+    [17] = "TG0_LACT_LEVEL",
+    [18] = "TG1_T0_LEVEL",
+    [19] = "TG1_T1_LEVEL",
+    [20] = "TG1_WDT_LEVEL",
+    [21] = "TG1_LACT_LEVEL",
+    [22] = "GPIO",
+    [23] = "GPIO_NMI",
+    [24] = "FROM_CPU0",
+    [25] = "FROM_CPU1",
+    [26] = "FROM_CPU2",
+    [27] = "FROM_CPU3",
+    [28] = "SPI0",
+    [29] = "SPI1",
+    [30] = "SPI2",
+    [31] = "SPI3",
+    [32] = "I2S0",
+    [33] = "I2S1",
+    [34] = "UART0",
+    [35] = "UART1",
+    [36] = "UART2",
+    [37] = "SDIO_HOST",
+    [38] = "ETH_MAC",
+    [39] = "PWM0",
+    [40] = "PWM1",
+    [41] = "PWM2",
+    [42] = "PWM3",
+    [43] = "LEDC",
+    [44] = "EFUSE",
+    [45] = "CAN",
+    [46] = "RTC_CORE",
+    [47] = "RMT",
+    [48] = "PCNT",
+    [49] = "I2C_EXT0",
+    [50] = "I2C_EXT1",
+    [51] = "RSA",
+    [52] = "SPI1_DMA",
+    [53] = "SPI2_DMA",
+    [54] = "SPI3_DMA",
+    [55] = "WDT",
+    [56] = "TIMER1",
+    [57] = "TIMER2",
+    [58] = "TG0_T0_EDGE",
+    [59] = "TG0_T1_EDGE",
+    [60] = "TG0_WDT_EDGE",
+    [61] = "TG0_LACT_EDGE",
+    [62] = "TG1_T0_EDGE",
+    [63] = "TG1_T1_EDGE",
+    [64] = "TG1_WDT_EDGE",
+    [65] = "TG1_LACT_EDGE",
+    [66] = "MMU_IA",
+    [67] = "MPU_IA",
+    [68] = "CACHE_IA",
+};

components/soc/esp32/sources.cmake

@@ -10,6 +10,7 @@ set(SOC_SRCS "cpu_util.c"
     "rtc_wdt.c"
     "sdio_slave_periph.c"
     "sdmmc_periph.c"
+    "interrupts.c"
     "soc_memory_layout.c"
     "spi_periph.c"
     "ledc_periph.c"

components/soc/esp32s2beta/include/soc/periph_defs.h

@@ -57,103 +57,6 @@ typedef enum {
     PERIPH_BT_LC_MODULE,
 } periph_module_t;
 
-typedef enum {
-    ETS_WIFI_MAC_INTR_SOURCE = 0,               /**< interrupt of WiFi MAC, level*/
-    ETS_WIFI_MAC_NMI_SOURCE,                    /**< interrupt of WiFi MAC, NMI, use if MAC have bug to fix in NMI*/
-    ETS_WIFI_PWR_INTR_SOURCE,                   /**< */
-    ETS_WIFI_BB_INTR_SOURCE,                    /**< interrupt of WiFi BB, level, we can do some calibartion*/
-    ETS_BT_MAC_INTR_SOURCE,                     /**< will be cancelled*/
-    ETS_BT_BB_INTR_SOURCE,                      /**< interrupt of BT BB, level*/
-    ETS_BT_BB_NMI_SOURCE,                       /**< interrupt of BT BB, NMI, use if BB have bug to fix in NMI*/
-    ETS_RWBT_INTR_SOURCE,                       /**< interrupt of RWBT, level*/
-    ETS_RWBLE_INTR_SOURCE,                      /**< interrupt of RWBLE, level*/
-    ETS_RWBT_NMI_SOURCE,                        /**< interrupt of RWBT, NMI, use if RWBT have bug to fix in NMI*/
-    ETS_RWBLE_NMI_SOURCE,                       /**< interrupt of RWBLE, NMI, use if RWBT have bug to fix in NMI*/
-    ETS_SLC0_INTR_SOURCE,                       /**< interrupt of SLC0, level*/
-    ETS_SLC1_INTR_SOURCE,                       /**< interrupt of SLC1, level*/
-    ETS_UHCI0_INTR_SOURCE,                      /**< interrupt of UHCI0, level*/
-    ETS_UHCI1_INTR_SOURCE,                      /**< interrupt of UHCI1, level*/
-    ETS_TG0_T0_LEVEL_INTR_SOURCE,               /**< interrupt of TIMER_GROUP0, TIMER0, level, we would like use EDGE for timer if permission*/
-
-    ETS_TG0_T1_LEVEL_INTR_SOURCE,               /**< interrupt of TIMER_GROUP0, TIMER1, level, we would like use EDGE for timer if permission*/
-    ETS_TG0_WDT_LEVEL_INTR_SOURCE,              /**< interrupt of TIMER_GROUP0, WATCHDOG, level*/
-    ETS_TG0_LACT_LEVEL_INTR_SOURCE,             /**< interrupt of TIMER_GROUP0, LACT, level*/
-    ETS_TG1_T0_LEVEL_INTR_SOURCE,               /**< interrupt of TIMER_GROUP1, TIMER0, level, we would like use EDGE for timer if permission*/
-    ETS_TG1_T1_LEVEL_INTR_SOURCE,               /**< interrupt of TIMER_GROUP1, TIMER1, level, we would like use EDGE for timer if permission*/
-    ETS_TG1_WDT_LEVEL_INTR_SOURCE,              /**< interrupt of TIMER_GROUP1, WATCHDOG, level*/
-    ETS_TG1_LACT_LEVEL_INTR_SOURCE,             /**< interrupt of TIMER_GROUP1, LACT, level*/
-    ETS_GPIO_INTR_SOURCE,                       /**< interrupt of GPIO, level*/
-    ETS_GPIO_NMI_SOURCE,                        /**< interrupt of GPIO, NMI*/
-    ETS_GPIO_INTR_SOURCE2,                      /**< interrupt of GPIO, level*/
-    ETS_GPIO_NMI_SOURCE2,                       /**< interrupt of GPIO, NMI*/
-    ETS_DEDICATED_GPIO_INTR_SOURCE,                 /**< interrupt of dedicated GPIO, level*/
-    ETS_FROM_CPU_INTR0_SOURCE,                  /**< interrupt0 generated from a CPU, level*/ /* Used for FreeRTOS */
-    ETS_FROM_CPU_INTR1_SOURCE,                  /**< interrupt1 generated from a CPU, level*/ /* Used for FreeRTOS */
-    ETS_FROM_CPU_INTR2_SOURCE,                  /**< interrupt2 generated from a CPU, level*/ /* Used for DPORT Access */
-    ETS_FROM_CPU_INTR3_SOURCE,                  /**< interrupt3 generated from a CPU, level*/ /* Used for DPORT Access */
-
-    ETS_SPI1_INTR_SOURCE = 32,                       /**< interrupt of SPI1, level, SPI1 is for flash read/write, do not use this*/
-    ETS_SPI2_INTR_SOURCE,                       /**< interrupt of SPI2, level*/
-    ETS_SPI3_INTR_SOURCE,                       /**< interrupt of SPI3, level*/
-    ETS_I2S0_INTR_SOURCE,                       /**< interrupt of I2S0, level*/
-    ETS_I2S1_INTR_SOURCE,                       /**< interrupt of I2S1, level*/
-    ETS_UART0_INTR_SOURCE,                      /**< interrupt of UART0, level*/
-    ETS_UART1_INTR_SOURCE,                      /**< interrupt of UART1, level*/
-    ETS_UART2_INTR_SOURCE,                      /**< interrupt of UART2, level*/
-    ETS_SDIO_HOST_INTR_SOURCE,                  /**< interrupt of SD/SDIO/MMC HOST, level*/
-    ETS_PWM0_INTR_SOURCE,                       /**< interrupt of PWM0, level, Reserved*/
-    ETS_PWM1_INTR_SOURCE,                       /**< interrupt of PWM1, level, Reserved*/
-    ETS_PWM2_INTR_SOURCE,                       /**< interrupt of PWM2, level*/
-    ETS_PWM3_INTR_SOURCE,                       /**< interruot of PWM3, level*/
-    ETS_LEDC_INTR_SOURCE,                       /**< interrupt of LED PWM, level*/
-    ETS_EFUSE_INTR_SOURCE,                      /**< interrupt of efuse, level, not likely to use*/
-    ETS_CAN_INTR_SOURCE ,                       /**< interrupt of can, level*/
-
-    ETS_USB_INTR_SOURCE = 48,                   /**< interrupt of USB, level*/
-    ETS_RTC_CORE_INTR_SOURCE,                   /**< interrupt of rtc core, level, include rtc watchdog*/
-    ETS_RMT_INTR_SOURCE,                        /**< interrupt of remote controller, level*/
-    ETS_PCNT_INTR_SOURCE,                       /**< interrupt of pluse count, level*/
-    ETS_I2C_EXT0_INTR_SOURCE,                   /**< interrupt of I2C controller1, level*/
-    ETS_I2C_EXT1_INTR_SOURCE,                   /**< interrupt of I2C controller0, level*/
-    ETS_RSA_INTR_SOURCE,                        /**< interrupt of RSA accelerator, level*/
-    ETS_SPI1_DMA_INTR_SOURCE,                   /**< interrupt of SPI1 DMA, SPI1 is for flash read/write, do not use this*/
-    ETS_SPI2_DMA_INTR_SOURCE,                   /**< interrupt of SPI2 DMA, level*/
-    ETS_SPI3_DMA_INTR_SOURCE,                   /**< interrupt of SPI3 DMA, level*/
-    ETS_WDT_INTR_SOURCE,                        /**< will be cancelled*/
-    ETS_TIMER1_INTR_SOURCE,                     /**< will be cancelled*/
-    ETS_TIMER2_INTR_SOURCE,                     /**< will be cancelled*/
-    ETS_TG0_T0_EDGE_INTR_SOURCE,                /**< interrupt of TIMER_GROUP0, TIMER0, EDGE*/
-    ETS_TG0_T1_EDGE_INTR_SOURCE,                /**< interrupt of TIMER_GROUP0, TIMER1, EDGE*/
-    ETS_TG0_WDT_EDGE_INTR_SOURCE,               /**< interrupt of TIMER_GROUP0, WATCH DOG, EDGE*/
-
-    ETS_TG0_LACT_EDGE_INTR_SOURCE = 64,         /**< interrupt of TIMER_GROUP0, LACT, EDGE*/
-    ETS_TG1_T0_EDGE_INTR_SOURCE,                /**< interrupt of TIMER_GROUP1, TIMER0, EDGE*/
-    ETS_TG1_T1_EDGE_INTR_SOURCE,                /**< interrupt of TIMER_GROUP1, TIMER1, EDGE*/
-    ETS_TG1_WDT_EDGE_INTR_SOURCE,               /**< interrupt of TIMER_GROUP1, WATCHDOG, EDGE*/
-    ETS_TG1_LACT_EDGE_INTR_SOURCE,              /**< interrupt of TIMER_GROUP0, LACT, EDGE*/
-    ETS_CACHE_IA_INTR_SOURCE,                   /**< interrupt of Cache Invalied Access, LEVEL*/
-    ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE,      /**< interrupt of system timer 0, EDGE*/
-    ETS_SYSTIMER_TARGET1_EDGE_INTR_SOURCE,      /**< interrupt of system timer 1, EDGE*/
-    ETS_SYSTIMER_TARGET2_EDGE_INTR_SOURCE,      /**< interrupt of system timer 2, EDGE*/
-    ETS_ASSIST_DEBUG_INTR_SOURCE,               /**< interrupt of Assist debug module, LEVEL*/
-    ETS_PMS_PRO_IRAM0_ILG_INTR_SOURCE,          /**< interrupt of illegal IRAM1 access, LEVEL*/
-    ETS_PMS_PRO_DRAM0_ILG_INTR_SOURCE,          /**< interrupt of illegal DRAM0 access, LEVEL*/
-    ETS_PMS_PRO_DPORT_ILG_INTR_SOURCE,          /**< interrupt of illegal DPORT access, LEVEL*/
-    ETS_PMS_PRO_AHB_ILG_INTR_SOURCE,            /**< interrupt of illegal AHB access, LEVEL*/
-    ETS_PMS_PRO_CACHE_ILG_INTR_SOURCE,          /**< interrupt of illegal CACHE access, LEVEL*/
-    ETS_PMS_DMA_APB_I_ILG_INTR_SOURCE,          /**< interrupt of illegal APB access, LEVEL*/
-
-    ETS_PMS_DMA_RX_I_ILG_INTR_SOURCE = 80,      /**< interrupt of illegal DMA RX access, LEVEL*/
-    ETS_PMS_DMA_TX_I_ILG_INTR_SOURCE,           /**< interrupt of illegal DMA TX access, LEVEL*/
-    ETS_SPI0_REJECT_CACHE_INTR_SOURCE,          /**< interrupt of SPI0 Cache access rejected, LEVEL*/
-    ETS_SPI1_REJECT_CPU_INTR_SOURCE,            /**< interrupt of SPI1 access rejected, LEVEL*/
-    ETS_DMA_COPY_INTR_SOURCE,                   /**< interrupt of DMA copy, LEVEL*/
-    ETS_SPI4_DMA_INTR_SOURCE,                   /**< interrupt of SPI4 DMA, LEVEL*/
-    ETS_SPI4_INTR_SOURCE,                       /**< interrupt of SPI4, LEVEL*/
-    ETS_MAX_INTR_SOURCE,                        /**< number of interrupt sources */
-
-} periph_interrput_t;
-
 #ifdef __cplusplus
 }
 #endif

components/soc/esp32s2beta/include/soc/soc.h

@@ -218,6 +218,97 @@
 #define SOC_MEM_INTERNAL_LOW        0x3FF9E000
 #define SOC_MEM_INTERNAL_HIGH       0x40072000
 
+//Interrupt hardware source table
+//This table is decided by hardware, don't touch this.
+#define ETS_WIFI_MAC_INTR_SOURCE                    0/**< interrupt of WiFi MAC, level*/
+#define ETS_WIFI_MAC_NMI_SOURCE                     1/**< interrupt of WiFi MAC, NMI, use if MAC have bug to fix in NMI*/
+#define ETS_WIFI_PWR_INTR_SOURCE                    2/**< */
+#define ETS_WIFI_BB_INTR_SOURCE                     3/**< interrupt of WiFi BB, level, we can do some calibartion*/
+#define ETS_BT_MAC_INTR_SOURCE                      4/**< will be cancelled*/
+#define ETS_BT_BB_INTR_SOURCE                       5/**< interrupt of BT BB, level*/
+#define ETS_BT_BB_NMI_SOURCE                        6/**< interrupt of BT BB, NMI, use if BB have bug to fix in NMI*/
+#define ETS_RWBT_INTR_SOURCE                        7/**< interrupt of RWBT, level*/
+#define ETS_RWBLE_INTR_SOURCE                       8/**< interrupt of RWBLE, level*/
+#define ETS_RWBT_NMI_SOURCE                         9/**< interrupt of RWBT, NMI, use if RWBT have bug to fix in NMI*/
+#define ETS_RWBLE_NMI_SOURCE                        10/**< interrupt of RWBLE, NMI, use if RWBT have bug to fix in NMI*/
+#define ETS_SLC0_INTR_SOURCE                        11/**< interrupt of SLC0, level*/
+#define ETS_SLC1_INTR_SOURCE                        12/**< interrupt of SLC1, level*/
+#define ETS_UHCI0_INTR_SOURCE                       13/**< interrupt of UHCI0, level*/
+#define ETS_UHCI1_INTR_SOURCE                       14/**< interrupt of UHCI1, level*/
+#define ETS_TG0_T0_LEVEL_INTR_SOURCE                15/**< interrupt of TIMER_GROUP0, TIMER0, level, we would like use EDGE for timer if permission*/
+#define ETS_TG0_T1_LEVEL_INTR_SOURCE                16/**< interrupt of TIMER_GROUP0, TIMER1, level, we would like use EDGE for timer if permission*/
+#define ETS_TG0_WDT_LEVEL_INTR_SOURCE               17/**< interrupt of TIMER_GROUP0, WATCHDOG, level*/
+#define ETS_TG0_LACT_LEVEL_INTR_SOURCE              18/**< interrupt of TIMER_GROUP0, LACT, level*/
+#define ETS_TG1_T0_LEVEL_INTR_SOURCE                19/**< interrupt of TIMER_GROUP1, TIMER0, level, we would like use EDGE for timer if permission*/
+#define ETS_TG1_T1_LEVEL_INTR_SOURCE                20/**< interrupt of TIMER_GROUP1, TIMER1, level, we would like use EDGE for timer if permission*/
+#define ETS_TG1_WDT_LEVEL_INTR_SOURCE               21/**< interrupt of TIMER_GROUP1, WATCHDOG, level*/
+#define ETS_TG1_LACT_LEVEL_INTR_SOURCE              22/**< interrupt of TIMER_GROUP1, LACT, level*/
+#define ETS_GPIO_INTR_SOURCE                        23/**< interrupt of GPIO, level*/
+#define ETS_GPIO_NMI_SOURCE                         24/**< interrupt of GPIO, NMI*/
+#define ETS_GPIO_INTR_SOURCE2                       25/**< interrupt of GPIO, level*/
+#define ETS_GPIO_NMI_SOURCE2                        26/**< interrupt of GPIO, NMI*/
+#define ETS_DEDICATED_GPIO_INTR_SOURCE              27/**< interrupt of dedicated GPIO, level*/
+#define ETS_FROM_CPU_INTR0_SOURCE                   28/**< interrupt0 generated from a CPU, level*/ /* Used for FreeRTOS */
+#define ETS_FROM_CPU_INTR1_SOURCE                   29/**< interrupt1 generated from a CPU, level*/ /* Used for FreeRTOS */
+#define ETS_FROM_CPU_INTR2_SOURCE                   30/**< interrupt2 generated from a CPU, level*/ /* Used for DPORT Access */
+#define ETS_FROM_CPU_INTR3_SOURCE                   31/**< interrupt3 generated from a CPU, level*/ /* Used for DPORT Access */
+#define ETS_SPI1_INTR_SOURCE                        32/**< interrupt of SPI1, level, SPI1 is for flash read/write, do not use this*/
+#define ETS_SPI2_INTR_SOURCE                        33/**< interrupt of SPI2, level*/
+#define ETS_SPI3_INTR_SOURCE                        34/**< interrupt of SPI3, level*/
+#define ETS_I2S0_INTR_SOURCE                        35/**< interrupt of I2S0, level*/
+#define ETS_I2S1_INTR_SOURCE                        36/**< interrupt of I2S1, level*/
+#define ETS_UART0_INTR_SOURCE                       37/**< interrupt of UART0, level*/
+#define ETS_UART1_INTR_SOURCE                       38/**< interrupt of UART1, level*/
+#define ETS_UART2_INTR_SOURCE                       39/**< interrupt of UART2, level*/
+#define ETS_SDIO_HOST_INTR_SOURCE                   40/**< interrupt of SD/SDIO/MMC HOST, level*/
+#define ETS_PWM0_INTR_SOURCE                        41/**< interrupt of PWM0, level, Reserved*/
+#define ETS_PWM1_INTR_SOURCE                        42/**< interrupt of PWM1, level, Reserved*/
+#define ETS_PWM2_INTR_SOURCE                        43/**< interrupt of PWM2, level*/
+#define ETS_PWM3_INTR_SOURCE                        44/**< interruot of PWM3, level*/
+#define ETS_LEDC_INTR_SOURCE                        45/**< interrupt of LED PWM, level*/
+#define ETS_EFUSE_INTR_SOURCE                       46/**< interrupt of efuse, level, not likely to use*/
+#define ETS_CAN_INTR_SOURCE                         47/**< interrupt of can, level*/
+#define ETS_USB_INTR_SOURCE                         48/**< interrupt of USB, level*/
+#define ETS_RTC_CORE_INTR_SOURCE                    49/**< interrupt of rtc core, level, include rtc watchdog*/
+#define ETS_RMT_INTR_SOURCE                         50/**< interrupt of remote controller, level*/
+#define ETS_PCNT_INTR_SOURCE                        51/**< interrupt of pluse count, level*/
+#define ETS_I2C_EXT0_INTR_SOURCE                    52/**< interrupt of I2C controller1, level*/
+#define ETS_I2C_EXT1_INTR_SOURCE                    53/**< interrupt of I2C controller0, level*/
+#define ETS_RSA_INTR_SOURCE                         54/**< interrupt of RSA accelerator, level*/
+#define ETS_SPI1_DMA_INTR_SOURCE                    55/**< interrupt of SPI1 DMA, SPI1 is for flash read/write, do not use this*/
+#define ETS_SPI2_DMA_INTR_SOURCE                    56/**< interrupt of SPI2 DMA, level*/
+#define ETS_SPI3_DMA_INTR_SOURCE                    57/**< interrupt of SPI3 DMA, level*/
+#define ETS_WDT_INTR_SOURCE                         58/**< will be cancelled*/
+#define ETS_TIMER1_INTR_SOURCE                      59/**< will be cancelled*/
+#define ETS_TIMER2_INTR_SOURCE                      60/**< will be cancelled*/
+#define ETS_TG0_T0_EDGE_INTR_SOURCE                 61/**< interrupt of TIMER_GROUP0, TIMER0, EDGE*/
+#define ETS_TG0_T1_EDGE_INTR_SOURCE                 62/**< interrupt of TIMER_GROUP0, TIMER1, EDGE*/
+#define ETS_TG0_WDT_EDGE_INTR_SOURCE                63/**< interrupt of TIMER_GROUP0, WATCH DOG, EDGE*/
+#define ETS_TG0_LACT_EDGE_INTR_SOURCE               64/**< interrupt of TIMER_GROUP0, LACT, EDGE*/
+#define ETS_TG1_T0_EDGE_INTR_SOURCE                 65/**< interrupt of TIMER_GROUP1, TIMER0, EDGE*/
+#define ETS_TG1_T1_EDGE_INTR_SOURCE                 66/**< interrupt of TIMER_GROUP1, TIMER1, EDGE*/
+#define ETS_TG1_WDT_EDGE_INTR_SOURCE                67/**< interrupt of TIMER_GROUP1, WATCHDOG, EDGE*/
+#define ETS_TG1_LACT_EDGE_INTR_SOURCE               68/**< interrupt of TIMER_GROUP0, LACT, EDGE*/
+#define ETS_CACHE_IA_INTR_SOURCE                    69/**< interrupt of Cache Invalied Access, LEVEL*/
+#define ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE       70/**< interrupt of system timer 0, EDGE*/
+#define ETS_SYSTIMER_TARGET1_EDGE_INTR_SOURCE       71/**< interrupt of system timer 1, EDGE*/
+#define ETS_SYSTIMER_TARGET2_EDGE_INTR_SOURCE       72/**< interrupt of system timer 2, EDGE*/
+#define ETS_ASSIST_DEBUG_INTR_SOURCE                73/**< interrupt of Assist debug module, LEVEL*/
+#define ETS_PMS_PRO_IRAM0_ILG_INTR_SOURCE           74/**< interrupt of illegal IRAM1 access, LEVEL*/
+#define ETS_PMS_PRO_DRAM0_ILG_INTR_SOURCE           75/**< interrupt of illegal DRAM0 access, LEVEL*/
+#define ETS_PMS_PRO_DPORT_ILG_INTR_SOURCE           76/**< interrupt of illegal DPORT access, LEVEL*/
+#define ETS_PMS_PRO_AHB_ILG_INTR_SOURCE             77/**< interrupt of illegal AHB access, LEVEL*/
+#define ETS_PMS_PRO_CACHE_ILG_INTR_SOURCE           78/**< interrupt of illegal CACHE access, LEVEL*/
+#define ETS_PMS_DMA_APB_I_ILG_INTR_SOURCE           79/**< interrupt of illegal APB access, LEVEL*/
+#define ETS_PMS_DMA_RX_I_ILG_INTR_SOURCE            80/**< interrupt of illegal DMA RX access, LEVEL*/
+#define ETS_PMS_DMA_TX_I_ILG_INTR_SOURCE            81/**< interrupt of illegal DMA TX access, LEVEL*/
+#define ETS_SPI0_REJECT_CACHE_INTR_SOURCE           82/**< interrupt of SPI0 Cache access rejected, LEVEL*/
+#define ETS_SPI1_REJECT_CPU_INTR_SOURCE             83/**< interrupt of SPI1 access rejected, LEVEL*/
+#define ETS_DMA_COPY_INTR_SOURCE                    84/**< interrupt of DMA copy, LEVEL*/
+#define ETS_SPI4_DMA_INTR_SOURCE                    85/**< interrupt of SPI4 DMA, LEVEL*/
+#define ETS_SPI4_INTR_SOURCE                        86/**< interrupt of SPI4, LEVEL*/
+#define ETS_MAX_INTR_SOURCE                         87/**< number of interrupt sources */
+
 //interrupt cpu using table, Please see the core-isa.h
 /*************************************************************************************************************
  *      Intr num                Level           Type                    PRO CPU usage           APP CPU uasge

components/soc/esp32s2beta/interrupts.c

@@ -0,0 +1,105 @@
+// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include "soc/interrupts.h"
+
+const char * const esp_isr_names[ETS_MAX_INTR_SOURCE] = {
+    [0] = "WIFI_MAC",
+    [1] = "WIFI_NMI",
+    [2] = "WIFI_PWR",
+    [3] = "WIFI_BB",
+    [4] = "BT_MAC",
+    [5] = "BT_BB",
+    [6] = "BT_BB_NMI",
+    [7] = "RWBT",
+    [8] = "RWBLE",
+    [9] = "RWBT_NMI",
+    [10] = "RWBLE_NMI",
+    [11] = "SLC0",
+    [12] = "SLC1",
+    [13] = "UHCI0",
+    [14] = "UHCI1",
+    [15] = "TG0_T0_LEVEL",
+    [16] = "TG0_T1_LEVEL",
+    [17] = "TG0_WDT_LEVEL",
+    [18] = "TG0_LACT_LEVEL",
+    [19] = "TG1_T0_LEVEL",
+    [20] = "TG1_T1_LEVEL",
+    [21] = "TG1_WDT_LEVEL",
+    [22] = "TG1_LACT_LEVEL",
+    [23] = "GPIO",
+    [24] = "GPIO_NMI",
+    [25] = "GPIO_INTR_2",
+    [26] = "GPIO_NMI_2",
+    [27] = "DEDICATED_GPIO",
+    [28] = "FROM_CPU_INTR0",
+    [29] = "FROM_CPU_INTR1",
+    [30] = "FROM_CPU_INTR2",
+    [31] = "FROM_CPU_INTR3",
+    [32] = "SPI1",
+    [33] = "SPI2",
+    [34] = "SPI3",
+    [35] = "I2S0",
+    [36] = "I2S1",
+    [37] = "UART0",
+    [38] = "UART1",
+    [39] = "UART2",
+    [40] = "SDIO_HOST",
+    [41] = "PWM0",
+    [42] = "PWM1",
+    [43] = "PWM2",
+    [44] = "PWM3",
+    [45] = "LEDC",
+    [46] = "EFUSE",
+    [47] = "CAN",
+    [48] = "USB",
+    [49] = "RTC_CORE",
+    [50] = "RMT",
+    [51] = "PCNT",
+    [52] = "I2C_EXT0",
+    [53] = "I2C_EXT1",
+    [54] = "RSA",
+    [55] = "SPI1_DMA",
+    [56] = "SPI2_DMA",
+    [57] = "SPI3_DMA",
+    [58] = "WDT",
+    [59] = "TIMER1",
+    [60] = "TIMER2",
+    [61] = "TG0_T0_EDGE",
+    [62] = "TG0_T1_EDGE",
+    [63] = "TG0_WDT_EDGE",
+    [64] = "TG0_LACT_EDGE",
+    [65] = "TG1_T0_EDGE",
+    [66] = "TG1_T1_EDGE",
+    [67] = "TG1_WDT_EDGE",
+    [68] = "TG1_LACT_EDGE",
+    [69] = "CACHE_IA",
+    [70] = "SYSTIMER_TARGET0",
+    [71] = "SYSTIMER_TARGET1",
+    [72] = "SYSTIMER_TARGET2",
+    [73] = "ASSIST_DEBUG",
+    [74] = "PMS_PRO_IRAM0_ILG",
+    [75] = "PMS_PRO_DRAM0_ILG",
+    [76] = "PMS_PRO_DPORT_ILG",
+    [77] = "PMS_PRO_AHB_ILG",
+    [78] = "PMS_PRO_CACHE_ILG",
+    [79] = "PMS_DMA_APB_I_ILG",
+    [80] = "PMS_DMA_RX_I_ILG",
+    [81] = "PMS_DMA_TX_I_ILG",
+    [82] = "SPI0_REJECT_CACHE",
+    [83] = "SPI1_REJECT_CPU",
+    [84] = "DMA_COPY",
+    [85] = "SPI4_DMA",
+    [86] = "SPI4",
+};

components/soc/esp32s2beta/rtc_clk.c

@@ -37,7 +37,7 @@
 
 /* Frequency of the 8M oscillator is 8.5MHz +/- 5%, at the default DCAP setting */
 #define RTC_FAST_CLK_FREQ_8M        8500000
-#define RTC_SLOW_CLK_FREQ_150K      150000
+#define RTC_SLOW_CLK_FREQ_90K       90000
 #define RTC_SLOW_CLK_FREQ_8MD256    (RTC_FAST_CLK_FREQ_8M / 256)
 #define RTC_SLOW_CLK_FREQ_32K       32768
 
@@ -314,7 +314,7 @@ rtc_slow_freq_t rtc_clk_slow_freq_get(void)
 uint32_t rtc_clk_slow_freq_get_hz(void)
 {
     switch(rtc_clk_slow_freq_get()) {
-        case RTC_SLOW_FREQ_RTC: return RTC_SLOW_CLK_FREQ_150K;
+        case RTC_SLOW_FREQ_RTC: return RTC_SLOW_CLK_FREQ_90K;
         case RTC_SLOW_FREQ_32K_XTAL: return RTC_SLOW_CLK_FREQ_32K;
         case RTC_SLOW_FREQ_8MD256: return RTC_SLOW_CLK_FREQ_8MD256;
     }

components/soc/esp32s2beta/rtc_wdt.c

@@ -14,6 +14,7 @@
 
 #include "soc/rtc_wdt.h"
 #include "soc/rtc.h"
+#include "soc/efuse_periph.h"
 
 
 bool rtc_wdt_get_protect_status(void)
@@ -94,6 +95,9 @@ esp_err_t rtc_wdt_set_time(rtc_wdt_stage_t stage, unsigned int timeout_ms)
         return ESP_ERR_INVALID_ARG;
     }
     uint32_t timeout = (uint32_t) ((uint64_t) rtc_clk_slow_freq_get_hz() * timeout_ms / 1000);
+    if (stage == RTC_WDT_STAGE0) {
+        timeout = timeout >> (1 + REG_GET_FIELD(EFUSE_RD_REPEAT_DATA1_REG, EFUSE_WDT_DELAY_SEL));
+    }
     WRITE_PERI_REG(get_addr_reg(stage), timeout);
     return ESP_OK;
 }

components/soc/esp32s2beta/sources.cmake

@@ -7,6 +7,7 @@ set(SOC_SRCS    "cpu_util.c"
                 "rtc_sleep.c"
                 "rtc_time.c"
                 "rtc_wdt.c"
+                "interrupts.c"
                 "soc_memory_layout.c"
                 "spi_periph.c"
                 "ledc_periph.c"

components/soc/include/soc/interrupts.h

@@ -0,0 +1,28 @@
+// Copyright 2018 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+#include "stdint.h"
+#include "soc/soc.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+extern const char * const esp_isr_names[ETS_MAX_INTR_SOURCE];
+
+#ifdef __cplusplus
+}
+#endif