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@@ -73,8 +73,31 @@ static const char *RTC_MODULE_TAG = "RTC_MODULE";
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return ESP_FAIL;\
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}
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+#define ADC2_CHECK_FUNCTION_RET(fun_ret) do { if(fun_ret!=ESP_OK){\
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+ ESP_LOGE(RTC_MODULE_TAG,"%s:%d\n",__FUNCTION__,__LINE__);\
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+ return ESP_FAIL;\
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+} }while (0)
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+
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portMUX_TYPE rtc_spinlock = portMUX_INITIALIZER_UNLOCKED;
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static SemaphoreHandle_t rtc_touch_mux = NULL;
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+/*
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+In ADC2, there're two locks used for different cases:
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+1. lock shared with app and WIFI:
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+ when wifi using the ADC2, we assume it will never stop,
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+ so app checks the lock and returns immediately if failed.
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+
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+2. lock shared between tasks:
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+ when several tasks sharing the ADC2, we want to guarantee
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+ all the requests will be handled.
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+ Since conversions are short (about 31us), app returns the lock very soon,
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+ we use a spinlock to stand there waiting to do conversions one by one.
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+
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+adc2_spinlock should be acquired first, then adc2_wifi_lock or rtc_spinlock.
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+*/
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+//prevent ADC2 being used by wifi and other tasks at the same time.
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+static _lock_t adc2_wifi_lock = NULL;
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+//prevent ADC2 being used by tasks (regardless of WIFI)
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+portMUX_TYPE adc2_spinlock = portMUX_INITIALIZER_UNLOCKED;
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typedef struct {
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TimerHandle_t timer;
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@@ -903,44 +926,8 @@ esp_err_t touch_pad_filter_delete()
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}
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/*---------------------------------------------------------------
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- ADC
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+ ADC Common
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---------------------------------------------------------------*/
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-static esp_err_t adc1_pad_get_io_num(adc1_channel_t channel, gpio_num_t *gpio_num)
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-{
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- RTC_MODULE_CHECK(channel < ADC1_CHANNEL_MAX, "ADC Channel Err", ESP_ERR_INVALID_ARG);
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-
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- switch (channel) {
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- case ADC1_CHANNEL_0:
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- *gpio_num = ADC1_CHANNEL_0_GPIO_NUM;
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- break;
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- case ADC1_CHANNEL_1:
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- *gpio_num = ADC1_CHANNEL_1_GPIO_NUM;
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- break;
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- case ADC1_CHANNEL_2:
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- *gpio_num = ADC1_CHANNEL_2_GPIO_NUM;
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- break;
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- case ADC1_CHANNEL_3:
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- *gpio_num = ADC1_CHANNEL_3_GPIO_NUM;
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- break;
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- case ADC1_CHANNEL_4:
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- *gpio_num = ADC1_CHANNEL_4_GPIO_NUM;
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- break;
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- case ADC1_CHANNEL_5:
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- *gpio_num = ADC1_CHANNEL_5_GPIO_NUM;
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- break;
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- case ADC1_CHANNEL_6:
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- *gpio_num = ADC1_CHANNEL_6_GPIO_NUM;
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- break;
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- case ADC1_CHANNEL_7:
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- *gpio_num = ADC1_CHANNEL_7_GPIO_NUM;
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- break;
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- default:
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- return ESP_ERR_INVALID_ARG;
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- }
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-
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- return ESP_OK;
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-}
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-
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static esp_err_t adc_set_fsm_time(int rst_wait, int start_wait, int standby_wait, int sample_cycle)
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{
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portENTER_CRITICAL(&rtc_spinlock);
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@@ -1034,9 +1021,7 @@ static esp_err_t adc_set_atten(adc_unit_t adc_unit, adc_channel_t channel, adc_a
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void adc_power_on()
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{
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portENTER_CRITICAL(&rtc_spinlock);
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- //Bit1 0:Fsm 1: SW mode
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- //Bit0 0:SW mode power down 1: SW mode power on
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- SENS.sar_meas_wait2.force_xpd_sar = ADC_FORCE_ENABLE;
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+ SENS.sar_meas_wait2.force_xpd_sar = ADC_FORCE_FSM;
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portEXIT_CRITICAL(&rtc_spinlock);
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}
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@@ -1115,6 +1100,9 @@ esp_err_t adc_set_data_width(adc_unit_t adc_unit, adc_bits_width_t bits)
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return ESP_OK;
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}
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+/*-------------------------------------------------------------------------------------
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+ * ADC I2S
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+ *------------------------------------------------------------------------------------*/
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static esp_err_t adc_set_i2s_data_len(adc_unit_t adc_unit, int patt_len)
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{
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ADC_CHECK_UNIT(adc_unit);
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@@ -1195,6 +1183,45 @@ esp_err_t adc_i2s_mode_init(adc_unit_t adc_unit, adc_channel_t channel)
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return ESP_OK;
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}
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+/*-------------------------------------------------------------------------------------
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+ * ADC1
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+ *------------------------------------------------------------------------------------*/
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+esp_err_t adc1_pad_get_io_num(adc1_channel_t channel, gpio_num_t *gpio_num)
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+{
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+ RTC_MODULE_CHECK(channel < ADC1_CHANNEL_MAX, "ADC1 Channel Err", ESP_ERR_INVALID_ARG);
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+
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+ switch (channel) {
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+ case ADC1_CHANNEL_0:
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+ *gpio_num = ADC1_CHANNEL_0_GPIO_NUM;
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+ break;
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+ case ADC1_CHANNEL_1:
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+ *gpio_num = ADC1_CHANNEL_1_GPIO_NUM;
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+ break;
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+ case ADC1_CHANNEL_2:
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+ *gpio_num = ADC1_CHANNEL_2_GPIO_NUM;
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+ break;
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+ case ADC1_CHANNEL_3:
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+ *gpio_num = ADC1_CHANNEL_3_GPIO_NUM;
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+ break;
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+ case ADC1_CHANNEL_4:
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+ *gpio_num = ADC1_CHANNEL_4_GPIO_NUM;
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+ break;
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+ case ADC1_CHANNEL_5:
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+ *gpio_num = ADC1_CHANNEL_5_GPIO_NUM;
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+ break;
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+ case ADC1_CHANNEL_6:
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+ *gpio_num = ADC1_CHANNEL_6_GPIO_NUM;
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+ break;
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+ case ADC1_CHANNEL_7:
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+ *gpio_num = ADC1_CHANNEL_7_GPIO_NUM;
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+ break;
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+ default:
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+ return ESP_ERR_INVALID_ARG;
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+ }
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+
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+ return ESP_OK;
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+}
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+
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esp_err_t adc1_config_channel_atten(adc1_channel_t channel, adc_atten_t atten)
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{
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RTC_MODULE_CHECK(channel < ADC1_CHANNEL_MAX, "ADC Channel Err", ESP_ERR_INVALID_ARG);
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@@ -1216,11 +1243,12 @@ int adc1_get_raw(adc1_channel_t channel)
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{
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uint16_t adc_value;
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RTC_MODULE_CHECK(channel < ADC1_CHANNEL_MAX, "ADC Channel Err", ESP_ERR_INVALID_ARG);
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+
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+ adc_power_on();
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+
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portENTER_CRITICAL(&rtc_spinlock);
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//Adc Controler is Rtc module,not ulp coprocessor
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SENS.sar_meas_start1.meas1_start_force = 1;
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- //Bit1=0:Fsm Bit1=1(Bit0=0:PownDown Bit10=1:Powerup)
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- SENS.sar_meas_wait2.force_xpd_sar = 0;
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//Disable Amp Bit1=0:Fsm Bit1=1(Bit0=0:PownDown Bit10=1:Powerup)
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SENS.sar_meas_wait2.force_xpd_amp = 0x2;
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//Open the ADC1 Data port Not ulp coprocessor
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@@ -1249,20 +1277,170 @@ int adc1_get_voltage(adc1_channel_t channel) //Deprecated. Use adc1_get_raw()
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void adc1_ulp_enable(void)
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{
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+ adc_power_on();
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+
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portENTER_CRITICAL(&rtc_spinlock);
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SENS.sar_meas_start1.meas1_start_force = 0;
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SENS.sar_meas_start1.sar1_en_pad_force = 0;
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SENS.sar_meas_wait2.force_xpd_amp = 0x2;
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- SENS.sar_meas_wait2.force_xpd_sar = 0;
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SENS.sar_meas_ctrl.amp_rst_fb_fsm = 0;
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SENS.sar_meas_ctrl.amp_short_ref_fsm = 0;
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SENS.sar_meas_ctrl.amp_short_ref_gnd_fsm = 0;
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SENS.sar_meas_wait1.sar_amp_wait1 = 0x1;
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- SENS.sar_meas_wait1.sar_amp_wait2 = 1;
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+ SENS.sar_meas_wait1.sar_amp_wait2 = 0x1;
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SENS.sar_meas_wait2.sar_amp_wait3 = 0x1;
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portEXIT_CRITICAL(&rtc_spinlock);
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}
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+/*---------------------------------------------------------------
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+ ADC2
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+---------------------------------------------------------------*/
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+esp_err_t adc2_pad_get_io_num(adc2_channel_t channel, gpio_num_t *gpio_num)
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+{
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+ RTC_MODULE_CHECK(channel < ADC2_CHANNEL_MAX, "ADC2 Channel Err", ESP_ERR_INVALID_ARG);
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+
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+ switch (channel) {
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+ case ADC2_CHANNEL_0:
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+ *gpio_num = ADC2_CHANNEL_0_GPIO_NUM;
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+ break;
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+ case ADC2_CHANNEL_1:
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+ *gpio_num = ADC2_CHANNEL_1_GPIO_NUM;
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+ break;
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+ case ADC2_CHANNEL_2:
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+ *gpio_num = ADC2_CHANNEL_2_GPIO_NUM;
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+ break;
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+ case ADC2_CHANNEL_3:
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+ *gpio_num = ADC2_CHANNEL_3_GPIO_NUM;
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+ break;
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+ case ADC2_CHANNEL_4:
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+ *gpio_num = ADC2_CHANNEL_4_GPIO_NUM;
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+ break;
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+ case ADC2_CHANNEL_5:
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+ *gpio_num = ADC2_CHANNEL_5_GPIO_NUM;
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+ break;
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+ case ADC2_CHANNEL_6:
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+ *gpio_num = ADC2_CHANNEL_6_GPIO_NUM;
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+ break;
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+ case ADC2_CHANNEL_7:
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+ *gpio_num = ADC2_CHANNEL_7_GPIO_NUM;
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+ break;
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+ case ADC2_CHANNEL_8:
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+ *gpio_num = ADC2_CHANNEL_8_GPIO_NUM;
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+ break;
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+ case ADC2_CHANNEL_9:
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+ *gpio_num = ADC2_CHANNEL_9_GPIO_NUM;
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+ break;
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+ default:
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+ return ESP_ERR_INVALID_ARG;
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+ }
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+
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+ return ESP_OK;
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+}
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+
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+esp_err_t adc2_wifi_acquire()
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+{
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+ //lazy initialization
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+ //for wifi, block until acquire the lock
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+ _lock_acquire( &adc2_wifi_lock );
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+ ESP_LOGD( RTC_MODULE_TAG, "Wi-Fi takes adc2 lock." );
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+ return ESP_OK;
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+}
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+
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+esp_err_t adc2_wifi_release()
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+{
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+ RTC_MODULE_CHECK((uint32_t*)adc2_wifi_lock != NULL, "wifi release called before acquire", ESP_ERR_INVALID_STATE );
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+
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+ _lock_release( &adc2_wifi_lock );
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+ ESP_LOGD( RTC_MODULE_TAG, "Wi-Fi returns adc2 lock." );
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+ return ESP_OK;
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+}
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+
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+static esp_err_t adc2_pad_init(adc2_channel_t channel)
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|
+{
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+ gpio_num_t gpio_num = 0;
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+ ADC2_CHECK_FUNCTION_RET(adc2_pad_get_io_num(channel, &gpio_num));
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+ ADC2_CHECK_FUNCTION_RET(rtc_gpio_init(gpio_num));
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+ ADC2_CHECK_FUNCTION_RET(rtc_gpio_output_disable(gpio_num));
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+ ADC2_CHECK_FUNCTION_RET(rtc_gpio_input_disable(gpio_num));
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|
+ ADC2_CHECK_FUNCTION_RET(gpio_set_pull_mode(gpio_num, GPIO_FLOATING));
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+ return ESP_OK;
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+}
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+
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+esp_err_t adc2_config_channel_atten(adc2_channel_t channel, adc_atten_t atten)
|
|
|
+{
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|
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+ RTC_MODULE_CHECK(channel < ADC2_CHANNEL_MAX, "ADC2 Channel Err", ESP_ERR_INVALID_ARG);
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+ RTC_MODULE_CHECK(atten <= ADC_ATTEN_11db, "ADC2 Atten Err", ESP_ERR_INVALID_ARG);
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+
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+ adc2_pad_init(channel);
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+ portENTER_CRITICAL( &adc2_spinlock );
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+
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+ //lazy initialization
|
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+ //avoid collision with other tasks
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+ if ( _lock_try_acquire( &adc2_wifi_lock ) == -1 ) {
|
|
|
+ //try the lock, return if failed (wifi using).
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+ portEXIT_CRITICAL( &adc2_spinlock );
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+ return ESP_ERR_TIMEOUT;
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|
+ }
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|
+ SENS.sar_atten2 = ( SENS.sar_atten2 & ~(3<<(channel*2)) ) | ((atten&3) << (channel*2));
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|
|
+ _lock_release( &adc2_wifi_lock );
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+
|
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|
+ portEXIT_CRITICAL( &adc2_spinlock );
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|
+ return ESP_OK;
|
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|
+}
|
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+
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|
|
+static inline void adc2_config_width(adc_bits_width_t width_bit)
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|
|
+{
|
|
|
+ portENTER_CRITICAL(&rtc_spinlock);
|
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|
+ //sar_start_force shared with ADC1
|
|
|
+ SENS.sar_start_force.sar2_bit_width = width_bit;
|
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|
+ portEXIT_CRITICAL(&rtc_spinlock);
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+
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|
|
+ //Invert the adc value,the Output value is invert
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|
+ SENS.sar_read_ctrl2.sar2_data_inv = 1;
|
|
|
+ //Set The adc sample width,invert adc value,must digital sar2_bit_width[1:0]=3
|
|
|
+ SENS.sar_read_ctrl2.sar2_sample_bit = width_bit;
|
|
|
+ //Take the control from WIFI
|
|
|
+ SENS.sar_read_ctrl2.sar2_pwdet_force = 0;
|
|
|
+}
|
|
|
+
|
|
|
+//registers in critical section with adc1:
|
|
|
+//SENS_SAR_START_FORCE_REG,
|
|
|
+esp_err_t adc2_get_raw(adc2_channel_t channel, adc_bits_width_t width_bit, int* raw_out)
|
|
|
+{
|
|
|
+ uint16_t adc_value = 0;
|
|
|
+ RTC_MODULE_CHECK(channel < ADC2_CHANNEL_MAX, "ADC Channel Err", ESP_ERR_INVALID_ARG);
|
|
|
+
|
|
|
+ //in critical section with whole rtc module
|
|
|
+ adc_power_on();
|
|
|
+
|
|
|
+ //avoid collision with other tasks
|
|
|
+ portENTER_CRITICAL(&adc2_spinlock);
|
|
|
+ //lazy initialization
|
|
|
+ //try the lock, return if failed (wifi using).
|
|
|
+ if ( _lock_try_acquire( &adc2_wifi_lock ) == -1 ) {
|
|
|
+ portEXIT_CRITICAL( &adc2_spinlock );
|
|
|
+ return ESP_ERR_TIMEOUT;
|
|
|
+ }
|
|
|
+ //in critical section with whole rtc module
|
|
|
+ adc2_config_width( width_bit );
|
|
|
+
|
|
|
+ //Adc Controler is Rtc module,not ulp coprocessor
|
|
|
+ SENS.sar_meas_start2.meas2_start_force = 1; //force pad mux and force start
|
|
|
+ //Open the ADC2 Data port Not ulp coprocessor
|
|
|
+ SENS.sar_meas_start2.sar2_en_pad_force = 1; //open the ADC2 data port
|
|
|
+ //Select channel
|
|
|
+ SENS.sar_meas_start2.sar2_en_pad = 1 << channel; //pad enable
|
|
|
+ SENS.sar_meas_start2.meas2_start_sar = 0; //start force 0
|
|
|
+ SENS.sar_meas_start2.meas2_start_sar = 1; //start force 1
|
|
|
+ while (SENS.sar_meas_start2.meas2_done_sar == 0) {}; //read done
|
|
|
+ adc_value = SENS.sar_meas_start2.meas2_data_sar;
|
|
|
+ _lock_release( &adc2_wifi_lock );
|
|
|
+ portEXIT_CRITICAL(&adc2_spinlock);
|
|
|
+
|
|
|
+ *raw_out = (int)adc_value;
|
|
|
+ return ESP_OK;
|
|
|
+}
|
|
|
+
|
|
|
esp_err_t adc2_vref_to_gpio(gpio_num_t gpio)
|
|
|
{
|
|
|
int channel;
|
|
|
@@ -1283,19 +1461,19 @@ esp_err_t adc2_vref_to_gpio(gpio_num_t gpio)
|
|
|
rtc_gpio_pullup_dis(gpio);
|
|
|
rtc_gpio_pulldown_dis(gpio);
|
|
|
|
|
|
- SET_PERI_REG_BITS(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN, 0, RTC_CNTL_DBG_ATTEN_S); //Check DBG effect outside sleep mode
|
|
|
+ RTCCNTL.bias_conf.dbg_atten = 0; //Check DBG effect outside sleep mode
|
|
|
//set dtest (MUX_SEL : 0 -> RTC; 1-> vdd_sar2)
|
|
|
- SET_PERI_REG_BITS(RTC_CNTL_TEST_MUX_REG, RTC_CNTL_DTEST_RTC, 1, RTC_CNTL_DTEST_RTC_S); //Config test mux to route v_ref to ADC2 Channels
|
|
|
+ RTCCNTL.test_mux.dtest_rtc = 1; //Config test mux to route v_ref to ADC2 Channels
|
|
|
//set ent
|
|
|
- SET_PERI_REG_MASK(RTC_CNTL_TEST_MUX_REG, RTC_CNTL_ENT_RTC_M);
|
|
|
+ RTCCNTL.test_mux.ent_rtc = 1;
|
|
|
//set sar2_en_test
|
|
|
- SET_PERI_REG_MASK(SENS_SAR_START_FORCE_REG, SENS_SAR2_EN_TEST_M);
|
|
|
+ SENS.sar_start_force.sar2_en_test = 1;
|
|
|
//force fsm
|
|
|
- SET_PERI_REG_BITS(SENS_SAR_MEAS_WAIT2_REG, SENS_FORCE_XPD_SAR, 3, SENS_FORCE_XPD_SAR_S); //Select power source of ADC
|
|
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+ SENS.sar_meas_wait2.force_xpd_sar = ADC_FORCE_ENABLE; //Select power source of ADC
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//set sar2 en force
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- SET_PERI_REG_MASK(SENS_SAR_MEAS_START2_REG, SENS_SAR2_EN_PAD_FORCE_M); //Pad bitmap controlled by SW
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+ SENS.sar_meas_start2.sar2_en_pad_force = 1; //Pad bitmap controlled by SW
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//set en_pad for channels 7,8,9 (bits 0x380)
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- SET_PERI_REG_BITS(SENS_SAR_MEAS_START2_REG, SENS_SAR2_EN_PAD, 1<<channel, SENS_SAR2_EN_PAD_S);
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+ SENS.sar_meas_start2.sar2_en_pad = 1<<channel;
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return ESP_OK;
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}
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@@ -1303,7 +1481,7 @@ esp_err_t adc2_vref_to_gpio(gpio_num_t gpio)
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/*---------------------------------------------------------------
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DAC
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---------------------------------------------------------------*/
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-static esp_err_t dac_pad_get_io_num(dac_channel_t channel, gpio_num_t *gpio_num)
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+esp_err_t dac_pad_get_io_num(dac_channel_t channel, gpio_num_t *gpio_num)
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{
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RTC_MODULE_CHECK((channel >= DAC_CHANNEL_1) && (channel < DAC_CHANNEL_MAX), DAC_ERR_STR_CHANNEL_ERROR, ESP_ERR_INVALID_ARG);
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RTC_MODULE_CHECK(gpio_num, "Param null", ESP_ERR_INVALID_ARG);
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@@ -1446,20 +1624,23 @@ static int hall_sensor_get_value() //hall sensor without LNA
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int Sens_Vp1;
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int Sens_Vn1;
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int hall_value;
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+
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+ adc_power_on();
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portENTER_CRITICAL(&rtc_spinlock);
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- SET_PERI_REG_MASK(SENS_SAR_TOUCH_CTRL1_REG, SENS_XPD_HALL_FORCE_M); // hall sens force enable
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- SET_PERI_REG_MASK(RTC_IO_HALL_SENS_REG, RTC_IO_XPD_HALL); // xpd hall
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- SET_PERI_REG_MASK(SENS_SAR_TOUCH_CTRL1_REG, SENS_HALL_PHASE_FORCE_M); // phase force
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- CLEAR_PERI_REG_MASK(RTC_IO_HALL_SENS_REG, RTC_IO_HALL_PHASE); // hall phase
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+ SENS.sar_touch_ctrl1.xpd_hall_force = 1; // hall sens force enable
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+ RTCIO.hall_sens.xpd_hall = 1; // xpd hall
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+ SENS.sar_touch_ctrl1.hall_phase_force = 1; // phase force
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+
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+ RTCIO.hall_sens.hall_phase = 0; // hall phase
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Sens_Vp0 = adc1_get_raw(ADC1_CHANNEL_0);
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Sens_Vn0 = adc1_get_raw(ADC1_CHANNEL_3);
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- SET_PERI_REG_MASK(RTC_IO_HALL_SENS_REG, RTC_IO_HALL_PHASE);
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+ RTCIO.hall_sens.hall_phase = 1;
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Sens_Vp1 = adc1_get_raw(ADC1_CHANNEL_0);
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Sens_Vn1 = adc1_get_raw(ADC1_CHANNEL_3);
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- SET_PERI_REG_BITS(SENS_SAR_MEAS_WAIT2_REG, SENS_FORCE_XPD_SAR, 0, SENS_FORCE_XPD_SAR_S);
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- CLEAR_PERI_REG_MASK(SENS_SAR_TOUCH_CTRL1_REG, SENS_XPD_HALL_FORCE);
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- CLEAR_PERI_REG_MASK(SENS_SAR_TOUCH_CTRL1_REG, SENS_HALL_PHASE_FORCE);
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+
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+ SENS.sar_touch_ctrl1.xpd_hall_force = 0;
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+ SENS.sar_touch_ctrl1.hall_phase_force = 0;
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portEXIT_CRITICAL(&rtc_spinlock);
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hall_value = (Sens_Vp1 - Sens_Vp0) - (Sens_Vn1 - Sens_Vn0);
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