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@@ -19,20 +19,41 @@
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/** @cond */ //Doxy command to hide preprocessor definitions from docs */
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-// In case the compiler optimise a 32bit instruction (e.g. s32i) into 8/16bit instruction with size optimization enabled
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-// which is not allowed on s2 and later chips (s2, s3, c3, h2)
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-// use these wrappers for manually read-modify-write with l32i and s32i
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-
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-// modify register as uint32_t
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-#define HAL_FORCE_MODIFY_U32_REG_FIELD(base_reg, field, val) \
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+/**
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+ * @brief Macro to force a 32-bit read, modify, then write on a peripheral register
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+ *
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+ * Due to a GCC bug, the compiler may still try to optimize read/writes to peripheral register fields by using 8/16 bit
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+ * access, even if they are marked volatile (i.e., -fstrict-volatile-bitfields has no effect).
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+ *
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+ * For ESP chips, the peripheral bus only allows 32-bit read/writes. The following macro works around the compiler issue
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+ * by forcing a 32-bit read/modify/write.
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+ *
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+ * @note This macro should only be called on register fields of xxx_struct.h type headers, as it depends on the presence
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+ * of a 'val' field of the register union.
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+ * @note Current implementation reads into a uint32_t instead of copy base_reg direclty to temp_reg. The reason being
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+ * that C++ does not create a copy constructor for volatile structs.
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+ */
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+#define HAL_FORCE_MODIFY_U32_REG_FIELD(base_reg, reg_field, field_val) \
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{ \
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- typeof(base_reg) temp_reg = (base_reg); \
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- temp_reg.field = (val); \
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- (base_reg) = temp_reg; \
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+ uint32_t temp_val = base_reg.val; \
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+ typeof(base_reg) temp_reg; \
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+ temp_reg.val = temp_val; \
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+ temp_reg.reg_field = (field_val); \
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+ (base_reg).val = temp_reg.val; \
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}
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-// read register as uint32_t
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-#define HAL_FORCE_READ_U32_REG_FIELD(base_reg, field) \
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-( ((typeof(base_reg))((base_reg).val)).field )
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+/**
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+ * @brief Macro to force a 32-bit read on a peripheral register
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+ *
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+ * @note This macro should only be called on register fields of xxx_struct.h type headers. See description above for
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+ * more details.
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+ * @note Current implementation reads into a uint32_t. See description above for more details.
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+ */
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+#define HAL_FORCE_READ_U32_REG_FIELD(base_reg, reg_field) ({ \
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+ uint32_t temp_val = base_reg.val; \
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+ typeof(base_reg) temp_reg; \
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+ temp_reg.val = temp_val; \
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+ temp_reg.reg_field; \
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+})
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/** @endcond */
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