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@@ -36,6 +36,10 @@
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#include "esp32c2/rom/cache.h"
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#include "soc/extmem_reg.h"
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#include "soc/ext_mem_defs.h"
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+#elif CONFIG_IDF_TARGET_ESP32C6
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+#include "esp32c6/rom/cache.h"
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+#include "soc/extmem_reg.h"
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+#include "soc/ext_mem_defs.h"
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#endif
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#include "esp_rom_spiflash.h"
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#include <soc/soc.h>
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@@ -70,6 +74,14 @@ static void spi_flash_restore_cache(uint32_t cpuid, uint32_t saved_state);
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static uint32_t s_flash_op_cache_state[2];
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+#if CONFIG_IDF_TARGET_ESP32C6
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+/* esp32c6 does not has a register indicating if cache is enabled
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+ * so we use s static data to store to state of cache, every time
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+ * disable/restore api is called, the state will be updated
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+ */
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+static volatile DRAM_ATTR bool s_cache_enabled = 1;
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+#endif
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+
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#ifndef CONFIG_FREERTOS_UNICORE
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static SemaphoreHandle_t s_flash_op_mutex;
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static volatile bool s_flash_op_can_start = false;
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@@ -372,6 +384,11 @@ static void IRAM_ATTR spi_flash_disable_cache(uint32_t cpuid, uint32_t *saved_st
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uint32_t icache_state;
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icache_state = Cache_Suspend_ICache() << 16;
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*saved_state = icache_state;
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+#elif CONFIG_IDF_TARGET_ESP32C6
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+ uint32_t icache_state;
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+ icache_state = Cache_Suspend_ICache();
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+ *saved_state = icache_state;
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+ s_cache_enabled = 0;
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#endif
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}
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@@ -396,6 +413,9 @@ static void IRAM_ATTR spi_flash_restore_cache(uint32_t cpuid, uint32_t saved_sta
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Cache_Resume_ICache(saved_state >> 16);
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#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C2
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Cache_Resume_ICache(saved_state >> 16);
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+#elif CONFIG_IDF_TARGET_ESP32C6
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+ Cache_Resume_ICache(saved_state);
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+ s_cache_enabled = 1;
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#endif
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}
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@@ -410,6 +430,8 @@ IRAM_ATTR bool spi_flash_cache_enabled(void)
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bool result = (REG_GET_BIT(EXTMEM_PRO_ICACHE_CTRL_REG, EXTMEM_PRO_ICACHE_ENABLE) != 0);
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#elif CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C2
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bool result = (REG_GET_BIT(EXTMEM_ICACHE_CTRL_REG, EXTMEM_ICACHE_ENABLE) != 0);
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+#elif CONFIG_IDF_TARGET_ESP32C6
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+ bool result = s_cache_enabled;
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#endif
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return result;
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}
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@@ -523,7 +545,7 @@ esp_err_t esp_enable_cache_wrap(bool icache_wrap_enable, bool dcache_wrap_enable
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int i;
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bool flash_spiram_wrap_together, flash_support_wrap = true, spiram_support_wrap = true;
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uint32_t drom0_in_icache = 1;//always 1 in esp32s2
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-#if CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C2
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+#if CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6
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drom0_in_icache = 0;
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#endif
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@@ -912,7 +934,7 @@ esp_err_t esp_enable_cache_wrap(bool icache_wrap_enable, bool dcache_wrap_enable
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}
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#endif
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-#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C2
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+#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6
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static IRAM_ATTR void esp_enable_cache_flash_wrap(bool icache)
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{
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@@ -954,7 +976,7 @@ esp_err_t esp_enable_cache_wrap(bool icache_wrap_enable)
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}
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return ESP_OK;
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}
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-#endif // CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C2
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+#endif // CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6
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void IRAM_ATTR spi_flash_enable_cache(uint32_t cpuid)
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{
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