Merge branch 'bugfix/simple_ota_example_test' into 'master'

ota: fix ota with flash encryption

Closes IDFGH-4740, IDFCI-442, and IDFCI-448

See merge request espressif/esp-idf!12412

components/spi_flash/esp32/flash_ops_esp32.c

@@ -32,6 +32,7 @@ static inline void IRAM_ATTR spi_flash_guard_end(void)
     }
 }
 
+extern void IRAM_ATTR flash_rom_init(void);
 esp_rom_spiflash_result_t IRAM_ATTR spi_flash_write_encrypted_chip(size_t dest_addr, const void *src, size_t size)
 {
     const uint8_t *ssrc = (const uint8_t *)src;
@@ -73,6 +74,7 @@ esp_rom_spiflash_result_t IRAM_ATTR spi_flash_write_encrypted_chip(size_t dest_a
         }
 
         spi_flash_guard_start();
+        flash_rom_init();
         rc = esp_rom_spiflash_write_encrypted(row_addr, (uint32_t *)encrypt_buf, 32);
         spi_flash_guard_end();
         if (rc != ESP_ROM_SPIFLASH_RESULT_OK) {

components/spi_flash/esp32c3/flash_ops_esp32c3.c

@@ -30,6 +30,7 @@ static const char *TAG = "spiflash_c3";
 #define SPICACHE SPIMEM0
 #define SPIFLASH SPIMEM1
 
+extern void IRAM_ATTR flash_rom_init(void);
 esp_rom_spiflash_result_t IRAM_ATTR spi_flash_write_encrypted_chip(size_t dest_addr, const void *src, size_t size)
 {
     const spi_flash_guard_funcs_t *ops = spi_flash_guard_get();
@@ -69,6 +70,7 @@ esp_rom_spiflash_result_t IRAM_ATTR spi_flash_write_encrypted_chip(size_t dest_a
         if (ops && ops->start) {
             ops->start();
         }
+        flash_rom_init();
         rc = esp_rom_spiflash_write_encrypted(dest_addr, (uint32_t *)src, size);
         if (ops && ops->end) {
             ops->end();

components/spi_flash/esp32s2/flash_ops_esp32s2.c

@@ -30,6 +30,7 @@ static const char *TAG = "spiflash_s2";
 #define SPICACHE SPIMEM0
 #define SPIFLASH SPIMEM1
 
+extern void IRAM_ATTR flash_rom_init(void);
 esp_rom_spiflash_result_t IRAM_ATTR spi_flash_write_encrypted_chip(size_t dest_addr, const void *src, size_t size)
 {
     const spi_flash_guard_funcs_t *ops = spi_flash_guard_get();
@@ -69,6 +70,7 @@ esp_rom_spiflash_result_t IRAM_ATTR spi_flash_write_encrypted_chip(size_t dest_a
         if (ops && ops->start) {
             ops->start();
         }
+        flash_rom_init();
         rc = SPI_Encrypt_Write(dest_addr, src, size);
         if (ops && ops->end) {
             ops->end();

components/spi_flash/esp32s3/flash_ops_esp32s3.c

@@ -30,6 +30,7 @@ static const char *TAG = "spiflash_s3";
 #define SPICACHE SPIMEM0
 #define SPIFLASH SPIMEM1
 
+extern void IRAM_ATTR flash_rom_init(void);
 esp_rom_spiflash_result_t IRAM_ATTR spi_flash_write_encrypted_chip(size_t dest_addr, const void *src, size_t size)
 {
     const spi_flash_guard_funcs_t *ops = spi_flash_guard_get();
@@ -68,6 +69,7 @@ esp_rom_spiflash_result_t IRAM_ATTR spi_flash_write_encrypted_chip(size_t dest_a
         if (ops && ops->start) {
             ops->start();
         }
+        flash_rom_init();
         rc = SPI_Encrypt_Write(dest_addr, src, size);
         if (ops && ops->end) {
             ops->end();

components/spi_flash/flash_ops.c

@@ -510,10 +510,9 @@ out:
 #if !CONFIG_SPI_FLASH_USE_LEGACY_IMPL
 extern void spi_common_set_dummy_output(esp_rom_spiflash_read_mode_t mode);
 extern void spi_dummy_len_fix(uint8_t spi, uint8_t freqdiv);
-static void IRAM_ATTR flash_rom_init(void)
+void IRAM_ATTR flash_rom_init(void)
 {
     uint32_t freqdiv = 0;
-    esp_rom_spiflash_read_mode_t read_mode;
 
 #if CONFIG_IDF_TARGET_ESP32
     uint32_t dummy_bit = 0;
@@ -538,6 +537,8 @@ static void IRAM_ATTR flash_rom_init(void)
     freqdiv = 4;
 #endif
 
+#if !CONFIG_IDF_TARGET_ESP32S2 && !CONFIG_IDF_TARGET_ESP32
+    esp_rom_spiflash_read_mode_t read_mode;
 #if CONFIG_ESPTOOLPY_FLASHMODE_QIO
     read_mode = ESP_ROM_SPIFLASH_QIO_MODE;
 #elif CONFIG_ESPTOOLPY_FLASHMODE_QOUT
@@ -547,6 +548,7 @@ static void IRAM_ATTR flash_rom_init(void)
 #elif CONFIG_ESPTOOLPY_FLASHMODE_DOUT
     read_mode = ESP_ROM_SPIFLASH_DOUT_MODE;
 #endif
+#endif //!CONFIG_IDF_TARGET_ESP32S2 && !CONFIG_IDF_TARGET_ESP32
 
 #if CONFIG_IDF_TARGET_ESP32
     g_rom_spiflash_dummy_len_plus[1] = dummy_bit;
@@ -557,11 +559,10 @@ static void IRAM_ATTR flash_rom_init(void)
 #if !CONFIG_IDF_TARGET_ESP32S2 && !CONFIG_IDF_TARGET_ESP32
     spi_common_set_dummy_output(read_mode);
 #endif //!CONFIG_IDF_TARGET_ESP32S2
-    esp_rom_spiflash_config_readmode(read_mode);
     esp_rom_spiflash_config_clk(freqdiv, 1);
 }
 #else
-static void IRAM_ATTR flash_rom_init(void)
+void IRAM_ATTR flash_rom_init(void)
 {
     return;
 }
@@ -570,7 +571,6 @@ static void IRAM_ATTR flash_rom_init(void)
 esp_err_t IRAM_ATTR spi_flash_write_encrypted(size_t dest_addr, const void *src, size_t size)
 {
     esp_err_t err = ESP_OK;
-    flash_rom_init();
     const spi_flash_guard_funcs_t *guard =  spi_flash_guard_get();
     CHECK_WRITE_ADDRESS(dest_addr, size);
     if ((dest_addr % 16) != 0) {
@@ -817,7 +817,6 @@ out:
 
 esp_err_t IRAM_ATTR spi_flash_read_encrypted(size_t src, void *dstv, size_t size)
 {
-    flash_rom_init();
     if (src + size > g_rom_flashchip.chip_size) {
         return ESP_ERR_INVALID_SIZE;
     }