spi_flash.rst 2.3 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061
  1. .. include:: ../../../components/spi_flash/README.rst
  2. See also
  3. --------
  4. - :doc:`Partition Table documentation <../../api-guides/partition-tables>`
  5. - :doc:`Over The Air Update (OTA) API <../system/ota>` provides high-level API for updating app firmware stored in flash.
  6. - :doc:`Non-Volatile Storage (NVS) API <nvs_flash>` provides a structured API for storing small items of data in SPI flash.
  7. .. _spi-flash-implementation-details:
  8. Implementation details
  9. ----------------------
  10. In order to perform some flash operations, we need to make sure both CPUs
  11. are not running any code from flash for the duration of the flash operation.
  12. In a single-core setup this is easy: we disable interrupts/scheduler and do
  13. the flash operation. In the dual-core setup this is slightly more complicated.
  14. We need to make sure that the other CPU doesn't run any code from flash.
  15. When SPI flash API is called on CPU A (can be PRO or APP), we start
  16. spi_flash_op_block_func function on CPU B using esp_ipc_call API. This API
  17. wakes up high priority task on CPU B and tells it to execute given function,
  18. in this case spi_flash_op_block_func. This function disables cache on CPU B and
  19. signals that cache is disabled by setting s_flash_op_can_start flag.
  20. Then the task on CPU A disables cache as well, and proceeds to execute flash
  21. operation.
  22. While flash operation is running, interrupts can still run on CPUs A and B.
  23. We assume that all interrupt code is placed into RAM. Once interrupt allocation
  24. API is added, we should add a flag to request interrupt to be disabled for
  25. the duration of flash operations.
  26. Once flash operation is complete, function on CPU A sets another flag,
  27. s_flash_op_complete, to let the task on CPU B know that it can re-enable
  28. cache and release the CPU. Then the function on CPU A re-enables the cache on
  29. CPU A as well and returns control to the calling code.
  30. Additionally, all API functions are protected with a mutex (s_flash_op_mutex).
  31. In a single core environment (CONFIG_FREERTOS_UNICORE enabled), we simply
  32. disable both caches, no inter-CPU communication takes place.
  33. API Reference - SPI Flash
  34. -------------------------
  35. .. include:: /_build/inc/esp_spi_flash.inc
  36. API Reference - Partition Table
  37. -------------------------------
  38. .. include:: /_build/inc/esp_partition.inc
  39. API Reference - Flash Encrypt
  40. -----------------------------
  41. .. include:: /_build/inc/esp_flash_encrypt.inc