pm_impl.c 34 KB

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  1. /*
  2. * SPDX-FileCopyrightText: 2016-2023 Espressif Systems (Shanghai) CO LTD
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. */
  6. #include <stdlib.h>
  7. #include <stdbool.h>
  8. #include <string.h>
  9. #include <stdint.h>
  10. #include <sys/param.h>
  11. #include "esp_attr.h"
  12. #include "esp_err.h"
  13. #include "esp_pm.h"
  14. #include "esp_log.h"
  15. #include "esp_cpu.h"
  16. #include "esp_private/crosscore_int.h"
  17. #include "esp_private/uart_private.h"
  18. #include "soc/rtc.h"
  19. #include "hal/uart_ll.h"
  20. #include "hal/uart_types.h"
  21. #include "driver/uart.h"
  22. #include "driver/gpio.h"
  23. #include "freertos/FreeRTOS.h"
  24. #include "freertos/task.h"
  25. #if CONFIG_FREERTOS_SYSTICK_USES_CCOUNT
  26. #include "freertos/xtensa_timer.h"
  27. #include "xtensa/core-macros.h"
  28. #endif
  29. #if SOC_SPI_MEM_SUPPORT_TIMING_TUNING
  30. #include "esp_private/mspi_timing_tuning.h"
  31. #endif
  32. #include "esp_private/pm_impl.h"
  33. #include "esp_private/pm_trace.h"
  34. #include "esp_private/esp_timer_private.h"
  35. #include "esp_private/esp_clk.h"
  36. #include "esp_private/sleep_cpu.h"
  37. #include "esp_private/sleep_gpio.h"
  38. #include "esp_private/sleep_modem.h"
  39. #include "esp_sleep.h"
  40. #include "esp_memory_utils.h"
  41. #include "sdkconfig.h"
  42. #define MHZ (1000000)
  43. #ifdef CONFIG_FREERTOS_SYSTICK_USES_CCOUNT
  44. /* CCOMPARE update timeout, in CPU cycles. Any value above ~600 cycles will work
  45. * for the purpose of detecting a deadlock.
  46. */
  47. #define CCOMPARE_UPDATE_TIMEOUT 1000000
  48. /* When changing CCOMPARE, don't allow changes if the difference is less
  49. * than this. This is to prevent setting CCOMPARE below CCOUNT.
  50. */
  51. #define CCOMPARE_MIN_CYCLES_IN_FUTURE 1000
  52. #endif // CONFIG_FREERTOS_SYSTICK_USES_CCOUNT
  53. /* When light sleep is used, wake this number of microseconds earlier than
  54. * the next tick.
  55. */
  56. #define LIGHT_SLEEP_EARLY_WAKEUP_US 100
  57. #if CONFIG_IDF_TARGET_ESP32
  58. /* Minimal divider at which REF_CLK_FREQ can be obtained */
  59. #define REF_CLK_DIV_MIN 10
  60. #elif CONFIG_IDF_TARGET_ESP32S2
  61. /* Minimal divider at which REF_CLK_FREQ can be obtained */
  62. #define REF_CLK_DIV_MIN 2
  63. #elif CONFIG_IDF_TARGET_ESP32S3
  64. /* Minimal divider at which REF_CLK_FREQ can be obtained */
  65. #define REF_CLK_DIV_MIN 2 // TODO: IDF-5660
  66. #elif CONFIG_IDF_TARGET_ESP32C3
  67. #define REF_CLK_DIV_MIN 2
  68. #elif CONFIG_IDF_TARGET_ESP32C2
  69. #define REF_CLK_DIV_MIN 2
  70. #elif CONFIG_IDF_TARGET_ESP32C6
  71. #define REF_CLK_DIV_MIN 2
  72. #elif CONFIG_IDF_TARGET_ESP32H2
  73. #define REF_CLK_DIV_MIN 2
  74. #elif CONFIG_IDF_TARGET_ESP32P4
  75. #define REF_CLK_DIV_MIN 2
  76. #endif
  77. #ifdef CONFIG_PM_PROFILING
  78. #define WITH_PROFILING
  79. #endif
  80. static portMUX_TYPE s_switch_lock = portMUX_INITIALIZER_UNLOCKED;
  81. /* The following state variables are protected using s_switch_lock: */
  82. /* Current sleep mode; When switching, contains old mode until switch is complete */
  83. static pm_mode_t s_mode = PM_MODE_CPU_MAX;
  84. /* True when switch is in progress */
  85. static volatile bool s_is_switching;
  86. /* Number of times each mode was locked */
  87. static size_t s_mode_lock_counts[PM_MODE_COUNT];
  88. /* Bit mask of locked modes. BIT(i) is set iff s_mode_lock_counts[i] > 0. */
  89. static uint32_t s_mode_mask;
  90. #if CONFIG_FREERTOS_USE_TICKLESS_IDLE
  91. #define PERIPH_SKIP_LIGHT_SLEEP_NO 2
  92. /* Indicates if light sleep shoule be skipped by peripherals. */
  93. static skip_light_sleep_cb_t s_periph_skip_light_sleep_cb[PERIPH_SKIP_LIGHT_SLEEP_NO];
  94. /* Indicates if light sleep entry was skipped in vApplicationSleep for given CPU.
  95. * This in turn gets used in IDLE hook to decide if `waiti` needs
  96. * to be invoked or not.
  97. */
  98. static bool s_skipped_light_sleep[portNUM_PROCESSORS];
  99. #if portNUM_PROCESSORS == 2
  100. /* When light sleep is finished on one CPU, it is possible that the other CPU
  101. * will enter light sleep again very soon, before interrupts on the first CPU
  102. * get a chance to run. To avoid such situation, set a flag for the other CPU to
  103. * skip light sleep attempt.
  104. */
  105. static bool s_skip_light_sleep[portNUM_PROCESSORS];
  106. #endif // portNUM_PROCESSORS == 2
  107. static _lock_t s_skip_light_sleep_lock;
  108. #endif // CONFIG_FREERTOS_USE_TICKLESS_IDLE
  109. /* A flag indicating that Idle hook has run on a given CPU;
  110. * Next interrupt on the same CPU will take s_rtos_lock_handle.
  111. */
  112. static bool s_core_idle[portNUM_PROCESSORS];
  113. /* When no RTOS tasks are active, these locks are released to allow going into
  114. * a lower power mode. Used by ISR hook and idle hook.
  115. */
  116. static esp_pm_lock_handle_t s_rtos_lock_handle[portNUM_PROCESSORS];
  117. /* Lookup table of CPU frequency configs to be used in each mode.
  118. * Initialized by esp_pm_impl_init and modified by esp_pm_configure.
  119. */
  120. static rtc_cpu_freq_config_t s_cpu_freq_by_mode[PM_MODE_COUNT];
  121. /* Whether automatic light sleep is enabled */
  122. static bool s_light_sleep_en = false;
  123. /* When configuration is changed, current frequency may not match the
  124. * newly configured frequency for the current mode. This is an indicator
  125. * to the mode switch code to get the actual current frequency instead of
  126. * relying on the current mode.
  127. */
  128. static bool s_config_changed = false;
  129. #ifdef WITH_PROFILING
  130. /* Time, in microseconds, spent so far in each mode */
  131. static pm_time_t s_time_in_mode[PM_MODE_COUNT];
  132. /* Timestamp, in microseconds, when the mode switch last happened */
  133. static pm_time_t s_last_mode_change_time;
  134. /* User-readable mode names, used by esp_pm_impl_dump_stats */
  135. static const char* s_mode_names[] = {
  136. "SLEEP",
  137. "APB_MIN",
  138. "APB_MAX",
  139. "CPU_MAX"
  140. };
  141. static uint32_t s_light_sleep_counts, s_light_sleep_reject_counts;
  142. #endif // WITH_PROFILING
  143. #ifdef CONFIG_FREERTOS_SYSTICK_USES_CCOUNT
  144. /* Indicates to the ISR hook that CCOMPARE needs to be updated on the given CPU.
  145. * Used in conjunction with cross-core interrupt to update CCOMPARE on the other CPU.
  146. */
  147. static volatile bool s_need_update_ccompare[portNUM_PROCESSORS];
  148. /* Divider and multiplier used to adjust (ccompare - ccount) duration.
  149. * Only set to non-zero values when switch is in progress.
  150. */
  151. static uint32_t s_ccount_div;
  152. static uint32_t s_ccount_mul;
  153. static void update_ccompare(void);
  154. #endif // CONFIG_FREERTOS_SYSTICK_USES_CCOUNT
  155. static const char* TAG = "pm";
  156. static void do_switch(pm_mode_t new_mode);
  157. static void leave_idle(void);
  158. static void on_freq_update(uint32_t old_ticks_per_us, uint32_t ticks_per_us);
  159. pm_mode_t esp_pm_impl_get_mode(esp_pm_lock_type_t type, int arg)
  160. {
  161. (void) arg;
  162. if (type == ESP_PM_CPU_FREQ_MAX) {
  163. return PM_MODE_CPU_MAX;
  164. } else if (type == ESP_PM_APB_FREQ_MAX) {
  165. return PM_MODE_APB_MAX;
  166. } else if (type == ESP_PM_NO_LIGHT_SLEEP) {
  167. return PM_MODE_APB_MIN;
  168. } else {
  169. // unsupported mode
  170. abort();
  171. }
  172. }
  173. #if CONFIG_PM_LIGHT_SLEEP_CALLBACKS
  174. /**
  175. * @brief Function entry parameter types for light sleep callback functions (if CONFIG_FREERTOS_USE_TICKLESS_IDLE)
  176. */
  177. typedef struct {
  178. /**
  179. * Callback function defined by user.
  180. */
  181. esp_pm_light_sleep_cb_t cb;
  182. /**
  183. * Input parameters of callback function defined by user.
  184. */
  185. void *arg;
  186. /**
  187. * Execution priority of callback function defined by user.
  188. */
  189. uint32_t prior;
  190. /**
  191. * Next callback function defined by user.
  192. */
  193. struct _esp_pm_sleep_cb_config_t *next;
  194. } esp_pm_sleep_cb_config_t;
  195. static esp_pm_sleep_cb_config_t *s_light_sleep_enter_cb_config;
  196. static esp_pm_sleep_cb_config_t *s_light_sleep_exit_cb_config;
  197. static portMUX_TYPE s_sleep_pm_cb_mutex = portMUX_INITIALIZER_UNLOCKED;
  198. esp_err_t esp_pm_light_sleep_register_cbs(esp_pm_sleep_cbs_register_config_t *cbs_conf)
  199. {
  200. if (cbs_conf->enter_cb == NULL && cbs_conf->exit_cb == NULL) {
  201. return ESP_ERR_INVALID_ARG;
  202. }
  203. portENTER_CRITICAL(&s_sleep_pm_cb_mutex);
  204. if (cbs_conf->enter_cb != NULL) {
  205. esp_pm_sleep_cb_config_t **current_enter_ptr = &(s_light_sleep_enter_cb_config);
  206. while (*current_enter_ptr != NULL) {
  207. if (((*current_enter_ptr)->cb) == (cbs_conf->enter_cb)) {
  208. portEXIT_CRITICAL(&s_sleep_pm_cb_mutex);
  209. return ESP_FAIL;
  210. }
  211. current_enter_ptr = &((*current_enter_ptr)->next);
  212. }
  213. esp_pm_sleep_cb_config_t *new_enter_config = (esp_pm_sleep_cb_config_t *)heap_caps_malloc(sizeof(esp_pm_sleep_cb_config_t), MALLOC_CAP_INTERNAL);
  214. if (new_enter_config == NULL) {
  215. portEXIT_CRITICAL(&s_sleep_pm_cb_mutex);
  216. return ESP_ERR_NO_MEM; /* Memory allocation failed */
  217. }
  218. new_enter_config->cb = cbs_conf->enter_cb;
  219. new_enter_config->arg = cbs_conf->enter_cb_user_arg;
  220. new_enter_config->prior = cbs_conf->enter_cb_prior;
  221. while (*current_enter_ptr != NULL && (*current_enter_ptr)->prior <= new_enter_config->prior) {
  222. current_enter_ptr = &((*current_enter_ptr)->next);
  223. }
  224. new_enter_config->next = *current_enter_ptr;
  225. *current_enter_ptr = new_enter_config;
  226. }
  227. if (cbs_conf->exit_cb != NULL) {
  228. esp_pm_sleep_cb_config_t **current_exit_ptr = &(s_light_sleep_exit_cb_config);
  229. while (*current_exit_ptr != NULL) {
  230. if (((*current_exit_ptr)->cb) == (cbs_conf->exit_cb)) {
  231. portEXIT_CRITICAL(&s_sleep_pm_cb_mutex);
  232. return ESP_FAIL;
  233. }
  234. current_exit_ptr = &((*current_exit_ptr)->next);
  235. }
  236. esp_pm_sleep_cb_config_t *new_exit_config = (esp_pm_sleep_cb_config_t *)heap_caps_malloc(sizeof(esp_pm_sleep_cb_config_t), MALLOC_CAP_INTERNAL);
  237. if (new_exit_config == NULL) {
  238. portEXIT_CRITICAL(&s_sleep_pm_cb_mutex);
  239. return ESP_ERR_NO_MEM; /* Memory allocation failed */
  240. }
  241. new_exit_config->cb = cbs_conf->exit_cb;
  242. new_exit_config->arg = cbs_conf->exit_cb_user_arg;
  243. new_exit_config->prior = cbs_conf->exit_cb_prior;
  244. while (*current_exit_ptr != NULL && (*current_exit_ptr)->prior <= new_exit_config->prior) {
  245. current_exit_ptr = &((*current_exit_ptr)->next);
  246. }
  247. new_exit_config->next = *current_exit_ptr;
  248. *current_exit_ptr = new_exit_config;
  249. }
  250. portEXIT_CRITICAL(&s_sleep_pm_cb_mutex);
  251. return ESP_OK;
  252. }
  253. esp_err_t esp_pm_light_sleep_unregister_cbs(esp_pm_sleep_cbs_register_config_t *cbs_conf)
  254. {
  255. if (cbs_conf->enter_cb == NULL && cbs_conf->exit_cb == NULL) {
  256. return ESP_ERR_INVALID_ARG;
  257. }
  258. portENTER_CRITICAL(&s_sleep_pm_cb_mutex);
  259. if (cbs_conf->enter_cb != NULL) {
  260. esp_pm_sleep_cb_config_t **current_enter_ptr = &(s_light_sleep_enter_cb_config);
  261. while (*current_enter_ptr != NULL) {
  262. if ((*current_enter_ptr)->cb == cbs_conf->enter_cb) {
  263. esp_pm_sleep_cb_config_t *temp = *current_enter_ptr;
  264. *current_enter_ptr = (*current_enter_ptr)->next;
  265. free(temp);
  266. break;
  267. }
  268. current_enter_ptr = &((*current_enter_ptr)->next);
  269. }
  270. }
  271. if (cbs_conf->exit_cb != NULL) {
  272. esp_pm_sleep_cb_config_t **current_exit_ptr = &(s_light_sleep_exit_cb_config);
  273. while (*current_exit_ptr != NULL) {
  274. if ((*current_exit_ptr)->cb == cbs_conf->exit_cb) {
  275. esp_pm_sleep_cb_config_t *temp = *current_exit_ptr;
  276. *current_exit_ptr = (*current_exit_ptr)->next;
  277. free(temp);
  278. break;
  279. }
  280. current_exit_ptr = &((*current_exit_ptr)->next);
  281. }
  282. }
  283. portEXIT_CRITICAL(&s_sleep_pm_cb_mutex);
  284. return ESP_OK;
  285. }
  286. static esp_err_t IRAM_ATTR esp_pm_execute_enter_sleep_callbacks(int64_t sleep_time_us)
  287. {
  288. esp_pm_sleep_cb_config_t *enter_current = s_light_sleep_enter_cb_config;
  289. while (enter_current != NULL) {
  290. enter_current->cb(sleep_time_us, enter_current->arg);
  291. enter_current = enter_current->next;
  292. }
  293. return ESP_OK;
  294. }
  295. static esp_err_t IRAM_ATTR esp_pm_execute_exit_sleep_callbacks(int64_t sleep_time_us)
  296. {
  297. esp_pm_sleep_cb_config_t *exit_current = s_light_sleep_exit_cb_config;
  298. while (exit_current != NULL) {
  299. exit_current->cb(sleep_time_us, exit_current->arg);
  300. exit_current = exit_current->next;
  301. }
  302. return ESP_OK;
  303. }
  304. #endif
  305. static esp_err_t esp_pm_sleep_configure(const void *vconfig)
  306. {
  307. esp_err_t err = ESP_OK;
  308. const esp_pm_config_t* config = (const esp_pm_config_t*) vconfig;
  309. #if SOC_PM_SUPPORT_CPU_PD
  310. err = sleep_cpu_configure(config->light_sleep_enable);
  311. if (err != ESP_OK) {
  312. return err;
  313. }
  314. #endif
  315. err = sleep_modem_configure(config->max_freq_mhz, config->min_freq_mhz, config->light_sleep_enable);
  316. return err;
  317. }
  318. esp_err_t esp_pm_configure(const void* vconfig)
  319. {
  320. #ifndef CONFIG_PM_ENABLE
  321. return ESP_ERR_NOT_SUPPORTED;
  322. #endif
  323. const esp_pm_config_t* config = (const esp_pm_config_t*) vconfig;
  324. #ifndef CONFIG_FREERTOS_USE_TICKLESS_IDLE
  325. if (config->light_sleep_enable) {
  326. return ESP_ERR_NOT_SUPPORTED;
  327. }
  328. #endif
  329. int min_freq_mhz = config->min_freq_mhz;
  330. int max_freq_mhz = config->max_freq_mhz;
  331. if (min_freq_mhz > max_freq_mhz) {
  332. return ESP_ERR_INVALID_ARG;
  333. }
  334. rtc_cpu_freq_config_t freq_config;
  335. if (!rtc_clk_cpu_freq_mhz_to_config(min_freq_mhz, &freq_config)) {
  336. ESP_LOGW(TAG, "invalid min_freq_mhz value (%d)", min_freq_mhz);
  337. return ESP_ERR_INVALID_ARG;
  338. }
  339. int xtal_freq_mhz = esp_clk_xtal_freq() / MHZ;
  340. if (min_freq_mhz < xtal_freq_mhz && min_freq_mhz * MHZ / REF_CLK_FREQ < REF_CLK_DIV_MIN) {
  341. ESP_LOGW(TAG, "min_freq_mhz should be >= %d", REF_CLK_FREQ * REF_CLK_DIV_MIN / MHZ);
  342. return ESP_ERR_INVALID_ARG;
  343. }
  344. if (!rtc_clk_cpu_freq_mhz_to_config(max_freq_mhz, &freq_config)) {
  345. ESP_LOGW(TAG, "invalid max_freq_mhz value (%d)", max_freq_mhz);
  346. return ESP_ERR_INVALID_ARG;
  347. }
  348. #if CONFIG_IDF_TARGET_ESP32
  349. int apb_max_freq = max_freq_mhz; /* CPU frequency in APB_MAX mode */
  350. if (max_freq_mhz == 240) {
  351. /* We can't switch between 240 and 80/160 without disabling PLL,
  352. * so use 240MHz CPU frequency when 80MHz APB frequency is requested.
  353. */
  354. apb_max_freq = 240;
  355. } else if (max_freq_mhz == 160 || max_freq_mhz == 80) {
  356. /* Otherwise, can use 80MHz
  357. * CPU frequency when 80MHz APB frequency is requested.
  358. */
  359. apb_max_freq = 80;
  360. }
  361. #else
  362. /* Maximum SOC APB clock frequency is 40 MHz, maximum Modem (WiFi,
  363. * Bluetooth, etc..) APB clock frequency is 80 MHz */
  364. int apb_clk_freq = esp_clk_apb_freq() / MHZ;
  365. #if CONFIG_ESP_WIFI_ENABLED || CONFIG_BT_ENABLED || CONFIG_IEEE802154_ENABLED
  366. apb_clk_freq = MAX(apb_clk_freq, MODEM_REQUIRED_MIN_APB_CLK_FREQ / MHZ);
  367. #endif
  368. int apb_max_freq = MIN(max_freq_mhz, apb_clk_freq); /* CPU frequency in APB_MAX mode */
  369. #endif
  370. apb_max_freq = MAX(apb_max_freq, min_freq_mhz);
  371. ESP_LOGI(TAG, "Frequency switching config: "
  372. "CPU_MAX: %d, APB_MAX: %d, APB_MIN: %d, Light sleep: %s",
  373. max_freq_mhz,
  374. apb_max_freq,
  375. min_freq_mhz,
  376. config->light_sleep_enable ? "ENABLED" : "DISABLED");
  377. portENTER_CRITICAL(&s_switch_lock);
  378. bool res __attribute__((unused));
  379. res = rtc_clk_cpu_freq_mhz_to_config(max_freq_mhz, &s_cpu_freq_by_mode[PM_MODE_CPU_MAX]);
  380. assert(res);
  381. res = rtc_clk_cpu_freq_mhz_to_config(apb_max_freq, &s_cpu_freq_by_mode[PM_MODE_APB_MAX]);
  382. assert(res);
  383. res = rtc_clk_cpu_freq_mhz_to_config(min_freq_mhz, &s_cpu_freq_by_mode[PM_MODE_APB_MIN]);
  384. assert(res);
  385. s_cpu_freq_by_mode[PM_MODE_LIGHT_SLEEP] = s_cpu_freq_by_mode[PM_MODE_APB_MIN];
  386. s_light_sleep_en = config->light_sleep_enable;
  387. s_config_changed = true;
  388. portEXIT_CRITICAL(&s_switch_lock);
  389. esp_pm_sleep_configure(config);
  390. return ESP_OK;
  391. }
  392. esp_err_t esp_pm_get_configuration(void* vconfig)
  393. {
  394. if (vconfig == NULL) {
  395. return ESP_ERR_INVALID_ARG;
  396. }
  397. esp_pm_config_t* config = (esp_pm_config_t*) vconfig;
  398. portENTER_CRITICAL(&s_switch_lock);
  399. config->light_sleep_enable = s_light_sleep_en;
  400. config->max_freq_mhz = s_cpu_freq_by_mode[PM_MODE_CPU_MAX].freq_mhz;
  401. config->min_freq_mhz = s_cpu_freq_by_mode[PM_MODE_APB_MIN].freq_mhz;
  402. portEXIT_CRITICAL(&s_switch_lock);
  403. return ESP_OK;
  404. }
  405. static pm_mode_t IRAM_ATTR get_lowest_allowed_mode(void)
  406. {
  407. /* TODO: optimize using ffs/clz */
  408. if (s_mode_mask >= BIT(PM_MODE_CPU_MAX)) {
  409. return PM_MODE_CPU_MAX;
  410. } else if (s_mode_mask >= BIT(PM_MODE_APB_MAX)) {
  411. return PM_MODE_APB_MAX;
  412. } else if (s_mode_mask >= BIT(PM_MODE_APB_MIN) || !s_light_sleep_en) {
  413. return PM_MODE_APB_MIN;
  414. } else {
  415. return PM_MODE_LIGHT_SLEEP;
  416. }
  417. }
  418. void IRAM_ATTR esp_pm_impl_switch_mode(pm_mode_t mode,
  419. pm_mode_switch_t lock_or_unlock, pm_time_t now)
  420. {
  421. bool need_switch = false;
  422. uint32_t mode_mask = BIT(mode);
  423. portENTER_CRITICAL_SAFE(&s_switch_lock);
  424. uint32_t count;
  425. if (lock_or_unlock == MODE_LOCK) {
  426. count = ++s_mode_lock_counts[mode];
  427. } else {
  428. count = s_mode_lock_counts[mode]--;
  429. }
  430. if (count == 1) {
  431. if (lock_or_unlock == MODE_LOCK) {
  432. s_mode_mask |= mode_mask;
  433. } else {
  434. s_mode_mask &= ~mode_mask;
  435. }
  436. need_switch = true;
  437. }
  438. pm_mode_t new_mode = s_mode;
  439. if (need_switch) {
  440. new_mode = get_lowest_allowed_mode();
  441. #ifdef WITH_PROFILING
  442. if (s_last_mode_change_time != 0) {
  443. pm_time_t diff = now - s_last_mode_change_time;
  444. s_time_in_mode[s_mode] += diff;
  445. }
  446. s_last_mode_change_time = now;
  447. #endif // WITH_PROFILING
  448. }
  449. portEXIT_CRITICAL_SAFE(&s_switch_lock);
  450. if (need_switch) {
  451. do_switch(new_mode);
  452. }
  453. }
  454. /**
  455. * @brief Update clock dividers in esp_timer and FreeRTOS, and adjust CCOMPARE
  456. * values on both CPUs.
  457. * @param old_ticks_per_us old CPU frequency
  458. * @param ticks_per_us new CPU frequency
  459. */
  460. static void IRAM_ATTR on_freq_update(uint32_t old_ticks_per_us, uint32_t ticks_per_us)
  461. {
  462. uint32_t old_apb_ticks_per_us = MIN(old_ticks_per_us, 80);
  463. uint32_t apb_ticks_per_us = MIN(ticks_per_us, 80);
  464. /* Update APB frequency value used by the timer */
  465. if (old_apb_ticks_per_us != apb_ticks_per_us) {
  466. esp_timer_private_update_apb_freq(apb_ticks_per_us);
  467. }
  468. #ifdef CONFIG_FREERTOS_SYSTICK_USES_CCOUNT
  469. #ifdef XT_RTOS_TIMER_INT
  470. /* Calculate new tick divisor */
  471. _xt_tick_divisor = ticks_per_us * MHZ / XT_TICK_PER_SEC;
  472. #endif
  473. int core_id = xPortGetCoreID();
  474. if (s_rtos_lock_handle[core_id] != NULL) {
  475. ESP_PM_TRACE_ENTER(CCOMPARE_UPDATE, core_id);
  476. /* ccount_div and ccount_mul are used in esp_pm_impl_update_ccompare
  477. * to calculate new CCOMPARE value.
  478. */
  479. s_ccount_div = old_ticks_per_us;
  480. s_ccount_mul = ticks_per_us;
  481. /* Update CCOMPARE value on this CPU */
  482. update_ccompare();
  483. #if portNUM_PROCESSORS == 2
  484. /* Send interrupt to the other CPU to update CCOMPARE value */
  485. int other_core_id = (core_id == 0) ? 1 : 0;
  486. s_need_update_ccompare[other_core_id] = true;
  487. esp_crosscore_int_send_freq_switch(other_core_id);
  488. int timeout = 0;
  489. while (s_need_update_ccompare[other_core_id]) {
  490. if (++timeout == CCOMPARE_UPDATE_TIMEOUT) {
  491. assert(false && "failed to update CCOMPARE, possible deadlock");
  492. }
  493. }
  494. #endif // portNUM_PROCESSORS == 2
  495. s_ccount_mul = 0;
  496. s_ccount_div = 0;
  497. ESP_PM_TRACE_EXIT(CCOMPARE_UPDATE, core_id);
  498. }
  499. #endif // CONFIG_FREERTOS_SYSTICK_USES_CCOUNT
  500. }
  501. /**
  502. * Perform the switch to new power mode.
  503. * Currently only changes the CPU frequency and adjusts clock dividers.
  504. * No light sleep yet.
  505. * @param new_mode mode to switch to
  506. */
  507. static void IRAM_ATTR do_switch(pm_mode_t new_mode)
  508. {
  509. const int core_id = xPortGetCoreID();
  510. do {
  511. portENTER_CRITICAL_ISR(&s_switch_lock);
  512. if (!s_is_switching) {
  513. break;
  514. }
  515. #ifdef CONFIG_FREERTOS_SYSTICK_USES_CCOUNT
  516. if (s_need_update_ccompare[core_id]) {
  517. s_need_update_ccompare[core_id] = false;
  518. }
  519. #endif
  520. portEXIT_CRITICAL_ISR(&s_switch_lock);
  521. } while (true);
  522. if (new_mode == s_mode) {
  523. portEXIT_CRITICAL_ISR(&s_switch_lock);
  524. return;
  525. }
  526. s_is_switching = true;
  527. bool config_changed = s_config_changed;
  528. s_config_changed = false;
  529. portEXIT_CRITICAL_ISR(&s_switch_lock);
  530. rtc_cpu_freq_config_t new_config = s_cpu_freq_by_mode[new_mode];
  531. rtc_cpu_freq_config_t old_config;
  532. if (!config_changed) {
  533. old_config = s_cpu_freq_by_mode[s_mode];
  534. } else {
  535. rtc_clk_cpu_freq_get_config(&old_config);
  536. }
  537. if (new_config.freq_mhz != old_config.freq_mhz) {
  538. uint32_t old_ticks_per_us = old_config.freq_mhz;
  539. uint32_t new_ticks_per_us = new_config.freq_mhz;
  540. bool switch_down = new_ticks_per_us < old_ticks_per_us;
  541. ESP_PM_TRACE_ENTER(FREQ_SWITCH, core_id);
  542. if (switch_down) {
  543. on_freq_update(old_ticks_per_us, new_ticks_per_us);
  544. }
  545. if (new_config.source == SOC_CPU_CLK_SRC_PLL) {
  546. rtc_clk_cpu_freq_set_config_fast(&new_config);
  547. #if SOC_SPI_MEM_SUPPORT_TIMING_TUNING
  548. mspi_timing_change_speed_mode_cache_safe(false);
  549. #endif
  550. } else {
  551. #if SOC_SPI_MEM_SUPPORT_TIMING_TUNING
  552. mspi_timing_change_speed_mode_cache_safe(true);
  553. #endif
  554. rtc_clk_cpu_freq_set_config_fast(&new_config);
  555. }
  556. if (!switch_down) {
  557. on_freq_update(old_ticks_per_us, new_ticks_per_us);
  558. }
  559. ESP_PM_TRACE_EXIT(FREQ_SWITCH, core_id);
  560. }
  561. portENTER_CRITICAL_ISR(&s_switch_lock);
  562. s_mode = new_mode;
  563. s_is_switching = false;
  564. portEXIT_CRITICAL_ISR(&s_switch_lock);
  565. }
  566. #ifdef CONFIG_FREERTOS_SYSTICK_USES_CCOUNT
  567. /**
  568. * @brief Calculate new CCOMPARE value based on s_ccount_{mul,div}
  569. *
  570. * Adjusts CCOMPARE value so that the interrupt happens at the same time as it
  571. * would happen without the frequency change.
  572. * Assumes that the new_frequency = old_frequency * s_ccount_mul / s_ccount_div.
  573. */
  574. static void IRAM_ATTR update_ccompare(void)
  575. {
  576. #if CONFIG_PM_UPDATE_CCOMPARE_HLI_WORKAROUND
  577. /* disable level 4 and below */
  578. uint32_t irq_status = XTOS_SET_INTLEVEL(XCHAL_DEBUGLEVEL - 2);
  579. #endif
  580. uint32_t ccount = esp_cpu_get_cycle_count();
  581. uint32_t ccompare = XTHAL_GET_CCOMPARE(XT_TIMER_INDEX);
  582. if ((ccompare - CCOMPARE_MIN_CYCLES_IN_FUTURE) - ccount < UINT32_MAX / 2) {
  583. uint32_t diff = ccompare - ccount;
  584. uint32_t diff_scaled = (diff * s_ccount_mul + s_ccount_div - 1) / s_ccount_div;
  585. if (diff_scaled < _xt_tick_divisor) {
  586. uint32_t new_ccompare = ccount + diff_scaled;
  587. XTHAL_SET_CCOMPARE(XT_TIMER_INDEX, new_ccompare);
  588. }
  589. }
  590. #if CONFIG_PM_UPDATE_CCOMPARE_HLI_WORKAROUND
  591. XTOS_RESTORE_INTLEVEL(irq_status);
  592. #endif
  593. }
  594. #endif // CONFIG_FREERTOS_SYSTICK_USES_CCOUNT
  595. static void IRAM_ATTR leave_idle(void)
  596. {
  597. int core_id = xPortGetCoreID();
  598. if (s_core_idle[core_id]) {
  599. // TODO: possible optimization: raise frequency here first
  600. esp_pm_lock_acquire(s_rtos_lock_handle[core_id]);
  601. s_core_idle[core_id] = false;
  602. }
  603. }
  604. #if CONFIG_FREERTOS_USE_TICKLESS_IDLE
  605. esp_err_t esp_pm_register_skip_light_sleep_callback(skip_light_sleep_cb_t cb)
  606. {
  607. _lock_acquire(&s_skip_light_sleep_lock);
  608. for (int i = 0; i < PERIPH_SKIP_LIGHT_SLEEP_NO; i++) {
  609. if (s_periph_skip_light_sleep_cb[i] == cb) {
  610. _lock_release(&s_skip_light_sleep_lock);
  611. return ESP_OK;
  612. } else if (s_periph_skip_light_sleep_cb[i] == NULL) {
  613. s_periph_skip_light_sleep_cb[i] = cb;
  614. _lock_release(&s_skip_light_sleep_lock);
  615. return ESP_OK;
  616. }
  617. }
  618. _lock_release(&s_skip_light_sleep_lock);
  619. return ESP_ERR_NO_MEM;
  620. }
  621. esp_err_t esp_pm_unregister_skip_light_sleep_callback(skip_light_sleep_cb_t cb)
  622. {
  623. _lock_acquire(&s_skip_light_sleep_lock);
  624. for (int i = 0; i < PERIPH_SKIP_LIGHT_SLEEP_NO; i++) {
  625. if (s_periph_skip_light_sleep_cb[i] == cb) {
  626. s_periph_skip_light_sleep_cb[i] = NULL;
  627. _lock_release(&s_skip_light_sleep_lock);
  628. return ESP_OK;
  629. }
  630. }
  631. _lock_release(&s_skip_light_sleep_lock);
  632. return ESP_ERR_INVALID_STATE;
  633. }
  634. static inline bool IRAM_ATTR periph_should_skip_light_sleep(void)
  635. {
  636. if (s_light_sleep_en) {
  637. for (int i = 0; i < PERIPH_SKIP_LIGHT_SLEEP_NO; i++) {
  638. if (s_periph_skip_light_sleep_cb[i]) {
  639. if (s_periph_skip_light_sleep_cb[i]() == true) {
  640. return true;
  641. }
  642. }
  643. }
  644. }
  645. return false;
  646. }
  647. static inline bool IRAM_ATTR should_skip_light_sleep(int core_id)
  648. {
  649. #if portNUM_PROCESSORS == 2
  650. if (s_skip_light_sleep[core_id]) {
  651. s_skip_light_sleep[core_id] = false;
  652. s_skipped_light_sleep[core_id] = true;
  653. return true;
  654. }
  655. #endif // portNUM_PROCESSORS == 2
  656. if (s_mode != PM_MODE_LIGHT_SLEEP || s_is_switching || periph_should_skip_light_sleep()) {
  657. s_skipped_light_sleep[core_id] = true;
  658. } else {
  659. s_skipped_light_sleep[core_id] = false;
  660. }
  661. return s_skipped_light_sleep[core_id];
  662. }
  663. static inline void IRAM_ATTR other_core_should_skip_light_sleep(int core_id)
  664. {
  665. #if portNUM_PROCESSORS == 2
  666. s_skip_light_sleep[!core_id] = true;
  667. #endif
  668. }
  669. void IRAM_ATTR vApplicationSleep( TickType_t xExpectedIdleTime )
  670. {
  671. portENTER_CRITICAL(&s_switch_lock);
  672. int core_id = xPortGetCoreID();
  673. if (!should_skip_light_sleep(core_id)) {
  674. /* Calculate how much we can sleep */
  675. int64_t next_esp_timer_alarm = esp_timer_get_next_alarm_for_wake_up();
  676. int64_t now = esp_timer_get_time();
  677. int64_t time_until_next_alarm = next_esp_timer_alarm - now;
  678. int64_t wakeup_delay_us = portTICK_PERIOD_MS * 1000LL * xExpectedIdleTime;
  679. int64_t sleep_time_us = MIN(wakeup_delay_us, time_until_next_alarm);
  680. if (sleep_time_us >= configEXPECTED_IDLE_TIME_BEFORE_SLEEP * portTICK_PERIOD_MS * 1000LL) {
  681. int64_t slept_us = 0;
  682. #if CONFIG_PM_LIGHT_SLEEP_CALLBACKS
  683. if (s_light_sleep_enter_cb_config != NULL && s_light_sleep_enter_cb_config->cb) {
  684. uint32_t cycle = esp_cpu_get_cycle_count();
  685. esp_err_t err = esp_pm_execute_enter_sleep_callbacks(sleep_time_us);
  686. if (err != ESP_OK) {
  687. portEXIT_CRITICAL(&s_switch_lock);
  688. return;
  689. }
  690. sleep_time_us -= (esp_cpu_get_cycle_count() - cycle) / (esp_clk_cpu_freq() / 1000000ULL);
  691. }
  692. if (sleep_time_us >= configEXPECTED_IDLE_TIME_BEFORE_SLEEP * portTICK_PERIOD_MS * 1000LL)
  693. {
  694. #endif
  695. esp_sleep_enable_timer_wakeup(sleep_time_us - LIGHT_SLEEP_EARLY_WAKEUP_US);
  696. #if CONFIG_PM_TRACE && SOC_PM_SUPPORT_RTC_PERIPH_PD
  697. /* to force tracing GPIOs to keep state */
  698. esp_sleep_pd_config(ESP_PD_DOMAIN_RTC_PERIPH, ESP_PD_OPTION_ON);
  699. #endif
  700. /* Enter sleep */
  701. ESP_PM_TRACE_ENTER(SLEEP, core_id);
  702. int64_t sleep_start = esp_timer_get_time();
  703. if (esp_light_sleep_start() != ESP_OK){
  704. #ifdef WITH_PROFILING
  705. s_light_sleep_reject_counts++;
  706. } else {
  707. s_light_sleep_counts++;
  708. #endif
  709. }
  710. slept_us = esp_timer_get_time() - sleep_start;
  711. ESP_PM_TRACE_EXIT(SLEEP, core_id);
  712. uint32_t slept_ticks = slept_us / (portTICK_PERIOD_MS * 1000LL);
  713. if (slept_ticks > 0) {
  714. /* Adjust RTOS tick count based on the amount of time spent in sleep */
  715. vTaskStepTick(slept_ticks);
  716. #ifdef CONFIG_FREERTOS_SYSTICK_USES_CCOUNT
  717. /* Trigger tick interrupt, since sleep time was longer
  718. * than portTICK_PERIOD_MS. Note that setting INTSET does not
  719. * work for timer interrupt, and changing CCOMPARE would clear
  720. * the interrupt flag.
  721. */
  722. esp_cpu_set_cycle_count(XTHAL_GET_CCOMPARE(XT_TIMER_INDEX) - 16);
  723. while (!(XTHAL_GET_INTERRUPT() & BIT(XT_TIMER_INTNUM))) {
  724. ;
  725. }
  726. #else
  727. portYIELD_WITHIN_API();
  728. #endif
  729. }
  730. other_core_should_skip_light_sleep(core_id);
  731. #if CONFIG_PM_LIGHT_SLEEP_CALLBACKS
  732. }
  733. if (s_light_sleep_exit_cb_config != NULL && s_light_sleep_exit_cb_config->cb) {
  734. esp_pm_execute_exit_sleep_callbacks(slept_us);
  735. }
  736. #endif
  737. }
  738. }
  739. portEXIT_CRITICAL(&s_switch_lock);
  740. }
  741. #endif //CONFIG_FREERTOS_USE_TICKLESS_IDLE
  742. #ifdef WITH_PROFILING
  743. void esp_pm_impl_dump_stats(FILE* out)
  744. {
  745. pm_time_t time_in_mode[PM_MODE_COUNT];
  746. portENTER_CRITICAL_ISR(&s_switch_lock);
  747. memcpy(time_in_mode, s_time_in_mode, sizeof(time_in_mode));
  748. pm_time_t last_mode_change_time = s_last_mode_change_time;
  749. pm_mode_t cur_mode = s_mode;
  750. pm_time_t now = pm_get_time();
  751. bool light_sleep_en = s_light_sleep_en;
  752. uint32_t light_sleep_counts = s_light_sleep_counts;
  753. uint32_t light_sleep_reject_counts = s_light_sleep_reject_counts;
  754. portEXIT_CRITICAL_ISR(&s_switch_lock);
  755. time_in_mode[cur_mode] += now - last_mode_change_time;
  756. fprintf(out, "\nMode stats:\n");
  757. fprintf(out, "%-8s %-10s %-10s %-10s\n", "Mode", "CPU_freq", "Time(us)", "Time(%)");
  758. for (int i = 0; i < PM_MODE_COUNT; ++i) {
  759. if (i == PM_MODE_LIGHT_SLEEP && !light_sleep_en) {
  760. /* don't display light sleep mode if it's not enabled */
  761. continue;
  762. }
  763. fprintf(out, "%-8s %-3"PRIu32"M%-7s %-10lld %-2d%%\n",
  764. s_mode_names[i],
  765. s_cpu_freq_by_mode[i].freq_mhz,
  766. "", //Empty space to align columns
  767. time_in_mode[i],
  768. (int) (time_in_mode[i] * 100 / now));
  769. }
  770. if (light_sleep_en){
  771. fprintf(out, "\nSleep stats:\n");
  772. fprintf(out, "light_sleep_counts:%ld light_sleep_reject_counts:%ld\n", light_sleep_counts, light_sleep_reject_counts);
  773. }
  774. }
  775. #endif // WITH_PROFILING
  776. int esp_pm_impl_get_cpu_freq(pm_mode_t mode)
  777. {
  778. int freq_mhz;
  779. if (mode >= PM_MODE_LIGHT_SLEEP && mode < PM_MODE_COUNT) {
  780. portENTER_CRITICAL(&s_switch_lock);
  781. freq_mhz = s_cpu_freq_by_mode[mode].freq_mhz;
  782. portEXIT_CRITICAL(&s_switch_lock);
  783. } else {
  784. abort();
  785. }
  786. return freq_mhz;
  787. }
  788. void esp_pm_impl_init(void)
  789. {
  790. #if defined(CONFIG_ESP_CONSOLE_UART)
  791. //This clock source should be a source which won't be affected by DFS
  792. uart_sclk_t clk_source = UART_SCLK_DEFAULT;
  793. #if SOC_UART_SUPPORT_REF_TICK
  794. clk_source = UART_SCLK_REF_TICK;
  795. #elif SOC_UART_SUPPORT_XTAL_CLK
  796. clk_source = UART_SCLK_XTAL;
  797. #else
  798. #error "No UART clock source is aware of DFS"
  799. #endif // SOC_UART_SUPPORT_xxx
  800. while (!uart_ll_is_tx_idle(UART_LL_GET_HW(CONFIG_ESP_CONSOLE_UART_NUM))) {
  801. ;
  802. }
  803. /* When DFS is enabled, override system setting and use REFTICK as UART clock source */
  804. HP_UART_SRC_CLK_ATOMIC() {
  805. uart_ll_set_sclk(UART_LL_GET_HW(CONFIG_ESP_CONSOLE_UART_NUM), (soc_module_clk_t)clk_source);
  806. }
  807. uint32_t sclk_freq;
  808. esp_err_t err = uart_get_sclk_freq(clk_source, &sclk_freq);
  809. assert(err == ESP_OK);
  810. HP_UART_SRC_CLK_ATOMIC() {
  811. uart_ll_set_baudrate(UART_LL_GET_HW(CONFIG_ESP_CONSOLE_UART_NUM), CONFIG_ESP_CONSOLE_UART_BAUDRATE, sclk_freq);
  812. }
  813. #endif // CONFIG_ESP_CONSOLE_UART
  814. #ifdef CONFIG_PM_TRACE
  815. esp_pm_trace_init();
  816. #endif
  817. ESP_ERROR_CHECK(esp_pm_lock_create(ESP_PM_CPU_FREQ_MAX, 0, "rtos0",
  818. &s_rtos_lock_handle[0]));
  819. ESP_ERROR_CHECK(esp_pm_lock_acquire(s_rtos_lock_handle[0]));
  820. #if portNUM_PROCESSORS == 2
  821. ESP_ERROR_CHECK(esp_pm_lock_create(ESP_PM_CPU_FREQ_MAX, 0, "rtos1",
  822. &s_rtos_lock_handle[1]));
  823. ESP_ERROR_CHECK(esp_pm_lock_acquire(s_rtos_lock_handle[1]));
  824. #endif // portNUM_PROCESSORS == 2
  825. /* Configure all modes to use the default CPU frequency.
  826. * This will be modified later by a call to esp_pm_configure.
  827. */
  828. rtc_cpu_freq_config_t default_config;
  829. if (!rtc_clk_cpu_freq_mhz_to_config(CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ, &default_config)) {
  830. assert(false && "unsupported frequency");
  831. }
  832. for (size_t i = 0; i < PM_MODE_COUNT; ++i) {
  833. s_cpu_freq_by_mode[i] = default_config;
  834. }
  835. #ifdef CONFIG_PM_DFS_INIT_AUTO
  836. int xtal_freq_mhz = esp_clk_xtal_freq() / MHZ;
  837. esp_pm_config_t cfg = {
  838. .max_freq_mhz = CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ,
  839. .min_freq_mhz = xtal_freq_mhz,
  840. };
  841. esp_pm_configure(&cfg);
  842. #endif //CONFIG_PM_DFS_INIT_AUTO
  843. }
  844. void esp_pm_impl_idle_hook(void)
  845. {
  846. int core_id = xPortGetCoreID();
  847. #if CONFIG_FREERTOS_SMP
  848. uint32_t state = portDISABLE_INTERRUPTS();
  849. #else
  850. uint32_t state = portSET_INTERRUPT_MASK_FROM_ISR();
  851. #endif
  852. if (!s_core_idle[core_id]
  853. #ifdef CONFIG_FREERTOS_USE_TICKLESS_IDLE
  854. && !periph_should_skip_light_sleep()
  855. #endif
  856. ) {
  857. esp_pm_lock_release(s_rtos_lock_handle[core_id]);
  858. s_core_idle[core_id] = true;
  859. }
  860. #if CONFIG_FREERTOS_SMP
  861. portRESTORE_INTERRUPTS(state);
  862. #else
  863. portCLEAR_INTERRUPT_MASK_FROM_ISR(state);
  864. #endif
  865. ESP_PM_TRACE_ENTER(IDLE, core_id);
  866. }
  867. void IRAM_ATTR esp_pm_impl_isr_hook(void)
  868. {
  869. int core_id = xPortGetCoreID();
  870. ESP_PM_TRACE_ENTER(ISR_HOOK, core_id);
  871. /* Prevent higher level interrupts (than the one this function was called from)
  872. * from happening in this section, since they will also call into esp_pm_impl_isr_hook.
  873. */
  874. #if CONFIG_FREERTOS_SMP
  875. uint32_t state = portDISABLE_INTERRUPTS();
  876. #else
  877. uint32_t state = portSET_INTERRUPT_MASK_FROM_ISR();
  878. #endif
  879. #if defined(CONFIG_FREERTOS_SYSTICK_USES_CCOUNT) && (portNUM_PROCESSORS == 2)
  880. if (s_need_update_ccompare[core_id]) {
  881. update_ccompare();
  882. s_need_update_ccompare[core_id] = false;
  883. } else {
  884. leave_idle();
  885. }
  886. #else
  887. leave_idle();
  888. #endif // CONFIG_FREERTOS_SYSTICK_USES_CCOUNT && portNUM_PROCESSORS == 2
  889. #if CONFIG_FREERTOS_SMP
  890. portRESTORE_INTERRUPTS(state);
  891. #else
  892. portCLEAR_INTERRUPT_MASK_FROM_ISR(state);
  893. #endif
  894. ESP_PM_TRACE_EXIT(ISR_HOOK, core_id);
  895. }
  896. void esp_pm_impl_waiti(void)
  897. {
  898. #if CONFIG_FREERTOS_USE_TICKLESS_IDLE
  899. int core_id = xPortGetCoreID();
  900. if (s_skipped_light_sleep[core_id]) {
  901. esp_cpu_wait_for_intr();
  902. /* Interrupt took the CPU out of waiti and s_rtos_lock_handle[core_id]
  903. * is now taken. However since we are back to idle task, we can release
  904. * the lock so that vApplicationSleep can attempt to enter light sleep.
  905. */
  906. esp_pm_impl_idle_hook();
  907. }
  908. s_skipped_light_sleep[core_id] = true;
  909. #else
  910. esp_cpu_wait_for_intr();
  911. #endif // CONFIG_FREERTOS_USE_TICKLESS_IDLE
  912. }