Kconfig 22 KB

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  1. menu "ESP32S2-specific"
  2. # TODO: this component simply shouldn't be included
  3. # in the build at the CMake level, but this is currently
  4. # not working so we just hide all items here
  5. visible if IDF_TARGET_ESP32S2
  6. choice ESP32S2_DEFAULT_CPU_FREQ_MHZ
  7. prompt "CPU frequency"
  8. default ESP32S2_DEFAULT_CPU_FREQ_160 if !IDF_ENV_FPGA
  9. default ESP32S2_DEFAULT_CPU_FREQ_FPGA if IDF_ENV_FPGA
  10. help
  11. CPU frequency to be set on application startup.
  12. config ESP32S2_DEFAULT_CPU_FREQ_FPGA
  13. depends on IDF_ENV_FPGA
  14. bool "FPGA"
  15. config ESP32S2_DEFAULT_CPU_FREQ_80
  16. bool "80 MHz"
  17. config ESP32S2_DEFAULT_CPU_FREQ_160
  18. bool "160 MHz"
  19. config ESP32S2_DEFAULT_CPU_FREQ_240
  20. bool "240 MHz"
  21. endchoice
  22. config ESP32S2_DEFAULT_CPU_FREQ_MHZ
  23. int
  24. default 40 if IDF_ENV_FPGA
  25. default 80 if ESP32S2_DEFAULT_CPU_FREQ_80
  26. default 160 if ESP32S2_DEFAULT_CPU_FREQ_160
  27. default 240 if ESP32S2_DEFAULT_CPU_FREQ_240
  28. menu "Memory protection"
  29. config ESP32S2_MEMPROT_FEATURE
  30. bool "Enable memory protection"
  31. default "y"
  32. help
  33. If enabled, permission control module watches all memory access and fires panic handler
  34. if permission violation is detected. This feature automatically splits
  35. memory into data and instruction segments and sets Read/Execute permissions
  36. for instruction part (below splitting address) and Read/Write permissions
  37. for data part (above splitting address). The memory protection is effective
  38. on all access through IRAM0 and DRAM0 buses.
  39. config ESP32S2_MEMPROT_FEATURE_LOCK
  40. depends on ESP32S2_MEMPROT_FEATURE
  41. bool "Lock memory protection settings"
  42. default "y"
  43. help
  44. Once locked, memory protection settings cannot be changed anymore.
  45. The lock is reset only on the chip startup.
  46. endmenu # Memory protection
  47. menu "Cache config"
  48. choice ESP32S2_INSTRUCTION_CACHE_SIZE
  49. prompt "Instruction cache size"
  50. default ESP32S2_INSTRUCTION_CACHE_8KB
  51. help
  52. Instruction cache size to be set on application startup.
  53. If you use 8KB instruction cache rather than 16KB instruction cache,
  54. then the other 8KB will be added to the heap.
  55. config ESP32S2_INSTRUCTION_CACHE_8KB
  56. bool "8KB"
  57. config ESP32S2_INSTRUCTION_CACHE_16KB
  58. bool "16KB"
  59. endchoice
  60. choice ESP32S2_INSTRUCTION_CACHE_LINE_SIZE
  61. prompt "Instruction cache line size"
  62. default ESP32S2_INSTRUCTION_CACHE_LINE_32B
  63. help
  64. Instruction cache line size to be set on application startup.
  65. config ESP32S2_INSTRUCTION_CACHE_LINE_16B
  66. bool "16 Bytes"
  67. config ESP32S2_INSTRUCTION_CACHE_LINE_32B
  68. bool "32 Bytes"
  69. endchoice
  70. choice ESP32S2_DATA_CACHE_SIZE
  71. prompt "Data cache size"
  72. default ESP32S2_DATA_CACHE_0KB if !ESP32S2_SPIRAM_SUPPORT
  73. default ESP32S2_DATA_CACHE_8KB if ESP32S2_SPIRAM_SUPPORT
  74. help
  75. Data cache size to be set on application startup.
  76. If you use 0KB data cache, the other 16KB will be added to the heap
  77. If you use 8KB data cache rather than 16KB data cache, the other 8KB will be added to the heap
  78. config ESP32S2_DATA_CACHE_0KB
  79. depends on !ESP32S2_SPIRAM_SUPPORT
  80. bool "0KB"
  81. config ESP32S2_DATA_CACHE_8KB
  82. bool "8KB"
  83. config ESP32S2_DATA_CACHE_16KB
  84. bool "16KB"
  85. endchoice
  86. choice ESP32S2_DATA_CACHE_LINE_SIZE
  87. prompt "Data cache line size"
  88. default ESP32S2_DATA_CACHE_LINE_32B
  89. help
  90. Data cache line size to be set on application startup.
  91. config ESP32S2_DATA_CACHE_LINE_16B
  92. bool "16 Bytes"
  93. config ESP32S2_DATA_CACHE_LINE_32B
  94. bool "32 Bytes"
  95. endchoice
  96. config ESP32S2_INSTRUCTION_CACHE_WRAP
  97. bool "Enable instruction cache wrap"
  98. default "n"
  99. help
  100. If enabled, instruction cache will use wrap mode to read spi flash (maybe spiram).
  101. The wrap length equals to INSTRUCTION_CACHE_LINE_SIZE.
  102. However, it depends on complex conditions.
  103. config ESP32S2_DATA_CACHE_WRAP
  104. bool "Enable data cache wrap"
  105. default "n"
  106. help
  107. If enabled, data cache will use wrap mode to read spiram (maybe spi flash).
  108. The wrap length equals to DATA_CACHE_LINE_SIZE.
  109. However, it depends on complex conditions.
  110. endmenu # Cache config
  111. # Note: to support SPIRAM across multiple chips, check CONFIG_SPIRAM
  112. # instead
  113. config ESP32S2_SPIRAM_SUPPORT
  114. bool "Support for external, SPI-connected RAM"
  115. default "n"
  116. select SPIRAM
  117. help
  118. This enables support for an external SPI RAM chip, connected in parallel with the
  119. main SPI flash chip.
  120. menu "SPI RAM config"
  121. depends on ESP32S2_SPIRAM_SUPPORT
  122. choice SPIRAM_TYPE
  123. prompt "Type of SPI RAM chip in use"
  124. default SPIRAM_TYPE_AUTO
  125. config SPIRAM_TYPE_AUTO
  126. bool "Auto-detect"
  127. config SPIRAM_TYPE_ESPPSRAM16
  128. bool "ESP-PSRAM16 or APS1604"
  129. config SPIRAM_TYPE_ESPPSRAM32
  130. bool "ESP-PSRAM32 or IS25WP032"
  131. config SPIRAM_TYPE_ESPPSRAM64
  132. bool "ESP-PSRAM64 or LY68L6400"
  133. endchoice
  134. config SPIRAM_SIZE
  135. int
  136. default -1 if SPIRAM_TYPE_AUTO
  137. default 2097152 if SPIRAM_TYPE_ESPPSRAM16
  138. default 4194304 if SPIRAM_TYPE_ESPPSRAM32
  139. default 8388608 if SPIRAM_TYPE_ESPPSRAM64
  140. default 0
  141. menu "PSRAM clock and cs IO for ESP32S2"
  142. depends on ESP32S2_SPIRAM_SUPPORT
  143. config DEFAULT_PSRAM_CLK_IO
  144. int "PSRAM CLK IO number"
  145. range 0 33
  146. default 30
  147. help
  148. The PSRAM CLOCK IO can be any unused GPIO, user can config it based on hardware design.
  149. config DEFAULT_PSRAM_CS_IO
  150. int "PSRAM CS IO number"
  151. range 0 33
  152. default 26
  153. help
  154. The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design.
  155. endmenu
  156. config SPIRAM_FETCH_INSTRUCTIONS
  157. bool "Cache fetch instructions from SPI RAM"
  158. default n
  159. help
  160. If enabled, instruction in flash will be copied into SPIRAM.
  161. If SPIRAM_RODATA also enabled,
  162. you can run the instruction when erasing or programming the flash.
  163. config SPIRAM_RODATA
  164. bool "Cache load read only data from SPI RAM"
  165. default n
  166. help
  167. If enabled, radata in flash will be copied into SPIRAM.
  168. If SPIRAM_FETCH_INSTRUCTIONS also enabled,
  169. you can run the instruction when erasing or programming the flash.
  170. choice SPIRAM_SPEED
  171. prompt "Set RAM clock speed"
  172. default SPIRAM_SPEED_40M
  173. help
  174. Select the speed for the SPI RAM chip.
  175. config SPIRAM_SPEED_80M
  176. bool "80MHz clock speed"
  177. config SPIRAM_SPEED_40M
  178. bool "40Mhz clock speed"
  179. config SPIRAM_SPEED_26M
  180. bool "26Mhz clock speed"
  181. config SPIRAM_SPEED_20M
  182. bool "20Mhz clock speed"
  183. endchoice
  184. # insert non-chip-specific items here
  185. source "$IDF_PATH/components/esp_common/Kconfig.spiram.common"
  186. endmenu
  187. config ESP32S2_MEMMAP_TRACEMEM
  188. bool
  189. default "n"
  190. config ESP32S2_MEMMAP_TRACEMEM_TWOBANKS
  191. bool
  192. default "n"
  193. config ESP32S2_TRAX
  194. bool "Use TRAX tracing feature"
  195. default "n"
  196. select ESP32S2_MEMMAP_TRACEMEM
  197. help
  198. The ESP32S2 contains a feature which allows you to trace the execution path the processor
  199. has taken through the program. This is stored in a chunk of 32K (16K for single-processor)
  200. of memory that can't be used for general purposes anymore. Disable this if you do not know
  201. what this is.
  202. config ESP32S2_TRACEMEM_RESERVE_DRAM
  203. hex
  204. default 0x8000 if ESP32S2_MEMMAP_TRACEMEM && ESP32S2_MEMMAP_TRACEMEM_TWOBANKS
  205. default 0x4000 if ESP32S2_MEMMAP_TRACEMEM && !ESP32S2_MEMMAP_TRACEMEM_TWOBANKS
  206. default 0x0
  207. choice ESP32S2_UNIVERSAL_MAC_ADDRESSES
  208. bool "Number of universally administered (by IEEE) MAC address"
  209. default ESP32S2_UNIVERSAL_MAC_ADDRESSES_TWO
  210. help
  211. Configure the number of universally administered (by IEEE) MAC addresses.
  212. During initialization, MAC addresses for each network interface are generated or derived from a
  213. single base MAC address.
  214. If the number of universal MAC addresses is Two, all interfaces (WiFi station, WiFi softap) receive a
  215. universally administered MAC address. They are generated sequentially by adding 0, and 1 (respectively)
  216. to the final octet of the base MAC address. If the number of universal MAC addresses is one,
  217. only WiFi station receives a universally administered MAC address.
  218. It's generated by adding 0 to the base MAC address.
  219. The WiFi softap receives local MAC addresses. It's derived from the universal WiFi station MAC addresses.
  220. When using the default (Espressif-assigned) base MAC address, either setting can be used. When using
  221. a custom universal MAC address range, the correct setting will depend on the allocation of MAC
  222. addresses in this range (either 1 or 2 per device.)
  223. config ESP32S2_UNIVERSAL_MAC_ADDRESSES_ONE
  224. bool "One"
  225. select ESP_MAC_ADDR_UNIVERSE_WIFI_STA
  226. config ESP32S2_UNIVERSAL_MAC_ADDRESSES_TWO
  227. bool "Two"
  228. select ESP_MAC_ADDR_UNIVERSE_WIFI_STA
  229. select ESP_MAC_ADDR_UNIVERSE_WIFI_AP
  230. endchoice
  231. config ESP32S2_UNIVERSAL_MAC_ADDRESSES
  232. int
  233. default 1 if ESP32S2_UNIVERSAL_MAC_ADDRESSES_ONE
  234. default 2 if ESP32S2_UNIVERSAL_MAC_ADDRESSES_TWO
  235. config ESP32S2_ULP_COPROC_ENABLED
  236. bool "Enable Ultra Low Power (ULP) Coprocessor"
  237. default "n"
  238. help
  239. Set to 'y' if you plan to load a firmware for the coprocessor.
  240. If this option is enabled, further coprocessor configuration will appear in the Components menu.
  241. config ESP32S2_ULP_COPROC_RESERVE_MEM
  242. int
  243. prompt "RTC slow memory reserved for coprocessor" if ESP32S2_ULP_COPROC_ENABLED
  244. default 2048 if ESP32S2_ULP_COPROC_ENABLED
  245. range 32 8192 if ESP32S2_ULP_COPROC_ENABLED
  246. default 0 if !ESP32S2_ULP_COPROC_ENABLED
  247. range 0 0 if !ESP32S2_ULP_COPROC_ENABLED
  248. help
  249. Bytes of memory to reserve for ULP coprocessor firmware & data.
  250. Data is reserved at the beginning of RTC slow memory.
  251. config ESP32S2_ULP_COPROC_RISCV
  252. bool "Enable RISC-V as ULP coprocessor"
  253. depends on ESP32S2_ULP_COPROC_ENABLED
  254. default n
  255. help
  256. Set this to y to use the RISC-V coprocessor instead of the FSM-ULP.
  257. config ESP32S2_DEBUG_OCDAWARE
  258. bool "Make exception and panic handlers JTAG/OCD aware"
  259. default y
  260. select FREERTOS_DEBUG_OCDAWARE
  261. help
  262. The FreeRTOS panic and unhandled exception handers can detect a JTAG OCD debugger and
  263. instead of panicking, have the debugger stop on the offending instruction.
  264. config ESP32S2_DEBUG_STUBS_ENABLE
  265. bool "OpenOCD debug stubs"
  266. default COMPILER_OPTIMIZATION_LEVEL_DEBUG
  267. depends on !ESP32S2_TRAX
  268. help
  269. Debug stubs are used by OpenOCD to execute pre-compiled onboard code which does some useful debugging,
  270. e.g. GCOV data dump.
  271. config ESP32S2_BROWNOUT_DET
  272. bool "Hardware brownout detect & reset"
  273. default y
  274. help
  275. The ESP32-S2 has a built-in brownout detector which can detect if the voltage is lower than
  276. a specific value. If this happens, it will reset the chip in order to prevent unintended
  277. behaviour.
  278. choice ESP32S2_BROWNOUT_DET_LVL_SEL
  279. prompt "Brownout voltage level"
  280. depends on ESP32S2_BROWNOUT_DET
  281. default ESP32S2_BROWNOUT_DET_LVL_SEL_7
  282. help
  283. The brownout detector will reset the chip when the supply voltage is approximately
  284. below this level. Note that there may be some variation of brownout voltage level
  285. between each ESP3-S2 chip.
  286. #The voltage levels here are estimates, more work needs to be done to figure out the exact voltages
  287. #of the brownout threshold levels.
  288. config ESP32S2_BROWNOUT_DET_LVL_SEL_7
  289. bool "2.44V"
  290. config ESP32S2_BROWNOUT_DET_LVL_SEL_6
  291. bool "2.56V"
  292. config ESP32S2_BROWNOUT_DET_LVL_SEL_5
  293. bool "2.67V"
  294. config ESP32S2_BROWNOUT_DET_LVL_SEL_4
  295. bool "2.84V"
  296. config ESP32S2_BROWNOUT_DET_LVL_SEL_3
  297. bool "2.98V"
  298. config ESP32S2_BROWNOUT_DET_LVL_SEL_2
  299. bool "3.19V"
  300. config ESP32S2_BROWNOUT_DET_LVL_SEL_1
  301. bool "3.30V"
  302. endchoice
  303. config ESP32S2_BROWNOUT_DET_LVL
  304. int
  305. default 1 if ESP32S2_BROWNOUT_DET_LVL_SEL_1
  306. default 2 if ESP32S2_BROWNOUT_DET_LVL_SEL_2
  307. default 3 if ESP32S2_BROWNOUT_DET_LVL_SEL_3
  308. default 4 if ESP32S2_BROWNOUT_DET_LVL_SEL_4
  309. default 5 if ESP32S2_BROWNOUT_DET_LVL_SEL_5
  310. default 6 if ESP32S2_BROWNOUT_DET_LVL_SEL_6
  311. default 7 if ESP32S2_BROWNOUT_DET_LVL_SEL_7
  312. # Note about the use of "FRC1" name: currently FRC1 timer is not used for
  313. # high resolution timekeeping anymore. Instead the esp_timer API, implemented
  314. # using FRC2 timer, is used.
  315. # FRC1 name in the option name is kept for compatibility.
  316. choice ESP32S2_TIME_SYSCALL
  317. prompt "Timers used for gettimeofday function"
  318. default ESP32S2_TIME_SYSCALL_USE_RTC_FRC1
  319. help
  320. This setting defines which hardware timers are used to
  321. implement 'gettimeofday' and 'time' functions in C library.
  322. - If both high-resolution and RTC timers are used, timekeeping will
  323. continue in deep sleep. Time will be reported at 1 microsecond
  324. resolution. This is the default, and the recommended option.
  325. - If only high-resolution timer is used, gettimeofday will
  326. provide time at microsecond resolution.
  327. Time will not be preserved when going into deep sleep mode.
  328. - If only RTC timer is used, timekeeping will continue in
  329. deep sleep, but time will be measured at 6.(6) microsecond
  330. resolution. Also the gettimeofday function itself may take
  331. longer to run.
  332. - If no timers are used, gettimeofday and time functions
  333. return -1 and set errno to ENOSYS.
  334. - When RTC is used for timekeeping, two RTC_STORE registers are
  335. used to keep time in deep sleep mode.
  336. config ESP32S2_TIME_SYSCALL_USE_RTC_FRC1
  337. bool "RTC and high-resolution timer"
  338. select ESP_TIME_FUNCS_USE_RTC_TIMER
  339. select ESP_TIME_FUNCS_USE_ESP_TIMER
  340. config ESP32S2_TIME_SYSCALL_USE_RTC
  341. bool "RTC"
  342. select ESP_TIME_FUNCS_USE_RTC_TIMER
  343. config ESP32S2_TIME_SYSCALL_USE_FRC1
  344. bool "High-resolution timer"
  345. select ESP_TIME_FUNCS_USE_ESP_TIMER
  346. config ESP32S2_TIME_SYSCALL_USE_NONE
  347. bool "None"
  348. select ESP_TIME_FUNCS_USE_NONE
  349. endchoice
  350. choice ESP32S2_RTC_CLK_SRC
  351. prompt "RTC clock source"
  352. default ESP32S2_RTC_CLK_SRC_INT_RC
  353. help
  354. Choose which clock is used as RTC clock source.
  355. - "Internal 90kHz oscillator" option provides lowest deep sleep current
  356. consumption, and does not require extra external components. However
  357. frequency stability with respect to temperature is poor, so time may
  358. drift in deep/light sleep modes.
  359. - "External 32kHz crystal" provides better frequency stability, at the
  360. expense of slightly higher (1uA) deep sleep current consumption.
  361. - "External 32kHz oscillator" allows using 32kHz clock generated by an
  362. external circuit. In this case, external clock signal must be connected
  363. to 32K_XN pin. Amplitude should be <1.2V in case of sine wave signal,
  364. and <1V in case of square wave signal. Common mode voltage should be
  365. 0.1 < Vcm < 0.5Vamp, where Vamp is the signal amplitude.
  366. Additionally, 1nF capacitor must be connected between 32K_XP pin and
  367. ground. 32K_XP pin can not be used as a GPIO in this case.
  368. - "Internal 8MHz oscillator divided by 256" option results in higher
  369. deep sleep current (by 5uA) but has better frequency stability than
  370. the internal 90kHz oscillator. It does not require external components.
  371. config ESP32S2_RTC_CLK_SRC_INT_RC
  372. bool "Internal 90kHz RC oscillator"
  373. config ESP32S2_RTC_CLK_SRC_EXT_CRYS
  374. bool "External 32kHz crystal"
  375. select ESP_SYSTEM_RTC_EXT_XTAL
  376. config ESP32S2_RTC_CLK_SRC_EXT_OSC
  377. bool "External 32kHz oscillator at 32K_XN pin"
  378. config ESP32S2_RTC_CLK_SRC_INT_8MD256
  379. bool "Internal 8MHz oscillator, divided by 256 (~32kHz)"
  380. endchoice
  381. config ESP32S2_RTC_CLK_CAL_CYCLES
  382. int "Number of cycles for RTC_SLOW_CLK calibration"
  383. default 3000 if ESP32S2_RTC_CLK_SRC_EXT_CRYS || ESP32S2_RTC_CLK_SRC_EXT_OSC || ESP32S2_RTC_CLK_SRC_INT_8MD256
  384. default 576 if ESP32S2_RTC_CLK_SRC_INT_RC
  385. range 0 125000
  386. help
  387. When the startup code initializes RTC_SLOW_CLK, it can perform
  388. calibration by comparing the RTC_SLOW_CLK frequency with main XTAL
  389. frequency. This option sets the number of RTC_SLOW_CLK cycles measured
  390. by the calibration routine. Higher numbers increase calibration
  391. precision, which may be important for applications which spend a lot of
  392. time in deep sleep. Lower numbers reduce startup time.
  393. When this option is set to 0, clock calibration will not be performed at
  394. startup, and approximate clock frequencies will be assumed:
  395. - 90000 Hz if internal RC oscillator is used as clock source. For this use value 1024.
  396. - 32768 Hz if the 32k crystal oscillator is used. For this use value 3000 or more.
  397. In case more value will help improve the definition of the launch of the crystal.
  398. If the crystal could not start, it will be switched to internal RC.
  399. config ESP32S2_RTC_XTAL_CAL_RETRY
  400. int "Number of attempts to repeat 32k XTAL calibration"
  401. default 3
  402. depends on ESP32S2_RTC_CLK_SRC_EXT_CRYS
  403. help
  404. Number of attempts to repeat 32k XTAL calibration
  405. before giving up and switching to the internal RC.
  406. Increase this option if the 32k crystal oscillator
  407. does not start and switches to internal RC.
  408. config ESP32S2_NO_BLOBS
  409. bool "No Binary Blobs"
  410. depends on !BT_ENABLED
  411. default n
  412. help
  413. If enabled, this disables the linking of binary libraries in the application build. Note
  414. that after enabling this Wi-Fi/Bluetooth will not work.
  415. config ESP32S2_KEEP_USB_ALIVE
  416. bool "Keep USB peripheral enabled at start up" if !ESP_CONSOLE_USB_CDC
  417. default y if ESP_CONSOLE_USB_CDC
  418. help
  419. During the application initialization process, all the peripherals except UARTs and timers
  420. are reset. Enable this option to keep USB peripheral enabled.
  421. This option is automatically enabled if "USB CDC" console is selected.
  422. config ESP32S2_RTCDATA_IN_FAST_MEM
  423. bool "Place RTC_DATA_ATTR and RTC_RODATA_ATTR variables into RTC fast memory segment"
  424. default n
  425. help
  426. This option allows to place .rtc_data and .rtc_rodata sections into
  427. RTC fast memory segment to free the slow memory region for ULP programs.
  428. config ESP32S2_USE_FIXED_STATIC_RAM_SIZE
  429. bool "Use fixed static RAM size"
  430. default n
  431. help
  432. If this option is disabled, the DRAM part of the heap starts right after the .bss section,
  433. within the dram0_0 region. As a result, adding or removing some static variables
  434. will change the available heap size.
  435. If this option is enabled, the DRAM part of the heap starts right after the dram0_0 region,
  436. where its length is set with ESP32S2_FIXED_STATIC_RAM_SIZE
  437. config ESP32S2_FIXED_STATIC_RAM_SIZE
  438. hex "Fixed Static RAM size"
  439. default 0x10000
  440. range 0 0x34000
  441. depends on ESP32S2_USE_FIXED_STATIC_RAM_SIZE
  442. help
  443. RAM size dedicated for static variables (.data & .bss sections).
  444. config ESP32S2_ALLOW_RTC_FAST_MEM_AS_HEAP
  445. bool "Enable RTC fast memory for dynamic allocations"
  446. default y
  447. help
  448. This config option allows to add RTC fast memory region to system heap with capability
  449. similar to that of DRAM region but without DMA. This memory will be consumed first per
  450. heap initialization order by early startup services and scheduler related code. Speed
  451. wise RTC fast memory operates on APB clock and hence does not have much performance impact.
  452. endmenu # ESP32S2-Specific