Kconfig 12 KB

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  1. menu "Common ESP-related"
  2. config ESP_ERR_TO_NAME_LOOKUP
  3. bool "Enable lookup of error code strings"
  4. default "y"
  5. help
  6. Functions esp_err_to_name() and esp_err_to_name_r() return string representations of error codes from a
  7. pre-generated lookup table. This option can be used to turn off the use of the look-up table in order to
  8. save memory but this comes at the price of sacrificing distinguishable (meaningful) output string
  9. representations.
  10. config ESP_SYSTEM_EVENT_QUEUE_SIZE
  11. int "System event queue size"
  12. default 32
  13. help
  14. Config system event queue size in different application.
  15. config ESP_SYSTEM_EVENT_TASK_STACK_SIZE
  16. int "Event loop task stack size"
  17. default 2304
  18. help
  19. Config system event task stack size in different application.
  20. config ESP_MAIN_TASK_STACK_SIZE
  21. int "Main task stack size"
  22. default 3584
  23. help
  24. Configure the "main task" stack size. This is the stack of the task
  25. which calls app_main(). If app_main() returns then this task is deleted
  26. and its stack memory is freed.
  27. config ESP_IPC_TASK_STACK_SIZE
  28. int "Inter-Processor Call (IPC) task stack size"
  29. range 512 65536 if !APPTRACE_ENABLE
  30. range 2048 65536 if APPTRACE_ENABLE
  31. default 2048 if APPTRACE_ENABLE
  32. default 1024
  33. help
  34. Configure the IPC tasks stack size. One IPC task runs on each core
  35. (in dual core mode), and allows for cross-core function calls.
  36. See IPC documentation for more details.
  37. The default stack size should be enough for most common use cases.
  38. It can be shrunk if you are sure that you do not use any custom
  39. IPC functionality.
  40. config ESP_IPC_USES_CALLERS_PRIORITY
  41. bool "IPC runs at caller's priority"
  42. default y
  43. depends on !FREERTOS_UNICORE
  44. help
  45. If this option is not enabled then the IPC task will keep behavior
  46. same as prior to that of ESP-IDF v4.0, and hence IPC task will run
  47. at (configMAX_PRIORITIES - 1) priority.
  48. config ESP_MINIMAL_SHARED_STACK_SIZE
  49. int "Minimal allowed size for shared stack"
  50. default 2048
  51. help
  52. Minimal value of size, in bytes, accepted to execute a expression
  53. with shared stack.
  54. choice ESP_CONSOLE_UART
  55. prompt "Channel for console output"
  56. default ESP_CONSOLE_UART_DEFAULT
  57. help
  58. Select where to send console output (through stdout and stderr).
  59. - Default is to use UART0 on pre-defined GPIOs.
  60. - If "Custom" is selected, UART0 or UART1 can be chosen,
  61. and any pins can be selected.
  62. - If "None" is selected, there will be no console output on any UART, except
  63. for initial output from ROM bootloader. This ROM output can be suppressed by
  64. GPIO strapping or EFUSE, refer to chip datasheet for details.
  65. - On chips with USB peripheral, "USB CDC" option redirects output to the
  66. CDC port. This option uses the CDC driver in the chip ROM.
  67. This option is incompatible with TinyUSB stack.
  68. config ESP_CONSOLE_UART_DEFAULT
  69. bool "Default: UART0"
  70. config ESP_CONSOLE_USB_CDC
  71. bool "USB CDC"
  72. # The naming is confusing: USB_ENABLED means that TinyUSB driver is enabled, not USB in general.
  73. # && !USB_ENABLED is because the ROM CDC driver is currently incompatible with TinyUSB.
  74. depends on IDF_TARGET_ESP32S2 && !USB_ENABLED
  75. config ESP_CONSOLE_UART_CUSTOM
  76. bool "Custom UART"
  77. config ESP_CONSOLE_NONE
  78. bool "None"
  79. endchoice
  80. # Internal option, indicates that console UART is used (and not USB, for example)
  81. config ESP_CONSOLE_UART
  82. bool
  83. default y if ESP_CONSOLE_UART_DEFAULT || ESP_CONSOLE_UART_CUSTOM
  84. choice ESP_CONSOLE_UART_NUM
  85. prompt "UART peripheral to use for console output (0-1)"
  86. depends on ESP_CONSOLE_UART_CUSTOM
  87. default ESP_CONSOLE_UART_CUSTOM_NUM_0
  88. help
  89. This UART peripheral is used for console output from the ESP-IDF Bootloader and the app.
  90. If the configuration is different in the Bootloader binary compared to the app binary, UART
  91. is reconfigured after the bootloader exits and the app starts.
  92. Due to an ESP32 ROM bug, UART2 is not supported for console output
  93. via esp_rom_printf.
  94. config ESP_CONSOLE_UART_CUSTOM_NUM_0
  95. bool "UART0"
  96. config ESP_CONSOLE_UART_CUSTOM_NUM_1
  97. bool "UART1"
  98. endchoice
  99. config ESP_CONSOLE_UART_NUM
  100. int
  101. default 0 if ESP_CONSOLE_UART_DEFAULT
  102. default 0 if ESP_CONSOLE_UART_CUSTOM_NUM_0
  103. default 1 if ESP_CONSOLE_UART_CUSTOM_NUM_1
  104. default -1 if !ESP_CONSOLE_UART
  105. config ESP_CONSOLE_UART_TX_GPIO
  106. int "UART TX on GPIO#"
  107. depends on ESP_CONSOLE_UART_CUSTOM
  108. range 0 46
  109. default 1 if IDF_TARGET_ESP32
  110. default 43
  111. help
  112. This GPIO is used for console UART TX output in the ESP-IDF Bootloader and the app (including
  113. boot log output and default standard output and standard error of the app).
  114. If the configuration is different in the Bootloader binary compared to the app binary, UART
  115. is reconfigured after the bootloader exits and the app starts.
  116. config ESP_CONSOLE_UART_RX_GPIO
  117. int "UART RX on GPIO#"
  118. depends on ESP_CONSOLE_UART_CUSTOM
  119. range 0 46
  120. default 3 if IDF_TARGET_ESP32
  121. default 44
  122. help
  123. This GPIO is used for UART RX input in the ESP-IDF Bootloader and the app (including
  124. default default standard input of the app).
  125. Note: The default ESP-IDF Bootloader configures this pin but doesn't read anything from the UART.
  126. If the configuration is different in the Bootloader binary compared to the app binary, UART
  127. is reconfigured after the bootloader exits and the app starts.
  128. config ESP_CONSOLE_UART_BAUDRATE
  129. int
  130. prompt "UART console baud rate" if ESP_CONSOLE_UART_CUSTOM
  131. depends on ESP_CONSOLE_UART
  132. default 115200
  133. range 1200 4000000 if !PM_ENABLE
  134. range 1200 1000000 if PM_ENABLE
  135. help
  136. This baud rate is used by both the ESP-IDF Bootloader and the app (including
  137. boot log output and default standard input/output/error of the app).
  138. The app's maximum baud rate depends on the UART clock source. If Power Management is disabled,
  139. the UART clock source is the APB clock and all baud rates in the available range will be sufficiently
  140. accurate. If Power Management is enabled, REF_TICK clock source is used so the baud rate is divided
  141. from 1MHz. Baud rates above 1Mbps are not possible and values between 500Kbps and 1Mbps may not be
  142. accurate.
  143. If the configuration is different in the Bootloader binary compared to the app binary, UART
  144. is reconfigured after the bootloader exits and the app starts.
  145. config ESP_CONSOLE_USB_CDC_RX_BUF_SIZE
  146. int "Size of USB CDC RX buffer"
  147. depends on ESP_CONSOLE_USB_CDC
  148. default 64
  149. range 4 16384
  150. help
  151. Set the size of USB CDC RX buffer. Increase the buffer size if your application
  152. is often receiving data over USB CDC.
  153. config ESP_CONSOLE_USB_CDC_SUPPORT_ETS_PRINTF
  154. bool "Enable esp_rom_printf / ESP_EARLY_LOG via USB CDC"
  155. depends on ESP_CONSOLE_USB_CDC
  156. default n
  157. help
  158. If enabled, esp_rom_printf and ESP_EARLY_LOG output will also be sent over USB CDC.
  159. Disabling this option saves about 1kB or RAM.
  160. config ESP_INT_WDT
  161. bool "Interrupt watchdog"
  162. default y
  163. help
  164. This watchdog timer can detect if the FreeRTOS tick interrupt has not been called for a certain time,
  165. either because a task turned off interrupts and did not turn them on for a long time, or because an
  166. interrupt handler did not return. It will try to invoke the panic handler first and failing that
  167. reset the SoC.
  168. config ESP_INT_WDT_TIMEOUT_MS
  169. int "Interrupt watchdog timeout (ms)"
  170. depends on ESP_INT_WDT
  171. default 300 if !ESP32_SPIRAM_SUPPORT
  172. default 800 if ESP32_SPIRAM_SUPPORT
  173. range 10 10000
  174. help
  175. The timeout of the watchdog, in miliseconds. Make this higher than the FreeRTOS tick rate.
  176. config ESP_INT_WDT_CHECK_CPU1
  177. bool "Also watch CPU1 tick interrupt"
  178. depends on ESP_INT_WDT && !FREERTOS_UNICORE
  179. default y
  180. help
  181. Also detect if interrupts on CPU 1 are disabled for too long.
  182. config ESP_TASK_WDT
  183. bool "Initialize Task Watchdog Timer on startup"
  184. default y
  185. help
  186. The Task Watchdog Timer can be used to make sure individual tasks are still
  187. running. Enabling this option will cause the Task Watchdog Timer to be
  188. initialized automatically at startup. The Task Watchdog timer can be
  189. initialized after startup as well (see Task Watchdog Timer API Reference)
  190. config ESP_TASK_WDT_PANIC
  191. bool "Invoke panic handler on Task Watchdog timeout"
  192. depends on ESP_TASK_WDT
  193. default n
  194. help
  195. If this option is enabled, the Task Watchdog Timer will be configured to
  196. trigger the panic handler when it times out. This can also be configured
  197. at run time (see Task Watchdog Timer API Reference)
  198. config ESP_TASK_WDT_TIMEOUT_S
  199. int "Task Watchdog timeout period (seconds)"
  200. depends on ESP_TASK_WDT
  201. range 1 60
  202. default 5
  203. help
  204. Timeout period configuration for the Task Watchdog Timer in seconds.
  205. This is also configurable at run time (see Task Watchdog Timer API Reference)
  206. config ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0
  207. bool "Watch CPU0 Idle Task"
  208. depends on ESP_TASK_WDT
  209. default y
  210. help
  211. If this option is enabled, the Task Watchdog Timer will watch the CPU0
  212. Idle Task. Having the Task Watchdog watch the Idle Task allows for detection
  213. of CPU starvation as the Idle Task not being called is usually a symptom of
  214. CPU starvation. Starvation of the Idle Task is detrimental as FreeRTOS household
  215. tasks depend on the Idle Task getting some runtime every now and then.
  216. config ESP_TASK_WDT_CHECK_IDLE_TASK_CPU1
  217. bool "Watch CPU1 Idle Task"
  218. depends on ESP_TASK_WDT && !FREERTOS_UNICORE
  219. default y
  220. help
  221. If this option is enabled, the Task Wtachdog Timer will wach the CPU1
  222. Idle Task.
  223. config ESP_PANIC_HANDLER_IRAM
  224. bool "Place panic handler code in IRAM"
  225. default n
  226. help
  227. If this option is disabled (default), the panic handler code is placed in flash not IRAM.
  228. This means that if ESP-IDF crashes while flash cache is disabled, the panic handler will
  229. automatically re-enable flash cache before running GDB Stub or Core Dump. This adds some minor
  230. risk, if the flash cache status is also corrupted during the crash.
  231. If this option is enabled, the panic handler code is placed in IRAM. This allows the panic
  232. handler to run without needing to re-enable cache first. This may be necessary to debug some
  233. complex issues with crashes while flash cache is disabled (for example, when writing to
  234. SPI flash.)
  235. config ESP_DEBUG_STUBS_ENABLE
  236. bool
  237. default COMPILER_OPTIMIZATION_LEVEL_DEBUG
  238. depends on !ESP32_TRAX && !ESP32S2_TRAX
  239. help
  240. Debug stubs are used by OpenOCD to execute pre-compiled onboard code
  241. which does some useful debugging stuff, e.g. GCOV data dump.
  242. config ESP_MAC_ADDR_UNIVERSE_WIFI_STA
  243. bool
  244. config ESP_MAC_ADDR_UNIVERSE_WIFI_AP
  245. bool
  246. config ESP_MAC_ADDR_UNIVERSE_BT
  247. bool
  248. config ESP_MAC_ADDR_UNIVERSE_BT_OFFSET
  249. int
  250. default 2 if ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR
  251. default 1 if ESP32_UNIVERSAL_MAC_ADDRESSES_TWO
  252. default 1
  253. config ESP_MAC_ADDR_UNIVERSE_ETH
  254. bool
  255. endmenu # Common ESP-related