esp_flash_spi_init.c 9.0 KB

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  1. // Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
  2. //
  3. // Licensed under the Apache License, Version 2.0 (the "License");
  4. // you may not use this file except in compliance with the License.
  5. // You may obtain a copy of the License at
  6. //
  7. // http://www.apache.org/licenses/LICENSE-2.0
  8. //
  9. // Unless required by applicable law or agreed to in writing, software
  10. // distributed under the License is distributed on an "AS IS" BASIS,
  11. // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  12. // See the License for the specific language governing permissions and
  13. // limitations under the License.
  14. #include "sdkconfig.h"
  15. #include "esp_flash.h"
  16. #include "memspi_host_driver.h"
  17. #include "esp_flash_spi_init.h"
  18. #include "driver/gpio.h"
  19. #include "esp_rom_gpio.h"
  20. #include "esp_rom_efuse.h"
  21. #include "esp_log.h"
  22. #include "esp_heap_caps.h"
  23. #include "hal/spi_types.h"
  24. #include "driver/spi_common_internal.h"
  25. #include "esp_flash_internal.h"
  26. #include "esp_rom_gpio.h"
  27. #if CONFIG_IDF_TARGET_ESP32
  28. #include "esp32/rom/spi_flash.h"
  29. #elif CONFIG_IDF_TARGET_ESP32S2
  30. #include "esp32s2/rom/spi_flash.h"
  31. #elif CONFIG_IDF_TARGET_ESP32S3
  32. #include "esp32s3/rom/spi_flash.h"
  33. #elif CONFIG_IDF_TARGET_ESP32C3
  34. #include "esp32c3/rom/spi_flash.h"
  35. #endif
  36. __attribute__((unused)) static const char TAG[] = "spi_flash";
  37. #ifdef CONFIG_ESPTOOLPY_FLASHFREQ_80M
  38. #define DEFAULT_FLASH_SPEED ESP_FLASH_80MHZ
  39. #elif defined CONFIG_ESPTOOLPY_FLASHFREQ_40M
  40. #define DEFAULT_FLASH_SPEED ESP_FLASH_40MHZ
  41. #elif defined CONFIG_ESPTOOLPY_FLASHFREQ_26M
  42. #define DEFAULT_FLASH_SPEED ESP_FLASH_26MHZ
  43. #elif defined CONFIG_ESPTOOLPY_FLASHFREQ_20M
  44. #define DEFAULT_FLASH_SPEED ESP_FLASH_20MHZ
  45. #else
  46. #error Flash frequency not defined! Check the ``CONFIG_ESPTOOLPY_FLASHFREQ_*`` options.
  47. #endif
  48. #if defined(CONFIG_ESPTOOLPY_FLASHMODE_QIO)
  49. #define DEFAULT_FLASH_MODE SPI_FLASH_QIO
  50. #elif defined(CONFIG_ESPTOOLPY_FLASHMODE_QOUT)
  51. #define DEFAULT_FLASH_MODE SPI_FLASH_QOUT
  52. #elif defined(CONFIG_ESPTOOLPY_FLASHMODE_DIO)
  53. #define DEFAULT_FLASH_MODE SPI_FLASH_DIO
  54. #elif defined(CONFIG_ESPTOOLPY_FLASHMODE_DOUT)
  55. #define DEFAULT_FLASH_MODE SPI_FLASH_DOUT
  56. #else
  57. #define DEFAULT_FLASH_MODE SPI_FLASH_FASTRD
  58. #endif
  59. //TODO: modify cs hold to meet requirements of all chips!!!
  60. #if CONFIG_IDF_TARGET_ESP32
  61. #define ESP_FLASH_HOST_CONFIG_DEFAULT() (memspi_host_config_t){ \
  62. .host_id = SPI_HOST,\
  63. .speed = DEFAULT_FLASH_SPEED, \
  64. .cs_num = 0, \
  65. .iomux = false, \
  66. .input_delay_ns = 0,\
  67. }
  68. #elif CONFIG_IDF_TARGET_ESP32S2
  69. #define ESP_FLASH_HOST_CONFIG_DEFAULT() (memspi_host_config_t){ \
  70. .host_id = SPI_HOST,\
  71. .speed = DEFAULT_FLASH_SPEED, \
  72. .cs_num = 0, \
  73. .iomux = true, \
  74. .input_delay_ns = 0,\
  75. }
  76. #elif CONFIG_IDF_TARGET_ESP32S3
  77. #include "esp32s3/rom/efuse.h"
  78. #define ESP_FLASH_HOST_CONFIG_DEFAULT() (memspi_host_config_t){ \
  79. .host_id = SPI_HOST,\
  80. .speed = DEFAULT_FLASH_SPEED, \
  81. .cs_num = 0, \
  82. .iomux = true, \
  83. .input_delay_ns = 0,\
  84. }
  85. #endif
  86. esp_flash_t *esp_flash_default_chip = NULL;
  87. static IRAM_ATTR NOINLINE_ATTR void cs_initialize(esp_flash_t *chip, const esp_flash_spi_device_config_t *config, bool use_iomux, int cs_id)
  88. {
  89. //Not using spicommon_cs_initialize since we don't want to put the whole
  90. //spi_periph_signal into the DRAM. Copy these data from flash before the
  91. //cache disabling
  92. int cs_io_num = config->cs_io_num;
  93. int spics_in = spi_periph_signal[config->host_id].spics_in;
  94. int spics_out = spi_periph_signal[config->host_id].spics_out[cs_id];
  95. int spics_func = spi_periph_signal[config->host_id].func;
  96. uint32_t iomux_reg = GPIO_PIN_MUX_REG[cs_io_num];
  97. //To avoid the panic caused by flash data line conflicts during cs line
  98. //initialization, disable the cache temporarily
  99. chip->os_func->start(chip->os_func_data);
  100. PIN_INPUT_ENABLE(iomux_reg);
  101. if (use_iomux) {
  102. PIN_FUNC_SELECT(iomux_reg, spics_func);
  103. } else {
  104. if (cs_io_num < 32) {
  105. GPIO.enable_w1ts = (0x1 << cs_io_num);
  106. } else {
  107. GPIO.enable1_w1ts.data = (0x1 << (cs_io_num - 32));
  108. }
  109. GPIO.pin[cs_io_num].pad_driver = 0;
  110. esp_rom_gpio_connect_out_signal(cs_io_num, spics_out, false, false);
  111. if (cs_id == 0) {
  112. esp_rom_gpio_connect_in_signal(cs_io_num, spics_in, false);
  113. }
  114. PIN_FUNC_SELECT(iomux_reg, PIN_FUNC_GPIO);
  115. }
  116. chip->os_func->end(chip->os_func_data);
  117. }
  118. esp_err_t spi_bus_add_flash_device(esp_flash_t **out_chip, const esp_flash_spi_device_config_t *config)
  119. {
  120. if (out_chip == NULL) {
  121. return ESP_ERR_INVALID_ARG;
  122. }
  123. esp_flash_t *chip = NULL;
  124. memspi_host_inst_t *host = NULL;
  125. esp_err_t ret = ESP_OK;
  126. uint32_t caps = MALLOC_CAP_DEFAULT;
  127. if (config->host_id == SPI_HOST) caps = MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT;
  128. chip = (esp_flash_t*)heap_caps_malloc(sizeof(esp_flash_t), caps);
  129. if (!chip) {
  130. ret = ESP_ERR_NO_MEM;
  131. goto fail;
  132. }
  133. host = (memspi_host_inst_t*)heap_caps_malloc(sizeof(memspi_host_inst_t), caps);
  134. *chip = (esp_flash_t) {
  135. .read_mode = config->io_mode,
  136. .host = (spi_flash_host_inst_t*)host,
  137. };
  138. if (!host) {
  139. ret = ESP_ERR_NO_MEM;
  140. goto fail;
  141. }
  142. int dev_id = -1;
  143. esp_err_t err = esp_flash_init_os_functions(chip, config->host_id, &dev_id);
  144. if (err == ESP_ERR_NOT_SUPPORTED) {
  145. ESP_LOGE(TAG, "Init os functions failed! No free CS.");
  146. } else if (err == ESP_ERR_INVALID_ARG) {
  147. ESP_LOGE(TAG, "Init os functions failed! Bus lock not initialized (check CONFIG_SPI_FLASH_SHARE_SPI1_BUS).");
  148. }
  149. if (err != ESP_OK) {
  150. ret = err;
  151. goto fail;
  152. }
  153. // When `CONFIG_SPI_FLASH_SHARE_SPI1_BUS` is not enabled on SPI1 bus, the
  154. // `esp_flash_init_os_functions` will not be able to assign a new device ID. In this case, we
  155. // use the `cs_id` in the config structure.
  156. if (dev_id == -1 && config->host_id == SPI_HOST) {
  157. dev_id = config->cs_id;
  158. }
  159. assert(dev_id < SOC_SPI_PERIPH_CS_NUM(config->host_id) && dev_id >= 0);
  160. bool use_iomux = spicommon_bus_using_iomux(config->host_id);
  161. memspi_host_config_t host_cfg = {
  162. .host_id = config->host_id,
  163. .cs_num = dev_id,
  164. .iomux = use_iomux,
  165. .input_delay_ns = config->input_delay_ns,
  166. .speed = config->speed,
  167. };
  168. err = memspi_host_init_pointers(host, &host_cfg);
  169. if (err != ESP_OK) {
  170. ret = err;
  171. goto fail;
  172. }
  173. // The cs_id inside `config` is deprecated, use the `dev_id` provided by the bus lock instead.
  174. cs_initialize(chip, config, use_iomux, dev_id);
  175. *out_chip = chip;
  176. return ret;
  177. fail:
  178. // The memory allocated are free'd in the `spi_bus_remove_flash_device`.
  179. spi_bus_remove_flash_device(chip);
  180. return ret;
  181. }
  182. esp_err_t spi_bus_remove_flash_device(esp_flash_t *chip)
  183. {
  184. if (chip==NULL) {
  185. return ESP_ERR_INVALID_ARG;
  186. }
  187. esp_flash_deinit_os_functions(chip);
  188. free(chip->host);
  189. free(chip);
  190. return ESP_OK;
  191. }
  192. /* The default (ie initial boot) no-OS ROM esp_flash_os_functions_t */
  193. extern const esp_flash_os_functions_t esp_flash_noos_functions;
  194. #ifndef CONFIG_SPI_FLASH_USE_LEGACY_IMPL
  195. static DRAM_ATTR memspi_host_inst_t esp_flash_default_host;
  196. static DRAM_ATTR esp_flash_t default_chip = {
  197. .read_mode = DEFAULT_FLASH_MODE,
  198. .host = (spi_flash_host_inst_t*)&esp_flash_default_host,
  199. .os_func = &esp_flash_noos_functions,
  200. };
  201. esp_err_t esp_flash_init_default_chip(void)
  202. {
  203. memspi_host_config_t cfg = ESP_FLASH_HOST_CONFIG_DEFAULT();
  204. #if !CONFIG_IDF_TARGET_ESP32
  205. // For esp32s2 spi IOs are configured as from IO MUX by default
  206. cfg.iomux = esp_rom_efuse_get_flash_gpio_info() == 0 ? true : false;
  207. #endif
  208. //the host is already initialized, only do init for the data and load it to the host
  209. esp_err_t err = memspi_host_init_pointers(&esp_flash_default_host, &cfg);
  210. if (err != ESP_OK) {
  211. return err;
  212. }
  213. // ROM TODO: account for non-standard default pins in efuse
  214. // ROM TODO: to account for chips which are slow to power on, maybe keep probing in a loop here
  215. err = esp_flash_init(&default_chip);
  216. if (err != ESP_OK) {
  217. return err;
  218. }
  219. if (default_chip.size < g_rom_flashchip.chip_size) {
  220. ESP_EARLY_LOGE(TAG, "Detected size(%dk) smaller than the size in the binary image header(%dk). Probe failed.", default_chip.size/1024, g_rom_flashchip.chip_size/1024);
  221. return ESP_ERR_FLASH_SIZE_NOT_MATCH;
  222. } else if (default_chip.size > g_rom_flashchip.chip_size) {
  223. ESP_EARLY_LOGW(TAG, "Detected size(%dk) larger than the size in the binary image header(%dk). Using the size in the binary image header.", default_chip.size/1024, g_rom_flashchip.chip_size/1024);
  224. default_chip.size = g_rom_flashchip.chip_size;
  225. }
  226. default_chip.size = g_rom_flashchip.chip_size;
  227. esp_flash_default_chip = &default_chip;
  228. return ESP_OK;
  229. }
  230. esp_err_t esp_flash_app_init(void)
  231. {
  232. esp_err_t err = ESP_OK;
  233. #if CONFIG_SPI_FLASH_SHARE_SPI1_BUS
  234. err = esp_flash_init_main_bus_lock();
  235. if (err != ESP_OK) return err;
  236. #endif
  237. err = esp_flash_app_enable_os_functions(&default_chip);
  238. return err;
  239. }
  240. #endif //!CONFIG_SPI_FLASH_USE_LEGACY_IMPL