esp_async_memcpy.c 12 KB

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  1. // Copyright 2020 Espressif Systems (Shanghai) PTE LTD
  2. //
  3. // Licensed under the Apache License, Version 2.0 (the "License");
  4. // you may not use this file except in compliance with the License.
  5. // You may obtain a copy of the License at
  6. //
  7. // http://www.apache.org/licenses/LICENSE-2.0
  8. //
  9. // Unless required by applicable law or agreed to in writing, software
  10. // distributed under the License is distributed on an "AS IS" BASIS,
  11. // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  12. // See the License for the specific language governing permissions and
  13. // limitations under the License.
  14. #include "freertos/FreeRTOS.h"
  15. #include "freertos/semphr.h"
  16. #include "hal/dma_types.h"
  17. #include "esp_compiler.h"
  18. #include "esp_heap_caps.h"
  19. #include "esp_log.h"
  20. #include "esp_async_memcpy.h"
  21. #include "esp_async_memcpy_impl.h"
  22. static const char *TAG = "async_memcpy";
  23. #define ASMCP_CHECK(a, msg, tag, ret, ...) \
  24. do \
  25. { \
  26. if (unlikely(!(a))) \
  27. { \
  28. ESP_LOGE(TAG, "%s(%d): " msg, __FUNCTION__, __LINE__, ##__VA_ARGS__); \
  29. ret_code = ret; \
  30. goto tag; \
  31. } \
  32. } while (0)
  33. /**
  34. * @brief Type of async mcp stream
  35. * mcp stream inherits DMA descriptor, besides that, it has a callback function member
  36. */
  37. typedef struct {
  38. dma_descriptor_t desc;
  39. async_memcpy_isr_cb_t cb;
  40. void *cb_args;
  41. } async_memcpy_stream_t;
  42. /**
  43. * @brief Type of async mcp driver context
  44. */
  45. typedef struct async_memcpy_context_t {
  46. async_memcpy_impl_t mcp_impl; // implementation layer
  47. portMUX_TYPE spinlock; // spinlock, prevent operating descriptors concurrently
  48. intr_handle_t intr_hdl; // interrupt handle
  49. uint32_t flags; // extra driver flags
  50. dma_descriptor_t *tx_desc; // pointer to the next free TX descriptor
  51. dma_descriptor_t *rx_desc; // pointer to the next free RX descriptor
  52. dma_descriptor_t *next_rx_desc_to_check; // pointer to the next RX descriptor to recycle
  53. uint32_t max_stream_num; // maximum number of streams
  54. async_memcpy_stream_t *out_streams; // pointer to the first TX stream
  55. async_memcpy_stream_t *in_streams; // pointer to the first RX stream
  56. async_memcpy_stream_t streams_pool[0]; // stream pool (TX + RX), the size is configured during driver installation
  57. } async_memcpy_context_t;
  58. esp_err_t esp_async_memcpy_install(const async_memcpy_config_t *config, async_memcpy_t *asmcp)
  59. {
  60. esp_err_t ret_code = ESP_OK;
  61. async_memcpy_context_t *mcp_hdl = NULL;
  62. ASMCP_CHECK(config, "configuration can't be null", err, ESP_ERR_INVALID_ARG);
  63. ASMCP_CHECK(asmcp, "can't assign mcp handle to null", err, ESP_ERR_INVALID_ARG);
  64. // context memory size + stream pool size
  65. size_t total_malloc_size = sizeof(async_memcpy_context_t) + sizeof(async_memcpy_stream_t) * config->backlog * 2;
  66. // to work when cache is disabled, the driver handle should located in SRAM
  67. mcp_hdl = heap_caps_calloc(1, total_malloc_size, MALLOC_CAP_8BIT | MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL);
  68. ASMCP_CHECK(mcp_hdl, "allocate context memory failed", err, ESP_ERR_NO_MEM);
  69. mcp_hdl->flags = config->flags;
  70. mcp_hdl->out_streams = mcp_hdl->streams_pool;
  71. mcp_hdl->in_streams = mcp_hdl->streams_pool + config->backlog;
  72. mcp_hdl->max_stream_num = config->backlog;
  73. // circle TX/RX descriptors
  74. for (size_t i = 0; i < mcp_hdl->max_stream_num; i++) {
  75. mcp_hdl->out_streams[i].desc.dw0.owner = DMA_DESCRIPTOR_BUFFER_OWNER_CPU;
  76. mcp_hdl->out_streams[i].desc.next = &mcp_hdl->out_streams[i + 1].desc;
  77. mcp_hdl->in_streams[i].desc.dw0.owner = DMA_DESCRIPTOR_BUFFER_OWNER_CPU;
  78. mcp_hdl->in_streams[i].desc.next = &mcp_hdl->in_streams[i + 1].desc;
  79. }
  80. mcp_hdl->out_streams[mcp_hdl->max_stream_num - 1].desc.next = &mcp_hdl->out_streams[0].desc;
  81. mcp_hdl->in_streams[mcp_hdl->max_stream_num - 1].desc.next = &mcp_hdl->in_streams[0].desc;
  82. mcp_hdl->tx_desc = &mcp_hdl->out_streams[0].desc;
  83. mcp_hdl->rx_desc = &mcp_hdl->in_streams[0].desc;
  84. mcp_hdl->next_rx_desc_to_check = &mcp_hdl->in_streams[0].desc;
  85. mcp_hdl->spinlock = (portMUX_TYPE)portMUX_INITIALIZER_UNLOCKED;
  86. // initialize implementation layer
  87. async_memcpy_impl_init(&mcp_hdl->mcp_impl);
  88. *asmcp = mcp_hdl;
  89. async_memcpy_impl_start(&mcp_hdl->mcp_impl, (intptr_t)&mcp_hdl->out_streams[0].desc, (intptr_t)&mcp_hdl->in_streams[0].desc);
  90. return ESP_OK;
  91. err:
  92. if (mcp_hdl) {
  93. free(mcp_hdl);
  94. }
  95. if (asmcp) {
  96. *asmcp = NULL;
  97. }
  98. return ret_code;
  99. }
  100. esp_err_t esp_async_memcpy_uninstall(async_memcpy_t asmcp)
  101. {
  102. esp_err_t ret_code = ESP_OK;
  103. ASMCP_CHECK(asmcp, "mcp handle can't be null", err, ESP_ERR_INVALID_ARG);
  104. async_memcpy_impl_stop(&asmcp->mcp_impl);
  105. async_memcpy_impl_deinit(&asmcp->mcp_impl);
  106. free(asmcp);
  107. return ESP_OK;
  108. err:
  109. return ret_code;
  110. }
  111. static int async_memcpy_prepare_receive(async_memcpy_t asmcp, void *buffer, size_t size, dma_descriptor_t **start_desc, dma_descriptor_t **end_desc)
  112. {
  113. uint32_t prepared_length = 0;
  114. uint8_t *buf = (uint8_t *)buffer;
  115. dma_descriptor_t *desc = asmcp->rx_desc; // descriptor iterator
  116. dma_descriptor_t *start = desc;
  117. dma_descriptor_t *end = desc;
  118. while (size > DMA_DESCRIPTOR_BUFFER_MAX_SIZE) {
  119. if (desc->dw0.owner != DMA_DESCRIPTOR_BUFFER_OWNER_DMA) {
  120. desc->dw0.size = DMA_DESCRIPTOR_BUFFER_MAX_SIZE;
  121. desc->buffer = &buf[prepared_length];
  122. desc = desc->next; // move to next descriptor
  123. prepared_length += DMA_DESCRIPTOR_BUFFER_MAX_SIZE;
  124. size -= DMA_DESCRIPTOR_BUFFER_MAX_SIZE;
  125. } else {
  126. // out of RX descriptors
  127. goto _exit;
  128. }
  129. }
  130. if (size) {
  131. if (desc->dw0.owner != DMA_DESCRIPTOR_BUFFER_OWNER_DMA) {
  132. end = desc; // the last descriptor used
  133. desc->dw0.size = size;
  134. desc->buffer = &buf[prepared_length];
  135. desc = desc->next; // move to next descriptor
  136. prepared_length += size;
  137. } else {
  138. // out of RX descriptors
  139. goto _exit;
  140. }
  141. }
  142. _exit:
  143. *start_desc = start;
  144. *end_desc = end;
  145. return prepared_length;
  146. }
  147. static int async_memcpy_prepare_transmit(async_memcpy_t asmcp, void *buffer, size_t len, dma_descriptor_t **start_desc, dma_descriptor_t **end_desc)
  148. {
  149. uint32_t prepared_length = 0;
  150. uint8_t *buf = (uint8_t *)buffer;
  151. dma_descriptor_t *desc = asmcp->tx_desc; // descriptor iterator
  152. dma_descriptor_t *start = desc;
  153. dma_descriptor_t *end = desc;
  154. while (len > DMA_DESCRIPTOR_BUFFER_MAX_SIZE) {
  155. if (desc->dw0.owner != DMA_DESCRIPTOR_BUFFER_OWNER_DMA) {
  156. desc->dw0.suc_eof = 0; // not the end of the transaction
  157. desc->dw0.size = DMA_DESCRIPTOR_BUFFER_MAX_SIZE;
  158. desc->dw0.length = DMA_DESCRIPTOR_BUFFER_MAX_SIZE;
  159. desc->buffer = &buf[prepared_length];
  160. desc = desc->next; // move to next descriptor
  161. prepared_length += DMA_DESCRIPTOR_BUFFER_MAX_SIZE;
  162. len -= DMA_DESCRIPTOR_BUFFER_MAX_SIZE;
  163. } else {
  164. // out of TX descriptors
  165. goto _exit;
  166. }
  167. }
  168. if (len) {
  169. if (desc->dw0.owner != DMA_DESCRIPTOR_BUFFER_OWNER_DMA) {
  170. end = desc; // the last descriptor used
  171. desc->dw0.suc_eof = 1; // end of the transaction
  172. desc->dw0.size = len;
  173. desc->dw0.length = len;
  174. desc->buffer = &buf[prepared_length];
  175. desc = desc->next; // move to next descriptor
  176. prepared_length += len;
  177. } else {
  178. // out of TX descriptors
  179. goto _exit;
  180. }
  181. }
  182. *start_desc = start;
  183. *end_desc = end;
  184. _exit:
  185. return prepared_length;
  186. }
  187. static bool async_memcpy_get_next_rx_descriptor(async_memcpy_t asmcp, dma_descriptor_t *eof_desc, dma_descriptor_t **next_desc)
  188. {
  189. dma_descriptor_t *next = asmcp->next_rx_desc_to_check;
  190. // additional check, to avoid potential interrupt got triggered by mistake
  191. if (next->dw0.owner == DMA_DESCRIPTOR_BUFFER_OWNER_CPU) {
  192. asmcp->next_rx_desc_to_check = asmcp->next_rx_desc_to_check->next;
  193. *next_desc = next;
  194. // return if we need to continue
  195. return eof_desc == next ? false : true;
  196. }
  197. *next_desc = NULL;
  198. return false;
  199. }
  200. esp_err_t esp_async_memcpy(async_memcpy_t asmcp, void *dst, void *src, size_t n, async_memcpy_isr_cb_t cb_isr, void *cb_args)
  201. {
  202. esp_err_t ret_code = ESP_OK;
  203. dma_descriptor_t *rx_start_desc = NULL;
  204. dma_descriptor_t *rx_end_desc = NULL;
  205. dma_descriptor_t *tx_start_desc = NULL;
  206. dma_descriptor_t *tx_end_desc = NULL;
  207. size_t rx_prepared_size = 0;
  208. size_t tx_prepared_size = 0;
  209. ASMCP_CHECK(asmcp, "mcp handle can't be null", err, ESP_ERR_INVALID_ARG);
  210. ASMCP_CHECK(async_memcpy_impl_is_buffer_address_valid(&asmcp->mcp_impl, src, dst), "buffer address not valid", err, ESP_ERR_INVALID_ARG);
  211. ASMCP_CHECK(n <= DMA_DESCRIPTOR_BUFFER_MAX_SIZE * asmcp->max_stream_num, "buffer size too large", err, ESP_ERR_INVALID_ARG);
  212. // Prepare TX and RX descriptor
  213. portENTER_CRITICAL_SAFE(&asmcp->spinlock);
  214. rx_prepared_size = async_memcpy_prepare_receive(asmcp, dst, n, &rx_start_desc, &rx_end_desc);
  215. tx_prepared_size = async_memcpy_prepare_transmit(asmcp, src, n, &tx_start_desc, &tx_end_desc);
  216. if ((rx_prepared_size == n) && (tx_prepared_size == n)) {
  217. // register user callback to the last descriptor
  218. async_memcpy_stream_t *mcp_stream = __containerof(rx_end_desc, async_memcpy_stream_t, desc);
  219. mcp_stream->cb = cb_isr;
  220. mcp_stream->cb_args = cb_args;
  221. // restart RX firstly
  222. dma_descriptor_t *desc = rx_start_desc;
  223. while (desc != rx_end_desc) {
  224. desc->dw0.owner = DMA_DESCRIPTOR_BUFFER_OWNER_DMA;
  225. desc = desc->next;
  226. }
  227. desc->dw0.owner = DMA_DESCRIPTOR_BUFFER_OWNER_DMA;
  228. asmcp->rx_desc = desc->next;
  229. // restart TX secondly
  230. desc = tx_start_desc;
  231. while (desc != tx_end_desc) {
  232. desc->dw0.owner = DMA_DESCRIPTOR_BUFFER_OWNER_DMA;
  233. desc = desc->next;
  234. }
  235. desc->dw0.owner = DMA_DESCRIPTOR_BUFFER_OWNER_DMA;
  236. asmcp->tx_desc = desc->next;
  237. async_memcpy_impl_restart(&asmcp->mcp_impl);
  238. }
  239. portEXIT_CRITICAL_SAFE(&asmcp->spinlock);
  240. // It's unlikely that we have space for rx descriptor but no space for tx descriptor
  241. // Both tx and rx descriptor should move in the same pace
  242. ASMCP_CHECK(rx_prepared_size == n, "out of rx descriptor", err, ESP_FAIL);
  243. ASMCP_CHECK(tx_prepared_size == n, "out of tx descriptor", err, ESP_FAIL);
  244. return ESP_OK;
  245. err:
  246. return ret_code;
  247. }
  248. IRAM_ATTR void async_memcpy_isr_on_rx_done_event(async_memcpy_impl_t *impl)
  249. {
  250. bool to_continue = false;
  251. async_memcpy_stream_t *in_stream = NULL;
  252. dma_descriptor_t *next_desc = NULL;
  253. async_memcpy_context_t *asmcp = __containerof(impl, async_memcpy_context_t, mcp_impl);
  254. // get the RX eof descriptor address
  255. dma_descriptor_t *eof = (dma_descriptor_t *)impl->rx_eof_addr;
  256. // traversal all unchecked descriptors
  257. do {
  258. portENTER_CRITICAL_ISR(&asmcp->spinlock);
  259. // There is an assumption that the usage of rx descriptors are in the same pace as tx descriptors (this is determined by M2M DMA working mechanism)
  260. // And once the rx descriptor is recycled, the corresponding tx desc is guaranteed to be returned by DMA
  261. to_continue = async_memcpy_get_next_rx_descriptor(asmcp, eof, &next_desc);
  262. portEXIT_CRITICAL_ISR(&asmcp->spinlock);
  263. if (next_desc) {
  264. in_stream = __containerof(next_desc, async_memcpy_stream_t, desc);
  265. // invoke user registered callback if available
  266. if (in_stream->cb) {
  267. async_memcpy_event_t e = {0};
  268. if (in_stream->cb(asmcp, &e, in_stream->cb_args)) {
  269. impl->isr_need_yield = true;
  270. }
  271. in_stream->cb = NULL;
  272. in_stream->cb_args = NULL;
  273. }
  274. }
  275. } while (to_continue);
  276. }