ulp_riscv.c 2.1 KB

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  1. /*
  2. * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. */
  6. #include <stdio.h>
  7. #include <string.h>
  8. #include <stdlib.h>
  9. #include "sdkconfig.h"
  10. #include "esp_attr.h"
  11. #include "esp_err.h"
  12. #include "esp_log.h"
  13. #include "esp_private/esp_clk.h"
  14. #include "esp32s2/ulp.h"
  15. #include "esp32s2/ulp_riscv.h"
  16. #include "soc/soc.h"
  17. #include "soc/rtc.h"
  18. #include "soc/rtc_cntl_reg.h"
  19. #include "soc/sens_reg.h"
  20. #include "ulp_private.h"
  21. #include "esp_rom_sys.h"
  22. esp_err_t ulp_riscv_run(void)
  23. {
  24. /* Reset COCPU when power on. */
  25. SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT_RESET_EN);
  26. esp_rom_delay_us(20);
  27. CLEAR_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT_RESET_EN);
  28. /* The coprocessor cpu trap signal doesnt have a stable reset value,
  29. force ULP-RISC-V clock on to stop RTC_COCPU_TRAP_TRIG_EN from waking the CPU*/
  30. SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_CLK_FO);
  31. /* Disable ULP timer */
  32. CLEAR_PERI_REG_MASK(RTC_CNTL_ULP_CP_TIMER_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN);
  33. /* wait for at least 1 RTC_SLOW_CLK cycle */
  34. esp_rom_delay_us(20);
  35. /* Select RISC-V as the ULP_TIMER trigger target. */
  36. CLEAR_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SEL);
  37. /* Select ULP-RISC-V to send the DONE signal. */
  38. SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_DONE_FORCE);
  39. /* start ULP_TIMER */
  40. CLEAR_PERI_REG_MASK(RTC_CNTL_ULP_CP_CTRL_REG, RTC_CNTL_ULP_CP_FORCE_START_TOP);
  41. SET_PERI_REG_MASK(RTC_CNTL_ULP_CP_TIMER_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN);
  42. return ESP_OK;
  43. }
  44. esp_err_t ulp_riscv_load_binary(const uint8_t* program_binary, size_t program_size_bytes)
  45. {
  46. if (program_binary == NULL) {
  47. return ESP_ERR_INVALID_ARG;
  48. }
  49. if (program_size_bytes > ULP_RESERVE_MEM) {
  50. return ESP_ERR_INVALID_SIZE;
  51. }
  52. uint8_t* base = (uint8_t*) RTC_SLOW_MEM;
  53. //Start by clearing memory reserved with zeros, this will also will initialize the bss:
  54. memset(base, 0, ULP_RESERVE_MEM);
  55. memcpy(base, program_binary, program_size_bytes);
  56. return ESP_OK;
  57. }