sdmmc_transaction.c 12 KB

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  1. // Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
  2. //
  3. // Licensed under the Apache License, Version 2.0 (the "License");
  4. // you may not use this file except in compliance with the License.
  5. // You may obtain a copy of the License at
  6. //
  7. // http://www.apache.org/licenses/LICENSE-2.0
  8. //
  9. // Unless required by applicable law or agreed to in writing, software
  10. // distributed under the License is distributed on an "AS IS" BASIS,
  11. // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  12. // See the License for the specific language governing permissions and
  13. // limitations under the License.
  14. #include <string.h>
  15. #include "esp_err.h"
  16. #include "esp_log.h"
  17. #include "freertos/FreeRTOS.h"
  18. #include "freertos/queue.h"
  19. #include "freertos/semphr.h"
  20. #include "soc/sdmmc_reg.h"
  21. #include "soc/sdmmc_struct.h"
  22. #include "driver/sdmmc_types.h"
  23. #include "driver/sdmmc_defs.h"
  24. #include "driver/sdmmc_host.h"
  25. #include "sdmmc_private.h"
  26. /* Number of DMA descriptors used for transfer.
  27. * Increasing this value above 4 doesn't improve performance for the usual case
  28. * of SD memory cards (most data transfers are multiples of 512 bytes).
  29. */
  30. #define SDMMC_DMA_DESC_CNT 4
  31. static const char* TAG = "sdmmc_req";
  32. typedef enum {
  33. SDMMC_IDLE,
  34. SDMMC_SENDING_CMD,
  35. SDMMC_SENDING_DATA,
  36. SDMMC_BUSY,
  37. } sdmmc_req_state_t;
  38. typedef struct {
  39. uint8_t* ptr;
  40. size_t size_remaining;
  41. size_t next_desc;
  42. size_t desc_remaining;
  43. } sdmmc_transfer_state_t;
  44. const uint32_t SDMMC_DATA_ERR_MASK =
  45. SDMMC_INTMASK_DTO | SDMMC_INTMASK_DCRC |
  46. SDMMC_INTMASK_HTO | SDMMC_INTMASK_SBE |
  47. SDMMC_INTMASK_EBE;
  48. const uint32_t SDMMC_DMA_DONE_MASK =
  49. SDMMC_IDMAC_INTMASK_RI | SDMMC_IDMAC_INTMASK_TI |
  50. SDMMC_IDMAC_INTMASK_NI;
  51. const uint32_t SDMMC_CMD_ERR_MASK =
  52. SDMMC_INTMASK_RTO |
  53. SDMMC_INTMASK_RCRC |
  54. SDMMC_INTMASK_RESP_ERR;
  55. static sdmmc_desc_t s_dma_desc[SDMMC_DMA_DESC_CNT];
  56. static sdmmc_transfer_state_t s_cur_transfer = { 0 };
  57. static QueueHandle_t s_request_mutex;
  58. static esp_err_t handle_idle_state_events();
  59. static sdmmc_hw_cmd_t make_hw_cmd(sdmmc_command_t* cmd);
  60. static esp_err_t handle_event(sdmmc_command_t* cmd, sdmmc_req_state_t* pstate);
  61. static esp_err_t process_events(sdmmc_event_t evt, sdmmc_command_t* cmd, sdmmc_req_state_t* pstate);
  62. static void process_command_response(uint32_t status, sdmmc_command_t* cmd);
  63. static void fill_dma_descriptors(size_t num_desc);
  64. esp_err_t sdmmc_host_transaction_handler_init()
  65. {
  66. assert(s_request_mutex == NULL);
  67. s_request_mutex = xSemaphoreCreateMutex();
  68. if (!s_request_mutex) {
  69. return ESP_ERR_NO_MEM;
  70. }
  71. return ESP_OK;
  72. }
  73. void sdmmc_host_transaction_handler_deinit()
  74. {
  75. assert(s_request_mutex);
  76. vSemaphoreDelete(s_request_mutex);
  77. s_request_mutex = NULL;
  78. }
  79. esp_err_t sdmmc_host_do_transaction(int slot, sdmmc_command_t* cmdinfo)
  80. {
  81. xSemaphoreTake(s_request_mutex, portMAX_DELAY);
  82. // dispose of any events which happened asynchronously
  83. handle_idle_state_events();
  84. // convert cmdinfo to hardware register value
  85. sdmmc_hw_cmd_t hw_cmd = make_hw_cmd(cmdinfo);
  86. if (cmdinfo->data) {
  87. // these constraints should be handled by upper layer
  88. assert(cmdinfo->datalen >= 4);
  89. assert(cmdinfo->blklen % 4 == 0);
  90. // this clears "owned by IDMAC" bits
  91. memset(s_dma_desc, 0, sizeof(s_dma_desc));
  92. // initialize first descriptor
  93. s_dma_desc[0].first_descriptor = 1;
  94. // save transfer info
  95. s_cur_transfer.ptr = (uint8_t*) cmdinfo->data;
  96. s_cur_transfer.size_remaining = cmdinfo->datalen;
  97. s_cur_transfer.next_desc = 0;
  98. s_cur_transfer.desc_remaining = (cmdinfo->datalen + SDMMC_DMA_MAX_BUF_LEN - 1) / SDMMC_DMA_MAX_BUF_LEN;
  99. // prepare descriptors
  100. fill_dma_descriptors(SDMMC_DMA_DESC_CNT);
  101. // write transfer info into hardware
  102. sdmmc_host_dma_prepare(&s_dma_desc[0], cmdinfo->blklen, cmdinfo->datalen);
  103. }
  104. // write command into hardware, this also sends the command to the card
  105. esp_err_t ret = sdmmc_host_start_command(slot, hw_cmd, cmdinfo->arg);
  106. if (ret != ESP_OK) {
  107. xSemaphoreGive(s_request_mutex);
  108. return ret;
  109. }
  110. // process events until transfer is complete
  111. cmdinfo->error = ESP_OK;
  112. sdmmc_req_state_t state = SDMMC_SENDING_CMD;
  113. while (state != SDMMC_IDLE) {
  114. ret = handle_event(cmdinfo, &state);
  115. if (ret != ESP_OK) {
  116. break;
  117. }
  118. }
  119. xSemaphoreGive(s_request_mutex);
  120. return ret;
  121. }
  122. static void fill_dma_descriptors(size_t num_desc)
  123. {
  124. for (size_t i = 0; i < num_desc; ++i) {
  125. if (s_cur_transfer.size_remaining == 0) {
  126. return;
  127. }
  128. const size_t next = s_cur_transfer.next_desc;
  129. sdmmc_desc_t* desc = &s_dma_desc[next];
  130. assert(!desc->owned_by_idmac);
  131. size_t size_to_fill =
  132. (s_cur_transfer.size_remaining < SDMMC_DMA_MAX_BUF_LEN) ?
  133. s_cur_transfer.size_remaining : SDMMC_DMA_MAX_BUF_LEN;
  134. bool last = size_to_fill == s_cur_transfer.size_remaining;
  135. desc->last_descriptor = last;
  136. desc->second_address_chained = 1;
  137. desc->owned_by_idmac = 1;
  138. desc->buffer1_ptr = s_cur_transfer.ptr;
  139. desc->next_desc_ptr = (last) ? NULL : &s_dma_desc[(next + 1) % SDMMC_DMA_DESC_CNT];
  140. desc->buffer1_size = size_to_fill;
  141. s_cur_transfer.size_remaining -= size_to_fill;
  142. s_cur_transfer.ptr += size_to_fill;
  143. s_cur_transfer.next_desc = (s_cur_transfer.next_desc + 1) % SDMMC_DMA_DESC_CNT;
  144. ESP_LOGV(TAG, "fill %d desc=%d rem=%d next=%d last=%d sz=%d",
  145. num_desc, next, s_cur_transfer.size_remaining,
  146. s_cur_transfer.next_desc, desc->last_descriptor, desc->buffer1_size);
  147. }
  148. }
  149. static esp_err_t handle_idle_state_events()
  150. {
  151. /* Handle any events which have happened in between transfers.
  152. * Under current assumptions (no SDIO support) only card detect events
  153. * can happen in the idle state.
  154. */
  155. sdmmc_event_t evt;
  156. while (sdmmc_host_wait_for_event(0, &evt) == ESP_OK) {
  157. if (evt.sdmmc_status & SDMMC_INTMASK_CD) {
  158. ESP_LOGV(TAG, "card detect event");
  159. evt.sdmmc_status &= ~SDMMC_INTMASK_CD;
  160. }
  161. if (evt.sdmmc_status != 0 || evt.dma_status != 0) {
  162. ESP_LOGE(TAG, "handle_idle_state_events unhandled: %08x %08x",
  163. evt.sdmmc_status, evt.dma_status);
  164. }
  165. }
  166. return ESP_OK;
  167. }
  168. static esp_err_t handle_event(sdmmc_command_t* cmd, sdmmc_req_state_t* state)
  169. {
  170. sdmmc_event_t evt;
  171. esp_err_t err = sdmmc_host_wait_for_event(portMAX_DELAY, &evt);
  172. if (err != ESP_OK) {
  173. ESP_LOGE(TAG, "sdmmc_host_wait_for_event returned %d", err);
  174. return err;
  175. }
  176. ESP_LOGV(TAG, "sdmmc_handle_event: evt %08x %08x", evt.sdmmc_status, evt.dma_status);
  177. process_events(evt, cmd, state);
  178. return ESP_OK;
  179. }
  180. static sdmmc_hw_cmd_t make_hw_cmd(sdmmc_command_t* cmd)
  181. {
  182. sdmmc_hw_cmd_t res = { 0 };
  183. res.cmd_index = cmd->opcode;
  184. if (cmd->opcode == MMC_STOP_TRANSMISSION) {
  185. res.stop_abort_cmd = 1;
  186. } else {
  187. res.wait_complete = 1;
  188. }
  189. if (cmd->opcode == SD_APP_SET_BUS_WIDTH) {
  190. res.send_auto_stop = 1;
  191. res.data_expected = 1;
  192. }
  193. if (cmd->flags & SCF_RSP_PRESENT) {
  194. res.response_expect = 1;
  195. if (cmd->flags & SCF_RSP_136) {
  196. res.response_long = 1;
  197. }
  198. }
  199. if (cmd->flags & SCF_RSP_CRC) {
  200. res.check_response_crc = 1;
  201. }
  202. res.use_hold_reg = 1;
  203. if (cmd->data) {
  204. res.data_expected = 1;
  205. if ((cmd->flags & SCF_CMD_READ) == 0) {
  206. res.rw = 1;
  207. }
  208. assert(cmd->datalen % cmd->blklen == 0);
  209. if ((cmd->datalen / cmd->blklen) > 1) {
  210. res.send_auto_stop = 1;
  211. }
  212. }
  213. ESP_LOGV(TAG, "%s: opcode=%d, rexp=%d, crc=%d", __func__,
  214. res.cmd_index, res.response_expect, res.check_response_crc);
  215. return res;
  216. }
  217. static void process_command_response(uint32_t status, sdmmc_command_t* cmd)
  218. {
  219. if (cmd->flags & SCF_RSP_PRESENT) {
  220. if (cmd->flags & SCF_RSP_136) {
  221. cmd->response[3] = SDMMC.resp[0];
  222. cmd->response[2] = SDMMC.resp[1];
  223. cmd->response[1] = SDMMC.resp[2];
  224. cmd->response[0] = SDMMC.resp[3];
  225. } else {
  226. cmd->response[0] = SDMMC.resp[0];
  227. cmd->response[1] = 0;
  228. cmd->response[2] = 0;
  229. cmd->response[3] = 0;
  230. }
  231. }
  232. if ((status & SDMMC_INTMASK_RTO) &&
  233. cmd->opcode != MMC_ALL_SEND_CID &&
  234. cmd->opcode != MMC_SELECT_CARD &&
  235. cmd->opcode != MMC_STOP_TRANSMISSION) {
  236. cmd->error = ESP_ERR_TIMEOUT;
  237. } else if ((cmd->flags & SCF_RSP_CRC) && (status & SDMMC_INTMASK_RCRC)) {
  238. cmd->error = ESP_ERR_INVALID_CRC;
  239. } else if (status & SDMMC_INTMASK_RESP_ERR) {
  240. cmd->error = ESP_ERR_INVALID_RESPONSE;
  241. }
  242. if (cmd->error != 0) {
  243. if (cmd->data) {
  244. sdmmc_host_dma_stop();
  245. }
  246. ESP_LOGD(TAG, "%s: error %d", __func__, cmd->error);
  247. }
  248. }
  249. static void process_data_status(uint32_t status, sdmmc_command_t* cmd)
  250. {
  251. if (status & SDMMC_DATA_ERR_MASK) {
  252. if (status & SDMMC_INTMASK_DTO) {
  253. cmd->error = ESP_ERR_TIMEOUT;
  254. } else if (status & SDMMC_INTMASK_DCRC) {
  255. cmd->error = ESP_ERR_INVALID_CRC;
  256. } else if ((status & SDMMC_INTMASK_EBE) &&
  257. (cmd->flags & SCF_CMD_READ) == 0) {
  258. cmd->error = ESP_ERR_TIMEOUT;
  259. } else {
  260. cmd->error = ESP_FAIL;
  261. }
  262. SDMMC.ctrl.fifo_reset = 1;
  263. }
  264. if (cmd->error != 0) {
  265. if (cmd->data) {
  266. sdmmc_host_dma_stop();
  267. }
  268. ESP_LOGD(TAG, "%s: error %d", __func__, cmd->error);
  269. }
  270. }
  271. static inline bool mask_check_and_clear(uint32_t* state, uint32_t mask) {
  272. bool ret = ((*state) & mask) != 0;
  273. *state &= ~mask;
  274. return ret;
  275. }
  276. static esp_err_t process_events(sdmmc_event_t evt, sdmmc_command_t* cmd, sdmmc_req_state_t* pstate)
  277. {
  278. const char* const s_state_names[] __attribute__((unused)) = {
  279. "IDLE",
  280. "SENDING_CMD",
  281. "SENDIND_DATA",
  282. "BUSY"
  283. };
  284. sdmmc_event_t orig_evt = evt;
  285. ESP_LOGV(TAG, "%s: state=%s", __func__, s_state_names[*pstate]);
  286. sdmmc_req_state_t next_state = *pstate;
  287. sdmmc_req_state_t state = (sdmmc_req_state_t) -1;
  288. while (next_state != state) {
  289. state = next_state;
  290. switch (state) {
  291. case SDMMC_IDLE:
  292. break;
  293. case SDMMC_SENDING_CMD:
  294. if (mask_check_and_clear(&evt.sdmmc_status, SDMMC_CMD_ERR_MASK)) {
  295. process_command_response(orig_evt.sdmmc_status, cmd);
  296. break;
  297. }
  298. if (!mask_check_and_clear(&evt.sdmmc_status, SDMMC_INTMASK_CMD_DONE)) {
  299. break;
  300. }
  301. process_command_response(orig_evt.sdmmc_status, cmd);
  302. if (cmd->error != ESP_OK || cmd->data == NULL) {
  303. next_state = SDMMC_IDLE;
  304. break;
  305. }
  306. next_state = SDMMC_SENDING_DATA;
  307. break;
  308. case SDMMC_SENDING_DATA:
  309. if (mask_check_and_clear(&evt.sdmmc_status, SDMMC_DATA_ERR_MASK)) {
  310. process_data_status(orig_evt.sdmmc_status, cmd);
  311. sdmmc_host_dma_stop();
  312. }
  313. if (mask_check_and_clear(&evt.dma_status, SDMMC_DMA_DONE_MASK)) {
  314. s_cur_transfer.desc_remaining--;
  315. if (s_cur_transfer.size_remaining) {
  316. fill_dma_descriptors(1);
  317. sdmmc_host_dma_resume();
  318. }
  319. if (s_cur_transfer.desc_remaining == 0) {
  320. next_state = SDMMC_BUSY;
  321. }
  322. }
  323. break;
  324. case SDMMC_BUSY:
  325. if (!mask_check_and_clear(&evt.sdmmc_status, SDMMC_INTMASK_DATA_OVER)) {
  326. break;
  327. }
  328. process_data_status(orig_evt.sdmmc_status, cmd);
  329. next_state = SDMMC_IDLE;
  330. break;
  331. }
  332. ESP_LOGV(TAG, "%s state=%s next_state=%s", __func__, s_state_names[state], s_state_names[next_state]);
  333. }
  334. *pstate = state;
  335. return ESP_OK;
  336. }