uart-16550.h 5.0 KB

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  1. /*******************************************************************************
  2. Copyright (c) 2006-2007 Tensilica Inc.
  3. Permission is hereby granted, free of charge, to any person obtaining
  4. a copy of this software and associated documentation files (the
  5. "Software"), to deal in the Software without restriction, including
  6. without limitation the rights to use, copy, modify, merge, publish,
  7. distribute, sublicense, and/or sell copies of the Software, and to
  8. permit persons to whom the Software is furnished to do so, subject to
  9. the following conditions:
  10. The above copyright notice and this permission notice shall be included
  11. in all copies or substantial portions of the Software.
  12. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  13. EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  14. MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  15. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
  16. CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  17. TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  18. SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  19. --------------------------------------------------------------------------------
  20. uart-16550.h Generic definitions for National Semiconductor 16550 UART
  21. This is used by board-support-packages with one or more 16550 compatible UARTs.
  22. A BSP provides a base address for each instance of a 16550 UART on the board.
  23. Note that a 16552 DUART (Dual UART) is simply two instances of a 16550 UART.
  24. *******************************************************************************/
  25. #ifndef _UART_16550_H_
  26. #define _UART_16550_H_
  27. /* C interface to UART registers. */
  28. struct uart_dev_s {
  29. union {
  30. uart16550_reg_t rxb; /* DLAB=0: receive buffer, read-only */
  31. uart16550_reg_t txb; /* DLAB=0: transmit buffer, write-only */
  32. uart16550_reg_t dll; /* DLAB=1: divisor, LS byte latch */
  33. } w0;
  34. union {
  35. uart16550_reg_t ier; /* DLAB=0: interrupt-enable register */
  36. uart16550_reg_t dlm; /* DLAB=1: divisor, MS byte latch */
  37. } w1;
  38. union {
  39. uart16550_reg_t isr; /* DLAB=0: interrupt status register, read-only */
  40. uart16550_reg_t fcr; /* DLAB=0: FIFO control register, write-only */
  41. uart16550_reg_t afr; /* DLAB=1: alternate function register */
  42. } w2;
  43. uart16550_reg_t lcr; /* line control-register, write-only */
  44. uart16550_reg_t mcr; /* modem control-regsiter, write-only */
  45. uart16550_reg_t lsr; /* line status register, read-only */
  46. uart16550_reg_t msr; /* modem status register, read-only */
  47. uart16550_reg_t scr; /* scratch regsiter, read/write */
  48. };
  49. #define _RXB(u) ((u)->w0.rxb)
  50. #define _TXB(u) ((u)->w0.txb)
  51. #define _DLL(u) ((u)->w0.dll)
  52. #define _IER(u) ((u)->w1.ier)
  53. #define _DLM(u) ((u)->w1.dlm)
  54. #define _ISR(u) ((u)->w2.isr)
  55. #define _FCR(u) ((u)->w2.fcr)
  56. #define _AFR(u) ((u)->w2.afr)
  57. #define _LCR(u) ((u)->lcr)
  58. #define _MCR(u) ((u)->mcr)
  59. #define _LSR(u) ((u)->lsr)
  60. #define _MSR(u) ((u)->msr)
  61. #define _SCR(u) ((u)->scr)
  62. typedef volatile struct uart_dev_s uart_dev_t;
  63. /* IER bits */
  64. #define RCVR_DATA_REG_INTENABLE 0x01
  65. #define XMIT_HOLD_REG_INTENABLE 0x02
  66. #define RCVR_STATUS_INTENABLE 0x04
  67. #define MODEM_STATUS_INTENABLE 0x08
  68. /* FCR bits */
  69. #define _FIFO_ENABLE 0x01
  70. #define RCVR_FIFO_RESET 0x02
  71. #define XMIT_FIFO_RESET 0x04
  72. #define DMA_MODE_SELECT 0x08
  73. #define RCVR_TRIGGER_LSB 0x40
  74. #define RCVR_TRIGGER_MSB 0x80
  75. /* AFR bits */
  76. #define AFR_CONC_WRITE 0x01
  77. #define AFR_BAUDOUT_SEL 0x02
  78. #define AFR_RXRDY_SEL 0x04
  79. /* ISR bits */
  80. #define INT_STATUS(r) ((r)&1)
  81. #define INT_PRIORITY(r) (((r)>>1)&0x7)
  82. /* LCR bits */
  83. #define WORD_LENGTH(n) (((n)-5)&0x3)
  84. #define STOP_BIT_ENABLE 0x04
  85. #define PARITY_ENABLE 0x08
  86. #define EVEN_PARITY 0x10
  87. #define FORCE_PARITY 0x20
  88. #define XMIT_BREAK 0x40
  89. #define DLAB_ENABLE 0x80
  90. /* MCR bits */
  91. #define _DTR 0x01
  92. #define _RTS 0x02
  93. #define _OP1 0x04
  94. #define _OP2 0x08
  95. #define LOOP_BACK 0x10
  96. /* LSR Bits */
  97. #define RCVR_DATA_READY 0x01
  98. #define OVERRUN_ERROR 0x02
  99. #define PARITY_ERROR 0x04
  100. #define FRAMING_ERROR 0x08
  101. #define BREAK_INTERRUPT 0x10
  102. #define XMIT_HOLD_EMPTY 0x20
  103. #define XMIT_EMPTY 0x40
  104. #define FIFO_ERROR 0x80
  105. #define RCVR_READY(u) (_LSR(u)&RCVR_DATA_READY)
  106. #define XMIT_READY(u) (_LSR(u)&XMIT_HOLD_EMPTY)
  107. /* MSR bits */
  108. #define _RDR 0x01
  109. #define DELTA_DSR 0x02
  110. #define DELTA_RI 0x04
  111. #define DELTA_CD 0x08
  112. #define _CTS 0x10
  113. #define _DSR 0x20
  114. #define _RI 0x40
  115. #define _CD 0x80
  116. /* Compute 16-bit divisor for baudrate generator, with rounding: */
  117. #define UART_DIVISOR(clock,baud) (((clock)/16 + (baud)/2)/(baud))
  118. /* Prototypes of driver functions */
  119. extern void uart16550_init( uart_dev_t *u, unsigned baud, unsigned ndata,
  120. unsigned parity, unsigned nstop );
  121. extern void uart16550_out( uart_dev_t *u, char c );
  122. extern char uart16550_in( uart_dev_t *u );
  123. extern unsigned uart16550_measure_sys_clk( uart_dev_t *u );
  124. #endif /* _UART_16550_H_ */