spi_master.rst 6.6 KB

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  1. SPI Master driver
  2. =================
  3. Overview
  4. --------
  5. The ESP32 has four SPI peripheral devices, called SPI0, SPI1, HSPI and VSPI. SPI0 is entirely dedicated to
  6. the flash cache the ESP32 uses to map the SPI flash device it is connected to into memory. SPI1 is
  7. connected to the same hardware lines as SPI0 and is used to write to the flash chip. HSPI and VSPI
  8. are free to use. SPI1, HSPI and VSPI all have three chip select lines, allowing them to drive up to
  9. three SPI devices each as a master. The SPI peripherals also can be used in slave mode, driven from
  10. another SPI master.
  11. The spi_master driver
  12. ^^^^^^^^^^^^^^^^^^^^^
  13. The spi_master driver allows easy communicating with SPI slave devices, even in a multithreaded environment.
  14. It fully transparently handles DMA transfers to read and write data and automatically takes care of
  15. multiplexing between different SPI slaves on the same master
  16. Terminology
  17. ^^^^^^^^^^^
  18. The spi_master driver uses the following terms:
  19. * Host: The SPI peripheral inside the ESP32 initiating the SPI transmissions. One of SPI, HSPI or VSPI. (For
  20. now, only HSPI or VSPI are actually supported in the driver; it will support all 3 peripherals
  21. somewhere in the future.)
  22. * Bus: The SPI bus, common to all SPI devices connected to one host. In general the bus consists of the
  23. miso, mosi, sclk and optionally quadwp and quadhd signals. The SPI slaves are connected to these
  24. signals in parallel.
  25. - miso - Also known as q, this is the input of the serial stream into the ESP32
  26. - mosi - Also known as d, this is the output of the serial stream from the ESP32
  27. - sclk - Clock signal. Each data bit is clocked out or in on the positive or negative edge of this signal
  28. - quadwp - Write Protect signal. Only used for 4-bit (qio/qout) transactions.
  29. - quadhd - Hold signal. Only used for 4-bit (qio/qout) transactions.
  30. * Device: A SPI slave. Each SPI slave has its own chip select (CS) line, which is made active when
  31. a transmission to/from the SPI slave occurs.
  32. * Transaction: One instance of CS going active, data transfer from and/or to a device happening, and
  33. CS going inactive again. Transactions are atomic, as in they will never be interrupted by another
  34. transaction.
  35. SPI transactions
  36. ^^^^^^^^^^^^^^^^
  37. A transaction on the SPI bus consists of five phases, any of which may be skipped:
  38. * The command phase. In this phase, a command (0-16 bit) is clocked out.
  39. * The address phase. In this phase, an address (0-64 bit) is clocked out.
  40. * The read phase. The slave sends data to the master.
  41. * The write phase. The master sends data to the slave.
  42. In full duplex, the read and write phases are combined, causing the SPI host to read and
  43. write data simultaneously.
  44. The command and address phase are optional in that not every SPI device will need to be sent a command
  45. and/or address. Tis is reflected in the device configuration: when the ``command_bits`` or ``data_bits``
  46. fields are set to zero, no command or address phase is done.
  47. Something similar is true for the read and write phase: not every transaction needs both data to be written
  48. as well as data to be read. When ``rx_buffer`` is NULL (and SPI_USE_RXDATA) is not set) the read phase
  49. is skipped. When ``tx_buffer`` is NULL (and SPI_USE_TXDATA) is not set) the write phase is skipped.
  50. Using the spi_master driver
  51. ^^^^^^^^^^^^^^^^^^^^^^^^^^^
  52. - Initialize a SPI bus by calling ``spi_bus_initialize``. Make sure to set the correct IO pins in
  53. the ``bus_config`` struct. Take care to set signals that are not needed to -1.
  54. - Tell the driver about a SPI slave device conencted to the bus by calling spi_bus_add_device.
  55. Make sure to configure any timing requirements the device has in the ``dev_config`` structure.
  56. You should now have a handle for the device, to be used when sending it a transaction.
  57. - To interact with the device, fill one or more spi_transaction_t structure with any transaction
  58. parameters you need. Either queue all transactions by calling ``spi_device_queue_trans``, later
  59. quering the result using ``spi_device_get_trans_result``, or handle all requests synchroneously
  60. by feeding them into ``spi_device_transmit``.
  61. - Optional: to unload the driver for a device, call ``spi_bus_remove_device`` with the device
  62. handle as an argument
  63. - Optional: to remove the driver for a bus, make sure no more drivers are attached and call
  64. ``spi_bus_free``.
  65. Transaction data
  66. ^^^^^^^^^^^^^^^^
  67. Normally, data to be transferred to or from a device will be read from or written to a chunk of memory
  68. indicated by the ``rx_buffer`` and ``tx_buffer`` members of the transaction structure. The SPI driver
  69. may decide to use DMA for transfers, so these buffers should be allocated in DMA-capable memory using
  70. ``pvPortMallocCaps(size, MALLOC_CAP_DMA)``.
  71. Sometimes, the amount of data is very small making it less than optimal allocating a separate buffer
  72. for it. If the data to be transferred is 32 bits or less, it can be stored in the transaction struct
  73. itself. For transmitted data, use the ``tx_data`` member for this and set the ``SPI_USE_TXDATA`` flag
  74. on the transmission. For received data, use ``rx_data`` and set ``SPI_USE_RXDATA``. In both cases, do
  75. not touch the ``tx_buffer`` or ``rx_buffer`` members, because they use the same memory locations
  76. as ``tx_data`` and ``rx_data``.
  77. Application Example
  78. -------------------
  79. Display graphics on the ILI9341-based 320x240 LCD: :example:`peripherals/spi_master`.
  80. API Reference
  81. -------------
  82. Header Files
  83. ^^^^^^^^^^^^
  84. * :component_file:`driver/include/driver/spi_master.h`
  85. Macros
  86. ^^^^^^
  87. .. doxygendefine:: SPI_DEVICE_TXBIT_LSBFIRST
  88. .. doxygendefine:: SPI_DEVICE_RXBIT_LSBFIRST
  89. .. doxygendefine:: SPI_DEVICE_BIT_LSBFIRST
  90. .. doxygendefine:: SPI_DEVICE_3WIRE
  91. .. doxygendefine:: SPI_DEVICE_POSITIVE_CS
  92. .. doxygendefine:: SPI_DEVICE_HALFDUPLEX
  93. .. doxygendefine:: SPI_DEVICE_CLK_AS_CS
  94. .. doxygendefine:: SPI_TRANS_MODE_DIO
  95. .. doxygendefine:: SPI_TRANS_MODE_QIO
  96. .. doxygendefine:: SPI_TRANS_MODE_DIOQIO_ADDR
  97. .. doxygendefine:: SPI_TRANS_USE_RXDATA
  98. .. doxygendefine:: SPI_TRANS_USE_TXDATA
  99. Type Definitions
  100. ^^^^^^^^^^^^^^^^
  101. .. doxygentypedef:: spi_device_handle_t
  102. Enumerations
  103. ^^^^^^^^^^^^
  104. .. doxygenenum:: spi_host_device_t
  105. Structures
  106. ^^^^^^^^^^
  107. .. doxygenstruct:: spi_transaction_t
  108. :members:
  109. .. doxygenstruct:: spi_bus_config_t
  110. :members:
  111. .. doxygenstruct:: spi_device_interface_config_t
  112. :members:
  113. Functions
  114. ---------
  115. .. doxygenfunction:: spi_bus_initialize
  116. .. doxygenfunction:: spi_bus_free
  117. .. doxygenfunction:: spi_bus_add_device
  118. .. doxygenfunction:: spi_bus_remove_device
  119. .. doxygenfunction:: spi_device_queue_trans
  120. .. doxygenfunction:: spi_device_get_trans_result
  121. .. doxygenfunction:: spi_device_transmit