rmt.c 55 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373
  1. /*
  2. * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. */
  6. #include <stdlib.h>
  7. #include <string.h>
  8. #include <sys/lock.h>
  9. #include <sys/cdefs.h>
  10. #include "esp_compiler.h"
  11. #include "esp_intr_alloc.h"
  12. #include "esp_log.h"
  13. #include "esp_check.h"
  14. #include "driver/gpio.h"
  15. #include "driver/periph_ctrl.h"
  16. #include "driver/rmt.h"
  17. #include "freertos/FreeRTOS.h"
  18. #include "freertos/task.h"
  19. #include "freertos/semphr.h"
  20. #include "freertos/ringbuf.h"
  21. #include "soc/soc_memory_layout.h"
  22. #include "soc/rmt_periph.h"
  23. #include "soc/rtc.h"
  24. #include "hal/rmt_hal.h"
  25. #include "hal/rmt_ll.h"
  26. #include "hal/gpio_hal.h"
  27. #include "esp_rom_gpio.h"
  28. #define RMT_CHANNEL_ERROR_STR "RMT CHANNEL ERR"
  29. #define RMT_ADDR_ERROR_STR "RMT ADDRESS ERR"
  30. #define RMT_MEM_CNT_ERROR_STR "RMT MEM BLOCK NUM ERR"
  31. #define RMT_CARRIER_ERROR_STR "RMT CARRIER LEVEL ERR"
  32. #define RMT_MEM_OWNER_ERROR_STR "RMT MEM OWNER_ERR"
  33. #define RMT_BASECLK_ERROR_STR "RMT BASECLK ERR"
  34. #define RMT_WR_MEM_OVF_ERROR_STR "RMT WR MEM OVERFLOW"
  35. #define RMT_GPIO_ERROR_STR "RMT GPIO ERROR"
  36. #define RMT_MODE_ERROR_STR "RMT MODE ERROR"
  37. #define RMT_CLK_DIV_ERROR_STR "RMT CLK DIV ERR"
  38. #define RMT_DRIVER_ERROR_STR "RMT DRIVER ERR"
  39. #define RMT_DRIVER_LENGTH_ERROR_STR "RMT PARAM LEN ERROR"
  40. #define RMT_PSRAM_BUFFER_WARN_STR "Using buffer allocated from psram"
  41. #define RMT_TRANSLATOR_NULL_STR "RMT translator is null"
  42. #define RMT_TRANSLATOR_UNINIT_STR "RMT translator not init"
  43. #define RMT_PARAM_ERR_STR "RMT param error"
  44. static const char *TAG = "rmt";
  45. // Spinlock for protecting concurrent register-level access only
  46. #define RMT_ENTER_CRITICAL() portENTER_CRITICAL_SAFE(&(rmt_contex.rmt_spinlock))
  47. #define RMT_EXIT_CRITICAL() portEXIT_CRITICAL_SAFE(&(rmt_contex.rmt_spinlock))
  48. #define RMT_RX_CHANNEL_ENCODING_START (SOC_RMT_CHANNELS_PER_GROUP-SOC_RMT_TX_CANDIDATES_PER_GROUP)
  49. #define RMT_TX_CHANNEL_ENCODING_END (SOC_RMT_TX_CANDIDATES_PER_GROUP-1)
  50. #define RMT_IS_RX_CHANNEL(channel) ((channel) >= RMT_RX_CHANNEL_ENCODING_START)
  51. #define RMT_IS_TX_CHANNEL(channel) ((channel) <= RMT_TX_CHANNEL_ENCODING_END)
  52. #define RMT_DECODE_RX_CHANNEL(encode_chan) ((encode_chan - RMT_RX_CHANNEL_ENCODING_START))
  53. #define RMT_ENCODE_RX_CHANNEL(decode_chan) ((decode_chan + RMT_RX_CHANNEL_ENCODING_START))
  54. typedef struct {
  55. rmt_hal_context_t hal;
  56. _lock_t rmt_driver_isr_lock;
  57. portMUX_TYPE rmt_spinlock; // Mutex lock for protecting concurrent register/unregister of RMT channels' ISR
  58. rmt_isr_handle_t rmt_driver_intr_handle;
  59. rmt_tx_end_callback_t rmt_tx_end_callback;// Event called when transmission is ended
  60. uint8_t rmt_driver_channels; // Bitmask of installed drivers' channels
  61. bool rmt_module_enabled;
  62. uint32_t synchro_channel_mask; // Bitmap of channels already added in the synchronous group
  63. } rmt_contex_t;
  64. typedef struct {
  65. size_t tx_offset;
  66. size_t tx_len_rem;
  67. size_t tx_sub_len;
  68. bool translator;
  69. bool wait_done; //Mark whether wait tx done.
  70. rmt_channel_t channel;
  71. const rmt_item32_t *tx_data;
  72. xSemaphoreHandle tx_sem;
  73. #if CONFIG_SPIRAM_USE_MALLOC
  74. int intr_alloc_flags;
  75. StaticSemaphore_t tx_sem_buffer;
  76. #endif
  77. rmt_item32_t *tx_buf;
  78. RingbufHandle_t rx_buf;
  79. #if SOC_RMT_SUPPORT_RX_PINGPONG
  80. rmt_item32_t *rx_item_buf;
  81. uint32_t rx_item_buf_size;
  82. uint32_t rx_item_len;
  83. int rx_item_start_idx;
  84. #endif
  85. sample_to_rmt_t sample_to_rmt;
  86. void *tx_context;
  87. size_t sample_size_remain;
  88. const uint8_t *sample_cur;
  89. } rmt_obj_t;
  90. static rmt_contex_t rmt_contex = {
  91. .hal.regs = RMT_LL_HW_BASE,
  92. .hal.mem = RMT_LL_MEM_BASE,
  93. .rmt_spinlock = portMUX_INITIALIZER_UNLOCKED,
  94. .rmt_driver_intr_handle = NULL,
  95. .rmt_tx_end_callback = {
  96. .function = NULL,
  97. },
  98. .rmt_driver_channels = 0,
  99. .rmt_module_enabled = false,
  100. .synchro_channel_mask = 0
  101. };
  102. static rmt_obj_t *p_rmt_obj[RMT_CHANNEL_MAX] = {0};
  103. #if SOC_RMT_CHANNEL_CLK_INDEPENDENT
  104. static uint32_t s_rmt_source_clock_hz[RMT_CHANNEL_MAX];
  105. #else
  106. static uint32_t s_rmt_source_clock_hz;
  107. #endif
  108. //Enable RMT module
  109. static void rmt_module_enable(void)
  110. {
  111. RMT_ENTER_CRITICAL();
  112. if (rmt_contex.rmt_module_enabled == false) {
  113. periph_module_reset(rmt_periph_signals.groups[0].module);
  114. periph_module_enable(rmt_periph_signals.groups[0].module);
  115. rmt_contex.rmt_module_enabled = true;
  116. }
  117. RMT_EXIT_CRITICAL();
  118. }
  119. //Disable RMT module
  120. static void rmt_module_disable(void)
  121. {
  122. RMT_ENTER_CRITICAL();
  123. if (rmt_contex.rmt_module_enabled == true) {
  124. periph_module_disable(rmt_periph_signals.groups[0].module);
  125. rmt_contex.rmt_module_enabled = false;
  126. }
  127. RMT_EXIT_CRITICAL();
  128. }
  129. esp_err_t rmt_set_clk_div(rmt_channel_t channel, uint8_t div_cnt)
  130. {
  131. ESP_RETURN_ON_FALSE(channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  132. RMT_ENTER_CRITICAL();
  133. if (RMT_IS_RX_CHANNEL(channel)) {
  134. rmt_ll_rx_set_channel_clock_div(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), div_cnt);
  135. } else {
  136. rmt_ll_tx_set_channel_clock_div(rmt_contex.hal.regs, channel, div_cnt);
  137. }
  138. RMT_EXIT_CRITICAL();
  139. return ESP_OK;
  140. }
  141. esp_err_t rmt_get_clk_div(rmt_channel_t channel, uint8_t *div_cnt)
  142. {
  143. ESP_RETURN_ON_FALSE(channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  144. ESP_RETURN_ON_FALSE(div_cnt, ESP_ERR_INVALID_ARG, TAG, RMT_ADDR_ERROR_STR);
  145. RMT_ENTER_CRITICAL();
  146. if (RMT_IS_RX_CHANNEL(channel)) {
  147. *div_cnt = (uint8_t)rmt_ll_rx_get_channel_clock_div(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel));
  148. } else {
  149. *div_cnt = (uint8_t)rmt_ll_tx_get_channel_clock_div(rmt_contex.hal.regs, channel);
  150. }
  151. RMT_EXIT_CRITICAL();
  152. return ESP_OK;
  153. }
  154. esp_err_t rmt_set_rx_idle_thresh(rmt_channel_t channel, uint16_t thresh)
  155. {
  156. ESP_RETURN_ON_FALSE(RMT_IS_RX_CHANNEL(channel) && channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  157. RMT_ENTER_CRITICAL();
  158. rmt_ll_rx_set_idle_thres(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), thresh);
  159. RMT_EXIT_CRITICAL();
  160. return ESP_OK;
  161. }
  162. esp_err_t rmt_get_rx_idle_thresh(rmt_channel_t channel, uint16_t *thresh)
  163. {
  164. ESP_RETURN_ON_FALSE(RMT_IS_RX_CHANNEL(channel) && channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  165. ESP_RETURN_ON_FALSE(thresh, ESP_ERR_INVALID_ARG, TAG, RMT_ADDR_ERROR_STR);
  166. RMT_ENTER_CRITICAL();
  167. *thresh = (uint16_t)rmt_ll_rx_get_idle_thres(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel));
  168. RMT_EXIT_CRITICAL();
  169. return ESP_OK;
  170. }
  171. esp_err_t rmt_set_mem_block_num(rmt_channel_t channel, uint8_t rmt_mem_num)
  172. {
  173. ESP_RETURN_ON_FALSE(channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  174. ESP_RETURN_ON_FALSE(rmt_mem_num <= RMT_CHANNEL_MAX - channel, ESP_ERR_INVALID_ARG, TAG, RMT_MEM_CNT_ERROR_STR);
  175. RMT_ENTER_CRITICAL();
  176. if (RMT_IS_RX_CHANNEL(channel)) {
  177. rmt_ll_rx_set_mem_blocks(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), rmt_mem_num);
  178. } else {
  179. rmt_ll_tx_set_mem_blocks(rmt_contex.hal.regs, channel, rmt_mem_num);
  180. }
  181. RMT_EXIT_CRITICAL();
  182. return ESP_OK;
  183. }
  184. esp_err_t rmt_get_mem_block_num(rmt_channel_t channel, uint8_t *rmt_mem_num)
  185. {
  186. ESP_RETURN_ON_FALSE(channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  187. ESP_RETURN_ON_FALSE(rmt_mem_num, ESP_ERR_INVALID_ARG, TAG, RMT_ADDR_ERROR_STR);
  188. RMT_ENTER_CRITICAL();
  189. if (RMT_IS_RX_CHANNEL(channel)) {
  190. *rmt_mem_num = (uint8_t)rmt_ll_rx_get_mem_blocks(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel));
  191. } else {
  192. *rmt_mem_num = (uint8_t)rmt_ll_tx_get_mem_blocks(rmt_contex.hal.regs, channel);
  193. }
  194. RMT_EXIT_CRITICAL();
  195. return ESP_OK;
  196. }
  197. esp_err_t rmt_set_tx_carrier(rmt_channel_t channel, bool carrier_en, uint16_t high_level, uint16_t low_level,
  198. rmt_carrier_level_t carrier_level)
  199. {
  200. ESP_RETURN_ON_FALSE(RMT_IS_TX_CHANNEL(channel), ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  201. ESP_RETURN_ON_FALSE(carrier_level < RMT_CARRIER_LEVEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CARRIER_ERROR_STR);
  202. RMT_ENTER_CRITICAL();
  203. rmt_ll_tx_set_carrier_high_low_ticks(rmt_contex.hal.regs, channel, high_level, low_level);
  204. rmt_ll_tx_set_carrier_level(rmt_contex.hal.regs, channel, carrier_level);
  205. rmt_ll_tx_enable_carrier_modulation(rmt_contex.hal.regs, channel, carrier_en);
  206. RMT_EXIT_CRITICAL();
  207. return ESP_OK;
  208. }
  209. esp_err_t rmt_set_mem_pd(rmt_channel_t channel, bool pd_en)
  210. {
  211. ESP_RETURN_ON_FALSE(channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  212. RMT_ENTER_CRITICAL();
  213. rmt_ll_power_down_mem(rmt_contex.hal.regs, pd_en);
  214. RMT_EXIT_CRITICAL();
  215. return ESP_OK;
  216. }
  217. esp_err_t rmt_get_mem_pd(rmt_channel_t channel, bool *pd_en)
  218. {
  219. ESP_RETURN_ON_FALSE(channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  220. RMT_ENTER_CRITICAL();
  221. *pd_en = rmt_ll_is_mem_power_down(rmt_contex.hal.regs);
  222. RMT_EXIT_CRITICAL();
  223. return ESP_OK;
  224. }
  225. esp_err_t rmt_tx_start(rmt_channel_t channel, bool tx_idx_rst)
  226. {
  227. ESP_RETURN_ON_FALSE(RMT_IS_TX_CHANNEL(channel), ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  228. RMT_ENTER_CRITICAL();
  229. if (tx_idx_rst) {
  230. rmt_ll_tx_reset_pointer(rmt_contex.hal.regs, channel);
  231. }
  232. rmt_ll_clear_tx_end_interrupt(rmt_contex.hal.regs, channel);
  233. // enable tx end interrupt in non-loop mode
  234. if (!rmt_ll_is_tx_loop_enabled(rmt_contex.hal.regs, channel)) {
  235. rmt_ll_enable_tx_end_interrupt(rmt_contex.hal.regs, channel, true);
  236. } else {
  237. #if SOC_RMT_SUPPORT_TX_LOOP_COUNT
  238. rmt_ll_tx_reset_loop(rmt_contex.hal.regs, channel);
  239. rmt_ll_tx_enable_loop_count(rmt_contex.hal.regs, channel, true);
  240. rmt_ll_clear_tx_loop_interrupt(rmt_contex.hal.regs, channel);
  241. rmt_ll_enable_tx_loop_interrupt(rmt_contex.hal.regs, channel, true);
  242. #endif
  243. }
  244. rmt_ll_tx_start(rmt_contex.hal.regs, channel);
  245. RMT_EXIT_CRITICAL();
  246. return ESP_OK;
  247. }
  248. esp_err_t rmt_tx_stop(rmt_channel_t channel)
  249. {
  250. ESP_RETURN_ON_FALSE(RMT_IS_TX_CHANNEL(channel), ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  251. RMT_ENTER_CRITICAL();
  252. rmt_ll_tx_stop(rmt_contex.hal.regs, channel);
  253. rmt_ll_tx_reset_pointer(rmt_contex.hal.regs, channel);
  254. RMT_EXIT_CRITICAL();
  255. return ESP_OK;
  256. }
  257. esp_err_t rmt_rx_start(rmt_channel_t channel, bool rx_idx_rst)
  258. {
  259. ESP_RETURN_ON_FALSE(RMT_IS_RX_CHANNEL(channel) && channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  260. RMT_ENTER_CRITICAL();
  261. rmt_ll_rx_enable(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), false);
  262. if (rx_idx_rst) {
  263. rmt_ll_rx_reset_pointer(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel));
  264. }
  265. rmt_ll_clear_rx_end_interrupt(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel));
  266. rmt_ll_enable_rx_end_interrupt(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), true);
  267. #if SOC_RMT_SUPPORT_RX_PINGPONG
  268. const uint32_t item_block_len = rmt_ll_rx_get_mem_blocks(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel)) * RMT_MEM_ITEM_NUM;
  269. p_rmt_obj[channel]->rx_item_start_idx = 0;
  270. p_rmt_obj[channel]->rx_item_len = 0;
  271. rmt_set_rx_thr_intr_en(channel, true, item_block_len / 2);
  272. #endif
  273. rmt_ll_rx_enable(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), true);
  274. RMT_EXIT_CRITICAL();
  275. return ESP_OK;
  276. }
  277. esp_err_t rmt_rx_stop(rmt_channel_t channel)
  278. {
  279. ESP_RETURN_ON_FALSE(RMT_IS_RX_CHANNEL(channel) && channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  280. RMT_ENTER_CRITICAL();
  281. rmt_ll_enable_rx_end_interrupt(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), false);
  282. rmt_ll_rx_enable(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), false);
  283. rmt_ll_rx_reset_pointer(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel));
  284. #if SOC_RMT_SUPPORT_RX_PINGPONG
  285. rmt_ll_enable_rx_thres_interrupt(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), false);
  286. #endif
  287. RMT_EXIT_CRITICAL();
  288. return ESP_OK;
  289. }
  290. esp_err_t rmt_tx_memory_reset(rmt_channel_t channel)
  291. {
  292. ESP_RETURN_ON_FALSE(RMT_IS_TX_CHANNEL(channel), ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  293. RMT_ENTER_CRITICAL();
  294. rmt_ll_tx_reset_pointer(rmt_contex.hal.regs, channel);
  295. RMT_EXIT_CRITICAL();
  296. return ESP_OK;
  297. }
  298. esp_err_t rmt_rx_memory_reset(rmt_channel_t channel)
  299. {
  300. ESP_RETURN_ON_FALSE(RMT_IS_RX_CHANNEL(channel) && channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  301. RMT_ENTER_CRITICAL();
  302. rmt_ll_rx_reset_pointer(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel));
  303. RMT_EXIT_CRITICAL();
  304. return ESP_OK;
  305. }
  306. esp_err_t rmt_set_memory_owner(rmt_channel_t channel, rmt_mem_owner_t owner)
  307. {
  308. ESP_RETURN_ON_FALSE(RMT_IS_RX_CHANNEL(channel) && channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  309. ESP_RETURN_ON_FALSE(owner < RMT_MEM_OWNER_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_MEM_OWNER_ERROR_STR);
  310. RMT_ENTER_CRITICAL();
  311. rmt_ll_rx_set_mem_owner(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), owner);
  312. RMT_EXIT_CRITICAL();
  313. return ESP_OK;
  314. }
  315. esp_err_t rmt_get_memory_owner(rmt_channel_t channel, rmt_mem_owner_t *owner)
  316. {
  317. ESP_RETURN_ON_FALSE(RMT_IS_RX_CHANNEL(channel) && channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  318. ESP_RETURN_ON_FALSE(owner, ESP_ERR_INVALID_ARG, TAG, RMT_MEM_OWNER_ERROR_STR);
  319. RMT_ENTER_CRITICAL();
  320. *owner = (rmt_mem_owner_t)rmt_ll_rx_get_mem_owner(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel));
  321. RMT_EXIT_CRITICAL();
  322. return ESP_OK;
  323. }
  324. esp_err_t rmt_set_tx_loop_mode(rmt_channel_t channel, bool loop_en)
  325. {
  326. ESP_RETURN_ON_FALSE(RMT_IS_TX_CHANNEL(channel), ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  327. RMT_ENTER_CRITICAL();
  328. rmt_ll_tx_enable_loop(rmt_contex.hal.regs, channel, loop_en);
  329. RMT_EXIT_CRITICAL();
  330. return ESP_OK;
  331. }
  332. esp_err_t rmt_get_tx_loop_mode(rmt_channel_t channel, bool *loop_en)
  333. {
  334. ESP_RETURN_ON_FALSE(RMT_IS_TX_CHANNEL(channel), ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  335. RMT_ENTER_CRITICAL();
  336. *loop_en = rmt_ll_is_tx_loop_enabled(rmt_contex.hal.regs, channel);
  337. RMT_EXIT_CRITICAL();
  338. return ESP_OK;
  339. }
  340. esp_err_t rmt_set_rx_filter(rmt_channel_t channel, bool rx_filter_en, uint8_t thresh)
  341. {
  342. ESP_RETURN_ON_FALSE(RMT_IS_RX_CHANNEL(channel) && channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  343. RMT_ENTER_CRITICAL();
  344. rmt_ll_rx_enable_filter(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), rx_filter_en);
  345. rmt_ll_rx_set_filter_thres(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), thresh);
  346. RMT_EXIT_CRITICAL();
  347. return ESP_OK;
  348. }
  349. esp_err_t rmt_set_source_clk(rmt_channel_t channel, rmt_source_clk_t base_clk)
  350. {
  351. ESP_RETURN_ON_FALSE(channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  352. ESP_RETURN_ON_FALSE(base_clk < RMT_BASECLK_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_BASECLK_ERROR_STR);
  353. RMT_ENTER_CRITICAL();
  354. rmt_ll_set_group_clock_src(rmt_contex.hal.regs, channel, base_clk, 0, 0, 0);
  355. RMT_EXIT_CRITICAL();
  356. return ESP_OK;
  357. }
  358. esp_err_t rmt_get_source_clk(rmt_channel_t channel, rmt_source_clk_t *src_clk)
  359. {
  360. ESP_RETURN_ON_FALSE(channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  361. RMT_ENTER_CRITICAL();
  362. *src_clk = (rmt_source_clk_t)rmt_ll_get_group_clock_src(rmt_contex.hal.regs, channel);
  363. RMT_EXIT_CRITICAL();
  364. return ESP_OK;
  365. }
  366. esp_err_t rmt_set_idle_level(rmt_channel_t channel, bool idle_out_en, rmt_idle_level_t level)
  367. {
  368. ESP_RETURN_ON_FALSE(channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  369. ESP_RETURN_ON_FALSE(level < RMT_IDLE_LEVEL_MAX, ESP_ERR_INVALID_ARG, TAG, "RMT IDLE LEVEL ERR");
  370. RMT_ENTER_CRITICAL();
  371. rmt_ll_tx_enable_idle(rmt_contex.hal.regs, channel, idle_out_en);
  372. rmt_ll_tx_set_idle_level(rmt_contex.hal.regs, channel, level);
  373. RMT_EXIT_CRITICAL();
  374. return ESP_OK;
  375. }
  376. esp_err_t rmt_get_idle_level(rmt_channel_t channel, bool *idle_out_en, rmt_idle_level_t *level)
  377. {
  378. ESP_RETURN_ON_FALSE(channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  379. RMT_ENTER_CRITICAL();
  380. *idle_out_en = rmt_ll_is_tx_idle_enabled(rmt_contex.hal.regs, channel);
  381. *level = rmt_ll_tx_get_idle_level(rmt_contex.hal.regs, channel);
  382. RMT_EXIT_CRITICAL();
  383. return ESP_OK;
  384. }
  385. esp_err_t rmt_get_status(rmt_channel_t channel, uint32_t *status)
  386. {
  387. ESP_RETURN_ON_FALSE(channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  388. RMT_ENTER_CRITICAL();
  389. if (RMT_IS_RX_CHANNEL(channel)) {
  390. *status = rmt_ll_rx_get_channel_status(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel));
  391. } else {
  392. *status = rmt_ll_tx_get_channel_status(rmt_contex.hal.regs, channel);
  393. }
  394. RMT_EXIT_CRITICAL();
  395. return ESP_OK;
  396. }
  397. void rmt_set_intr_enable_mask(uint32_t mask)
  398. {
  399. RMT_ENTER_CRITICAL();
  400. rmt_ll_enable_interrupt(rmt_contex.hal.regs, mask, true);
  401. RMT_EXIT_CRITICAL();
  402. }
  403. void rmt_clr_intr_enable_mask(uint32_t mask)
  404. {
  405. RMT_ENTER_CRITICAL();
  406. rmt_ll_enable_interrupt(rmt_contex.hal.regs, mask, false);
  407. RMT_EXIT_CRITICAL();
  408. }
  409. esp_err_t rmt_set_rx_intr_en(rmt_channel_t channel, bool en)
  410. {
  411. ESP_RETURN_ON_FALSE(RMT_IS_RX_CHANNEL(channel) && channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  412. RMT_ENTER_CRITICAL();
  413. rmt_ll_enable_rx_end_interrupt(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), en);
  414. RMT_EXIT_CRITICAL();
  415. return ESP_OK;
  416. }
  417. #if SOC_RMT_SUPPORT_RX_PINGPONG
  418. esp_err_t rmt_set_rx_thr_intr_en(rmt_channel_t channel, bool en, uint16_t evt_thresh)
  419. {
  420. ESP_RETURN_ON_FALSE(RMT_IS_RX_CHANNEL(channel) && channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  421. if (en) {
  422. uint32_t item_block_len = rmt_ll_rx_get_mem_blocks(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel)) * RMT_MEM_ITEM_NUM;
  423. ESP_RETURN_ON_FALSE(evt_thresh <= item_block_len, ESP_ERR_INVALID_ARG, TAG, "RMT EVT THRESH ERR");
  424. RMT_ENTER_CRITICAL();
  425. rmt_ll_rx_set_limit(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), evt_thresh);
  426. rmt_ll_enable_rx_thres_interrupt(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), true);
  427. RMT_EXIT_CRITICAL();
  428. } else {
  429. RMT_ENTER_CRITICAL();
  430. rmt_ll_enable_rx_thres_interrupt(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), false);
  431. RMT_EXIT_CRITICAL();
  432. }
  433. return ESP_OK;
  434. }
  435. #endif
  436. esp_err_t rmt_set_err_intr_en(rmt_channel_t channel, bool en)
  437. {
  438. ESP_RETURN_ON_FALSE(channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  439. RMT_ENTER_CRITICAL();
  440. if (RMT_IS_RX_CHANNEL(channel)) {
  441. rmt_ll_enable_rx_err_interrupt(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), en);
  442. } else {
  443. rmt_ll_enable_tx_err_interrupt(rmt_contex.hal.regs, channel, en);
  444. }
  445. RMT_EXIT_CRITICAL();
  446. return ESP_OK;
  447. }
  448. esp_err_t rmt_set_tx_intr_en(rmt_channel_t channel, bool en)
  449. {
  450. ESP_RETURN_ON_FALSE(RMT_IS_TX_CHANNEL(channel), ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  451. RMT_ENTER_CRITICAL();
  452. rmt_ll_enable_tx_end_interrupt(rmt_contex.hal.regs, channel, en);
  453. RMT_EXIT_CRITICAL();
  454. return ESP_OK;
  455. }
  456. esp_err_t rmt_set_tx_thr_intr_en(rmt_channel_t channel, bool en, uint16_t evt_thresh)
  457. {
  458. ESP_RETURN_ON_FALSE(RMT_IS_TX_CHANNEL(channel), ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  459. if (en) {
  460. uint32_t item_block_len = rmt_ll_tx_get_mem_blocks(rmt_contex.hal.regs, channel) * RMT_MEM_ITEM_NUM;
  461. ESP_RETURN_ON_FALSE(evt_thresh <= item_block_len, ESP_ERR_INVALID_ARG, TAG, "RMT EVT THRESH ERR");
  462. RMT_ENTER_CRITICAL();
  463. rmt_ll_tx_set_limit(rmt_contex.hal.regs, channel, evt_thresh);
  464. rmt_ll_enable_tx_thres_interrupt(rmt_contex.hal.regs, channel, true);
  465. RMT_EXIT_CRITICAL();
  466. } else {
  467. RMT_ENTER_CRITICAL();
  468. rmt_ll_enable_tx_thres_interrupt(rmt_contex.hal.regs, channel, false);
  469. RMT_EXIT_CRITICAL();
  470. }
  471. return ESP_OK;
  472. }
  473. esp_err_t rmt_set_gpio(rmt_channel_t channel, rmt_mode_t mode, gpio_num_t gpio_num, bool invert_signal)
  474. {
  475. ESP_RETURN_ON_FALSE(channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  476. ESP_RETURN_ON_FALSE(mode < RMT_MODE_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_MODE_ERROR_STR);
  477. ESP_RETURN_ON_FALSE(((GPIO_IS_VALID_GPIO(gpio_num) && (mode == RMT_MODE_RX)) ||
  478. (GPIO_IS_VALID_OUTPUT_GPIO(gpio_num) && (mode == RMT_MODE_TX))), ESP_ERR_INVALID_ARG, TAG, RMT_GPIO_ERROR_STR);
  479. gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_num], PIN_FUNC_GPIO);
  480. if (mode == RMT_MODE_TX) {
  481. ESP_RETURN_ON_FALSE(RMT_IS_TX_CHANNEL(channel), ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  482. gpio_set_direction(gpio_num, GPIO_MODE_OUTPUT);
  483. esp_rom_gpio_connect_out_signal(gpio_num, rmt_periph_signals.groups[0].channels[channel].tx_sig, invert_signal, 0);
  484. } else {
  485. ESP_RETURN_ON_FALSE(RMT_IS_RX_CHANNEL(channel), ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  486. gpio_set_direction(gpio_num, GPIO_MODE_INPUT);
  487. esp_rom_gpio_connect_in_signal(gpio_num, rmt_periph_signals.groups[0].channels[channel].rx_sig, invert_signal);
  488. }
  489. return ESP_OK;
  490. }
  491. esp_err_t rmt_set_pin(rmt_channel_t channel, rmt_mode_t mode, gpio_num_t gpio_num)
  492. {
  493. // only for backword compatibility
  494. return rmt_set_gpio(channel, mode, gpio_num, false);
  495. }
  496. static bool rmt_is_channel_number_valid(rmt_channel_t channel, uint8_t mode)
  497. {
  498. // RX mode
  499. if (mode == RMT_MODE_RX) {
  500. return RMT_IS_RX_CHANNEL(channel) && (channel < RMT_CHANNEL_MAX);
  501. }
  502. // TX mode
  503. return (channel >= 0) && RMT_IS_TX_CHANNEL(channel);
  504. }
  505. static esp_err_t rmt_internal_config(rmt_dev_t *dev, const rmt_config_t *rmt_param)
  506. {
  507. uint8_t mode = rmt_param->rmt_mode;
  508. uint8_t channel = rmt_param->channel;
  509. uint8_t gpio_num = rmt_param->gpio_num;
  510. uint8_t mem_cnt = rmt_param->mem_block_num;
  511. uint8_t clk_div = rmt_param->clk_div;
  512. uint32_t carrier_freq_hz = rmt_param->tx_config.carrier_freq_hz;
  513. bool carrier_en = rmt_param->tx_config.carrier_en;
  514. uint32_t rmt_source_clk_hz;
  515. ESP_RETURN_ON_FALSE(rmt_is_channel_number_valid(channel, mode), ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  516. ESP_RETURN_ON_FALSE(mem_cnt + channel <= 8 && mem_cnt > 0, ESP_ERR_INVALID_ARG, TAG, RMT_MEM_CNT_ERROR_STR);
  517. ESP_RETURN_ON_FALSE(clk_div > 0, ESP_ERR_INVALID_ARG, TAG, RMT_CLK_DIV_ERROR_STR);
  518. if (mode == RMT_MODE_TX) {
  519. ESP_RETURN_ON_FALSE(!carrier_en || carrier_freq_hz > 0, ESP_ERR_INVALID_ARG, TAG, "RMT carrier frequency can't be zero");
  520. }
  521. RMT_ENTER_CRITICAL();
  522. rmt_ll_enable_mem_access(dev, true);
  523. if (rmt_param->flags & RMT_CHANNEL_FLAGS_AWARE_DFS) {
  524. #if SOC_RMT_SUPPORT_XTAL
  525. // clock src: XTAL_CLK
  526. rmt_source_clk_hz = rtc_clk_xtal_freq_get() * 1000000;
  527. rmt_ll_set_group_clock_src(dev, channel, RMT_BASECLK_XTAL, 0, 0, 0);
  528. #elif SOC_RMT_SUPPORT_REF_TICK
  529. // clock src: REF_CLK
  530. rmt_source_clk_hz = REF_CLK_FREQ;
  531. rmt_ll_set_group_clock_src(dev, channel, RMT_BASECLK_REF, 0, 0, 0);
  532. #endif
  533. } else {
  534. // clock src: APB_CLK
  535. rmt_source_clk_hz = APB_CLK_FREQ;
  536. rmt_ll_set_group_clock_src(dev, channel, RMT_BASECLK_APB, 0, 0, 0);
  537. }
  538. RMT_EXIT_CRITICAL();
  539. #if SOC_RMT_CHANNEL_CLK_INDEPENDENT
  540. s_rmt_source_clock_hz[channel] = rmt_source_clk_hz;
  541. #else
  542. if (s_rmt_source_clock_hz && rmt_source_clk_hz != s_rmt_source_clock_hz) {
  543. ESP_LOGW(TAG, "RMT clock source has been configured to %d by other channel, now reconfigure it to %d", s_rmt_source_clock_hz, rmt_source_clk_hz);
  544. }
  545. s_rmt_source_clock_hz = rmt_source_clk_hz;
  546. #endif
  547. ESP_LOGD(TAG, "rmt_source_clk_hz: %d\n", rmt_source_clk_hz);
  548. if (mode == RMT_MODE_TX) {
  549. uint16_t carrier_duty_percent = rmt_param->tx_config.carrier_duty_percent;
  550. uint8_t carrier_level = rmt_param->tx_config.carrier_level;
  551. uint8_t idle_level = rmt_param->tx_config.idle_level;
  552. RMT_ENTER_CRITICAL();
  553. rmt_ll_tx_set_channel_clock_div(dev, channel, clk_div);
  554. rmt_ll_tx_set_mem_blocks(dev, channel, mem_cnt);
  555. rmt_ll_tx_reset_pointer(dev, channel);
  556. rmt_ll_tx_enable_loop(dev, channel, rmt_param->tx_config.loop_en);
  557. #if SOC_RMT_SUPPORT_TX_LOOP_COUNT
  558. if (rmt_param->tx_config.loop_en) {
  559. rmt_ll_tx_set_loop_count(dev, channel, rmt_param->tx_config.loop_count);
  560. }
  561. #endif
  562. /* always enable tx ping-pong */
  563. rmt_ll_tx_enable_pingpong(dev, channel, true);
  564. /*Set idle level */
  565. rmt_ll_tx_enable_idle(dev, channel, rmt_param->tx_config.idle_output_en);
  566. rmt_ll_tx_set_idle_level(dev, channel, idle_level);
  567. /*Set carrier*/
  568. rmt_ll_tx_enable_carrier_modulation(dev, channel, carrier_en);
  569. if (carrier_en) {
  570. uint32_t duty_div, duty_h, duty_l;
  571. duty_div = rmt_source_clk_hz / carrier_freq_hz;
  572. duty_h = duty_div * carrier_duty_percent / 100;
  573. duty_l = duty_div - duty_h;
  574. rmt_ll_tx_set_carrier_level(dev, channel, carrier_level);
  575. rmt_ll_tx_set_carrier_high_low_ticks(dev, channel, duty_h, duty_l);
  576. } else {
  577. rmt_ll_tx_set_carrier_level(dev, channel, 0);
  578. rmt_ll_tx_set_carrier_high_low_ticks(dev, channel, 0, 0);
  579. }
  580. RMT_EXIT_CRITICAL();
  581. ESP_LOGD(TAG, "Rmt Tx Channel %u|Gpio %u|Sclk_Hz %u|Div %u|Carrier_Hz %u|Duty %u",
  582. channel, gpio_num, rmt_source_clk_hz, clk_div, carrier_freq_hz, carrier_duty_percent);
  583. } else if (RMT_MODE_RX == mode) {
  584. uint8_t filter_cnt = rmt_param->rx_config.filter_ticks_thresh;
  585. uint16_t threshold = rmt_param->rx_config.idle_threshold;
  586. RMT_ENTER_CRITICAL();
  587. rmt_ll_rx_set_channel_clock_div(dev, RMT_DECODE_RX_CHANNEL(channel), clk_div);
  588. rmt_ll_rx_set_mem_blocks(dev, RMT_DECODE_RX_CHANNEL(channel), mem_cnt);
  589. rmt_ll_rx_reset_pointer(dev, RMT_DECODE_RX_CHANNEL(channel));
  590. rmt_ll_rx_set_mem_owner(dev, RMT_DECODE_RX_CHANNEL(channel), RMT_MEM_OWNER_HW);
  591. /*Set idle threshold*/
  592. rmt_ll_rx_set_idle_thres(dev, RMT_DECODE_RX_CHANNEL(channel), threshold);
  593. /* Set RX filter */
  594. rmt_ll_rx_set_filter_thres(dev, RMT_DECODE_RX_CHANNEL(channel), filter_cnt);
  595. rmt_ll_rx_enable_filter(dev, RMT_DECODE_RX_CHANNEL(channel), rmt_param->rx_config.filter_en);
  596. #if SOC_RMT_SUPPORT_RX_PINGPONG
  597. /* always enable rx ping-pong */
  598. rmt_ll_rx_enable_pingpong(dev, RMT_DECODE_RX_CHANNEL(channel), true);
  599. #endif
  600. #if SOC_RMT_SUPPORT_RX_DEMODULATION
  601. rmt_ll_rx_enable_carrier_demodulation(dev, RMT_DECODE_RX_CHANNEL(channel), rmt_param->rx_config.rm_carrier);
  602. if (rmt_param->rx_config.rm_carrier) {
  603. uint32_t duty_total = rmt_source_clk_hz / rmt_ll_rx_get_channel_clock_div(dev, RMT_DECODE_RX_CHANNEL(channel)) / rmt_param->rx_config.carrier_freq_hz;
  604. uint32_t duty_high = duty_total * rmt_param->rx_config.carrier_duty_percent / 100;
  605. // there could be residual in timing the carrier pulse, so double enlarge the theoretical value
  606. rmt_ll_rx_set_carrier_high_low_ticks(dev, RMT_DECODE_RX_CHANNEL(channel), duty_high * 2, (duty_total - duty_high) * 2);
  607. rmt_ll_rx_set_carrier_level(dev, RMT_DECODE_RX_CHANNEL(channel), rmt_param->rx_config.carrier_level);
  608. }
  609. #endif
  610. RMT_EXIT_CRITICAL();
  611. ESP_LOGD(TAG, "Rmt Rx Channel %u|Gpio %u|Sclk_Hz %u|Div %u|Thresold %u|Filter %u",
  612. channel, gpio_num, rmt_source_clk_hz, clk_div, threshold, filter_cnt);
  613. }
  614. return ESP_OK;
  615. }
  616. esp_err_t rmt_config(const rmt_config_t *rmt_param)
  617. {
  618. rmt_module_enable();
  619. ESP_RETURN_ON_ERROR(rmt_set_gpio(rmt_param->channel, rmt_param->rmt_mode, rmt_param->gpio_num, rmt_param->flags & RMT_CHANNEL_FLAGS_INVERT_SIG), TAG, "set gpio for RMT driver failed");
  620. ESP_RETURN_ON_ERROR(rmt_internal_config(&RMT, rmt_param), TAG, "initialize RMT driver failed");
  621. return ESP_OK;
  622. }
  623. static void IRAM_ATTR rmt_fill_memory(rmt_channel_t channel, const rmt_item32_t *item,
  624. uint16_t item_num, uint16_t mem_offset)
  625. {
  626. RMT_ENTER_CRITICAL();
  627. rmt_ll_write_memory(rmt_contex.hal.mem, channel, item, item_num, mem_offset);
  628. RMT_EXIT_CRITICAL();
  629. }
  630. esp_err_t rmt_fill_tx_items(rmt_channel_t channel, const rmt_item32_t *item, uint16_t item_num, uint16_t mem_offset)
  631. {
  632. ESP_RETURN_ON_FALSE(RMT_IS_TX_CHANNEL(channel), (0), TAG, RMT_CHANNEL_ERROR_STR);
  633. ESP_RETURN_ON_FALSE(item, ESP_ERR_INVALID_ARG, TAG, RMT_ADDR_ERROR_STR);
  634. ESP_RETURN_ON_FALSE(item_num > 0, ESP_ERR_INVALID_ARG, TAG, RMT_DRIVER_LENGTH_ERROR_STR);
  635. /*Each block has 64 x 32 bits of data*/
  636. uint8_t mem_cnt = rmt_ll_tx_get_mem_blocks(rmt_contex.hal.regs, channel);
  637. ESP_RETURN_ON_FALSE(mem_cnt * RMT_MEM_ITEM_NUM >= item_num, ESP_ERR_INVALID_ARG, TAG, RMT_WR_MEM_OVF_ERROR_STR);
  638. rmt_fill_memory(channel, item, item_num, mem_offset);
  639. return ESP_OK;
  640. }
  641. esp_err_t rmt_isr_register(void (*fn)(void *), void *arg, int intr_alloc_flags, rmt_isr_handle_t *handle)
  642. {
  643. ESP_RETURN_ON_FALSE(fn, ESP_ERR_INVALID_ARG, TAG, RMT_ADDR_ERROR_STR);
  644. ESP_RETURN_ON_FALSE(rmt_contex.rmt_driver_channels == 0, ESP_FAIL, TAG, "RMT driver installed, can not install generic ISR handler");
  645. return esp_intr_alloc(rmt_periph_signals.groups[0].irq, intr_alloc_flags, fn, arg, handle);
  646. }
  647. esp_err_t rmt_isr_deregister(rmt_isr_handle_t handle)
  648. {
  649. return esp_intr_free(handle);
  650. }
  651. static int IRAM_ATTR rmt_rx_get_mem_len_in_isr(rmt_channel_t channel)
  652. {
  653. int block_num = rmt_ll_rx_get_mem_blocks(rmt_contex.hal.regs, channel);
  654. int item_block_len = block_num * RMT_MEM_ITEM_NUM;
  655. volatile rmt_item32_t *data = (rmt_item32_t *)RMTMEM.chan[RMT_ENCODE_RX_CHANNEL(channel)].data32;
  656. int idx;
  657. for (idx = 0; idx < item_block_len; idx++) {
  658. if (data[idx].duration0 == 0) {
  659. return idx;
  660. } else if (data[idx].duration1 == 0) {
  661. return idx + 1;
  662. }
  663. }
  664. return idx;
  665. }
  666. static void IRAM_ATTR rmt_driver_isr_default(void *arg)
  667. {
  668. uint32_t status = 0;
  669. rmt_item32_t volatile *addr = NULL;
  670. uint8_t channel = 0;
  671. rmt_hal_context_t *hal = (rmt_hal_context_t *)arg;
  672. portBASE_TYPE HPTaskAwoken = pdFALSE;
  673. // Tx end interrupt
  674. status = rmt_ll_get_tx_end_interrupt_status(hal->regs);
  675. while (status) {
  676. channel = __builtin_ffs(status) - 1;
  677. status &= ~(1 << channel);
  678. rmt_obj_t *p_rmt = p_rmt_obj[channel];
  679. if (p_rmt) {
  680. xSemaphoreGiveFromISR(p_rmt->tx_sem, &HPTaskAwoken);
  681. rmt_ll_tx_reset_pointer(rmt_contex.hal.regs, channel);
  682. p_rmt->tx_data = NULL;
  683. p_rmt->tx_len_rem = 0;
  684. p_rmt->tx_offset = 0;
  685. p_rmt->tx_sub_len = 0;
  686. p_rmt->sample_cur = NULL;
  687. p_rmt->translator = false;
  688. if (rmt_contex.rmt_tx_end_callback.function) {
  689. rmt_contex.rmt_tx_end_callback.function(channel, rmt_contex.rmt_tx_end_callback.arg);
  690. }
  691. }
  692. rmt_ll_clear_tx_end_interrupt(hal->regs, channel);
  693. }
  694. // Tx thres interrupt
  695. status = rmt_ll_get_tx_thres_interrupt_status(hal->regs);
  696. while (status) {
  697. channel = __builtin_ffs(status) - 1;
  698. status &= ~(1 << channel);
  699. rmt_obj_t *p_rmt = p_rmt_obj[channel];
  700. if (p_rmt) {
  701. if (p_rmt->translator) {
  702. if (p_rmt->sample_size_remain > 0) {
  703. size_t translated_size = 0;
  704. p_rmt->sample_to_rmt((void *)p_rmt->sample_cur,
  705. p_rmt->tx_buf,
  706. p_rmt->sample_size_remain,
  707. p_rmt->tx_sub_len,
  708. &translated_size,
  709. &p_rmt->tx_len_rem);
  710. p_rmt->sample_size_remain -= translated_size;
  711. p_rmt->sample_cur += translated_size;
  712. p_rmt->tx_data = p_rmt->tx_buf;
  713. } else {
  714. p_rmt->sample_cur = NULL;
  715. p_rmt->translator = false;
  716. }
  717. }
  718. const rmt_item32_t *pdata = p_rmt->tx_data;
  719. size_t len_rem = p_rmt->tx_len_rem;
  720. if (len_rem >= p_rmt->tx_sub_len) {
  721. rmt_fill_memory(channel, pdata, p_rmt->tx_sub_len, p_rmt->tx_offset);
  722. p_rmt->tx_data += p_rmt->tx_sub_len;
  723. p_rmt->tx_len_rem -= p_rmt->tx_sub_len;
  724. } else if (len_rem == 0) {
  725. rmt_item32_t stop_data = {0};
  726. rmt_ll_write_memory(rmt_contex.hal.mem, channel, &stop_data, 1, p_rmt->tx_offset);
  727. } else {
  728. rmt_fill_memory(channel, pdata, len_rem, p_rmt->tx_offset);
  729. rmt_item32_t stop_data = {0};
  730. rmt_ll_write_memory(rmt_contex.hal.mem, channel, &stop_data, 1, p_rmt->tx_offset + len_rem);
  731. p_rmt->tx_data += len_rem;
  732. p_rmt->tx_len_rem -= len_rem;
  733. }
  734. if (p_rmt->tx_offset == 0) {
  735. p_rmt->tx_offset = p_rmt->tx_sub_len;
  736. } else {
  737. p_rmt->tx_offset = 0;
  738. }
  739. }
  740. rmt_ll_clear_tx_thres_interrupt(hal->regs, channel);
  741. }
  742. // Rx end interrupt
  743. status = rmt_ll_get_rx_end_interrupt_status(hal->regs);
  744. while (status) {
  745. channel = __builtin_ffs(status) - 1;
  746. status &= ~(1 << channel);
  747. rmt_obj_t *p_rmt = p_rmt_obj[RMT_ENCODE_RX_CHANNEL(channel)];
  748. if (p_rmt) {
  749. rmt_ll_rx_enable(rmt_contex.hal.regs, channel, false);
  750. int item_len = rmt_rx_get_mem_len_in_isr(channel);
  751. rmt_ll_rx_set_mem_owner(rmt_contex.hal.regs, channel, RMT_MEM_OWNER_SW);
  752. if (p_rmt->rx_buf) {
  753. addr = RMTMEM.chan[RMT_ENCODE_RX_CHANNEL(channel)].data32;
  754. #if SOC_RMT_SUPPORT_RX_PINGPONG
  755. if (item_len > p_rmt->rx_item_start_idx) {
  756. item_len = item_len - p_rmt->rx_item_start_idx;
  757. }
  758. memcpy((void *)(p_rmt->rx_item_buf + p_rmt->rx_item_len), (void *)(addr + p_rmt->rx_item_start_idx), item_len * 4);
  759. p_rmt->rx_item_len += item_len;
  760. BaseType_t res = xRingbufferSendFromISR(p_rmt->rx_buf, (void *)(p_rmt->rx_item_buf), p_rmt->rx_item_len * 4, &HPTaskAwoken);
  761. #else
  762. BaseType_t res = xRingbufferSendFromISR(p_rmt->rx_buf, (void *)addr, item_len * 4, &HPTaskAwoken);
  763. #endif
  764. if (res == pdFALSE) {
  765. ESP_EARLY_LOGE(TAG, "RMT RX BUFFER FULL");
  766. }
  767. } else {
  768. ESP_EARLY_LOGE(TAG, "RMT RX BUFFER ERROR");
  769. }
  770. #if SOC_RMT_SUPPORT_RX_PINGPONG
  771. p_rmt->rx_item_start_idx = 0;
  772. p_rmt->rx_item_len = 0;
  773. memset((void *)p_rmt->rx_item_buf, 0, p_rmt->rx_item_buf_size);
  774. #endif
  775. rmt_ll_rx_reset_pointer(rmt_contex.hal.regs, channel);
  776. rmt_ll_rx_set_mem_owner(rmt_contex.hal.regs, channel, RMT_MEM_OWNER_HW);
  777. rmt_ll_rx_enable(rmt_contex.hal.regs, channel, true);
  778. }
  779. rmt_ll_clear_rx_end_interrupt(hal->regs, channel);
  780. }
  781. #if SOC_RMT_SUPPORT_RX_PINGPONG
  782. // Rx thres interrupt
  783. status = rmt_ll_get_rx_thres_interrupt_status(hal->regs);
  784. while (status) {
  785. channel = __builtin_ffs(status) - 1;
  786. status &= ~(1 << channel);
  787. rmt_obj_t *p_rmt = p_rmt_obj[RMT_ENCODE_RX_CHANNEL(channel)];
  788. int mem_item_size = rmt_ll_rx_get_mem_blocks(rmt_contex.hal.regs, channel) * RMT_MEM_ITEM_NUM;
  789. int rx_thres_lim = rmt_ll_rx_get_limit(rmt_contex.hal.regs, channel);
  790. int item_len = (p_rmt->rx_item_start_idx == 0) ? rx_thres_lim : (mem_item_size - rx_thres_lim);
  791. if ((p_rmt->rx_item_len + item_len) < (p_rmt->rx_item_buf_size / 4)) {
  792. rmt_ll_rx_set_mem_owner(rmt_contex.hal.regs, channel, RMT_MEM_OWNER_SW);
  793. memcpy((void *)(p_rmt->rx_item_buf + p_rmt->rx_item_len), (void *)(RMTMEM.chan[RMT_ENCODE_RX_CHANNEL(channel)].data32 + p_rmt->rx_item_start_idx), item_len * 4);
  794. rmt_ll_rx_set_mem_owner(rmt_contex.hal.regs, channel, RMT_MEM_OWNER_HW);
  795. p_rmt->rx_item_len += item_len;
  796. p_rmt->rx_item_start_idx += item_len;
  797. if (p_rmt->rx_item_start_idx >= mem_item_size) {
  798. p_rmt->rx_item_start_idx = 0;
  799. }
  800. } else {
  801. ESP_EARLY_LOGE(TAG, "---RX buffer too small: %d", sizeof(p_rmt->rx_item_buf));
  802. }
  803. rmt_ll_clear_rx_thres_interrupt(hal->regs, channel);
  804. }
  805. #endif
  806. #if SOC_RMT_SUPPORT_TX_LOOP_COUNT
  807. // loop count interrupt
  808. status = rmt_ll_get_tx_loop_interrupt_status(hal->regs);
  809. while (status) {
  810. channel = __builtin_ffs(status) - 1;
  811. status &= ~(1 << channel);
  812. rmt_obj_t *p_rmt = p_rmt_obj[channel];
  813. if (p_rmt) {
  814. xSemaphoreGiveFromISR(p_rmt->tx_sem, &HPTaskAwoken);
  815. if (rmt_contex.rmt_tx_end_callback.function) {
  816. rmt_contex.rmt_tx_end_callback.function(channel, rmt_contex.rmt_tx_end_callback.arg);
  817. }
  818. }
  819. rmt_ll_clear_tx_loop_interrupt(hal->regs, channel);
  820. }
  821. #endif
  822. // RX Err interrupt
  823. status = rmt_ll_get_rx_err_interrupt_status(hal->regs);
  824. while (status) {
  825. channel = __builtin_ffs(status) - 1;
  826. status &= ~(1 << channel);
  827. rmt_obj_t *p_rmt = p_rmt_obj[RMT_ENCODE_RX_CHANNEL(channel)];
  828. if (p_rmt) {
  829. // Reset the receiver's write/read addresses to prevent endless err interrupts.
  830. rmt_ll_rx_reset_pointer(rmt_contex.hal.regs, channel);
  831. ESP_EARLY_LOGD(TAG, "RMT RX channel %d error", channel);
  832. ESP_EARLY_LOGD(TAG, "status: 0x%08x", rmt_ll_rx_get_channel_status(rmt_contex.hal.regs, channel));
  833. }
  834. rmt_ll_clear_rx_err_interrupt(hal->regs, channel);
  835. }
  836. // TX Err interrupt
  837. status = rmt_ll_get_tx_err_interrupt_status(hal->regs);
  838. while (status) {
  839. channel = __builtin_ffs(status) - 1;
  840. status &= ~(1 << channel);
  841. rmt_obj_t *p_rmt = p_rmt_obj[channel];
  842. if (p_rmt) {
  843. // Reset the transmitter's write/read addresses to prevent endless err interrupts.
  844. rmt_ll_tx_reset_pointer(rmt_contex.hal.regs, channel);
  845. ESP_EARLY_LOGD(TAG, "RMT TX channel %d error", channel);
  846. ESP_EARLY_LOGD(TAG, "status: 0x%08x", rmt_ll_tx_get_channel_status(rmt_contex.hal.regs, channel));
  847. }
  848. rmt_ll_clear_tx_err_interrupt(hal->regs, channel);
  849. }
  850. if (HPTaskAwoken == pdTRUE) {
  851. portYIELD_FROM_ISR();
  852. }
  853. }
  854. esp_err_t rmt_driver_uninstall(rmt_channel_t channel)
  855. {
  856. esp_err_t err = ESP_OK;
  857. ESP_RETURN_ON_FALSE(channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  858. ESP_RETURN_ON_FALSE(rmt_contex.rmt_driver_channels & BIT(channel), ESP_ERR_INVALID_STATE, TAG, "No RMT driver for this channel");
  859. if (p_rmt_obj[channel] == NULL) {
  860. return ESP_OK;
  861. }
  862. //Avoid blocking here(when the interrupt is disabled and do not wait tx done).
  863. if (p_rmt_obj[channel]->wait_done) {
  864. xSemaphoreTake(p_rmt_obj[channel]->tx_sem, portMAX_DELAY);
  865. }
  866. RMT_ENTER_CRITICAL();
  867. // check channel's working mode
  868. if (p_rmt_obj[channel]->rx_buf) {
  869. rmt_ll_enable_rx_end_interrupt(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), 0);
  870. rmt_ll_enable_rx_err_interrupt(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), 0);
  871. #if SOC_RMT_SUPPORT_RX_PINGPONG
  872. rmt_ll_enable_rx_thres_interrupt(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), 0);
  873. #endif
  874. } else {
  875. rmt_ll_enable_tx_end_interrupt(rmt_contex.hal.regs, channel, 0);
  876. rmt_ll_enable_tx_err_interrupt(rmt_contex.hal.regs, channel, 0);
  877. rmt_ll_enable_tx_thres_interrupt(rmt_contex.hal.regs, channel, false);
  878. }
  879. RMT_EXIT_CRITICAL();
  880. _lock_acquire_recursive(&(rmt_contex.rmt_driver_isr_lock));
  881. rmt_contex.rmt_driver_channels &= ~BIT(channel);
  882. if (rmt_contex.rmt_driver_channels == 0) {
  883. rmt_module_disable();
  884. // all channels have driver disabled
  885. err = rmt_isr_deregister(rmt_contex.rmt_driver_intr_handle);
  886. rmt_contex.rmt_driver_intr_handle = NULL;
  887. }
  888. _lock_release_recursive(&(rmt_contex.rmt_driver_isr_lock));
  889. if (err != ESP_OK) {
  890. return err;
  891. }
  892. if (p_rmt_obj[channel]->tx_sem) {
  893. vSemaphoreDelete(p_rmt_obj[channel]->tx_sem);
  894. p_rmt_obj[channel]->tx_sem = NULL;
  895. }
  896. if (p_rmt_obj[channel]->rx_buf) {
  897. vRingbufferDelete(p_rmt_obj[channel]->rx_buf);
  898. p_rmt_obj[channel]->rx_buf = NULL;
  899. }
  900. if (p_rmt_obj[channel]->tx_buf) {
  901. free(p_rmt_obj[channel]->tx_buf);
  902. p_rmt_obj[channel]->tx_buf = NULL;
  903. }
  904. if (p_rmt_obj[channel]->sample_to_rmt) {
  905. p_rmt_obj[channel]->sample_to_rmt = NULL;
  906. }
  907. #if SOC_RMT_SUPPORT_RX_PINGPONG
  908. if (p_rmt_obj[channel]->rx_item_buf) {
  909. free(p_rmt_obj[channel]->rx_item_buf);
  910. p_rmt_obj[channel]->rx_item_buf = NULL;
  911. p_rmt_obj[channel]->rx_item_buf_size = 0;
  912. }
  913. #endif
  914. free(p_rmt_obj[channel]);
  915. p_rmt_obj[channel] = NULL;
  916. return ESP_OK;
  917. }
  918. esp_err_t rmt_driver_install(rmt_channel_t channel, size_t rx_buf_size, int intr_alloc_flags)
  919. {
  920. ESP_RETURN_ON_FALSE(channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  921. ESP_RETURN_ON_FALSE((rmt_contex.rmt_driver_channels & BIT(channel)) == 0, ESP_ERR_INVALID_STATE, TAG, "RMT driver already installed for channel");
  922. esp_err_t err = ESP_OK;
  923. if (p_rmt_obj[channel]) {
  924. ESP_LOGD(TAG, "RMT driver already installed");
  925. return ESP_ERR_INVALID_STATE;
  926. }
  927. #if !CONFIG_SPIRAM_USE_MALLOC
  928. p_rmt_obj[channel] = calloc(1, sizeof(rmt_obj_t));
  929. #else
  930. if (!(intr_alloc_flags & ESP_INTR_FLAG_IRAM)) {
  931. p_rmt_obj[channel] = calloc(1, sizeof(rmt_obj_t));
  932. } else {
  933. p_rmt_obj[channel] = heap_caps_calloc(1, sizeof(rmt_obj_t), MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
  934. }
  935. #endif
  936. if (p_rmt_obj[channel] == NULL) {
  937. ESP_LOGE(TAG, "RMT driver malloc error");
  938. return ESP_ERR_NO_MEM;
  939. }
  940. p_rmt_obj[channel]->tx_len_rem = 0;
  941. p_rmt_obj[channel]->tx_data = NULL;
  942. p_rmt_obj[channel]->channel = channel;
  943. p_rmt_obj[channel]->tx_offset = 0;
  944. p_rmt_obj[channel]->tx_sub_len = 0;
  945. p_rmt_obj[channel]->wait_done = false;
  946. p_rmt_obj[channel]->translator = false;
  947. p_rmt_obj[channel]->sample_to_rmt = NULL;
  948. if (p_rmt_obj[channel]->tx_sem == NULL) {
  949. #if !CONFIG_SPIRAM_USE_MALLOC
  950. p_rmt_obj[channel]->tx_sem = xSemaphoreCreateBinary();
  951. #else
  952. p_rmt_obj[channel]->intr_alloc_flags = intr_alloc_flags;
  953. if (!(intr_alloc_flags & ESP_INTR_FLAG_IRAM)) {
  954. p_rmt_obj[channel]->tx_sem = xSemaphoreCreateBinary();
  955. } else {
  956. p_rmt_obj[channel]->tx_sem = xSemaphoreCreateBinaryStatic(&p_rmt_obj[channel]->tx_sem_buffer);
  957. }
  958. #endif
  959. xSemaphoreGive(p_rmt_obj[channel]->tx_sem);
  960. }
  961. if (p_rmt_obj[channel]->rx_buf == NULL && rx_buf_size > 0) {
  962. p_rmt_obj[channel]->rx_buf = xRingbufferCreate(rx_buf_size, RINGBUF_TYPE_NOSPLIT);
  963. }
  964. #if SOC_RMT_SUPPORT_RX_PINGPONG
  965. if (p_rmt_obj[channel]->rx_item_buf == NULL && rx_buf_size > 0) {
  966. #if !CONFIG_SPIRAM_USE_MALLOC
  967. p_rmt_obj[channel]->rx_item_buf = calloc(1, rx_buf_size);
  968. #else
  969. if (!(p_rmt_obj[channel]->intr_alloc_flags & ESP_INTR_FLAG_IRAM)) {
  970. p_rmt_obj[channel]->rx_item_buf = calloc(1, rx_buf_size);
  971. } else {
  972. p_rmt_obj[channel]->rx_item_buf = heap_caps_calloc(1, rx_buf_size, MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
  973. }
  974. #endif
  975. if (p_rmt_obj[channel]->rx_item_buf == NULL) {
  976. ESP_LOGE(TAG, "RMT malloc fail");
  977. return ESP_FAIL;
  978. }
  979. p_rmt_obj[channel]->rx_item_buf_size = rx_buf_size;
  980. }
  981. #endif
  982. _lock_acquire_recursive(&(rmt_contex.rmt_driver_isr_lock));
  983. if (rmt_contex.rmt_driver_channels == 0) {
  984. // first RMT channel using driver
  985. err = rmt_isr_register(rmt_driver_isr_default, &rmt_contex.hal, intr_alloc_flags, &(rmt_contex.rmt_driver_intr_handle));
  986. }
  987. if (err == ESP_OK) {
  988. rmt_contex.rmt_driver_channels |= BIT(channel);
  989. }
  990. _lock_release_recursive(&(rmt_contex.rmt_driver_isr_lock));
  991. rmt_module_enable();
  992. if (RMT_IS_RX_CHANNEL(channel)) {
  993. rmt_hal_rx_channel_reset(&rmt_contex.hal, RMT_DECODE_RX_CHANNEL(channel));
  994. } else {
  995. rmt_hal_tx_channel_reset(&rmt_contex.hal, channel);
  996. }
  997. return err;
  998. }
  999. esp_err_t rmt_write_items(rmt_channel_t channel, const rmt_item32_t *rmt_item, int item_num, bool wait_tx_done)
  1000. {
  1001. ESP_RETURN_ON_FALSE(RMT_IS_TX_CHANNEL(channel), ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  1002. ESP_RETURN_ON_FALSE(p_rmt_obj[channel], ESP_FAIL, TAG, RMT_DRIVER_ERROR_STR);
  1003. ESP_RETURN_ON_FALSE(rmt_item, ESP_FAIL, TAG, RMT_ADDR_ERROR_STR);
  1004. ESP_RETURN_ON_FALSE(item_num > 0, ESP_ERR_INVALID_ARG, TAG, RMT_DRIVER_LENGTH_ERROR_STR);
  1005. #if CONFIG_SPIRAM_USE_MALLOC
  1006. if (p_rmt_obj[channel]->intr_alloc_flags & ESP_INTR_FLAG_IRAM) {
  1007. if (!esp_ptr_internal(rmt_item)) {
  1008. ESP_LOGE(TAG, RMT_PSRAM_BUFFER_WARN_STR);
  1009. return ESP_ERR_INVALID_ARG;
  1010. }
  1011. }
  1012. #endif
  1013. rmt_obj_t *p_rmt = p_rmt_obj[channel];
  1014. int block_num = rmt_ll_tx_get_mem_blocks(rmt_contex.hal.regs, channel);
  1015. int item_block_len = block_num * RMT_MEM_ITEM_NUM;
  1016. int item_sub_len = block_num * RMT_MEM_ITEM_NUM / 2;
  1017. int len_rem = item_num;
  1018. xSemaphoreTake(p_rmt->tx_sem, portMAX_DELAY);
  1019. // fill the memory block first
  1020. if (item_num >= item_block_len) {
  1021. rmt_fill_memory(channel, rmt_item, item_block_len, 0);
  1022. len_rem -= item_block_len;
  1023. rmt_set_tx_loop_mode(channel, false);
  1024. rmt_set_tx_thr_intr_en(channel, 1, item_sub_len);
  1025. p_rmt->tx_data = rmt_item + item_block_len;
  1026. p_rmt->tx_len_rem = len_rem;
  1027. p_rmt->tx_offset = 0;
  1028. p_rmt->tx_sub_len = item_sub_len;
  1029. } else {
  1030. rmt_fill_memory(channel, rmt_item, len_rem, 0);
  1031. rmt_item32_t stop_data = {0};
  1032. rmt_ll_write_memory(rmt_contex.hal.mem, channel, &stop_data, 1, len_rem);
  1033. p_rmt->tx_len_rem = 0;
  1034. }
  1035. rmt_tx_start(channel, true);
  1036. p_rmt->wait_done = wait_tx_done;
  1037. if (wait_tx_done) {
  1038. // wait loop done
  1039. if (rmt_ll_is_tx_loop_enabled(rmt_contex.hal.regs, channel)) {
  1040. #if SOC_RMT_SUPPORT_TX_LOOP_COUNT
  1041. xSemaphoreTake(p_rmt->tx_sem, portMAX_DELAY);
  1042. xSemaphoreGive(p_rmt->tx_sem);
  1043. #endif
  1044. } else {
  1045. // wait tx end
  1046. xSemaphoreTake(p_rmt->tx_sem, portMAX_DELAY);
  1047. xSemaphoreGive(p_rmt->tx_sem);
  1048. }
  1049. }
  1050. return ESP_OK;
  1051. }
  1052. esp_err_t rmt_wait_tx_done(rmt_channel_t channel, TickType_t wait_time)
  1053. {
  1054. ESP_RETURN_ON_FALSE(RMT_IS_TX_CHANNEL(channel), ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  1055. ESP_RETURN_ON_FALSE(p_rmt_obj[channel], ESP_FAIL, TAG, RMT_DRIVER_ERROR_STR);
  1056. if (xSemaphoreTake(p_rmt_obj[channel]->tx_sem, wait_time) == pdTRUE) {
  1057. p_rmt_obj[channel]->wait_done = false;
  1058. xSemaphoreGive(p_rmt_obj[channel]->tx_sem);
  1059. return ESP_OK;
  1060. } else {
  1061. if (wait_time != 0) {
  1062. // Don't emit error message if just polling.
  1063. ESP_LOGE(TAG, "Timeout on wait_tx_done");
  1064. }
  1065. return ESP_ERR_TIMEOUT;
  1066. }
  1067. }
  1068. esp_err_t rmt_get_ringbuf_handle(rmt_channel_t channel, RingbufHandle_t *buf_handle)
  1069. {
  1070. ESP_RETURN_ON_FALSE(channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  1071. ESP_RETURN_ON_FALSE(p_rmt_obj[channel], ESP_FAIL, TAG, RMT_DRIVER_ERROR_STR);
  1072. ESP_RETURN_ON_FALSE(buf_handle, ESP_ERR_INVALID_ARG, TAG, RMT_ADDR_ERROR_STR);
  1073. *buf_handle = p_rmt_obj[channel]->rx_buf;
  1074. return ESP_OK;
  1075. }
  1076. rmt_tx_end_callback_t rmt_register_tx_end_callback(rmt_tx_end_fn_t function, void *arg)
  1077. {
  1078. rmt_tx_end_callback_t previous = rmt_contex.rmt_tx_end_callback;
  1079. rmt_contex.rmt_tx_end_callback.function = function;
  1080. rmt_contex.rmt_tx_end_callback.arg = arg;
  1081. return previous;
  1082. }
  1083. esp_err_t rmt_translator_init(rmt_channel_t channel, sample_to_rmt_t fn)
  1084. {
  1085. ESP_RETURN_ON_FALSE(fn, ESP_ERR_INVALID_ARG, TAG, RMT_TRANSLATOR_NULL_STR);
  1086. ESP_RETURN_ON_FALSE(RMT_IS_TX_CHANNEL(channel), ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  1087. ESP_RETURN_ON_FALSE(p_rmt_obj[channel], ESP_FAIL, TAG, RMT_DRIVER_ERROR_STR);
  1088. const uint32_t block_size = rmt_ll_tx_get_mem_blocks(rmt_contex.hal.regs, channel) *
  1089. RMT_MEM_ITEM_NUM * sizeof(rmt_item32_t);
  1090. if (p_rmt_obj[channel]->tx_buf == NULL) {
  1091. #if !CONFIG_SPIRAM_USE_MALLOC
  1092. p_rmt_obj[channel]->tx_buf = (rmt_item32_t *)malloc(block_size);
  1093. #else
  1094. if (p_rmt_obj[channel]->intr_alloc_flags & ESP_INTR_FLAG_IRAM) {
  1095. p_rmt_obj[channel]->tx_buf = (rmt_item32_t *)malloc(block_size);
  1096. } else {
  1097. p_rmt_obj[channel]->tx_buf = (rmt_item32_t *)heap_caps_calloc(1, block_size, MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
  1098. }
  1099. #endif
  1100. if (p_rmt_obj[channel]->tx_buf == NULL) {
  1101. ESP_LOGE(TAG, "RMT translator buffer create fail");
  1102. return ESP_FAIL;
  1103. }
  1104. }
  1105. p_rmt_obj[channel]->sample_to_rmt = fn;
  1106. p_rmt_obj[channel]->tx_context = NULL;
  1107. p_rmt_obj[channel]->sample_size_remain = 0;
  1108. p_rmt_obj[channel]->sample_cur = NULL;
  1109. ESP_LOGD(TAG, "RMT translator init done");
  1110. return ESP_OK;
  1111. }
  1112. esp_err_t rmt_translator_set_context(rmt_channel_t channel, void *context)
  1113. {
  1114. ESP_RETURN_ON_FALSE(channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  1115. ESP_RETURN_ON_FALSE(p_rmt_obj[channel], ESP_FAIL, TAG, RMT_DRIVER_ERROR_STR);
  1116. p_rmt_obj[channel]->tx_context = context;
  1117. return ESP_OK;
  1118. }
  1119. esp_err_t rmt_translator_get_context(const size_t *item_num, void **context)
  1120. {
  1121. ESP_RETURN_ON_FALSE(item_num && context, ESP_ERR_INVALID_ARG, TAG, "invalid arguments");
  1122. // the address of tx_len_rem is directlly passed to the callback,
  1123. // so it's possible to get the object address from that
  1124. rmt_obj_t *obj = __containerof(item_num, rmt_obj_t, tx_len_rem);
  1125. *context = obj->tx_context;
  1126. return ESP_OK;
  1127. }
  1128. esp_err_t rmt_write_sample(rmt_channel_t channel, const uint8_t *src, size_t src_size, bool wait_tx_done)
  1129. {
  1130. ESP_RETURN_ON_FALSE(RMT_IS_TX_CHANNEL(channel), ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  1131. ESP_RETURN_ON_FALSE(p_rmt_obj[channel], ESP_FAIL, TAG, RMT_DRIVER_ERROR_STR);
  1132. ESP_RETURN_ON_FALSE(p_rmt_obj[channel]->sample_to_rmt, ESP_FAIL, TAG, RMT_TRANSLATOR_UNINIT_STR);
  1133. #if CONFIG_SPIRAM_USE_MALLOC
  1134. if (p_rmt_obj[channel]->intr_alloc_flags & ESP_INTR_FLAG_IRAM) {
  1135. if (!esp_ptr_internal(src)) {
  1136. ESP_LOGE(TAG, RMT_PSRAM_BUFFER_WARN_STR);
  1137. return ESP_ERR_INVALID_ARG;
  1138. }
  1139. }
  1140. #endif
  1141. size_t translated_size = 0;
  1142. rmt_obj_t *p_rmt = p_rmt_obj[channel];
  1143. const uint32_t item_block_len = rmt_ll_tx_get_mem_blocks(rmt_contex.hal.regs, channel) * RMT_MEM_ITEM_NUM;
  1144. const uint32_t item_sub_len = item_block_len / 2;
  1145. xSemaphoreTake(p_rmt->tx_sem, portMAX_DELAY);
  1146. p_rmt->sample_to_rmt((void *)src, p_rmt->tx_buf, src_size, item_block_len, &translated_size, &p_rmt->tx_len_rem);
  1147. p_rmt->sample_size_remain = src_size - translated_size;
  1148. p_rmt->sample_cur = src + translated_size;
  1149. rmt_fill_memory(channel, p_rmt->tx_buf, p_rmt->tx_len_rem, 0);
  1150. if (p_rmt->tx_len_rem == item_block_len) {
  1151. rmt_set_tx_thr_intr_en(channel, 1, item_sub_len);
  1152. p_rmt->tx_data = p_rmt->tx_buf;
  1153. p_rmt->tx_offset = 0;
  1154. p_rmt->tx_sub_len = item_sub_len;
  1155. p_rmt->translator = true;
  1156. } else {
  1157. rmt_item32_t stop_data = {0};
  1158. rmt_ll_write_memory(rmt_contex.hal.mem, channel, &stop_data, 1, p_rmt->tx_len_rem);
  1159. p_rmt->tx_len_rem = 0;
  1160. p_rmt->sample_cur = NULL;
  1161. p_rmt->translator = false;
  1162. }
  1163. rmt_tx_start(channel, true);
  1164. p_rmt->wait_done = wait_tx_done;
  1165. if (wait_tx_done) {
  1166. xSemaphoreTake(p_rmt->tx_sem, portMAX_DELAY);
  1167. xSemaphoreGive(p_rmt->tx_sem);
  1168. }
  1169. return ESP_OK;
  1170. }
  1171. esp_err_t rmt_get_channel_status(rmt_channel_status_result_t *channel_status)
  1172. {
  1173. ESP_RETURN_ON_FALSE(channel_status, ESP_ERR_INVALID_ARG, TAG, RMT_PARAM_ERR_STR);
  1174. for (int i = 0; i < RMT_CHANNEL_MAX; i++) {
  1175. channel_status->status[i] = RMT_CHANNEL_UNINIT;
  1176. if (p_rmt_obj[i]) {
  1177. if (p_rmt_obj[i]->tx_sem) {
  1178. if (xSemaphoreTake(p_rmt_obj[i]->tx_sem, (TickType_t)0) == pdTRUE) {
  1179. channel_status->status[i] = RMT_CHANNEL_IDLE;
  1180. xSemaphoreGive(p_rmt_obj[i]->tx_sem);
  1181. } else {
  1182. channel_status->status[i] = RMT_CHANNEL_BUSY;
  1183. }
  1184. }
  1185. }
  1186. }
  1187. return ESP_OK;
  1188. }
  1189. esp_err_t rmt_get_counter_clock(rmt_channel_t channel, uint32_t *clock_hz)
  1190. {
  1191. ESP_RETURN_ON_FALSE(channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  1192. ESP_RETURN_ON_FALSE(clock_hz, ESP_ERR_INVALID_ARG, TAG, "parameter clock_hz can't be null");
  1193. RMT_ENTER_CRITICAL();
  1194. uint32_t rmt_source_clk_hz = 0;
  1195. #if SOC_RMT_CHANNEL_CLK_INDEPENDENT
  1196. rmt_source_clk_hz = s_rmt_source_clock_hz[channel];
  1197. #else
  1198. rmt_source_clk_hz = s_rmt_source_clock_hz;
  1199. #endif
  1200. if (RMT_IS_RX_CHANNEL(channel)) {
  1201. *clock_hz = rmt_source_clk_hz / rmt_ll_rx_get_channel_clock_div(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel));
  1202. } else {
  1203. *clock_hz = rmt_source_clk_hz / rmt_ll_tx_get_channel_clock_div(rmt_contex.hal.regs, channel);
  1204. }
  1205. RMT_EXIT_CRITICAL();
  1206. return ESP_OK;
  1207. }
  1208. #if SOC_RMT_SUPPORT_TX_SYNCHRO
  1209. esp_err_t rmt_add_channel_to_group(rmt_channel_t channel)
  1210. {
  1211. ESP_RETURN_ON_FALSE(RMT_IS_TX_CHANNEL(channel), ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  1212. RMT_ENTER_CRITICAL();
  1213. rmt_ll_tx_enable_sync(rmt_contex.hal.regs, true);
  1214. rmt_contex.synchro_channel_mask |= (1 << channel);
  1215. rmt_ll_tx_add_to_sync_group(rmt_contex.hal.regs, channel);
  1216. rmt_ll_tx_reset_channels_clock_div(rmt_contex.hal.regs, rmt_contex.synchro_channel_mask);
  1217. RMT_EXIT_CRITICAL();
  1218. return ESP_OK;
  1219. }
  1220. esp_err_t rmt_remove_channel_from_group(rmt_channel_t channel)
  1221. {
  1222. ESP_RETURN_ON_FALSE(RMT_IS_TX_CHANNEL(channel), ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  1223. RMT_ENTER_CRITICAL();
  1224. rmt_contex.synchro_channel_mask &= ~(1 << channel);
  1225. rmt_ll_tx_remove_from_sync_group(rmt_contex.hal.regs, channel);
  1226. if (rmt_contex.synchro_channel_mask == 0) {
  1227. rmt_ll_tx_enable_sync(rmt_contex.hal.regs, false);
  1228. }
  1229. RMT_EXIT_CRITICAL();
  1230. return ESP_OK;
  1231. }
  1232. #endif
  1233. esp_err_t rmt_memory_rw_rst(rmt_channel_t channel)
  1234. {
  1235. ESP_RETURN_ON_FALSE(channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  1236. RMT_ENTER_CRITICAL();
  1237. if (RMT_IS_RX_CHANNEL(channel)) {
  1238. rmt_ll_rx_reset_pointer(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel));
  1239. } else {
  1240. rmt_ll_tx_reset_pointer(rmt_contex.hal.regs, channel);
  1241. }
  1242. RMT_EXIT_CRITICAL();
  1243. return ESP_OK;
  1244. }
  1245. #if SOC_RMT_SUPPORT_TX_LOOP_COUNT
  1246. esp_err_t rmt_set_tx_loop_count(rmt_channel_t channel, uint32_t count)
  1247. {
  1248. ESP_RETURN_ON_FALSE(RMT_IS_TX_CHANNEL(channel), ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
  1249. RMT_ENTER_CRITICAL();
  1250. rmt_ll_tx_set_loop_count(rmt_contex.hal.regs, channel, count);
  1251. RMT_EXIT_CRITICAL();
  1252. return ESP_OK;
  1253. }
  1254. #endif