esp_efuse_table.c 12 KB

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  1. // Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
  2. //
  3. // Licensed under the Apache License, Version 2.0 (the "License");
  4. // you may not use this file except in compliance with the License.
  5. // You may obtain a copy of the License at",
  6. //
  7. // http://www.apache.org/licenses/LICENSE-2.0
  8. //
  9. // Unless required by applicable law or agreed to in writing, software
  10. // distributed under the License is distributed on an "AS IS" BASIS,
  11. // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  12. // See the License for the specific language governing permissions and
  13. // limitations under the License
  14. #include "sdkconfig.h"
  15. #include "esp_efuse.h"
  16. #include <assert.h>
  17. #include "esp_efuse_table.h"
  18. // md5_digest_table 840523b9e1313240e6102615e3a497a5
  19. // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
  20. // If you want to change some fields, you need to change esp_efuse_table.csv file
  21. // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
  22. // To show efuse_table run the command 'show_efuse_table'.
  23. #define MAX_BLK_LEN CONFIG_EFUSE_MAX_BLK_LEN
  24. // The last free bit in the block is counted over the entire file.
  25. #define LAST_FREE_BIT_BLK1 MAX_BLK_LEN
  26. #define LAST_FREE_BIT_BLK2 MAX_BLK_LEN
  27. #define LAST_FREE_BIT_BLK3 192
  28. _Static_assert(LAST_FREE_BIT_BLK1 <= MAX_BLK_LEN, "The eFuse table does not match the coding scheme. Edit the table and restart the efuse_common_table or efuse_custom_table command to regenerate the new files.");
  29. _Static_assert(LAST_FREE_BIT_BLK2 <= MAX_BLK_LEN, "The eFuse table does not match the coding scheme. Edit the table and restart the efuse_common_table or efuse_custom_table command to regenerate the new files.");
  30. _Static_assert(LAST_FREE_BIT_BLK3 <= MAX_BLK_LEN, "The eFuse table does not match the coding scheme. Edit the table and restart the efuse_common_table or efuse_custom_table command to regenerate the new files.");
  31. static const esp_efuse_desc_t MAC_FACTORY[] = {
  32. {EFUSE_BLK0, 72, 8}, // Factory MAC addr [0],
  33. {EFUSE_BLK0, 64, 8}, // Factory MAC addr [1],
  34. {EFUSE_BLK0, 56, 8}, // Factory MAC addr [2],
  35. {EFUSE_BLK0, 48, 8}, // Factory MAC addr [3],
  36. {EFUSE_BLK0, 40, 8}, // Factory MAC addr [4],
  37. {EFUSE_BLK0, 32, 8}, // Factory MAC addr [5],
  38. };
  39. static const esp_efuse_desc_t MAC_FACTORY_CRC[] = {
  40. {EFUSE_BLK0, 80, 8}, // CRC8 for factory MAC address,
  41. };
  42. static const esp_efuse_desc_t MAC_CUSTOM_CRC[] = {
  43. {EFUSE_BLK3, 0, 8}, // CRC8 for custom MAC address.,
  44. };
  45. static const esp_efuse_desc_t MAC_CUSTOM[] = {
  46. {EFUSE_BLK3, 8, 48}, // Custom MAC,
  47. };
  48. static const esp_efuse_desc_t MAC_CUSTOM_VER[] = {
  49. {EFUSE_BLK3, 184, 8}, // Custom MAC version,
  50. };
  51. static const esp_efuse_desc_t SECURE_BOOT_KEY[] = {
  52. {EFUSE_BLK2, 0, MAX_BLK_LEN}, // Security boot. Key. (length = "None" - 256. "3/4" - 192. "REPEAT" - 128),
  53. };
  54. static const esp_efuse_desc_t ABS_DONE_0[] = {
  55. {EFUSE_BLK0, 196, 1}, // Secure boot is enabled for bootloader image. EFUSE_RD_ABS_DONE_0,
  56. };
  57. static const esp_efuse_desc_t ENCRYPT_FLASH_KEY[] = {
  58. {EFUSE_BLK1, 0, MAX_BLK_LEN}, // Flash encrypt. Key. (length = "None" - 256. "3/4" - 192. "REPEAT" - 128),
  59. };
  60. static const esp_efuse_desc_t ENCRYPT_CONFIG[] = {
  61. {EFUSE_BLK0, 188, 4}, // Flash encrypt. EFUSE_FLASH_CRYPT_CONFIG_M,
  62. };
  63. static const esp_efuse_desc_t DISABLE_DL_ENCRYPT[] = {
  64. {EFUSE_BLK0, 199, 1}, // Flash encrypt. Disable UART bootloader encryption. EFUSE_DISABLE_DL_ENCRYPT.,
  65. };
  66. static const esp_efuse_desc_t DISABLE_DL_DECRYPT[] = {
  67. {EFUSE_BLK0, 200, 1}, // Flash encrypt. Disable UART bootloader decryption. EFUSE_DISABLE_DL_DECRYPT.,
  68. };
  69. static const esp_efuse_desc_t DISABLE_DL_CACHE[] = {
  70. {EFUSE_BLK0, 201, 1}, // Flash encrypt. Disable UART bootloader MMU cache. EFUSE_DISABLE_DL_CACHE.,
  71. };
  72. static const esp_efuse_desc_t DISABLE_JTAG[] = {
  73. {EFUSE_BLK0, 198, 1}, // Flash encrypt. Disable JTAG. EFUSE_RD_DISABLE_JTAG.,
  74. };
  75. static const esp_efuse_desc_t CONSOLE_DEBUG_DISABLE[] = {
  76. {EFUSE_BLK0, 194, 1}, // Flash encrypt. Disable ROM BASIC interpreter fallback. EFUSE_RD_CONSOLE_DEBUG_DISABLE.,
  77. };
  78. static const esp_efuse_desc_t FLASH_CRYPT_CNT[] = {
  79. {EFUSE_BLK0, 20, 8}, // Flash encrypt. Flash encryption is enabled if this field has an odd number of bits set. EFUSE_FLASH_CRYPT_CNT.,
  80. };
  81. static const esp_efuse_desc_t WR_DIS_FLASH_CRYPT_CNT[] = {
  82. {EFUSE_BLK0, 2, 1}, // Flash encrypt. Write protection FLASH_CRYPT_CNT. EFUSE_WR_DIS_FLASH_CRYPT_CNT,
  83. };
  84. static const esp_efuse_desc_t WR_DIS_BLK1[] = {
  85. {EFUSE_BLK0, 7, 1}, // Flash encrypt. Write protection encryption key. EFUSE_WR_DIS_BLK1,
  86. };
  87. static const esp_efuse_desc_t WR_DIS_BLK2[] = {
  88. {EFUSE_BLK0, 8, 1}, // Security boot. Write protection security key. EFUSE_WR_DIS_BLK2,
  89. };
  90. static const esp_efuse_desc_t WR_DIS_BLK3[] = {
  91. {EFUSE_BLK0, 9, 1}, // Write protection for EFUSE_BLK3. EFUSE_WR_DIS_BLK3,
  92. };
  93. static const esp_efuse_desc_t RD_DIS_BLK1[] = {
  94. {EFUSE_BLK0, 16, 1}, // Flash encrypt. efuse_key_read_protected. EFUSE_RD_DIS_BLK1,
  95. };
  96. static const esp_efuse_desc_t RD_DIS_BLK2[] = {
  97. {EFUSE_BLK0, 17, 1}, // Security boot. efuse_key_read_protected. EFUSE_RD_DIS_BLK2,
  98. };
  99. static const esp_efuse_desc_t RD_DIS_BLK3[] = {
  100. {EFUSE_BLK0, 18, 1}, // Read protection for EFUSE_BLK3. EFUSE_RD_DIS_BLK3,
  101. };
  102. static const esp_efuse_desc_t CHIP_VER_DIS_APP_CPU[] = {
  103. {EFUSE_BLK0, 96, 1}, // EFUSE_RD_CHIP_VER_DIS_APP_CPU,
  104. };
  105. static const esp_efuse_desc_t CHIP_VER_DIS_BT[] = {
  106. {EFUSE_BLK0, 97, 1}, // EFUSE_RD_CHIP_VER_DIS_BT,
  107. };
  108. static const esp_efuse_desc_t CHIP_VER_PKG[] = {
  109. {EFUSE_BLK0, 105, 3}, // EFUSE_RD_CHIP_VER_PKG,
  110. };
  111. static const esp_efuse_desc_t CHIP_CPU_FREQ_LOW[] = {
  112. {EFUSE_BLK0, 108, 1}, // EFUSE_RD_CHIP_CPU_FREQ_LOW,
  113. };
  114. static const esp_efuse_desc_t CHIP_CPU_FREQ_RATED[] = {
  115. {EFUSE_BLK0, 109, 1}, // EFUSE_RD_CHIP_CPU_FREQ_RATED,
  116. };
  117. static const esp_efuse_desc_t CHIP_VER_REV1[] = {
  118. {EFUSE_BLK0, 111, 1}, // EFUSE_RD_CHIP_VER_REV1,
  119. };
  120. static const esp_efuse_desc_t XPD_SDIO_REG[] = {
  121. {EFUSE_BLK0, 142, 1}, // EFUSE_RD_XPD_SDIO_REG,
  122. };
  123. static const esp_efuse_desc_t SDIO_TIEH[] = {
  124. {EFUSE_BLK0, 143, 1}, // EFUSE_RD_SDIO_TIEH,
  125. };
  126. static const esp_efuse_desc_t SDIO_FORCE[] = {
  127. {EFUSE_BLK0, 144, 1}, // EFUSE_RD_SDIO_FORCE,
  128. };
  129. static const esp_efuse_desc_t ADC_VREF_AND_SDIO_DREF[] = {
  130. {EFUSE_BLK0, 136, 6}, // EFUSE_RD_ADC_VREF[0..4] or ( SDIO_DREFH[0 1],
  131. };
  132. static const esp_efuse_desc_t ADC1_TP_LOW[] = {
  133. {EFUSE_BLK3, 96, 7}, // TP_REG EFUSE_RD_ADC1_TP_LOW,
  134. };
  135. static const esp_efuse_desc_t ADC2_TP_LOW[] = {
  136. {EFUSE_BLK3, 112, 7}, // TP_REG EFUSE_RD_ADC2_TP_LOW,
  137. };
  138. static const esp_efuse_desc_t ADC1_TP_HIGH[] = {
  139. {EFUSE_BLK3, 103, 9}, // TP_REG EFUSE_RD_ADC1_TP_HIGH,
  140. };
  141. static const esp_efuse_desc_t ADC2_TP_HIGH[] = {
  142. {EFUSE_BLK3, 119, 9}, // TP_REG EFUSE_RD_ADC2_TP_HIGH,
  143. };
  144. static const esp_efuse_desc_t SECURE_VERSION[] = {
  145. {EFUSE_BLK3, 128, 32}, // Secure version for anti-rollback,
  146. };
  147. const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[] = {
  148. &MAC_FACTORY[0], // Factory MAC addr [0]
  149. &MAC_FACTORY[1], // Factory MAC addr [1]
  150. &MAC_FACTORY[2], // Factory MAC addr [2]
  151. &MAC_FACTORY[3], // Factory MAC addr [3]
  152. &MAC_FACTORY[4], // Factory MAC addr [4]
  153. &MAC_FACTORY[5], // Factory MAC addr [5]
  154. NULL
  155. };
  156. const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY_CRC[] = {
  157. &MAC_FACTORY_CRC[0], // CRC8 for factory MAC address
  158. NULL
  159. };
  160. const esp_efuse_desc_t* ESP_EFUSE_MAC_CUSTOM_CRC[] = {
  161. &MAC_CUSTOM_CRC[0], // CRC8 for custom MAC address.
  162. NULL
  163. };
  164. const esp_efuse_desc_t* ESP_EFUSE_MAC_CUSTOM[] = {
  165. &MAC_CUSTOM[0], // Custom MAC
  166. NULL
  167. };
  168. const esp_efuse_desc_t* ESP_EFUSE_MAC_CUSTOM_VER[] = {
  169. &MAC_CUSTOM_VER[0], // Custom MAC version
  170. NULL
  171. };
  172. const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY[] = {
  173. &SECURE_BOOT_KEY[0], // Security boot. Key. (length = "None" - 256. "3/4" - 192. "REPEAT" - 128)
  174. NULL
  175. };
  176. const esp_efuse_desc_t* ESP_EFUSE_ABS_DONE_0[] = {
  177. &ABS_DONE_0[0], // Secure boot is enabled for bootloader image. EFUSE_RD_ABS_DONE_0
  178. NULL
  179. };
  180. const esp_efuse_desc_t* ESP_EFUSE_ENCRYPT_FLASH_KEY[] = {
  181. &ENCRYPT_FLASH_KEY[0], // Flash encrypt. Key. (length = "None" - 256. "3/4" - 192. "REPEAT" - 128)
  182. NULL
  183. };
  184. const esp_efuse_desc_t* ESP_EFUSE_ENCRYPT_CONFIG[] = {
  185. &ENCRYPT_CONFIG[0], // Flash encrypt. EFUSE_FLASH_CRYPT_CONFIG_M
  186. NULL
  187. };
  188. const esp_efuse_desc_t* ESP_EFUSE_DISABLE_DL_ENCRYPT[] = {
  189. &DISABLE_DL_ENCRYPT[0], // Flash encrypt. Disable UART bootloader encryption. EFUSE_DISABLE_DL_ENCRYPT.
  190. NULL
  191. };
  192. const esp_efuse_desc_t* ESP_EFUSE_DISABLE_DL_DECRYPT[] = {
  193. &DISABLE_DL_DECRYPT[0], // Flash encrypt. Disable UART bootloader decryption. EFUSE_DISABLE_DL_DECRYPT.
  194. NULL
  195. };
  196. const esp_efuse_desc_t* ESP_EFUSE_DISABLE_DL_CACHE[] = {
  197. &DISABLE_DL_CACHE[0], // Flash encrypt. Disable UART bootloader MMU cache. EFUSE_DISABLE_DL_CACHE.
  198. NULL
  199. };
  200. const esp_efuse_desc_t* ESP_EFUSE_DISABLE_JTAG[] = {
  201. &DISABLE_JTAG[0], // Flash encrypt. Disable JTAG. EFUSE_RD_DISABLE_JTAG.
  202. NULL
  203. };
  204. const esp_efuse_desc_t* ESP_EFUSE_CONSOLE_DEBUG_DISABLE[] = {
  205. &CONSOLE_DEBUG_DISABLE[0], // Flash encrypt. Disable ROM BASIC interpreter fallback. EFUSE_RD_CONSOLE_DEBUG_DISABLE.
  206. NULL
  207. };
  208. const esp_efuse_desc_t* ESP_EFUSE_FLASH_CRYPT_CNT[] = {
  209. &FLASH_CRYPT_CNT[0], // Flash encrypt. Flash encryption is enabled if this field has an odd number of bits set. EFUSE_FLASH_CRYPT_CNT.
  210. NULL
  211. };
  212. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_CRYPT_CNT[] = {
  213. &WR_DIS_FLASH_CRYPT_CNT[0], // Flash encrypt. Write protection FLASH_CRYPT_CNT. EFUSE_WR_DIS_FLASH_CRYPT_CNT
  214. NULL
  215. };
  216. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[] = {
  217. &WR_DIS_BLK1[0], // Flash encrypt. Write protection encryption key. EFUSE_WR_DIS_BLK1
  218. NULL
  219. };
  220. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK2[] = {
  221. &WR_DIS_BLK2[0], // Security boot. Write protection security key. EFUSE_WR_DIS_BLK2
  222. NULL
  223. };
  224. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK3[] = {
  225. &WR_DIS_BLK3[0], // Write protection for EFUSE_BLK3. EFUSE_WR_DIS_BLK3
  226. NULL
  227. };
  228. const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLK1[] = {
  229. &RD_DIS_BLK1[0], // Flash encrypt. efuse_key_read_protected. EFUSE_RD_DIS_BLK1
  230. NULL
  231. };
  232. const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLK2[] = {
  233. &RD_DIS_BLK2[0], // Security boot. efuse_key_read_protected. EFUSE_RD_DIS_BLK2
  234. NULL
  235. };
  236. const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLK3[] = {
  237. &RD_DIS_BLK3[0], // Read protection for EFUSE_BLK3. EFUSE_RD_DIS_BLK3
  238. NULL
  239. };
  240. const esp_efuse_desc_t* ESP_EFUSE_CHIP_VER_DIS_APP_CPU[] = {
  241. &CHIP_VER_DIS_APP_CPU[0], // EFUSE_RD_CHIP_VER_DIS_APP_CPU
  242. NULL
  243. };
  244. const esp_efuse_desc_t* ESP_EFUSE_CHIP_VER_DIS_BT[] = {
  245. &CHIP_VER_DIS_BT[0], // EFUSE_RD_CHIP_VER_DIS_BT
  246. NULL
  247. };
  248. const esp_efuse_desc_t* ESP_EFUSE_CHIP_VER_PKG[] = {
  249. &CHIP_VER_PKG[0], // EFUSE_RD_CHIP_VER_PKG
  250. NULL
  251. };
  252. const esp_efuse_desc_t* ESP_EFUSE_CHIP_CPU_FREQ_LOW[] = {
  253. &CHIP_CPU_FREQ_LOW[0], // EFUSE_RD_CHIP_CPU_FREQ_LOW
  254. NULL
  255. };
  256. const esp_efuse_desc_t* ESP_EFUSE_CHIP_CPU_FREQ_RATED[] = {
  257. &CHIP_CPU_FREQ_RATED[0], // EFUSE_RD_CHIP_CPU_FREQ_RATED
  258. NULL
  259. };
  260. const esp_efuse_desc_t* ESP_EFUSE_CHIP_VER_REV1[] = {
  261. &CHIP_VER_REV1[0], // EFUSE_RD_CHIP_VER_REV1
  262. NULL
  263. };
  264. const esp_efuse_desc_t* ESP_EFUSE_XPD_SDIO_REG[] = {
  265. &XPD_SDIO_REG[0], // EFUSE_RD_XPD_SDIO_REG
  266. NULL
  267. };
  268. const esp_efuse_desc_t* ESP_EFUSE_SDIO_TIEH[] = {
  269. &SDIO_TIEH[0], // EFUSE_RD_SDIO_TIEH
  270. NULL
  271. };
  272. const esp_efuse_desc_t* ESP_EFUSE_SDIO_FORCE[] = {
  273. &SDIO_FORCE[0], // EFUSE_RD_SDIO_FORCE
  274. NULL
  275. };
  276. const esp_efuse_desc_t* ESP_EFUSE_ADC_VREF_AND_SDIO_DREF[] = {
  277. &ADC_VREF_AND_SDIO_DREF[0], // EFUSE_RD_ADC_VREF[0..4] or ( SDIO_DREFH[0 1]
  278. NULL
  279. };
  280. const esp_efuse_desc_t* ESP_EFUSE_ADC1_TP_LOW[] = {
  281. &ADC1_TP_LOW[0], // TP_REG EFUSE_RD_ADC1_TP_LOW
  282. NULL
  283. };
  284. const esp_efuse_desc_t* ESP_EFUSE_ADC2_TP_LOW[] = {
  285. &ADC2_TP_LOW[0], // TP_REG EFUSE_RD_ADC2_TP_LOW
  286. NULL
  287. };
  288. const esp_efuse_desc_t* ESP_EFUSE_ADC1_TP_HIGH[] = {
  289. &ADC1_TP_HIGH[0], // TP_REG EFUSE_RD_ADC1_TP_HIGH
  290. NULL
  291. };
  292. const esp_efuse_desc_t* ESP_EFUSE_ADC2_TP_HIGH[] = {
  293. &ADC2_TP_HIGH[0], // TP_REG EFUSE_RD_ADC2_TP_HIGH
  294. NULL
  295. };
  296. const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[] = {
  297. &SECURE_VERSION[0], // Secure version for anti-rollback
  298. NULL
  299. };