bootloader_efuse_esp32.c 2.0 KB

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  1. // Copyright 2019 Espressif Systems (Shanghai) PTE LTD
  2. //
  3. // Licensed under the Apache License, Version 2.0 (the "License");
  4. // you may not use this file except in compliance with the License.
  5. // You may obtain a copy of the License at
  6. //
  7. // http://www.apache.org/licenses/LICENSE-2.0
  8. //
  9. // Unless required by applicable law or agreed to in writing, software
  10. // distributed under the License is distributed on an "AS IS" BASIS,
  11. // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  12. // See the License for the specific language governing permissions and
  13. // limitations under the License.
  14. #include "bootloader_common.h"
  15. #include "bootloader_clock.h"
  16. #include "soc/efuse_reg.h"
  17. #include "soc/apb_ctrl_reg.h"
  18. uint8_t bootloader_common_get_chip_revision(void)
  19. {
  20. uint8_t eco_bit0, eco_bit1, eco_bit2;
  21. eco_bit0 = (REG_READ(EFUSE_BLK0_RDATA3_REG) & 0xF000) >> 15;
  22. eco_bit1 = (REG_READ(EFUSE_BLK0_RDATA5_REG) & 0x100000) >> 20;
  23. eco_bit2 = (REG_READ(APB_CTRL_DATE_REG) & 0x80000000) >> 31;
  24. uint32_t combine_value = (eco_bit2 << 2) | (eco_bit1 << 1) | eco_bit0;
  25. uint8_t chip_ver = 0;
  26. switch (combine_value) {
  27. case 0:
  28. chip_ver = 0;
  29. break;
  30. case 1:
  31. chip_ver = 1;
  32. break;
  33. case 3:
  34. chip_ver = 2;
  35. break;
  36. case 7:
  37. chip_ver = 3;
  38. break;
  39. default:
  40. chip_ver = 0;
  41. break;
  42. }
  43. return chip_ver;
  44. }
  45. uint32_t bootloader_common_get_chip_ver_pkg(void)
  46. {
  47. uint32_t pkg_version = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_PKG);
  48. uint32_t pkg_version_4bit = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_PKG_4BIT);
  49. return (pkg_version_4bit << 3) | pkg_version;
  50. }
  51. int bootloader_clock_get_rated_freq_mhz()
  52. {
  53. //Check if ESP32 is rated for a CPU frequency of 160MHz only
  54. if (REG_GET_BIT(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_CPU_FREQ_RATED) &&
  55. REG_GET_BIT(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_CPU_FREQ_LOW)) {
  56. return 160;
  57. }
  58. return 240;
  59. }