rtc_module.c 6.5 KB

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  1. /*
  2. * SPDX-FileCopyrightText: 2016-2023 Espressif Systems (Shanghai) CO LTD
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. */
  6. #include <stdlib.h>
  7. #include <ctype.h>
  8. #include "sdkconfig.h"
  9. #include "esp_types.h"
  10. #include "esp_log.h"
  11. #include "soc/rtc_periph.h"
  12. #include "soc/rtc.h"
  13. #include "soc/periph_defs.h"
  14. #include "freertos/FreeRTOS.h"
  15. #include "freertos/semphr.h"
  16. #include "freertos/timers.h"
  17. #include "esp_intr_alloc.h"
  18. #include "sys/lock.h"
  19. #include "esp_private/rtc_ctrl.h"
  20. #include "esp_attr.h"
  21. #ifndef NDEBUG
  22. // Enable built-in checks in queue.h in debug builds
  23. #define INVARIANTS
  24. #endif
  25. #include "sys/queue.h"
  26. #if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4// TODO: IDF-8008
  27. static const char *TAG = "rtc_module";
  28. #endif
  29. #if !CONFIG_IDF_TARGET_ESP32C6 && !CONFIG_IDF_TARGET_ESP32H2 && !CONFIG_IDF_TARGET_ESP32P4 // TODO: IDF-8008
  30. #define NOT_REGISTERED (-1)
  31. portMUX_TYPE rtc_spinlock = portMUX_INITIALIZER_UNLOCKED;
  32. // Disable the interrupt which cannot work without cache.
  33. static DRAM_ATTR uint32_t rtc_intr_cache;
  34. static DRAM_ATTR uint32_t rtc_intr_enabled;
  35. static DRAM_ATTR int rtc_isr_cpu = NOT_REGISTERED; // Unused number
  36. static void s_rtc_isr_noniram_hook(uint32_t rtc_intr_mask);
  37. static void s_rtc_isr_noniram_hook_relieve(uint32_t rtc_intr_mask);
  38. /*---------------------------------------------------------------
  39. INTERRUPT HANDLER
  40. ---------------------------------------------------------------*/
  41. typedef struct rtc_isr_handler_ {
  42. uint32_t mask;
  43. intr_handler_t handler;
  44. void* handler_arg;
  45. uint32_t flags;
  46. SLIST_ENTRY(rtc_isr_handler_) next;
  47. } rtc_isr_handler_t;
  48. static DRAM_ATTR SLIST_HEAD(rtc_isr_handler_list_, rtc_isr_handler_) s_rtc_isr_handler_list =
  49. SLIST_HEAD_INITIALIZER(s_rtc_isr_handler_list);
  50. static DRAM_ATTR portMUX_TYPE s_rtc_isr_handler_list_lock = portMUX_INITIALIZER_UNLOCKED;
  51. static intr_handle_t s_rtc_isr_handle;
  52. IRAM_ATTR static void rtc_isr(void* arg)
  53. {
  54. uint32_t status = REG_READ(RTC_CNTL_INT_ST_REG);
  55. rtc_isr_handler_t* it;
  56. portENTER_CRITICAL_ISR(&s_rtc_isr_handler_list_lock);
  57. SLIST_FOREACH(it, &s_rtc_isr_handler_list, next) {
  58. if (it->mask & status) {
  59. portEXIT_CRITICAL_ISR(&s_rtc_isr_handler_list_lock);
  60. (*it->handler)(it->handler_arg);
  61. portENTER_CRITICAL_ISR(&s_rtc_isr_handler_list_lock);
  62. }
  63. }
  64. portEXIT_CRITICAL_ISR(&s_rtc_isr_handler_list_lock);
  65. REG_WRITE(RTC_CNTL_INT_CLR_REG, status);
  66. }
  67. static esp_err_t rtc_isr_ensure_installed(void)
  68. {
  69. esp_err_t err = ESP_OK;
  70. portENTER_CRITICAL(&s_rtc_isr_handler_list_lock);
  71. if (s_rtc_isr_handle) {
  72. goto out;
  73. }
  74. REG_WRITE(RTC_CNTL_INT_ENA_REG, 0);
  75. REG_WRITE(RTC_CNTL_INT_CLR_REG, UINT32_MAX);
  76. err = esp_intr_alloc(ETS_RTC_CORE_INTR_SOURCE, ESP_INTR_FLAG_IRAM, &rtc_isr, NULL, &s_rtc_isr_handle);
  77. if (err != ESP_OK) {
  78. goto out;
  79. }
  80. rtc_isr_cpu = esp_intr_get_cpu(s_rtc_isr_handle);
  81. out:
  82. portEXIT_CRITICAL(&s_rtc_isr_handler_list_lock);
  83. return err;
  84. }
  85. #endif // !CONFIG_IDF_TARGET_ESP32C6 TODO: IDF-8008
  86. esp_err_t rtc_isr_register(intr_handler_t handler, void* handler_arg, uint32_t rtc_intr_mask, uint32_t flags)
  87. {
  88. #if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 // TODO: IDF-8008
  89. ESP_EARLY_LOGW(TAG, "rtc_isr_register() has not been implemented yet");
  90. return ESP_OK;
  91. #else
  92. esp_err_t err = rtc_isr_ensure_installed();
  93. if (err != ESP_OK) {
  94. return err;
  95. }
  96. rtc_isr_handler_t* item = heap_caps_malloc(sizeof(*item), MALLOC_CAP_INTERNAL);
  97. if (item == NULL) {
  98. return ESP_ERR_NO_MEM;
  99. }
  100. item->handler = handler;
  101. item->handler_arg = handler_arg;
  102. item->mask = rtc_intr_mask;
  103. item->flags = flags;
  104. portENTER_CRITICAL(&s_rtc_isr_handler_list_lock);
  105. if (flags & RTC_INTR_FLAG_IRAM) {
  106. s_rtc_isr_noniram_hook(rtc_intr_mask);
  107. } else {
  108. s_rtc_isr_noniram_hook_relieve(rtc_intr_mask);
  109. }
  110. SLIST_INSERT_HEAD(&s_rtc_isr_handler_list, item, next);
  111. portEXIT_CRITICAL(&s_rtc_isr_handler_list_lock);
  112. return ESP_OK;
  113. #endif
  114. }
  115. esp_err_t rtc_isr_deregister(intr_handler_t handler, void* handler_arg)
  116. {
  117. #if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 // TODO: IDF-8008
  118. ESP_EARLY_LOGW(TAG, "rtc_isr_deregister() has not been implemented yet");
  119. return ESP_OK;
  120. #else
  121. rtc_isr_handler_t* it;
  122. rtc_isr_handler_t* prev = NULL;
  123. bool found = false;
  124. portENTER_CRITICAL(&s_rtc_isr_handler_list_lock);
  125. SLIST_FOREACH(it, &s_rtc_isr_handler_list, next) {
  126. if (it->handler == handler && it->handler_arg == handler_arg) {
  127. if (it == SLIST_FIRST(&s_rtc_isr_handler_list)) {
  128. SLIST_REMOVE_HEAD(&s_rtc_isr_handler_list, next);
  129. } else {
  130. SLIST_REMOVE_AFTER(prev, next);
  131. }
  132. found = true;
  133. if (it->flags & RTC_INTR_FLAG_IRAM) {
  134. s_rtc_isr_noniram_hook_relieve(it->mask);
  135. }
  136. free(it);
  137. break;
  138. }
  139. prev = it;
  140. }
  141. portEXIT_CRITICAL(&s_rtc_isr_handler_list_lock);
  142. return found ? ESP_OK : ESP_ERR_INVALID_STATE;
  143. #endif
  144. }
  145. #if !CONFIG_IDF_TARGET_ESP32C6 && !CONFIG_IDF_TARGET_ESP32H2 && !CONFIG_IDF_TARGET_ESP32P4 // TODO: IDF-8008
  146. /**
  147. * @brief This helper function can be used to avoid the interrupt to be triggered with cache disabled.
  148. * There are lots of different signals on RTC module (i.e. sleep_wakeup, wdt, brownout_detect, etc.)
  149. * We might want some of them can be triggered with cache disabled, some are not. Therefore, this function
  150. * is created to avoid those which do not want to be triggered with cache disabled.
  151. *
  152. * @param rtc_intr_mask the mask of the rtc interrupt.
  153. */
  154. static void s_rtc_isr_noniram_hook(uint32_t rtc_intr_mask)
  155. {
  156. rtc_intr_cache |= rtc_intr_mask;
  157. }
  158. static void s_rtc_isr_noniram_hook_relieve(uint32_t rtc_intr_mask)
  159. {
  160. rtc_intr_cache &= ~rtc_intr_mask;
  161. }
  162. #endif
  163. IRAM_ATTR void rtc_isr_noniram_disable(uint32_t cpu)
  164. {
  165. #if !CONFIG_IDF_TARGET_ESP32C6 && !CONFIG_IDF_TARGET_ESP32H2 && !CONFIG_IDF_TARGET_ESP32P4 // TODO: IDF-8008
  166. if (rtc_isr_cpu == cpu) {
  167. rtc_intr_enabled |= RTCCNTL.int_ena.val;
  168. RTCCNTL.int_ena.val &= rtc_intr_cache;
  169. }
  170. #endif
  171. }
  172. IRAM_ATTR void rtc_isr_noniram_enable(uint32_t cpu)
  173. {
  174. #if !CONFIG_IDF_TARGET_ESP32C6 && !CONFIG_IDF_TARGET_ESP32H2 && !CONFIG_IDF_TARGET_ESP32P4 // TODO: IDF-8008
  175. if (rtc_isr_cpu == cpu) {
  176. RTCCNTL.int_ena.val = rtc_intr_enabled;
  177. rtc_intr_enabled = 0;
  178. }
  179. #endif
  180. }