esp_cache.c 2.2 KB

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  1. /*
  2. * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. */
  6. #include <sys/param.h>
  7. #include <inttypes.h>
  8. #include "sdkconfig.h"
  9. #include "esp_check.h"
  10. #include "esp_log.h"
  11. #include "esp_rom_caps.h"
  12. #include "soc/soc_caps.h"
  13. #include "hal/mmu_hal.h"
  14. #include "hal/cache_hal.h"
  15. #include "esp_cache.h"
  16. #include "esp_private/critical_section.h"
  17. static const char *TAG = "cache";
  18. DEFINE_CRIT_SECTION_LOCK_STATIC(s_spinlock);
  19. esp_err_t esp_cache_msync(void *addr, size_t size, int flags)
  20. {
  21. ESP_RETURN_ON_FALSE_ISR(addr, ESP_ERR_INVALID_ARG, TAG, "null pointer");
  22. ESP_RETURN_ON_FALSE_ISR(mmu_hal_check_valid_ext_vaddr_region(0, (uint32_t)addr, size, MMU_VADDR_DATA), ESP_ERR_INVALID_ARG, TAG, "invalid address");
  23. bool both_dir = (flags & ESP_CACHE_MSYNC_FLAG_DIR_C2M) && (flags & ESP_CACHE_MSYNC_FLAG_DIR_M2C);
  24. ESP_RETURN_ON_FALSE_ISR(!both_dir, ESP_ERR_INVALID_ARG, TAG, "both C2M and M2C directions are selected, you should only select one");
  25. uint32_t data_cache_line_size = cache_hal_get_cache_line_size(CACHE_TYPE_DATA);
  26. if ((flags & ESP_CACHE_MSYNC_FLAG_UNALIGNED) == 0) {
  27. bool aligned_addr = (((uint32_t)addr % data_cache_line_size) == 0) && ((size % data_cache_line_size) == 0);
  28. ESP_RETURN_ON_FALSE_ISR(aligned_addr, ESP_ERR_INVALID_ARG, TAG, "start address, end address or the size is(are) not aligned with the data cache line size (%d)B", data_cache_line_size);
  29. }
  30. uint32_t vaddr = (uint32_t)addr;
  31. if (flags & ESP_CACHE_MSYNC_FLAG_DIR_M2C) {
  32. ESP_EARLY_LOGD(TAG, "M2C DIR");
  33. esp_os_enter_critical_safe(&s_spinlock);
  34. //Add preload feature / flag here, IDF-7800
  35. cache_hal_invalidate_addr(vaddr, size);
  36. esp_os_exit_critical_safe(&s_spinlock);
  37. } else {
  38. ESP_EARLY_LOGD(TAG, "C2M DIR");
  39. #if SOC_CACHE_WRITEBACK_SUPPORTED
  40. esp_os_enter_critical_safe(&s_spinlock);
  41. cache_hal_writeback_addr(vaddr, size);
  42. esp_os_exit_critical_safe(&s_spinlock);
  43. if (flags & ESP_CACHE_MSYNC_FLAG_INVALIDATE) {
  44. esp_os_enter_critical_safe(&s_spinlock);
  45. cache_hal_invalidate_addr(vaddr, size);
  46. esp_os_exit_critical_safe(&s_spinlock);
  47. }
  48. #endif
  49. }
  50. return ESP_OK;
  51. }