ccomp_timer_test_data.c 4.5 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179
  1. #include <stdlib.h>
  2. #include <stdint.h>
  3. #include "esp_timer.h"
  4. #include "esp_log.h"
  5. #include "esp_attr.h"
  6. #include "ccomp_timer.h"
  7. #include "freertos/FreeRTOS.h"
  8. #include "freertos/task.h"
  9. #include "esp_private/esp_clk.h"
  10. #include "unity.h"
  11. #include "sdkconfig.h"
  12. /* No performance monitor in RISCV for now
  13. */
  14. #if !DISABLED_FOR_TARGETS(ESP32C3)
  15. static const char* TAG = "test_ccomp_timer";
  16. #if CONFIG_IDF_TARGET_ESP32
  17. #define CACHE_WAYS 2
  18. #define CACHE_LINE_SIZE 32
  19. #define CACHE_SIZE (1 << 15)
  20. // Only test half due to lack of memory
  21. #define TEST_SIZE (CACHE_SIZE / 2)
  22. #elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
  23. // Default cache configuration - no override specified on
  24. // test_utils config
  25. #define CACHE_WAYS 8
  26. #define CACHE_LINE_SIZE 32
  27. #define CACHE_SIZE (1 << 13)
  28. #define TEST_SIZE (CACHE_SIZE)
  29. #elif CONFIG_IDF_TARGET_ESP32C3
  30. #define CACHE_WAYS 8
  31. #define CACHE_LINE_SIZE 32
  32. #define CACHE_SIZE (1 << 14)
  33. #define TEST_SIZE (CACHE_SIZE)
  34. #endif
  35. typedef struct {
  36. uint8_t **accesses;
  37. size_t len;
  38. } ccomp_test_access_t;
  39. typedef struct {
  40. int64_t wall;
  41. int64_t ccomp;
  42. } ccomp_test_time_t;
  43. #if CONFIG_ESP32_SPIRAM_SUPPORT
  44. static uint8_t *flash_mem;
  45. #else
  46. static const uint8_t flash_mem[2 * CACHE_SIZE] = {0};
  47. #endif
  48. static IRAM_ATTR void perform_accesses(ccomp_test_access_t *access)
  49. {
  50. volatile int a = 0;
  51. for (int i = 0; i < access->len; i++) {
  52. a += (int)(*(access->accesses[i]));
  53. }
  54. }
  55. static void prepare_cache(const uint8_t *to_cache)
  56. {
  57. volatile int a = 0;
  58. for (int i = 0; i < CACHE_SIZE; i++) {
  59. a += to_cache[i];
  60. }
  61. }
  62. static void prepare_access_pattern(int hit_rate, const uint8_t *cached, ccomp_test_access_t *out)
  63. {
  64. assert(hit_rate <= 100);
  65. assert(hit_rate >= 0);
  66. int misses = (100 - hit_rate) * CACHE_LINE_SIZE;
  67. int hits = hit_rate * CACHE_LINE_SIZE;
  68. uint8_t **accesses = calloc(TEST_SIZE, sizeof(uint8_t *));
  69. for (int i = 0, h = 0, i_h = 1, m = -1, i_m = 0; i < TEST_SIZE; i++, h += i_h, m += i_m) {
  70. if (i_m) {
  71. accesses[i] = (uint8_t*) (cached + CACHE_SIZE + i);
  72. }
  73. else {
  74. accesses[i] = (uint8_t*) (cached + i);
  75. }
  76. if (h >= hits) {
  77. h = -1;
  78. i_h = 0;
  79. m = 0;
  80. i_m = 1;
  81. }
  82. if (m >= misses) {
  83. m = -1;
  84. i_m = 0;
  85. h = 0;
  86. i_h = 1;
  87. }
  88. }
  89. out->accesses = accesses;
  90. out->len = TEST_SIZE;
  91. }
  92. static ccomp_test_time_t perform_test_at_hit_rate(int hit_rate, const uint8_t *mem)
  93. {
  94. ccomp_test_access_t access;
  95. prepare_access_pattern(hit_rate, mem, &access);
  96. prepare_cache(mem);
  97. int64_t start = esp_timer_get_time();
  98. ccomp_timer_start();
  99. perform_accesses(&access);
  100. ccomp_test_time_t t = {
  101. .ccomp = ccomp_timer_stop(),
  102. .wall = esp_timer_get_time() - start
  103. };
  104. free(access.accesses);
  105. return t;
  106. }
  107. static ccomp_test_time_t ccomp_test_ref_time(void)
  108. {
  109. #if CONFIG_ESP32_SPIRAM_SUPPORT
  110. uint8_t *mem = heap_caps_malloc(2 * CACHE_SIZE, MALLOC_CAP_INTERNAL | MALLOC_CAP_DEFAULT);
  111. #else
  112. uint8_t *mem = heap_caps_malloc(sizeof(flash_mem), MALLOC_CAP_INTERNAL | MALLOC_CAP_DEFAULT);
  113. #endif
  114. ccomp_test_time_t t = perform_test_at_hit_rate(0, mem);
  115. free(mem);
  116. return t;
  117. }
  118. TEST_CASE("data cache hit rate sweep", "[test_utils][ccomp_timer]")
  119. {
  120. ccomp_test_time_t t_ref;
  121. ccomp_test_time_t t_hr;
  122. #if CONFIG_ESP32_SPIRAM_SUPPORT
  123. flash_mem = heap_caps_malloc(2 * CACHE_SIZE, MALLOC_CAP_8BIT | MALLOC_CAP_SPIRAM);
  124. #endif
  125. // Perform accesses on RAM. The time recorded here serves as
  126. // reference.
  127. t_ref = ccomp_test_ref_time();
  128. ESP_LOGI(TAG, "Reference Time(us): %lld", (long long)t_ref.ccomp);
  129. // Measure time at particular hit rates
  130. for (int i = 0; i <= 100; i += 5)
  131. {
  132. t_hr = perform_test_at_hit_rate(i, flash_mem);
  133. float error = (abs(t_ref.ccomp - t_hr.ccomp) / (float)t_ref.ccomp) * 100.0f;
  134. ESP_LOGI(TAG, "Hit Rate(%%): %d Wall Time(us): %lld Compensated Time(us): %lld Error(%%): %f", i, (long long)t_hr.wall, (long long)t_hr.ccomp, error);
  135. // Check if the measured time is at least within some percent of the
  136. // reference.
  137. TEST_ASSERT(error <= 5.0f);
  138. }
  139. #if CONFIG_ESP32_SPIRAM_SUPPORT
  140. free(flash_mem);
  141. #endif
  142. }
  143. #endif // !DISABLED_FOR_TARGETS(ESP32C3)