cpu_start.c 9.1 KB

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  1. // Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
  2. //
  3. // Licensed under the Apache License, Version 2.0 (the "License");
  4. // you may not use this file except in compliance with the License.
  5. // You may obtain a copy of the License at
  6. //
  7. // http://www.apache.org/licenses/LICENSE-2.0
  8. //
  9. // Unless required by applicable law or agreed to in writing, software
  10. // distributed under the License is distributed on an "AS IS" BASIS,
  11. // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  12. // See the License for the specific language governing permissions and
  13. // limitations under the License.
  14. #include <stdint.h>
  15. #include <string.h>
  16. #include "esp_attr.h"
  17. #include "esp_err.h"
  18. #include "rom/ets_sys.h"
  19. #include "rom/uart.h"
  20. #include "rom/rtc.h"
  21. #include "rom/cache.h"
  22. #include "soc/cpu.h"
  23. #include "soc/rtc.h"
  24. #include "soc/dport_reg.h"
  25. #include "soc/io_mux_reg.h"
  26. #include "soc/rtc_cntl_reg.h"
  27. #include "soc/timer_group_reg.h"
  28. #include "driver/rtc_io.h"
  29. #include "freertos/FreeRTOS.h"
  30. #include "freertos/task.h"
  31. #include "freertos/semphr.h"
  32. #include "freertos/queue.h"
  33. #include "freertos/portmacro.h"
  34. #include "tcpip_adapter.h"
  35. #include "esp_heap_alloc_caps.h"
  36. #include "sdkconfig.h"
  37. #include "esp_system.h"
  38. #include "esp_spi_flash.h"
  39. #include "nvs_flash.h"
  40. #include "esp_event.h"
  41. #include "esp_spi_flash.h"
  42. #include "esp_ipc.h"
  43. #include "esp_crosscore_int.h"
  44. #include "esp_dport_access.h"
  45. #include "esp_log.h"
  46. #include "esp_vfs_dev.h"
  47. #include "esp_newlib.h"
  48. #include "esp_brownout.h"
  49. #include "esp_int_wdt.h"
  50. #include "esp_task_wdt.h"
  51. #include "esp_phy_init.h"
  52. #include "esp_cache_err_int.h"
  53. #include "esp_coexist.h"
  54. #include "esp_panic.h"
  55. #include "esp_core_dump.h"
  56. #include "esp_app_trace.h"
  57. #include "esp_clk.h"
  58. #include "trax.h"
  59. #define STRINGIFY(s) STRINGIFY2(s)
  60. #define STRINGIFY2(s) #s
  61. void start_cpu0(void) __attribute__((weak, alias("start_cpu0_default")));
  62. void start_cpu0_default(void) IRAM_ATTR;
  63. #if !CONFIG_FREERTOS_UNICORE
  64. static void IRAM_ATTR call_start_cpu1();
  65. void start_cpu1(void) __attribute__((weak, alias("start_cpu1_default")));
  66. void start_cpu1_default(void) IRAM_ATTR;
  67. static bool app_cpu_started = false;
  68. #endif //!CONFIG_FREERTOS_UNICORE
  69. static void do_global_ctors(void);
  70. static void main_task(void* args);
  71. extern void app_main(void);
  72. extern int _bss_start;
  73. extern int _bss_end;
  74. extern int _rtc_bss_start;
  75. extern int _rtc_bss_end;
  76. extern int _init_start;
  77. extern void (*__init_array_start)(void);
  78. extern void (*__init_array_end)(void);
  79. extern volatile int port_xSchedulerRunning[2];
  80. static const char* TAG = "cpu_start";
  81. /*
  82. * We arrive here after the bootloader finished loading the program from flash. The hardware is mostly uninitialized,
  83. * and the app CPU is in reset. We do have a stack, so we can do the initialization in C.
  84. */
  85. void IRAM_ATTR call_start_cpu0()
  86. {
  87. #if CONFIG_FREERTOS_UNICORE
  88. RESET_REASON rst_reas[1];
  89. #else
  90. RESET_REASON rst_reas[2];
  91. #endif
  92. cpu_configure_region_protection();
  93. //Move exception vectors to IRAM
  94. asm volatile (\
  95. "wsr %0, vecbase\n" \
  96. ::"r"(&_init_start));
  97. rst_reas[0] = rtc_get_reset_reason(0);
  98. #if !CONFIG_FREERTOS_UNICORE
  99. rst_reas[1] = rtc_get_reset_reason(1);
  100. #endif
  101. // from panic handler we can be reset by RWDT or TG0WDT
  102. if (rst_reas[0] == RTCWDT_SYS_RESET || rst_reas[0] == TG0WDT_SYS_RESET
  103. #if !CONFIG_FREERTOS_UNICORE
  104. || rst_reas[1] == RTCWDT_SYS_RESET || rst_reas[1] == TG0WDT_SYS_RESET
  105. #endif
  106. ) {
  107. esp_panic_wdt_stop();
  108. }
  109. //Clear BSS. Please do not attempt to do any complex stuff (like early logging) before this.
  110. memset(&_bss_start, 0, (&_bss_end - &_bss_start) * sizeof(_bss_start));
  111. /* Unless waking from deep sleep (implying RTC memory is intact), clear RTC bss */
  112. if (rst_reas[0] != DEEPSLEEP_RESET) {
  113. memset(&_rtc_bss_start, 0, (&_rtc_bss_end - &_rtc_bss_start) * sizeof(_rtc_bss_start));
  114. }
  115. ESP_EARLY_LOGI(TAG, "Pro cpu up.");
  116. #if !CONFIG_FREERTOS_UNICORE
  117. ESP_EARLY_LOGI(TAG, "Starting app cpu, entry point is %p", call_start_cpu1);
  118. //Flush and enable icache for APP CPU
  119. Cache_Flush(1);
  120. Cache_Read_Enable(1);
  121. esp_cpu_unstall(1);
  122. //Enable clock gating and reset the app cpu.
  123. DPORT_SET_PERI_REG_MASK(DPORT_APPCPU_CTRL_B_REG, DPORT_APPCPU_CLKGATE_EN);
  124. DPORT_CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_C_REG, DPORT_APPCPU_RUNSTALL);
  125. DPORT_SET_PERI_REG_MASK(DPORT_APPCPU_CTRL_A_REG, DPORT_APPCPU_RESETTING);
  126. DPORT_CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_A_REG, DPORT_APPCPU_RESETTING);
  127. ets_set_appcpu_boot_addr((uint32_t)call_start_cpu1);
  128. while (!app_cpu_started) {
  129. ets_delay_us(100);
  130. }
  131. #else
  132. ESP_EARLY_LOGI(TAG, "Single core mode");
  133. DPORT_CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_B_REG, DPORT_APPCPU_CLKGATE_EN);
  134. #endif
  135. /* Initialize heap allocator. WARNING: This *needs* to happen *after* the app cpu has booted.
  136. If the heap allocator is initialized first, it will put free memory linked list items into
  137. memory also used by the ROM. Starting the app cpu will let its ROM initialize that memory,
  138. corrupting those linked lists. Initializing the allocator *after* the app cpu has booted
  139. works around this problem. */
  140. heap_alloc_caps_init();
  141. ESP_EARLY_LOGI(TAG, "Pro cpu start user code");
  142. start_cpu0();
  143. }
  144. #if !CONFIG_FREERTOS_UNICORE
  145. void IRAM_ATTR call_start_cpu1()
  146. {
  147. asm volatile (\
  148. "wsr %0, vecbase\n" \
  149. ::"r"(&_init_start));
  150. ets_set_appcpu_boot_addr(0);
  151. cpu_configure_region_protection();
  152. #if CONFIG_CONSOLE_UART_NONE
  153. ets_install_putc1(NULL);
  154. ets_install_putc2(NULL);
  155. #else // CONFIG_CONSOLE_UART_NONE
  156. uartAttach();
  157. ets_install_uart_printf();
  158. uart_tx_switch(CONFIG_CONSOLE_UART_NUM);
  159. #endif
  160. ESP_EARLY_LOGI(TAG, "App cpu up.");
  161. app_cpu_started = 1;
  162. start_cpu1();
  163. }
  164. #endif //!CONFIG_FREERTOS_UNICORE
  165. void start_cpu0_default(void)
  166. {
  167. esp_setup_syscall_table();
  168. //Enable trace memory and immediately start trace.
  169. #if CONFIG_ESP32_TRAX
  170. #if CONFIG_ESP32_TRAX_TWOBANKS
  171. trax_enable(TRAX_ENA_PRO_APP);
  172. #else
  173. trax_enable(TRAX_ENA_PRO);
  174. #endif
  175. trax_start_trace(TRAX_DOWNCOUNT_WORDS);
  176. #endif
  177. esp_clk_init();
  178. #ifndef CONFIG_CONSOLE_UART_NONE
  179. uart_div_modify(CONFIG_CONSOLE_UART_NUM, (rtc_clk_apb_freq_get() << 4) / CONFIG_CONSOLE_UART_BAUDRATE);
  180. #endif
  181. #if CONFIG_BROWNOUT_DET
  182. esp_brownout_init();
  183. #endif
  184. rtc_gpio_force_hold_dis_all();
  185. esp_setup_time_syscalls();
  186. esp_vfs_dev_uart_register();
  187. esp_reent_init(_GLOBAL_REENT);
  188. #ifndef CONFIG_CONSOLE_UART_NONE
  189. const char* default_uart_dev = "/dev/uart/" STRINGIFY(CONFIG_CONSOLE_UART_NUM);
  190. _GLOBAL_REENT->_stdin = fopen(default_uart_dev, "r");
  191. _GLOBAL_REENT->_stdout = fopen(default_uart_dev, "w");
  192. _GLOBAL_REENT->_stderr = fopen(default_uart_dev, "w");
  193. #else
  194. _GLOBAL_REENT->_stdin = (FILE*) &__sf_fake_stdin;
  195. _GLOBAL_REENT->_stdout = (FILE*) &__sf_fake_stdout;
  196. _GLOBAL_REENT->_stderr = (FILE*) &__sf_fake_stderr;
  197. #endif
  198. #if CONFIG_ESP32_APPTRACE_ENABLE
  199. esp_err_t err = esp_apptrace_init();
  200. if (err != ESP_OK) {
  201. ESP_EARLY_LOGE(TAG, "Failed to init apptrace module on CPU0 (%d)!", err);
  202. }
  203. #endif
  204. do_global_ctors();
  205. #if CONFIG_INT_WDT
  206. esp_int_wdt_init();
  207. #endif
  208. #if CONFIG_TASK_WDT
  209. esp_task_wdt_init();
  210. #endif
  211. esp_cache_err_int_init();
  212. esp_crosscore_int_init();
  213. esp_ipc_init();
  214. #ifndef CONFIG_FREERTOS_UNICORE
  215. esp_dport_access_int_init();
  216. #endif
  217. spi_flash_init();
  218. /* init default OS-aware flash access critical section */
  219. spi_flash_guard_set(&g_flash_guard_default_ops);
  220. #if CONFIG_ESP32_ENABLE_COREDUMP
  221. esp_core_dump_init();
  222. #endif
  223. xTaskCreatePinnedToCore(&main_task, "main",
  224. ESP_TASK_MAIN_STACK, NULL,
  225. ESP_TASK_MAIN_PRIO, NULL, 0);
  226. ESP_LOGI(TAG, "Starting scheduler on PRO CPU.");
  227. vTaskStartScheduler();
  228. }
  229. #if !CONFIG_FREERTOS_UNICORE
  230. void start_cpu1_default(void)
  231. {
  232. #if CONFIG_ESP32_TRAX_TWOBANKS
  233. trax_start_trace(TRAX_DOWNCOUNT_WORDS);
  234. #endif
  235. #if CONFIG_ESP32_APPTRACE_ENABLE
  236. esp_err_t err = esp_apptrace_init();
  237. if (err != ESP_OK) {
  238. ESP_EARLY_LOGE(TAG, "Failed to init apptrace module on CPU1 (%d)!", err);
  239. }
  240. #endif
  241. // Wait for FreeRTOS initialization to finish on PRO CPU
  242. while (port_xSchedulerRunning[0] == 0) {
  243. ;
  244. }
  245. //Take care putting stuff here: if asked, FreeRTOS will happily tell you the scheduler
  246. //has started, but it isn't active *on this CPU* yet.
  247. esp_cache_err_int_init();
  248. esp_crosscore_int_init();
  249. esp_dport_access_int_init();
  250. ESP_EARLY_LOGI(TAG, "Starting scheduler on APP CPU.");
  251. xPortStartScheduler();
  252. }
  253. #endif //!CONFIG_FREERTOS_UNICORE
  254. static void do_global_ctors(void)
  255. {
  256. void (**p)(void);
  257. for (p = &__init_array_end - 1; p >= &__init_array_start; --p) {
  258. (*p)();
  259. }
  260. }
  261. static void main_task(void* args)
  262. {
  263. // Now that the application is about to start, disable boot watchdogs
  264. REG_CLR_BIT(TIMG_WDTCONFIG0_REG(0), TIMG_WDT_FLASHBOOT_MOD_EN_S);
  265. REG_CLR_BIT(RTC_CNTL_WDTCONFIG0_REG, RTC_CNTL_WDT_FLASHBOOT_MOD_EN);
  266. //Enable allocation in region where the startup stacks were located.
  267. heap_alloc_enable_nonos_stack_tag();
  268. app_main();
  269. vTaskDelete(NULL);
  270. }