cpu_start.c 8.2 KB

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  1. // Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
  2. //
  3. // Licensed under the Apache License, Version 2.0 (the "License");
  4. // you may not use this file except in compliance with the License.
  5. // You may obtain a copy of the License at
  6. // http://www.apache.org/licenses/LICENSE-2.0
  7. //
  8. // Unless required by applicable law or agreed to in writing, software
  9. // distributed under the License is distributed on an "AS IS" BASIS,
  10. // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  11. // See the License for the specific language governing permissions and
  12. // limitations under the License.
  13. #include <stdint.h>
  14. #include <string.h>
  15. #include "esp_attr.h"
  16. #include "esp_err.h"
  17. #include "rom/ets_sys.h"
  18. #include "rom/uart.h"
  19. #include "rom/rtc.h"
  20. #include "rom/cache.h"
  21. #include "soc/cpu.h"
  22. #include "soc/dport_reg.h"
  23. #include "soc/io_mux_reg.h"
  24. #include "soc/rtc_cntl_reg.h"
  25. #include "freertos/FreeRTOS.h"
  26. #include "freertos/task.h"
  27. #include "freertos/semphr.h"
  28. #include "freertos/queue.h"
  29. #include "freertos/portmacro.h"
  30. #include "tcpip_adapter.h"
  31. #include "heap_alloc_caps.h"
  32. #include "sdkconfig.h"
  33. #include "esp_system.h"
  34. #include "esp_spi_flash.h"
  35. #include "nvs_flash.h"
  36. #include "esp_event.h"
  37. #include "esp_spi_flash.h"
  38. #include "esp_ipc.h"
  39. #include "esp_crosscore_int.h"
  40. #include "esp_log.h"
  41. #include "esp_vfs_dev.h"
  42. #include "esp_newlib.h"
  43. #include "esp_brownout.h"
  44. #include "esp_int_wdt.h"
  45. #include "esp_task_wdt.h"
  46. #include "esp_phy_init.h"
  47. #include "esp_coexist.h"
  48. #include "trax.h"
  49. #define STRINGIFY(s) STRINGIFY2(s)
  50. #define STRINGIFY2(s) #s
  51. void start_cpu0(void) __attribute__((weak, alias("start_cpu0_default")));
  52. void start_cpu0_default(void) IRAM_ATTR;
  53. #if !CONFIG_FREERTOS_UNICORE
  54. static void IRAM_ATTR call_start_cpu1();
  55. void start_cpu1(void) __attribute__((weak, alias("start_cpu1_default")));
  56. void start_cpu1_default(void) IRAM_ATTR;
  57. static bool app_cpu_started = false;
  58. #endif //!CONFIG_FREERTOS_UNICORE
  59. static void do_global_ctors(void);
  60. static void do_phy_init();
  61. static void main_task(void* args);
  62. extern void app_main(void);
  63. extern int _bss_start;
  64. extern int _bss_end;
  65. extern int _rtc_bss_start;
  66. extern int _rtc_bss_end;
  67. extern int _init_start;
  68. extern void (*__init_array_start)(void);
  69. extern void (*__init_array_end)(void);
  70. extern volatile int port_xSchedulerRunning[2];
  71. static const char* TAG = "cpu_start";
  72. /*
  73. * We arrive here after the bootloader finished loading the program from flash. The hardware is mostly uninitialized,
  74. * and the app CPU is in reset. We do have a stack, so we can do the initialization in C.
  75. */
  76. void IRAM_ATTR call_start_cpu0()
  77. {
  78. //Kill wdt
  79. REG_CLR_BIT(RTC_CNTL_WDTCONFIG0_REG, RTC_CNTL_WDT_FLASHBOOT_MOD_EN);
  80. REG_CLR_BIT(0x6001f048, BIT(14)); //DR_REG_BB_BASE+48
  81. cpu_configure_region_protection();
  82. //Move exception vectors to IRAM
  83. asm volatile (\
  84. "wsr %0, vecbase\n" \
  85. ::"r"(&_init_start));
  86. memset(&_bss_start, 0, (&_bss_end - &_bss_start) * sizeof(_bss_start));
  87. /* Unless waking from deep sleep (implying RTC memory is intact), clear RTC bss */
  88. if (rtc_get_reset_reason(0) != DEEPSLEEP_RESET) {
  89. memset(&_rtc_bss_start, 0, (&_rtc_bss_end - &_rtc_bss_start) * sizeof(_rtc_bss_start));
  90. }
  91. // Initialize heap allocator
  92. heap_alloc_caps_init();
  93. ESP_EARLY_LOGI(TAG, "Pro cpu up.");
  94. #if !CONFIG_FREERTOS_UNICORE
  95. ESP_EARLY_LOGI(TAG, "Starting app cpu, entry point is %p", call_start_cpu1);
  96. //Flush and enable icache for APP CPU
  97. Cache_Flush(1);
  98. Cache_Read_Enable(1);
  99. esp_cpu_unstall(1);
  100. //Enable clock gating and reset the app cpu.
  101. SET_PERI_REG_MASK(DPORT_APPCPU_CTRL_B_REG, DPORT_APPCPU_CLKGATE_EN);
  102. CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_C_REG, DPORT_APPCPU_RUNSTALL);
  103. SET_PERI_REG_MASK(DPORT_APPCPU_CTRL_A_REG, DPORT_APPCPU_RESETTING);
  104. CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_A_REG, DPORT_APPCPU_RESETTING);
  105. ets_set_appcpu_boot_addr((uint32_t)call_start_cpu1);
  106. while (!app_cpu_started) {
  107. ets_delay_us(100);
  108. }
  109. #else
  110. ESP_EARLY_LOGI(TAG, "Single core mode");
  111. CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_B_REG, DPORT_APPCPU_CLKGATE_EN);
  112. #endif
  113. ESP_EARLY_LOGI(TAG, "Pro cpu start user code");
  114. start_cpu0();
  115. }
  116. #if !CONFIG_FREERTOS_UNICORE
  117. void IRAM_ATTR call_start_cpu1()
  118. {
  119. asm volatile (\
  120. "wsr %0, vecbase\n" \
  121. ::"r"(&_init_start));
  122. cpu_configure_region_protection();
  123. #if CONFIG_CONSOLE_UART_NONE
  124. ets_install_putc1(NULL);
  125. ets_install_putc2(NULL);
  126. #else // CONFIG_CONSOLE_UART_NONE
  127. uartAttach();
  128. ets_install_uart_printf();
  129. uart_tx_switch(CONFIG_CONSOLE_UART_NUM);
  130. #endif
  131. ESP_EARLY_LOGI(TAG, "App cpu up.");
  132. app_cpu_started = 1;
  133. start_cpu1();
  134. }
  135. #endif //!CONFIG_FREERTOS_UNICORE
  136. void start_cpu0_default(void)
  137. {
  138. esp_setup_syscall_table();
  139. //Enable trace memory and immediately start trace.
  140. #if CONFIG_MEMMAP_TRACEMEM
  141. #if CONFIG_MEMMAP_TRACEMEM_TWOBANKS
  142. trax_enable(TRAX_ENA_PRO_APP);
  143. #else
  144. trax_enable(TRAX_ENA_PRO);
  145. #endif
  146. trax_start_trace(TRAX_DOWNCOUNT_WORDS);
  147. #endif
  148. esp_set_cpu_freq(); // set CPU frequency configured in menuconfig
  149. uart_div_modify(CONFIG_CONSOLE_UART_NUM, (APB_CLK_FREQ << 4) / CONFIG_CONSOLE_UART_BAUDRATE);
  150. #if CONFIG_BROWNOUT_DET
  151. esp_brownout_init();
  152. #endif
  153. #if CONFIG_INT_WDT
  154. esp_int_wdt_init();
  155. #endif
  156. #if CONFIG_TASK_WDT
  157. esp_task_wdt_init();
  158. #endif
  159. esp_setup_time_syscalls();
  160. esp_vfs_dev_uart_register();
  161. esp_reent_init(_GLOBAL_REENT);
  162. #ifndef CONFIG_CONSOLE_UART_NONE
  163. const char* default_uart_dev = "/dev/uart/" STRINGIFY(CONFIG_CONSOLE_UART_NUM);
  164. _GLOBAL_REENT->_stdin = fopen(default_uart_dev, "r");
  165. _GLOBAL_REENT->_stdout = fopen(default_uart_dev, "w");
  166. _GLOBAL_REENT->_stderr = fopen(default_uart_dev, "w");
  167. #else
  168. _GLOBAL_REENT->_stdin = (FILE*) &__sf_fake_stdin;
  169. _GLOBAL_REENT->_stdout = (FILE*) &__sf_fake_stdout;
  170. _GLOBAL_REENT->_stderr = (FILE*) &__sf_fake_stderr;
  171. #endif
  172. do_global_ctors();
  173. #if !CONFIG_FREERTOS_UNICORE
  174. esp_crosscore_int_init();
  175. #endif
  176. esp_ipc_init();
  177. spi_flash_init();
  178. #if CONFIG_ESP32_PHY_AUTO_INIT
  179. nvs_flash_init();
  180. do_phy_init();
  181. #endif
  182. #if CONFIG_SW_COEXIST_ENABLE
  183. if (coex_init() == ESP_OK) {
  184. coexist_set_enable(true);
  185. }
  186. #endif
  187. xTaskCreatePinnedToCore(&main_task, "main",
  188. ESP_TASK_MAIN_STACK, NULL,
  189. ESP_TASK_MAIN_PRIO, NULL, 0);
  190. ESP_LOGI(TAG, "Starting scheduler on PRO CPU.");
  191. vTaskStartScheduler();
  192. }
  193. #if !CONFIG_FREERTOS_UNICORE
  194. void start_cpu1_default(void)
  195. {
  196. #if CONFIG_MEMMAP_TRACEMEM_TWOBANKS
  197. trax_start_trace(TRAX_DOWNCOUNT_WORDS);
  198. #endif
  199. // Wait for FreeRTOS initialization to finish on PRO CPU
  200. while (port_xSchedulerRunning[0] == 0) {
  201. ;
  202. }
  203. esp_crosscore_int_init();
  204. ESP_LOGI(TAG, "Starting scheduler on APP CPU.");
  205. xPortStartScheduler();
  206. }
  207. #endif //!CONFIG_FREERTOS_UNICORE
  208. static void do_global_ctors(void)
  209. {
  210. void (**p)(void);
  211. for (p = &__init_array_end - 1; p >= &__init_array_start; --p) {
  212. (*p)();
  213. }
  214. }
  215. static void main_task(void* args)
  216. {
  217. app_main();
  218. vTaskDelete(NULL);
  219. }
  220. static void do_phy_init()
  221. {
  222. esp_phy_calibration_mode_t calibration_mode = PHY_RF_CAL_PARTIAL;
  223. if (rtc_get_reset_reason(0) == DEEPSLEEP_RESET) {
  224. calibration_mode = PHY_RF_CAL_NONE;
  225. }
  226. const esp_phy_init_data_t* init_data = esp_phy_get_init_data();
  227. if (init_data == NULL) {
  228. ESP_LOGE(TAG, "failed to obtain PHY init data");
  229. abort();
  230. }
  231. esp_phy_calibration_data_t* cal_data =
  232. (esp_phy_calibration_data_t*) calloc(sizeof(esp_phy_calibration_data_t), 1);
  233. if (cal_data == NULL) {
  234. ESP_LOGE(TAG, "failed to allocate memory for RF calibration data");
  235. abort();
  236. }
  237. esp_err_t err = esp_phy_load_cal_data_from_nvs(cal_data);
  238. if (err != ESP_OK) {
  239. ESP_LOGW(TAG, "failed to load RF calibration data, falling back to full calibration");
  240. calibration_mode = PHY_RF_CAL_FULL;
  241. }
  242. esp_phy_init(init_data, calibration_mode, cal_data);
  243. if (calibration_mode != PHY_RF_CAL_NONE) {
  244. err = esp_phy_store_cal_data_to_nvs(cal_data);
  245. } else {
  246. err = ESP_OK;
  247. }
  248. esp_phy_release_init_data(init_data);
  249. free(cal_data); // PHY maintains a copy of calibration data, so we can free this
  250. }