emac_dev.c 3.6 KB

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  1. // Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
  2. //
  3. // Licensed under the Apache License, Version 2.0 (the "License");
  4. // you may not use this file except in compliance with the License.
  5. // You may obtain a copy of the License at
  6. // http://www.apache.org/licenses/LICENSE-2.0
  7. //
  8. // Unless required by applicable law or agreed to in writing, software
  9. // distributed under the License is distributed on an "AS IS" BASIS,
  10. // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  11. // See the License for the specific language governing permissions and
  12. // limitations under the License.
  13. #include <stdio.h>
  14. #include <string.h>
  15. #include "rom/ets_sys.h"
  16. #include "rom/gpio.h"
  17. #include "soc/dport_reg.h"
  18. #include "soc/io_mux_reg.h"
  19. #include "soc/rtc_cntl_reg.h"
  20. #include "soc/gpio_reg.h"
  21. #include "soc/gpio_sig_map.h"
  22. #include "soc/emac_reg_v2.h"
  23. #include "soc/emac_ex_reg.h"
  24. #include "esp_log.h"
  25. #include "driver/gpio.h"
  26. #include "sdkconfig.h"
  27. #include "emac_common.h"
  28. static const char *TAG = "emac";
  29. void emac_poll_tx_cmd(void)
  30. {
  31. //write any to wake up dma
  32. REG_WRITE(EMAC_DMATXPOLLDEMAND_REG, 1);
  33. }
  34. void emac_poll_rx_cmd(void)
  35. {
  36. //write any to wake up dma
  37. REG_WRITE(EMAC_DMARXPOLLDEMAND_REG, 1);
  38. }
  39. void emac_enable_dma_tx(void)
  40. {
  41. REG_SET_BIT(EMAC_DMAOPERATION_MODE_REG, EMAC_START_STOP_TRANSMISSION_COMMAND);
  42. }
  43. void emac_enable_dma_rx(void)
  44. {
  45. REG_SET_BIT(EMAC_DMAOPERATION_MODE_REG, EMAC_START_STOP_RECEIVE);
  46. }
  47. void emac_disable_dma_tx(void)
  48. {
  49. REG_CLR_BIT(EMAC_DMAOPERATION_MODE_REG, EMAC_OPERATE_SECOND_FRAME);
  50. }
  51. void emac_disable_dma_rx(void)
  52. {
  53. REG_CLR_BIT(EMAC_DMAOPERATION_MODE_REG, EMAC_START_STOP_RECEIVE);
  54. }
  55. uint32_t emac_read_tx_cur_reg(void)
  56. {
  57. return REG_READ(EMAC_DMATXCURRDESC_REG);
  58. }
  59. uint32_t emac_read_rx_cur_reg(void)
  60. {
  61. return REG_READ(EMAC_DMARXCURRDESC_REG);
  62. }
  63. uint32_t emac_read_mac_version(void)
  64. {
  65. uint32_t data = 0;
  66. data = REG_READ(EMAC_GMACVERSION_REG);
  67. return data;
  68. }
  69. void emac_reset(void)
  70. {
  71. REG_SET_BIT(EMAC_DMABUSMODE_REG, EMAC_SW_RST);
  72. while (REG_GET_BIT(EMAC_DMABUSMODE_REG, EMAC_SW_RST) == 1) {
  73. //nothing to do ,if stop here,maybe emac have not clk input.
  74. ESP_LOGI(TAG, "emac reseting ....");
  75. }
  76. ESP_LOGI(TAG, "emac reset done");
  77. }
  78. void emac_enable_clk(bool enable)
  79. {
  80. if (enable == true) {
  81. REG_SET_BIT(EMAC_CLK_EN_REG, EMAC_CLK_EN);
  82. } else {
  83. REG_CLR_BIT(EMAC_CLK_EN_REG, EMAC_CLK_EN);
  84. }
  85. }
  86. void emac_set_clk_mii(void)
  87. {
  88. //select ex clock source
  89. REG_SET_BIT(EMAC_EX_CLK_CTRL_REG, EMAC_EX_EXT_OSC_EN);
  90. //ex clk enable
  91. REG_SET_BIT(EMAC_EX_OSCCLK_CONF_REG, EMAC_EX_OSC_CLK_SEL);
  92. //set mii mode rx/tx clk enable
  93. REG_SET_BIT(EMAC_EX_CLK_CTRL_REG, EMAC_EX_MII_CLK_RX_EN);
  94. REG_SET_BIT(EMAC_EX_CLK_CTRL_REG, EMAC_EX_MII_CLK_TX_EN);
  95. }
  96. void emac_dma_init(void)
  97. {
  98. REG_SET_BIT(EMAC_DMAOPERATION_MODE_REG, EMAC_FORWARD_UNDERSIZED_GOOD_FRAMES);
  99. REG_SET_BIT(EMAC_DMAOPERATION_MODE_REG, EMAC_OPERATE_SECOND_FRAME);
  100. REG_SET_FIELD(EMAC_DMABUSMODE_REG, EMAC_PROG_BURST_LEN, 4);
  101. }
  102. void emac_mac_init(void)
  103. {
  104. REG_SET_BIT(EMAC_GMACCONFIG_REG, EMAC_GMACRX);
  105. REG_SET_BIT(EMAC_GMACCONFIG_REG, EMAC_GMACTX);
  106. REG_SET_BIT(EMAC_GMACCONFIG_REG, EMAC_GMACDUPLEX);
  107. REG_SET_BIT(EMAC_GMACCONFIG_REG, EMAC_GMACMIIGMII);
  108. REG_SET_BIT(EMAC_GMACCONFIG_REG, EMAC_GMACFESPEED);
  109. REG_SET_BIT(EMAC_GMACFRAMEFILTER_REG, EMAC_PROMISCUOUS_MODE);
  110. }
  111. void emac_set_clk_rmii(void)
  112. {
  113. //select ex clock source
  114. REG_SET_BIT(EMAC_EX_CLK_CTRL_REG, EMAC_EX_EXT_OSC_EN);
  115. //ex clk enable
  116. REG_SET_BIT(EMAC_EX_OSCCLK_CONF_REG, EMAC_EX_OSC_CLK_SEL);
  117. }