cpu_start.c 8.5 KB

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  1. // Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
  2. //
  3. // Licensed under the Apache License, Version 2.0 (the "License");
  4. // you may not use this file except in compliance with the License.
  5. // You may obtain a copy of the License at
  6. // http://www.apache.org/licenses/LICENSE-2.0
  7. //
  8. // Unless required by applicable law or agreed to in writing, software
  9. // distributed under the License is distributed on an "AS IS" BASIS,
  10. // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  11. // See the License for the specific language governing permissions and
  12. // limitations under the License.
  13. #include <stdint.h>
  14. #include <string.h>
  15. #include "esp_attr.h"
  16. #include "esp_err.h"
  17. #include "rom/ets_sys.h"
  18. #include "rom/uart.h"
  19. #include "rom/rtc.h"
  20. #include "rom/cache.h"
  21. #include "soc/cpu.h"
  22. #include "soc/dport_reg.h"
  23. #include "soc/io_mux_reg.h"
  24. #include "soc/rtc_cntl_reg.h"
  25. #include "soc/timer_group_reg.h"
  26. #include "driver/rtc_io.h"
  27. #include "freertos/FreeRTOS.h"
  28. #include "freertos/task.h"
  29. #include "freertos/semphr.h"
  30. #include "freertos/queue.h"
  31. #include "freertos/portmacro.h"
  32. #include "tcpip_adapter.h"
  33. #include "heap_alloc_caps.h"
  34. #include "sdkconfig.h"
  35. #include "esp_system.h"
  36. #include "esp_spi_flash.h"
  37. #include "nvs_flash.h"
  38. #include "esp_event.h"
  39. #include "esp_spi_flash.h"
  40. #include "esp_ipc.h"
  41. #include "esp_crosscore_int.h"
  42. #include "esp_log.h"
  43. #include "esp_vfs_dev.h"
  44. #include "esp_newlib.h"
  45. #include "esp_brownout.h"
  46. #include "esp_int_wdt.h"
  47. #include "esp_task_wdt.h"
  48. #include "esp_phy_init.h"
  49. #include "esp_coexist.h"
  50. #include "trax.h"
  51. #define STRINGIFY(s) STRINGIFY2(s)
  52. #define STRINGIFY2(s) #s
  53. void start_cpu0(void) __attribute__((weak, alias("start_cpu0_default")));
  54. void start_cpu0_default(void) IRAM_ATTR;
  55. #if !CONFIG_FREERTOS_UNICORE
  56. static void IRAM_ATTR call_start_cpu1();
  57. void start_cpu1(void) __attribute__((weak, alias("start_cpu1_default")));
  58. void start_cpu1_default(void) IRAM_ATTR;
  59. static bool app_cpu_started = false;
  60. #endif //!CONFIG_FREERTOS_UNICORE
  61. static void do_global_ctors(void);
  62. static void do_phy_init();
  63. static void main_task(void* args);
  64. extern void app_main(void);
  65. extern int _bss_start;
  66. extern int _bss_end;
  67. extern int _rtc_bss_start;
  68. extern int _rtc_bss_end;
  69. extern int _init_start;
  70. extern void (*__init_array_start)(void);
  71. extern void (*__init_array_end)(void);
  72. extern volatile int port_xSchedulerRunning[2];
  73. static const char* TAG = "cpu_start";
  74. /*
  75. * We arrive here after the bootloader finished loading the program from flash. The hardware is mostly uninitialized,
  76. * and the app CPU is in reset. We do have a stack, so we can do the initialization in C.
  77. */
  78. void IRAM_ATTR call_start_cpu0()
  79. {
  80. cpu_configure_region_protection();
  81. //Move exception vectors to IRAM
  82. asm volatile (\
  83. "wsr %0, vecbase\n" \
  84. ::"r"(&_init_start));
  85. memset(&_bss_start, 0, (&_bss_end - &_bss_start) * sizeof(_bss_start));
  86. /* Unless waking from deep sleep (implying RTC memory is intact), clear RTC bss */
  87. if (rtc_get_reset_reason(0) != DEEPSLEEP_RESET) {
  88. memset(&_rtc_bss_start, 0, (&_rtc_bss_end - &_rtc_bss_start) * sizeof(_rtc_bss_start));
  89. }
  90. // Initialize heap allocator
  91. heap_alloc_caps_init();
  92. ESP_EARLY_LOGI(TAG, "Pro cpu up.");
  93. #if !CONFIG_FREERTOS_UNICORE
  94. ESP_EARLY_LOGI(TAG, "Starting app cpu, entry point is %p", call_start_cpu1);
  95. //Flush and enable icache for APP CPU
  96. Cache_Flush(1);
  97. Cache_Read_Enable(1);
  98. esp_cpu_unstall(1);
  99. //Enable clock gating and reset the app cpu.
  100. SET_PERI_REG_MASK(DPORT_APPCPU_CTRL_B_REG, DPORT_APPCPU_CLKGATE_EN);
  101. CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_C_REG, DPORT_APPCPU_RUNSTALL);
  102. SET_PERI_REG_MASK(DPORT_APPCPU_CTRL_A_REG, DPORT_APPCPU_RESETTING);
  103. CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_A_REG, DPORT_APPCPU_RESETTING);
  104. ets_set_appcpu_boot_addr((uint32_t)call_start_cpu1);
  105. while (!app_cpu_started) {
  106. ets_delay_us(100);
  107. }
  108. #else
  109. ESP_EARLY_LOGI(TAG, "Single core mode");
  110. CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_B_REG, DPORT_APPCPU_CLKGATE_EN);
  111. #endif
  112. ESP_EARLY_LOGI(TAG, "Pro cpu start user code");
  113. start_cpu0();
  114. }
  115. #if !CONFIG_FREERTOS_UNICORE
  116. void IRAM_ATTR call_start_cpu1()
  117. {
  118. asm volatile (\
  119. "wsr %0, vecbase\n" \
  120. ::"r"(&_init_start));
  121. cpu_configure_region_protection();
  122. #if CONFIG_CONSOLE_UART_NONE
  123. ets_install_putc1(NULL);
  124. ets_install_putc2(NULL);
  125. #else // CONFIG_CONSOLE_UART_NONE
  126. uartAttach();
  127. ets_install_uart_printf();
  128. uart_tx_switch(CONFIG_CONSOLE_UART_NUM);
  129. #endif
  130. ESP_EARLY_LOGI(TAG, "App cpu up.");
  131. app_cpu_started = 1;
  132. start_cpu1();
  133. }
  134. #endif //!CONFIG_FREERTOS_UNICORE
  135. void start_cpu0_default(void)
  136. {
  137. esp_setup_syscall_table();
  138. //Enable trace memory and immediately start trace.
  139. #if CONFIG_MEMMAP_TRACEMEM
  140. #if CONFIG_MEMMAP_TRACEMEM_TWOBANKS
  141. trax_enable(TRAX_ENA_PRO_APP);
  142. #else
  143. trax_enable(TRAX_ENA_PRO);
  144. #endif
  145. trax_start_trace(TRAX_DOWNCOUNT_WORDS);
  146. #endif
  147. esp_set_cpu_freq(); // set CPU frequency configured in menuconfig
  148. uart_div_modify(CONFIG_CONSOLE_UART_NUM, (APB_CLK_FREQ << 4) / CONFIG_CONSOLE_UART_BAUDRATE);
  149. #if CONFIG_BROWNOUT_DET
  150. esp_brownout_init();
  151. #endif
  152. rtc_gpio_unhold_all();
  153. esp_setup_time_syscalls();
  154. esp_vfs_dev_uart_register();
  155. esp_reent_init(_GLOBAL_REENT);
  156. #ifndef CONFIG_CONSOLE_UART_NONE
  157. const char* default_uart_dev = "/dev/uart/" STRINGIFY(CONFIG_CONSOLE_UART_NUM);
  158. _GLOBAL_REENT->_stdin = fopen(default_uart_dev, "r");
  159. _GLOBAL_REENT->_stdout = fopen(default_uart_dev, "w");
  160. _GLOBAL_REENT->_stderr = fopen(default_uart_dev, "w");
  161. #else
  162. _GLOBAL_REENT->_stdin = (FILE*) &__sf_fake_stdin;
  163. _GLOBAL_REENT->_stdout = (FILE*) &__sf_fake_stdout;
  164. _GLOBAL_REENT->_stderr = (FILE*) &__sf_fake_stderr;
  165. #endif
  166. do_global_ctors();
  167. #if CONFIG_INT_WDT
  168. esp_int_wdt_init();
  169. #endif
  170. #if CONFIG_TASK_WDT
  171. esp_task_wdt_init();
  172. #endif
  173. #if !CONFIG_FREERTOS_UNICORE
  174. esp_crosscore_int_init();
  175. #endif
  176. esp_ipc_init();
  177. spi_flash_init();
  178. #if CONFIG_ESP32_PHY_AUTO_INIT
  179. nvs_flash_init();
  180. do_phy_init();
  181. #endif
  182. #if CONFIG_SW_COEXIST_ENABLE
  183. if (coex_init() == ESP_OK) {
  184. coexist_set_enable(true);
  185. }
  186. #endif
  187. xTaskCreatePinnedToCore(&main_task, "main",
  188. ESP_TASK_MAIN_STACK, NULL,
  189. ESP_TASK_MAIN_PRIO, NULL, 0);
  190. ESP_LOGI(TAG, "Starting scheduler on PRO CPU.");
  191. vTaskStartScheduler();
  192. }
  193. #if !CONFIG_FREERTOS_UNICORE
  194. void start_cpu1_default(void)
  195. {
  196. #if CONFIG_MEMMAP_TRACEMEM_TWOBANKS
  197. trax_start_trace(TRAX_DOWNCOUNT_WORDS);
  198. #endif
  199. // Wait for FreeRTOS initialization to finish on PRO CPU
  200. while (port_xSchedulerRunning[0] == 0) {
  201. ;
  202. }
  203. //Take care putting stuff here: if asked, FreeRTOS will happily tell you the scheduler
  204. //has started, but it isn't active *on this CPU* yet.
  205. esp_crosscore_int_init();
  206. ESP_EARLY_LOGI(TAG, "Starting scheduler on APP CPU.");
  207. xPortStartScheduler();
  208. }
  209. #endif //!CONFIG_FREERTOS_UNICORE
  210. static void do_global_ctors(void)
  211. {
  212. void (**p)(void);
  213. for (p = &__init_array_end - 1; p >= &__init_array_start; --p) {
  214. (*p)();
  215. }
  216. }
  217. static void main_task(void* args)
  218. {
  219. // Now that the application is about to start, disable boot watchdogs
  220. REG_CLR_BIT(TIMG_WDTCONFIG0_REG(0), TIMG_WDT_FLASHBOOT_MOD_EN_S);
  221. REG_CLR_BIT(RTC_CNTL_WDTCONFIG0_REG, RTC_CNTL_WDT_FLASHBOOT_MOD_EN);
  222. app_main();
  223. vTaskDelete(NULL);
  224. }
  225. static void do_phy_init()
  226. {
  227. esp_phy_calibration_mode_t calibration_mode = PHY_RF_CAL_PARTIAL;
  228. if (rtc_get_reset_reason(0) == DEEPSLEEP_RESET) {
  229. calibration_mode = PHY_RF_CAL_NONE;
  230. }
  231. const esp_phy_init_data_t* init_data = esp_phy_get_init_data();
  232. if (init_data == NULL) {
  233. ESP_LOGE(TAG, "failed to obtain PHY init data");
  234. abort();
  235. }
  236. esp_phy_calibration_data_t* cal_data =
  237. (esp_phy_calibration_data_t*) calloc(sizeof(esp_phy_calibration_data_t), 1);
  238. if (cal_data == NULL) {
  239. ESP_LOGE(TAG, "failed to allocate memory for RF calibration data");
  240. abort();
  241. }
  242. esp_err_t err = esp_phy_load_cal_data_from_nvs(cal_data);
  243. if (err != ESP_OK) {
  244. ESP_LOGW(TAG, "failed to load RF calibration data, falling back to full calibration");
  245. calibration_mode = PHY_RF_CAL_FULL;
  246. }
  247. esp_phy_init(init_data, calibration_mode, cal_data);
  248. if (calibration_mode != PHY_RF_CAL_NONE) {
  249. err = esp_phy_store_cal_data_to_nvs(cal_data);
  250. } else {
  251. err = ESP_OK;
  252. }
  253. esp_phy_release_init_data(init_data);
  254. free(cal_data); // PHY maintains a copy of calibration data, so we can free this
  255. }