Kconfig 9.1 KB

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  1. menu "Common ESP-related"
  2. config ESP_TIMER_PROFILING
  3. bool "Enable esp_timer profiling features"
  4. default n
  5. help
  6. If enabled, esp_timer_dump will dump information such as number of times the timer was started, number of
  7. times the timer has triggered, and the total time it took for the callback to run. This option has some
  8. effect on timer performance and the amount of memory used for timer storage, and should only be used for
  9. debugging/testing purposes.
  10. config ESP_ERR_TO_NAME_LOOKUP
  11. bool "Enable lookup of error code strings"
  12. default "y"
  13. help
  14. Functions esp_err_to_name() and esp_err_to_name_r() return string representations of error codes from a
  15. pre-generated lookup table. This option can be used to turn off the use of the look-up table in order to
  16. save memory but this comes at the price of sacrificing distinguishable (meaningful) output string
  17. representations.
  18. config ESP_SYSTEM_EVENT_QUEUE_SIZE
  19. int "System event queue size"
  20. default 32
  21. help
  22. Config system event queue size in different application.
  23. config ESP_SYSTEM_EVENT_TASK_STACK_SIZE
  24. int "Event loop task stack size"
  25. default 2304
  26. help
  27. Config system event task stack size in different application.
  28. config ESP_MAIN_TASK_STACK_SIZE
  29. int "Main task stack size"
  30. default 3584
  31. help
  32. Configure the "main task" stack size. This is the stack of the task
  33. which calls app_main(). If app_main() returns then this task is deleted
  34. and its stack memory is freed.
  35. config ESP_IPC_TASK_STACK_SIZE
  36. int "Inter-Processor Call (IPC) task stack size"
  37. range 512 65536 if !ESP32_APPTRACE_ENABLE
  38. range 2048 65536 if ESP32_APPTRACE_ENABLE
  39. default 2048 if ESP32_APPTRACE_ENABLE
  40. default 1024
  41. help
  42. Configure the IPC tasks stack size. One IPC task runs on each core
  43. (in dual core mode), and allows for cross-core function calls.
  44. See IPC documentation for more details.
  45. The default stack size should be enough for most common use cases.
  46. It can be shrunk if you are sure that you do not use any custom
  47. IPC functionality.
  48. config ESP_IPC_USES_CALLERS_PRIORITY
  49. bool "IPC runs at caller's priority"
  50. default y
  51. depends on !FREERTOS_UNICORE
  52. help
  53. If this option is not enabled then the IPC task will keep behavior
  54. same as prior to that of ESP-IDF v4.0, and hence IPC task will run
  55. at (configMAX_PRIORITIES - 1) priority.
  56. config ESP_TIMER_TASK_STACK_SIZE
  57. int "High-resolution timer task stack size"
  58. default 3584
  59. range 2048 65536
  60. help
  61. Configure the stack size of esp_timer/ets_timer task. This task is used
  62. to dispatch callbacks of timers created using ets_timer and esp_timer
  63. APIs. If you are seing stack overflow errors in timer task, increase
  64. this value.
  65. Note that this is not the same as FreeRTOS timer task. To configure
  66. FreeRTOS timer task size, see "FreeRTOS timer task stack size" option
  67. in "FreeRTOS" menu.
  68. choice ESP_CONSOLE_UART
  69. prompt "UART for console output"
  70. default ESP_CONSOLE_UART_DEFAULT
  71. help
  72. Select whether to use UART for console output (through stdout and stderr).
  73. - Default is to use UART0 on pins GPIO1(TX) and GPIO3(RX).
  74. - If "Custom" is selected, UART0 or UART1 can be chosen,
  75. and any pins can be selected.
  76. - If "None" is selected, there will be no console output on any UART, except
  77. for initial output from ROM bootloader. This output can be further suppressed by
  78. bootstrapping GPIO13 pin to low logic level.
  79. config ESP_CONSOLE_UART_DEFAULT
  80. bool "Default: UART0, TX=GPIO1, RX=GPIO3"
  81. config ESP_CONSOLE_UART_CUSTOM
  82. bool "Custom"
  83. config ESP_CONSOLE_UART_NONE
  84. bool "None"
  85. endchoice
  86. choice ESP_CONSOLE_UART_NUM
  87. prompt "UART peripheral to use for console output (0-1)"
  88. depends on ESP_CONSOLE_UART_CUSTOM
  89. default ESP_CONSOLE_UART_CUSTOM_NUM_0
  90. help
  91. Due of a ROM bug, UART2 is not supported for console output
  92. via ets_printf.
  93. config ESP_CONSOLE_UART_CUSTOM_NUM_0
  94. bool "UART0"
  95. config ESP_CONSOLE_UART_CUSTOM_NUM_1
  96. bool "UART1"
  97. endchoice
  98. config ESP_CONSOLE_UART_NUM
  99. int
  100. default 0 if ESP_CONSOLE_UART_DEFAULT || ESP_CONSOLE_UART_NONE
  101. default 0 if ESP_CONSOLE_UART_CUSTOM_NUM_0
  102. default 1 if ESP_CONSOLE_UART_CUSTOM_NUM_1
  103. config ESP_CONSOLE_UART_TX_GPIO
  104. int "UART TX on GPIO#"
  105. depends on ESP_CONSOLE_UART_CUSTOM
  106. range 0 33
  107. default 19
  108. config ESP_CONSOLE_UART_RX_GPIO
  109. int "UART RX on GPIO#"
  110. depends on ESP_CONSOLE_UART_CUSTOM
  111. range 0 39
  112. default 21
  113. config ESP_CONSOLE_UART_BAUDRATE
  114. int "UART console baud rate"
  115. depends on !ESP_CONSOLE_UART_NONE
  116. default 115200
  117. range 1200 4000000
  118. config ESP_INT_WDT
  119. bool "Interrupt watchdog"
  120. default y
  121. help
  122. This watchdog timer can detect if the FreeRTOS tick interrupt has not been called for a certain time,
  123. either because a task turned off interrupts and did not turn them on for a long time, or because an
  124. interrupt handler did not return. It will try to invoke the panic handler first and failing that
  125. reset the SoC.
  126. config ESP_INT_WDT_TIMEOUT_MS
  127. int "Interrupt watchdog timeout (ms)"
  128. depends on ESP_INT_WDT
  129. default 300 if !ESP32_SPIRAM_SUPPORT
  130. default 800 if ESP32_SPIRAM_SUPPORT
  131. range 10 10000
  132. help
  133. The timeout of the watchdog, in miliseconds. Make this higher than the FreeRTOS tick rate.
  134. config ESP_INT_WDT_CHECK_CPU1
  135. bool "Also watch CPU1 tick interrupt"
  136. depends on ESP_INT_WDT && !FREERTOS_UNICORE
  137. default y
  138. help
  139. Also detect if interrupts on CPU 1 are disabled for too long.
  140. config ESP_TASK_WDT
  141. bool "Initialize Task Watchdog Timer on startup"
  142. default y
  143. help
  144. The Task Watchdog Timer can be used to make sure individual tasks are still
  145. running. Enabling this option will cause the Task Watchdog Timer to be
  146. initialized automatically at startup. The Task Watchdog timer can be
  147. initialized after startup as well (see Task Watchdog Timer API Reference)
  148. config ESP_TASK_WDT_PANIC
  149. bool "Invoke panic handler on Task Watchdog timeout"
  150. depends on ESP_TASK_WDT
  151. default n
  152. help
  153. If this option is enabled, the Task Watchdog Timer will be configured to
  154. trigger the panic handler when it times out. This can also be configured
  155. at run time (see Task Watchdog Timer API Reference)
  156. config ESP_TASK_WDT_TIMEOUT_S
  157. int "Task Watchdog timeout period (seconds)"
  158. depends on ESP_TASK_WDT
  159. range 1 60
  160. default 5
  161. help
  162. Timeout period configuration for the Task Watchdog Timer in seconds.
  163. This is also configurable at run time (see Task Watchdog Timer API Reference)
  164. config ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0
  165. bool "Watch CPU0 Idle Task"
  166. depends on ESP_TASK_WDT
  167. default y
  168. help
  169. If this option is enabled, the Task Watchdog Timer will watch the CPU0
  170. Idle Task. Having the Task Watchdog watch the Idle Task allows for detection
  171. of CPU starvation as the Idle Task not being called is usually a symptom of
  172. CPU starvation. Starvation of the Idle Task is detrimental as FreeRTOS household
  173. tasks depend on the Idle Task getting some runtime every now and then.
  174. config ESP_TASK_WDT_CHECK_IDLE_TASK_CPU1
  175. bool "Watch CPU1 Idle Task"
  176. depends on ESP_TASK_WDT && !FREERTOS_UNICORE
  177. default y
  178. help
  179. If this option is enabled, the Task Wtachdog Timer will wach the CPU1
  180. Idle Task.
  181. config ESP_PANIC_HANDLER_IRAM
  182. bool "Place panic handler code in IRAM"
  183. default n
  184. depends on IDF_TARGET_ESP32 # pending ESP32-S2 Beta support
  185. help
  186. If this option is disabled (default), the panic handler code is placed in flash not IRAM.
  187. This means that if ESP-IDF crashes while flash cache is disabled, the panic handler will
  188. automatically re-enable flash cache before running GDB Stub or Core Dump. This adds some minor
  189. risk, if the flash cache status is also corrupted during the crash.
  190. If this option is enabled, the panic handler code is placed in IRAM. This allows the panic
  191. handler to run without needing to re-enable cache first. This may be necessary to debug some
  192. complex issues with crashes while flash cache is disabled (for example, when writing to
  193. SPI flash.)
  194. endmenu # Common ESP-related