Kconfig 6.5 KB

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  1. menu "Ethernet"
  2. # Invisible item that is enabled if any Ethernet
  3. # selection is made
  4. config ETH_ENABLED
  5. bool
  6. menuconfig ETH_USE_ESP32_EMAC
  7. depends on IDF_TARGET_ESP32
  8. bool "Support ESP32 internal EMAC controller"
  9. default y
  10. select ETH_ENABLED
  11. help
  12. ESP32 integrates a 10/100M Ethernet MAC controller.
  13. if ETH_USE_ESP32_EMAC
  14. choice ETH_PHY_INTERFACE
  15. prompt "PHY interface"
  16. default ETH_PHY_INTERFACE_RMII
  17. help
  18. Select the communication interface between MAC and PHY chip.
  19. config ETH_PHY_INTERFACE_RMII
  20. bool "Reduced Media Independent Interface (RMII)"
  21. config ETH_PHY_INTERFACE_MII
  22. bool "Media Independent Interface (MII)"
  23. endchoice
  24. if ETH_PHY_INTERFACE_RMII
  25. choice ETH_RMII_CLK_MODE
  26. prompt "RMII clock mode"
  27. default ETH_RMII_CLK_INPUT
  28. help
  29. Select external or internal RMII clock.
  30. config ETH_RMII_CLK_INPUT
  31. bool "Input RMII clock from external"
  32. help
  33. MAC will get RMII clock from outside.
  34. Note that ESP32 only supports GPIO0 to input the RMII clock.
  35. config ETH_RMII_CLK_OUTPUT
  36. bool "Output RMII clock from internal"
  37. help
  38. ESP32 can generate RMII clock by internal APLL.
  39. This clock can be routed to the external PHY device.
  40. ESP32 supports to route the RMII clock to GPIO0/16/17.
  41. endchoice
  42. endif
  43. if ETH_RMII_CLK_INPUT
  44. config ETH_RMII_CLK_IN_GPIO
  45. int
  46. range 0 0
  47. default 0
  48. help
  49. ESP32 only supports GPIO0 to input the RMII clock.
  50. endif
  51. if ETH_RMII_CLK_OUTPUT
  52. config ETH_RMII_CLK_OUTPUT_GPIO0
  53. bool "Output RMII clock from GPIO0 (Experimental!)"
  54. default n
  55. help
  56. GPIO0 can be set to output a pre-divided PLL clock (test only!).
  57. Enabling this option will configure GPIO0 to output a 50MHz clock.
  58. In fact this clock doesn't have directly relationship with EMAC peripheral.
  59. Sometimes this clock won't work well with your PHY chip. You might need to
  60. add some extra devices after GPIO0 (e.g. inverter).
  61. Note that outputting RMII clock on GPIO0 is an experimental practice.
  62. If you want the Ethernet to work with WiFi, don't select GPIO0 output mode for stability.
  63. if !ETH_RMII_CLK_OUTPUT_GPIO0
  64. config ETH_RMII_CLK_OUT_GPIO
  65. int "RMII clock GPIO number"
  66. range 16 17
  67. default 17
  68. help
  69. Set the GPIO number to output RMII Clock.
  70. endif
  71. endif
  72. config ETH_SMI_MDC_GPIO
  73. int "SMI MDC GPIO number"
  74. default 23
  75. range 0 33
  76. help
  77. Set the GPIO number used by SMI MDC.
  78. config ETH_SMI_MDIO_GPIO
  79. int "SMI MDIO GPIO number"
  80. default 18
  81. range 0 33
  82. help
  83. Set the GPIO number used by SMI MDIO.
  84. config ETH_PHY_USE_RST
  85. bool "Use Reset Pin of PHY Chip"
  86. default y
  87. help
  88. Set this option to true if you want to control PHY chip's reset using a GPIO.
  89. Check the schematic of you board to make sure if it's necessary to use this feature.
  90. if ETH_PHY_USE_RST
  91. config ETH_PHY_RST_GPIO
  92. int "PHY RST GPIO number"
  93. default 5
  94. range 0 33
  95. help
  96. Set the GPIO number used by the PHY chip's RST pin.
  97. endif
  98. config ETH_DMA_BUFFER_SIZE
  99. int "Ethernet DMA buffer size (Byte)"
  100. range 256 1600
  101. default 512
  102. help
  103. Set the size of each buffer used by Ethernet MAC DMA.
  104. config ETH_DMA_RX_BUFFER_NUM
  105. int "Amount of Ethernet DMA Rx buffers"
  106. range 3 30
  107. default 10
  108. help
  109. Number of DMA receive buffers. Each buffer's size is ETH_DMA_BUFFER_SIZE.
  110. Larger number of buffers could increase throughput somehow.
  111. config ETH_DMA_TX_BUFFER_NUM
  112. int "Amount of Ethernet DMA Tx buffers"
  113. range 3 30
  114. default 10
  115. help
  116. Number of DMA transmit buffers. Each buffer's size is ETH_DMA_BUFFER_SIZE.
  117. Larger number of buffers could increase throughput somehow.
  118. endif
  119. menuconfig ETH_USE_SPI_ETHERNET
  120. bool "Support SPI to Ethernet Module"
  121. default y
  122. select ETH_ENABLED
  123. help
  124. ESP-IDF can also support some SPI-Ethernet modules.
  125. if ETH_USE_SPI_ETHERNET
  126. menuconfig ETH_SPI_ETHERNET_DM9051
  127. bool "Use DM9051"
  128. default y
  129. help
  130. DM9051 is a fast Ethernet controller with an SPI interface.
  131. It's also integrated with a 10/100M PHY and MAC.
  132. Set true to enable DM9051 driver.
  133. if ETH_SPI_ETHERNET_DM9051
  134. config ETH_DM9051_INT_GPIO
  135. int "DM9051 Interrupt GPIO number"
  136. default 4
  137. range 0 33
  138. help
  139. Set the GPIO number used by DM9051's Interrupt pin.
  140. endif
  141. endif
  142. menuconfig ETH_USE_OPENETH
  143. bool "Support OpenCores Ethernet MAC (for use with QEMU)"
  144. default n
  145. help
  146. OpenCores Ethernet MAC driver can be used when an ESP-IDF application
  147. is executed in QEMU. This driver is not supported when running on a
  148. real chip.
  149. if ETH_USE_OPENETH
  150. config ETH_OPENETH_DMA_RX_BUFFER_NUM
  151. int "Number of Ethernet DMA Rx buffers"
  152. range 1 64
  153. default 4
  154. help
  155. Number of DMA receive buffers, each buffer is 1600 bytes.
  156. config ETH_OPENETH_DMA_TX_BUFFER_NUM
  157. int "Number of Ethernet DMA Tx buffers"
  158. range 1 64
  159. default 1
  160. help
  161. Number of DMA transmit buffers, each buffer is 1600 bytes.
  162. endif
  163. endmenu