periph_ctrl.c 11 KB

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  1. // Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
  2. //
  3. // Licensed under the Apache License, Version 2.0 (the "License");
  4. // you may not use this file except in compliance with the License.
  5. // You may obtain a copy of the License at
  6. // http://www.apache.org/licenses/LICENSE-2.0
  7. //
  8. // Unless required by applicable law or agreed to in writing, software
  9. // distributed under the License is distributed on an "AS IS" BASIS,
  10. // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  11. // See the License for the specific language governing permissions and
  12. // limitations under the License.
  13. #include "esp_types.h"
  14. #include "sdkconfig.h"
  15. #include "freertos/FreeRTOS.h"
  16. #include "freertos/semphr.h"
  17. #include "freertos/xtensa_api.h"
  18. #include "soc/dport_reg.h"
  19. #include "soc/syscon_reg.h"
  20. #include "driver/periph_ctrl.h"
  21. static portMUX_TYPE periph_spinlock = portMUX_INITIALIZER_UNLOCKED;
  22. /* Static functions to return register address & mask for clk_en / rst of each peripheral */
  23. static uint32_t get_clk_en_mask(periph_module_t periph);
  24. static uint32_t get_rst_en_mask(periph_module_t periph, bool enable);
  25. static uint32_t get_clk_en_reg(periph_module_t periph);
  26. static uint32_t get_rst_en_reg(periph_module_t periph);
  27. void periph_module_enable(periph_module_t periph)
  28. {
  29. portENTER_CRITICAL_SAFE(&periph_spinlock);
  30. DPORT_SET_PERI_REG_MASK(get_clk_en_reg(periph), get_clk_en_mask(periph));
  31. DPORT_CLEAR_PERI_REG_MASK(get_rst_en_reg(periph), get_rst_en_mask(periph, true));
  32. portEXIT_CRITICAL_SAFE(&periph_spinlock);
  33. }
  34. void periph_module_disable(periph_module_t periph)
  35. {
  36. portENTER_CRITICAL_SAFE(&periph_spinlock);
  37. DPORT_CLEAR_PERI_REG_MASK(get_clk_en_reg(periph), get_clk_en_mask(periph));
  38. DPORT_SET_PERI_REG_MASK(get_rst_en_reg(periph), get_rst_en_mask(periph, false));
  39. portEXIT_CRITICAL_SAFE(&periph_spinlock);
  40. }
  41. void periph_module_reset(periph_module_t periph)
  42. {
  43. portENTER_CRITICAL_SAFE(&periph_spinlock);
  44. DPORT_SET_PERI_REG_MASK(get_rst_en_reg(periph), get_rst_en_mask(periph, false));
  45. DPORT_CLEAR_PERI_REG_MASK(get_rst_en_reg(periph), get_rst_en_mask(periph, false));
  46. portEXIT_CRITICAL_SAFE(&periph_spinlock);
  47. }
  48. static uint32_t get_clk_en_mask(periph_module_t periph)
  49. {
  50. switch(periph) {
  51. case PERIPH_RMT_MODULE:
  52. return DPORT_RMT_CLK_EN;
  53. case PERIPH_LEDC_MODULE:
  54. return DPORT_LEDC_CLK_EN;
  55. case PERIPH_UART0_MODULE:
  56. return DPORT_UART_CLK_EN;
  57. case PERIPH_UART1_MODULE:
  58. return DPORT_UART1_CLK_EN;
  59. #if CONFIG_IDF_TARGET_ESP32
  60. case PERIPH_UART2_MODULE:
  61. return DPORT_UART2_CLK_EN;
  62. #elif CONFIG_IDF_TARGET_ESP32S2BETA
  63. case PERIPH_USB_MODULE:
  64. return DPORT_USB_CLK_EN;
  65. #endif
  66. case PERIPH_I2C0_MODULE:
  67. return DPORT_I2C_EXT0_CLK_EN;
  68. case PERIPH_I2C1_MODULE:
  69. return DPORT_I2C_EXT1_CLK_EN;
  70. case PERIPH_I2S0_MODULE:
  71. return DPORT_I2S0_CLK_EN;
  72. case PERIPH_I2S1_MODULE:
  73. return DPORT_I2S1_CLK_EN;
  74. case PERIPH_TIMG0_MODULE:
  75. return DPORT_TIMERGROUP_CLK_EN;
  76. case PERIPH_TIMG1_MODULE:
  77. return DPORT_TIMERGROUP1_CLK_EN;
  78. case PERIPH_PWM0_MODULE:
  79. return DPORT_PWM0_CLK_EN;
  80. case PERIPH_PWM1_MODULE:
  81. return DPORT_PWM1_CLK_EN;
  82. case PERIPH_PWM2_MODULE:
  83. return DPORT_PWM2_CLK_EN;
  84. case PERIPH_PWM3_MODULE:
  85. return DPORT_PWM3_CLK_EN;
  86. case PERIPH_UHCI0_MODULE:
  87. return DPORT_UHCI0_CLK_EN;
  88. case PERIPH_UHCI1_MODULE:
  89. return DPORT_UHCI1_CLK_EN;
  90. case PERIPH_PCNT_MODULE:
  91. return DPORT_PCNT_CLK_EN;
  92. case PERIPH_SPI_MODULE:
  93. return DPORT_SPI01_CLK_EN;
  94. #if CONFIG_IDF_TARGET_ESP32
  95. case PERIPH_HSPI_MODULE:
  96. return DPORT_SPI2_CLK_EN;
  97. case PERIPH_VSPI_MODULE:
  98. return DPORT_SPI3_CLK_EN;
  99. case PERIPH_SPI_DMA_MODULE:
  100. return DPORT_SPI_DMA_CLK_EN;
  101. #elif CONFIG_IDF_TARGET_ESP32S2BETA
  102. case PERIPH_FSPI_MODULE:
  103. return DPORT_SPI2_CLK_EN;
  104. case PERIPH_HSPI_MODULE:
  105. return DPORT_SPI3_CLK_EN;
  106. case PERIPH_VSPI_MODULE:
  107. return DPORT_SPI4_CLK_EN;
  108. case PERIPH_SPI2_DMA_MODULE:
  109. return DPORT_SPI2_DMA_CLK_EN;
  110. case PERIPH_SPI3_DMA_MODULE:
  111. return DPORT_SPI3_DMA_CLK_EN;
  112. #endif
  113. case PERIPH_SDMMC_MODULE:
  114. return DPORT_WIFI_CLK_SDIO_HOST_EN;
  115. case PERIPH_SDIO_SLAVE_MODULE:
  116. return DPORT_WIFI_CLK_SDIOSLAVE_EN;
  117. case PERIPH_CAN_MODULE:
  118. return DPORT_CAN_CLK_EN;
  119. case PERIPH_EMAC_MODULE:
  120. return DPORT_WIFI_CLK_EMAC_EN;
  121. case PERIPH_RNG_MODULE:
  122. return DPORT_WIFI_CLK_RNG_EN;
  123. case PERIPH_WIFI_MODULE:
  124. #if CONFIG_IDF_TARGET_ESP32
  125. return DPORT_WIFI_CLK_WIFI_EN_M;
  126. #elif CONFIG_IDF_TARGET_ESP32S2BETA
  127. return 0;
  128. #endif
  129. case PERIPH_BT_MODULE:
  130. return DPORT_WIFI_CLK_BT_EN_M;
  131. case PERIPH_WIFI_BT_COMMON_MODULE:
  132. return DPORT_WIFI_CLK_WIFI_BT_COMMON_M;
  133. case PERIPH_BT_BASEBAND_MODULE:
  134. return DPORT_BT_BASEBAND_EN;
  135. case PERIPH_BT_LC_MODULE:
  136. return DPORT_BT_LC_EN;
  137. #if CONFIG_IDF_TARGET_ESP32
  138. case PERIPH_AES_MODULE:
  139. return DPORT_PERI_EN_AES;
  140. case PERIPH_SHA_MODULE:
  141. return DPORT_PERI_EN_SHA;
  142. case PERIPH_RSA_MODULE:
  143. return DPORT_PERI_EN_RSA;
  144. #endif
  145. default:
  146. return 0;
  147. }
  148. }
  149. static uint32_t get_rst_en_mask(periph_module_t periph, bool enable)
  150. {
  151. switch(periph) {
  152. case PERIPH_RMT_MODULE:
  153. return DPORT_RMT_RST;
  154. case PERIPH_LEDC_MODULE:
  155. return DPORT_LEDC_RST;
  156. case PERIPH_UART0_MODULE:
  157. return DPORT_UART_RST;
  158. case PERIPH_UART1_MODULE:
  159. return DPORT_UART1_RST;
  160. #if CONFIG_IDF_TARGET_ESP32
  161. case PERIPH_UART2_MODULE:
  162. return DPORT_UART2_RST;
  163. #elif CONFIG_IDF_TARGET_ESP32S2BETA
  164. case PERIPH_USB_MODULE:
  165. return DPORT_USB_RST;
  166. #endif
  167. case PERIPH_I2C0_MODULE:
  168. return DPORT_I2C_EXT0_RST;
  169. case PERIPH_I2C1_MODULE:
  170. return DPORT_I2C_EXT1_RST;
  171. case PERIPH_I2S0_MODULE:
  172. return DPORT_I2S0_RST;
  173. case PERIPH_I2S1_MODULE:
  174. return DPORT_I2S1_RST;
  175. case PERIPH_TIMG0_MODULE:
  176. return DPORT_TIMERGROUP_RST;
  177. case PERIPH_TIMG1_MODULE:
  178. return DPORT_TIMERGROUP1_RST;
  179. case PERIPH_PWM0_MODULE:
  180. return DPORT_PWM0_RST;
  181. case PERIPH_PWM1_MODULE:
  182. return DPORT_PWM1_RST;
  183. case PERIPH_PWM2_MODULE:
  184. return DPORT_PWM2_RST;
  185. case PERIPH_PWM3_MODULE:
  186. return DPORT_PWM3_RST;
  187. case PERIPH_UHCI0_MODULE:
  188. return DPORT_UHCI0_RST;
  189. case PERIPH_UHCI1_MODULE:
  190. return DPORT_UHCI1_RST;
  191. case PERIPH_PCNT_MODULE:
  192. return DPORT_PCNT_RST;
  193. case PERIPH_SPI_MODULE:
  194. return DPORT_SPI01_RST;
  195. #if CONFIG_IDF_TARGET_ESP32
  196. case PERIPH_HSPI_MODULE:
  197. return DPORT_SPI2_RST;
  198. case PERIPH_VSPI_MODULE:
  199. return DPORT_SPI3_RST;
  200. case PERIPH_SPI_DMA_MODULE:
  201. return DPORT_SPI_DMA_RST;
  202. #elif CONFIG_IDF_TARGET_ESP32S2BETA
  203. case PERIPH_FSPI_MODULE:
  204. return DPORT_SPI2_RST;
  205. case PERIPH_HSPI_MODULE:
  206. return DPORT_SPI3_RST;
  207. case PERIPH_VSPI_MODULE:
  208. return DPORT_SPI4_RST;
  209. case PERIPH_SPI2_DMA_MODULE:
  210. return DPORT_SPI2_DMA_RST;
  211. case PERIPH_SPI3_DMA_MODULE:
  212. return DPORT_SPI3_DMA_RST;
  213. #endif
  214. case PERIPH_SDMMC_MODULE:
  215. return DPORT_SDIO_HOST_RST;
  216. case PERIPH_SDIO_SLAVE_MODULE:
  217. return DPORT_SDIO_RST;
  218. case PERIPH_CAN_MODULE:
  219. return DPORT_CAN_RST;
  220. case PERIPH_EMAC_MODULE:
  221. return DPORT_EMAC_RST;
  222. #if CONFIG_IDF_TARGET_ESP32
  223. case PERIPH_AES_MODULE:
  224. if (enable == true) {
  225. // Clear reset on digital signature & secure boot units, otherwise AES unit is held in reset also.
  226. return (DPORT_PERI_EN_AES | DPORT_PERI_EN_DIGITAL_SIGNATURE | DPORT_PERI_EN_SECUREBOOT);
  227. } else {
  228. //Don't return other units to reset, as this pulls reset on RSA & SHA units, respectively.
  229. return DPORT_PERI_EN_AES;
  230. }
  231. case PERIPH_SHA_MODULE:
  232. if (enable == true) {
  233. // Clear reset on secure boot, otherwise SHA is held in reset
  234. return (DPORT_PERI_EN_SHA | DPORT_PERI_EN_SECUREBOOT);
  235. } else {
  236. // Don't assert reset on secure boot, otherwise AES is held in reset
  237. return DPORT_PERI_EN_SHA;
  238. }
  239. case PERIPH_RSA_MODULE:
  240. if (enable == true) {
  241. // Also clear reset on digital signature, otherwise RSA is held in reset
  242. return (DPORT_PERI_EN_RSA | DPORT_PERI_EN_DIGITAL_SIGNATURE);
  243. } else {
  244. // Don't reset digital signature unit, as this resets AES also
  245. return DPORT_PERI_EN_RSA;
  246. }
  247. #endif
  248. case PERIPH_WIFI_MODULE:
  249. case PERIPH_BT_MODULE:
  250. case PERIPH_WIFI_BT_COMMON_MODULE:
  251. case PERIPH_BT_BASEBAND_MODULE:
  252. case PERIPH_BT_LC_MODULE:
  253. return 0;
  254. default:
  255. return 0;
  256. }
  257. }
  258. static bool is_wifi_clk_peripheral(periph_module_t periph)
  259. {
  260. /* A small subset of peripherals use WIFI_CLK_EN_REG and
  261. CORE_RST_EN_REG for their clock & reset registers */
  262. switch(periph) {
  263. case PERIPH_SDMMC_MODULE:
  264. case PERIPH_SDIO_SLAVE_MODULE:
  265. case PERIPH_EMAC_MODULE:
  266. case PERIPH_RNG_MODULE:
  267. case PERIPH_WIFI_MODULE:
  268. case PERIPH_BT_MODULE:
  269. case PERIPH_WIFI_BT_COMMON_MODULE:
  270. case PERIPH_BT_BASEBAND_MODULE:
  271. case PERIPH_BT_LC_MODULE:
  272. return true;
  273. default:
  274. return false;
  275. }
  276. }
  277. static uint32_t get_clk_en_reg(periph_module_t periph)
  278. {
  279. #if CONFIG_IDF_TARGET_ESP32
  280. if (periph == PERIPH_AES_MODULE || periph == PERIPH_SHA_MODULE || periph == PERIPH_RSA_MODULE) {
  281. return DPORT_PERI_CLK_EN_REG;
  282. }
  283. #elif CONFIG_IDF_TARGET_ESP32S2BETA
  284. if(periph == PERIPH_SPI_SHARED_DMA_MODULE) {
  285. return DPORT_PERIP_CLK_EN1_REG;
  286. }
  287. #endif
  288. else {
  289. return is_wifi_clk_peripheral(periph) ? DPORT_WIFI_CLK_EN_REG : DPORT_PERIP_CLK_EN_REG;
  290. }
  291. }
  292. static uint32_t get_rst_en_reg(periph_module_t periph)
  293. {
  294. #if CONFIG_IDF_TARGET_ESP32
  295. if (periph == PERIPH_AES_MODULE || periph == PERIPH_SHA_MODULE || periph == PERIPH_RSA_MODULE) {
  296. return DPORT_PERI_RST_EN_REG;
  297. }
  298. #elif CONFIG_IDF_TARGET_ESP32S2BETA
  299. if(periph == PERIPH_SPI_SHARED_DMA_MODULE){
  300. return DPORT_PERIP_CLK_EN1_REG;
  301. }
  302. #endif
  303. else {
  304. return is_wifi_clk_peripheral(periph) ? DPORT_CORE_RST_EN_REG : DPORT_PERIP_RST_EN_REG;
  305. }
  306. }