rmt.c 38 KB

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  1. // Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
  2. //
  3. // Licensed under the Apache License, Version 2.0 (the "License");
  4. // you may not use this file except in compliance with the License.
  5. // You may obtain a copy of the License at
  6. //
  7. // http://www.apache.org/licenses/LICENSE-2.0
  8. //
  9. // Unless required by applicable law or agreed to in writing, software
  10. // distributed under the License is distributed on an "AS IS" BASIS,
  11. // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  12. // See the License for the specific language governing permissions and
  13. // limitations under the License.
  14. #include <stdlib.h>
  15. #include <string.h>
  16. #include <sys/lock.h>
  17. #include "esp_intr_alloc.h"
  18. #include "esp_log.h"
  19. #include "driver/gpio.h"
  20. #include "driver/periph_ctrl.h"
  21. #include "driver/rmt.h"
  22. #include "freertos/FreeRTOS.h"
  23. #include "freertos/task.h"
  24. #include "freertos/semphr.h"
  25. #include "freertos/ringbuf.h"
  26. #include "soc/soc_memory_layout.h"
  27. #include "hal/rmt_hal.h"
  28. #include "hal/rmt_ll.h"
  29. #define RMT_SOUCCE_CLK_APB (APB_CLK_FREQ) /*!< RMT source clock is APB_CLK */
  30. #define RMT_SOURCE_CLK_REF (1 * 1000000) /*!< not used yet */
  31. #define RMT_SOURCE_CLK(select) ((select == RMT_BASECLK_REF) ? (RMT_SOURCE_CLK_REF) : (RMT_SOUCCE_CLK_APB))
  32. #define RMT_CHANNEL_ERROR_STR "RMT CHANNEL ERR"
  33. #define RMT_ADDR_ERROR_STR "RMT ADDRESS ERR"
  34. #define RMT_MEM_CNT_ERROR_STR "RMT MEM BLOCK NUM ERR"
  35. #define RMT_CARRIER_ERROR_STR "RMT CARRIER LEVEL ERR"
  36. #define RMT_MEM_OWNER_ERROR_STR "RMT MEM OWNER_ERR"
  37. #define RMT_BASECLK_ERROR_STR "RMT BASECLK ERR"
  38. #define RMT_WR_MEM_OVF_ERROR_STR "RMT WR MEM OVERFLOW"
  39. #define RMT_GPIO_ERROR_STR "RMT GPIO ERROR"
  40. #define RMT_MODE_ERROR_STR "RMT MODE ERROR"
  41. #define RMT_CLK_DIV_ERROR_STR "RMT CLK DIV ERR"
  42. #define RMT_DRIVER_ERROR_STR "RMT DRIVER ERR"
  43. #define RMT_DRIVER_LENGTH_ERROR_STR "RMT PARAM LEN ERROR"
  44. #define RMT_PSRAM_BUFFER_WARN_STR "Using buffer allocated from psram"
  45. #define RMT_TRANSLATOR_NULL_STR "RMT translator is null"
  46. #define RMT_TRANSLATOR_UNINIT_STR "RMT translator not init"
  47. #define RMT_PARAM_ERR_STR "RMT param error"
  48. static const char *RMT_TAG = "rmt";
  49. #define RMT_CHECK(a, str, ret_val) \
  50. if (!(a)) \
  51. { \
  52. ESP_LOGE(RMT_TAG, "%s(%d): %s", __FUNCTION__, __LINE__, str); \
  53. return (ret_val); \
  54. }
  55. static uint8_t s_rmt_driver_channels; // Bitmask of installed drivers' channels
  56. // Spinlock for protecting concurrent register-level access only
  57. static portMUX_TYPE rmt_spinlock = portMUX_INITIALIZER_UNLOCKED;
  58. #define RMT_ENTER_CRITICAL() portENTER_CRITICAL_SAFE(&rmt_spinlock)
  59. #define RMT_EXIT_CRITICAL() portEXIT_CRITICAL_SAFE(&rmt_spinlock)
  60. // Mutex lock for protecting concurrent register/unregister of RMT channels' ISR
  61. static _lock_t rmt_driver_isr_lock;
  62. static rmt_isr_handle_t s_rmt_driver_intr_handle;
  63. typedef struct {
  64. rmt_hal_context_t hal;
  65. size_t tx_offset;
  66. size_t tx_len_rem;
  67. size_t tx_sub_len;
  68. bool translator;
  69. bool wait_done; //Mark whether wait tx done.
  70. rmt_channel_t channel;
  71. const rmt_item32_t *tx_data;
  72. xSemaphoreHandle tx_sem;
  73. #if CONFIG_SPIRAM_USE_MALLOC
  74. int intr_alloc_flags;
  75. StaticSemaphore_t tx_sem_buffer;
  76. #endif
  77. rmt_item32_t *tx_buf;
  78. RingbufHandle_t rx_buf;
  79. sample_to_rmt_t sample_to_rmt;
  80. size_t sample_size_remain;
  81. const uint8_t *sample_cur;
  82. } rmt_obj_t;
  83. rmt_obj_t *p_rmt_obj[RMT_CHANNEL_MAX] = {0};
  84. // Event called when transmission is ended
  85. static rmt_tx_end_callback_t rmt_tx_end_callback;
  86. esp_err_t rmt_set_clk_div(rmt_channel_t channel, uint8_t div_cnt)
  87. {
  88. RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
  89. RMT_ENTER_CRITICAL();
  90. rmt_ll_set_counter_clock_div(p_rmt_obj[channel]->hal.regs, channel, div_cnt);
  91. RMT_EXIT_CRITICAL();
  92. return ESP_OK;
  93. }
  94. esp_err_t rmt_get_clk_div(rmt_channel_t channel, uint8_t *div_cnt)
  95. {
  96. RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
  97. RMT_CHECK(div_cnt != NULL, RMT_ADDR_ERROR_STR, ESP_ERR_INVALID_ARG);
  98. RMT_ENTER_CRITICAL();
  99. *div_cnt = (uint8_t)rmt_ll_get_counter_clock_div(p_rmt_obj[channel]->hal.regs, channel);
  100. RMT_EXIT_CRITICAL();
  101. return ESP_OK;
  102. }
  103. esp_err_t rmt_set_rx_idle_thresh(rmt_channel_t channel, uint16_t thresh)
  104. {
  105. RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
  106. RMT_ENTER_CRITICAL();
  107. rmt_ll_set_rx_idle_thres(p_rmt_obj[channel]->hal.regs, channel, thresh);
  108. RMT_EXIT_CRITICAL();
  109. return ESP_OK;
  110. }
  111. esp_err_t rmt_get_rx_idle_thresh(rmt_channel_t channel, uint16_t *thresh)
  112. {
  113. RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
  114. RMT_CHECK(thresh != NULL, RMT_ADDR_ERROR_STR, ESP_ERR_INVALID_ARG);
  115. RMT_ENTER_CRITICAL();
  116. *thresh = (uint16_t)rmt_ll_get_rx_idle_thres(p_rmt_obj[channel]->hal.regs, channel);
  117. RMT_EXIT_CRITICAL();
  118. return ESP_OK;
  119. }
  120. esp_err_t rmt_set_mem_block_num(rmt_channel_t channel, uint8_t rmt_mem_num)
  121. {
  122. RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
  123. RMT_CHECK(rmt_mem_num <= RMT_CHANNEL_MAX - channel, RMT_MEM_CNT_ERROR_STR, ESP_ERR_INVALID_ARG);
  124. RMT_ENTER_CRITICAL();
  125. rmt_ll_set_mem_blocks(p_rmt_obj[channel]->hal.regs, channel, rmt_mem_num);
  126. RMT_EXIT_CRITICAL();
  127. return ESP_OK;
  128. }
  129. esp_err_t rmt_get_mem_block_num(rmt_channel_t channel, uint8_t *rmt_mem_num)
  130. {
  131. RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
  132. RMT_CHECK(rmt_mem_num != NULL, RMT_ADDR_ERROR_STR, ESP_ERR_INVALID_ARG);
  133. RMT_ENTER_CRITICAL();
  134. *rmt_mem_num = (uint8_t)rmt_ll_get_mem_blocks(p_rmt_obj[channel]->hal.regs, channel);
  135. RMT_EXIT_CRITICAL();
  136. return ESP_OK;
  137. }
  138. esp_err_t rmt_set_tx_carrier(rmt_channel_t channel, bool carrier_en, uint16_t high_level, uint16_t low_level,
  139. rmt_carrier_level_t carrier_level)
  140. {
  141. RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
  142. RMT_CHECK(carrier_level < RMT_CARRIER_LEVEL_MAX, RMT_CARRIER_ERROR_STR, ESP_ERR_INVALID_ARG);
  143. RMT_ENTER_CRITICAL();
  144. rmt_ll_set_carrier_high_low_ticks(p_rmt_obj[channel]->hal.regs, channel, high_level, low_level);
  145. rmt_ll_set_carrier_to_level(p_rmt_obj[channel]->hal.regs, channel, carrier_level);
  146. rmt_ll_enable_tx_carrier(p_rmt_obj[channel]->hal.regs, channel, carrier_en);
  147. RMT_EXIT_CRITICAL();
  148. return ESP_OK;
  149. }
  150. esp_err_t rmt_set_mem_pd(rmt_channel_t channel, bool pd_en)
  151. {
  152. RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
  153. RMT_ENTER_CRITICAL();
  154. rmt_ll_power_down_mem(p_rmt_obj[channel]->hal.regs, channel, pd_en);
  155. RMT_EXIT_CRITICAL();
  156. return ESP_OK;
  157. }
  158. esp_err_t rmt_get_mem_pd(rmt_channel_t channel, bool *pd_en)
  159. {
  160. RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
  161. RMT_ENTER_CRITICAL();
  162. *pd_en = rmt_ll_is_mem_power_down(p_rmt_obj[channel]->hal.regs, channel);
  163. RMT_EXIT_CRITICAL();
  164. return ESP_OK;
  165. }
  166. esp_err_t rmt_tx_start(rmt_channel_t channel, bool tx_idx_rst)
  167. {
  168. RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
  169. RMT_ENTER_CRITICAL();
  170. if (tx_idx_rst) {
  171. rmt_ll_reset_tx_pointer(p_rmt_obj[channel]->hal.regs, channel);
  172. }
  173. rmt_ll_clear_tx_end_interrupt(p_rmt_obj[channel]->hal.regs, channel);
  174. rmt_ll_enable_tx_end_interrupt(p_rmt_obj[channel]->hal.regs, channel, true);
  175. rmt_ll_start_tx(p_rmt_obj[channel]->hal.regs, channel);
  176. RMT_EXIT_CRITICAL();
  177. return ESP_OK;
  178. }
  179. esp_err_t rmt_tx_stop(rmt_channel_t channel)
  180. {
  181. RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
  182. RMT_ENTER_CRITICAL();
  183. rmt_ll_stop_tx(p_rmt_obj[channel]->hal.regs, channel);
  184. rmt_ll_reset_tx_pointer(p_rmt_obj[channel]->hal.regs, channel);
  185. RMT_EXIT_CRITICAL();
  186. return ESP_OK;
  187. }
  188. esp_err_t rmt_rx_start(rmt_channel_t channel, bool rx_idx_rst)
  189. {
  190. RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
  191. RMT_ENTER_CRITICAL();
  192. rmt_ll_enable_rx(p_rmt_obj[channel]->hal.regs, channel, false);
  193. if (rx_idx_rst) {
  194. rmt_ll_reset_rx_pointer(p_rmt_obj[channel]->hal.regs, channel);
  195. }
  196. rmt_ll_clear_rx_end_interrupt(p_rmt_obj[channel]->hal.regs, channel);
  197. rmt_ll_enable_rx_end_interrupt(p_rmt_obj[channel]->hal.regs, channel, true);
  198. rmt_ll_enable_rx(p_rmt_obj[channel]->hal.regs, channel, true);
  199. RMT_EXIT_CRITICAL();
  200. return ESP_OK;
  201. }
  202. esp_err_t rmt_rx_stop(rmt_channel_t channel)
  203. {
  204. RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
  205. RMT_ENTER_CRITICAL();
  206. rmt_ll_enable_rx(p_rmt_obj[channel]->hal.regs, channel, false);
  207. rmt_ll_enable_rx_end_interrupt(p_rmt_obj[channel]->hal.regs, channel, false);
  208. RMT_EXIT_CRITICAL();
  209. return ESP_OK;
  210. }
  211. esp_err_t rmt_memory_rw_rst(rmt_channel_t channel)
  212. {
  213. RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
  214. RMT_ENTER_CRITICAL();
  215. rmt_ll_reset_tx_pointer(p_rmt_obj[channel]->hal.regs, channel);
  216. rmt_ll_reset_rx_pointer(p_rmt_obj[channel]->hal.regs, channel);
  217. RMT_EXIT_CRITICAL();
  218. return ESP_OK;
  219. }
  220. esp_err_t rmt_set_memory_owner(rmt_channel_t channel, rmt_mem_owner_t owner)
  221. {
  222. RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
  223. RMT_CHECK(owner < RMT_MEM_OWNER_MAX, RMT_MEM_OWNER_ERROR_STR, ESP_ERR_INVALID_ARG);
  224. RMT_ENTER_CRITICAL();
  225. rmt_ll_set_mem_owner(p_rmt_obj[channel]->hal.regs, channel, owner);
  226. RMT_EXIT_CRITICAL();
  227. return ESP_OK;
  228. }
  229. esp_err_t rmt_get_memory_owner(rmt_channel_t channel, rmt_mem_owner_t *owner)
  230. {
  231. RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
  232. RMT_CHECK(owner != NULL, RMT_MEM_OWNER_ERROR_STR, ESP_ERR_INVALID_ARG);
  233. RMT_ENTER_CRITICAL();
  234. *owner = (rmt_mem_owner_t)rmt_ll_get_mem_owner(p_rmt_obj[channel]->hal.regs, channel);
  235. RMT_EXIT_CRITICAL();
  236. return ESP_OK;
  237. }
  238. esp_err_t rmt_set_tx_loop_mode(rmt_channel_t channel, bool loop_en)
  239. {
  240. RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
  241. RMT_ENTER_CRITICAL();
  242. rmt_ll_enable_tx_cyclic(p_rmt_obj[channel]->hal.regs, channel, loop_en);
  243. RMT_EXIT_CRITICAL();
  244. return ESP_OK;
  245. }
  246. esp_err_t rmt_get_tx_loop_mode(rmt_channel_t channel, bool *loop_en)
  247. {
  248. RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
  249. RMT_ENTER_CRITICAL();
  250. *loop_en = rmt_ll_is_tx_cyclic_enabled(p_rmt_obj[channel]->hal.regs, channel);
  251. RMT_EXIT_CRITICAL();
  252. return ESP_OK;
  253. }
  254. esp_err_t rmt_set_rx_filter(rmt_channel_t channel, bool rx_filter_en, uint8_t thresh)
  255. {
  256. RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
  257. RMT_ENTER_CRITICAL();
  258. rmt_ll_enable_rx_filter(p_rmt_obj[channel]->hal.regs, channel, rx_filter_en);
  259. rmt_ll_set_rx_filter_thres(p_rmt_obj[channel]->hal.regs, channel, thresh);
  260. RMT_EXIT_CRITICAL();
  261. return ESP_OK;
  262. }
  263. esp_err_t rmt_set_source_clk(rmt_channel_t channel, rmt_source_clk_t base_clk)
  264. {
  265. RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
  266. RMT_CHECK(base_clk < RMT_BASECLK_MAX, RMT_BASECLK_ERROR_STR, ESP_ERR_INVALID_ARG);
  267. RMT_ENTER_CRITICAL();
  268. rmt_ll_set_counter_clock_src(p_rmt_obj[channel]->hal.regs, channel, base_clk);
  269. RMT_EXIT_CRITICAL();
  270. return ESP_OK;
  271. }
  272. esp_err_t rmt_get_source_clk(rmt_channel_t channel, rmt_source_clk_t *src_clk)
  273. {
  274. RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
  275. RMT_ENTER_CRITICAL();
  276. *src_clk = (rmt_source_clk_t)rmt_ll_get_counter_clock_src(p_rmt_obj[channel]->hal.regs, channel);
  277. RMT_EXIT_CRITICAL();
  278. return ESP_OK;
  279. }
  280. esp_err_t rmt_set_idle_level(rmt_channel_t channel, bool idle_out_en, rmt_idle_level_t level)
  281. {
  282. RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
  283. RMT_CHECK(level < RMT_IDLE_LEVEL_MAX, "RMT IDLE LEVEL ERR", ESP_ERR_INVALID_ARG);
  284. RMT_ENTER_CRITICAL();
  285. rmt_ll_enable_tx_idle(p_rmt_obj[channel]->hal.regs, channel, idle_out_en);
  286. rmt_ll_set_tx_idle_level(p_rmt_obj[channel]->hal.regs, channel, level);
  287. RMT_EXIT_CRITICAL();
  288. return ESP_OK;
  289. }
  290. esp_err_t rmt_get_idle_level(rmt_channel_t channel, bool *idle_out_en, rmt_idle_level_t *level)
  291. {
  292. RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
  293. RMT_ENTER_CRITICAL();
  294. *idle_out_en = rmt_ll_is_tx_idle_enabled(p_rmt_obj[channel]->hal.regs, channel);
  295. *level = rmt_ll_get_tx_idle_level(p_rmt_obj[channel]->hal.regs, channel);
  296. RMT_EXIT_CRITICAL();
  297. return ESP_OK;
  298. }
  299. esp_err_t rmt_get_status(rmt_channel_t channel, uint32_t *status)
  300. {
  301. RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
  302. RMT_ENTER_CRITICAL();
  303. *status = rmt_ll_get_channel_status(p_rmt_obj[channel]->hal.regs, channel);
  304. RMT_EXIT_CRITICAL();
  305. return ESP_OK;
  306. }
  307. void rmt_set_intr_enable_mask(uint32_t mask)
  308. {
  309. RMT_ENTER_CRITICAL();
  310. rmt_ll_set_intr_enable_mask(mask);
  311. RMT_EXIT_CRITICAL();
  312. }
  313. void rmt_clr_intr_enable_mask(uint32_t mask)
  314. {
  315. RMT_ENTER_CRITICAL();
  316. rmt_ll_clr_intr_enable_mask(mask);
  317. RMT_EXIT_CRITICAL();
  318. }
  319. esp_err_t rmt_set_rx_intr_en(rmt_channel_t channel, bool en)
  320. {
  321. RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
  322. RMT_ENTER_CRITICAL();
  323. rmt_ll_enable_rx_end_interrupt(p_rmt_obj[channel]->hal.regs, channel, en);
  324. RMT_EXIT_CRITICAL();
  325. return ESP_OK;
  326. }
  327. esp_err_t rmt_set_err_intr_en(rmt_channel_t channel, bool en)
  328. {
  329. RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
  330. RMT_ENTER_CRITICAL();
  331. rmt_ll_enable_err_interrupt(p_rmt_obj[channel]->hal.regs, channel, en);
  332. RMT_EXIT_CRITICAL();
  333. return ESP_OK;
  334. }
  335. esp_err_t rmt_set_tx_intr_en(rmt_channel_t channel, bool en)
  336. {
  337. RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
  338. RMT_ENTER_CRITICAL();
  339. rmt_ll_enable_tx_end_interrupt(p_rmt_obj[channel]->hal.regs, channel, en);
  340. RMT_EXIT_CRITICAL();
  341. return ESP_OK;
  342. }
  343. esp_err_t rmt_set_tx_thr_intr_en(rmt_channel_t channel, bool en, uint16_t evt_thresh)
  344. {
  345. RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
  346. if (en) {
  347. RMT_CHECK(evt_thresh <= 256, "RMT EVT THRESH ERR", ESP_ERR_INVALID_ARG);
  348. RMT_ENTER_CRITICAL();
  349. rmt_ll_set_tx_limit(p_rmt_obj[channel]->hal.regs, channel, evt_thresh);
  350. rmt_ll_enable_tx_thres_interrupt(p_rmt_obj[channel]->hal.regs, channel, true);
  351. RMT_EXIT_CRITICAL();
  352. } else {
  353. RMT_ENTER_CRITICAL();
  354. rmt_ll_enable_tx_thres_interrupt(p_rmt_obj[channel]->hal.regs, channel, false);
  355. RMT_EXIT_CRITICAL();
  356. }
  357. return ESP_OK;
  358. }
  359. esp_err_t rmt_set_pin(rmt_channel_t channel, rmt_mode_t mode, gpio_num_t gpio_num)
  360. {
  361. RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
  362. RMT_CHECK(mode < RMT_MODE_MAX, RMT_MODE_ERROR_STR, ESP_ERR_INVALID_ARG);
  363. RMT_CHECK(((GPIO_IS_VALID_GPIO(gpio_num) && (mode == RMT_MODE_RX)) ||
  364. (GPIO_IS_VALID_OUTPUT_GPIO(gpio_num) && (mode == RMT_MODE_TX))),
  365. RMT_GPIO_ERROR_STR, ESP_ERR_INVALID_ARG);
  366. PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[gpio_num], PIN_FUNC_GPIO);
  367. if (mode == RMT_MODE_TX) {
  368. gpio_set_direction(gpio_num, GPIO_MODE_OUTPUT);
  369. gpio_matrix_out(gpio_num, RMT_SIG_OUT0_IDX + channel, 0, 0);
  370. } else {
  371. gpio_set_direction(gpio_num, GPIO_MODE_INPUT);
  372. gpio_matrix_in(gpio_num, RMT_SIG_IN0_IDX + channel, 0);
  373. }
  374. return ESP_OK;
  375. }
  376. static esp_err_t rmt_internal_config(rmt_dev_t *dev, const rmt_config_t *rmt_param)
  377. {
  378. uint8_t mode = rmt_param->rmt_mode;
  379. uint8_t channel = rmt_param->channel;
  380. uint8_t gpio_num = rmt_param->gpio_num;
  381. uint8_t mem_cnt = rmt_param->mem_block_num;
  382. uint8_t clk_div = rmt_param->clk_div;
  383. uint32_t carrier_freq_hz = rmt_param->tx_config.carrier_freq_hz;
  384. bool carrier_en = rmt_param->tx_config.carrier_en;
  385. RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
  386. RMT_CHECK((mem_cnt + channel <= 8 && mem_cnt > 0), RMT_MEM_CNT_ERROR_STR, ESP_ERR_INVALID_ARG);
  387. RMT_CHECK((clk_div > 0), RMT_CLK_DIV_ERROR_STR, ESP_ERR_INVALID_ARG);
  388. if (mode == RMT_MODE_TX) {
  389. RMT_CHECK((!carrier_en || carrier_freq_hz > 0), "RMT carrier frequency can't be zero", ESP_ERR_INVALID_ARG);
  390. }
  391. RMT_ENTER_CRITICAL();
  392. rmt_ll_set_counter_clock_div(dev, channel, clk_div);
  393. rmt_ll_enable_mem_access(dev, true);
  394. rmt_ll_reset_tx_pointer(dev, channel);
  395. rmt_ll_reset_rx_pointer(dev, channel);
  396. rmt_ll_set_counter_clock_src(dev, channel, RMT_BASECLK_APB); // only support APB clock for now
  397. rmt_ll_set_mem_blocks(dev, channel, mem_cnt);
  398. rmt_ll_set_mem_owner(dev, channel, RMT_MEM_OWNER_HW);
  399. RMT_EXIT_CRITICAL();
  400. uint32_t rmt_source_clk_hz = RMT_SOURCE_CLK(RMT_BASECLK_APB);
  401. if (mode == RMT_MODE_TX) {
  402. uint16_t carrier_duty_percent = rmt_param->tx_config.carrier_duty_percent;
  403. uint8_t carrier_level = rmt_param->tx_config.carrier_level;
  404. uint8_t idle_level = rmt_param->tx_config.idle_level;
  405. RMT_ENTER_CRITICAL();
  406. rmt_ll_enable_tx_cyclic(dev, channel, rmt_param->tx_config.loop_en);
  407. rmt_ll_enable_tx_pingpong(dev, true);
  408. /*Set idle level */
  409. rmt_ll_enable_tx_idle(dev, channel, rmt_param->tx_config.idle_output_en);
  410. rmt_ll_set_tx_idle_level(dev, channel, idle_level);
  411. /*Set carrier*/
  412. rmt_ll_enable_tx_carrier(dev, channel, carrier_en);
  413. if (carrier_en) {
  414. uint32_t duty_div, duty_h, duty_l;
  415. duty_div = rmt_source_clk_hz / carrier_freq_hz;
  416. duty_h = duty_div * carrier_duty_percent / 100;
  417. duty_l = duty_div - duty_h;
  418. rmt_ll_set_carrier_to_level(dev, channel, carrier_level);
  419. rmt_ll_set_carrier_high_low_ticks(dev, channel, duty_h, duty_l);
  420. } else {
  421. rmt_ll_set_carrier_to_level(dev, channel, 0);
  422. rmt_ll_set_carrier_high_low_ticks(dev, channel, 0, 0);
  423. }
  424. RMT_EXIT_CRITICAL();
  425. ESP_LOGD(RMT_TAG, "Rmt Tx Channel %u|Gpio %u|Sclk_Hz %u|Div %u|Carrier_Hz %u|Duty %u",
  426. channel, gpio_num, rmt_source_clk_hz, clk_div, carrier_freq_hz, carrier_duty_percent);
  427. } else if (RMT_MODE_RX == mode) {
  428. uint8_t filter_cnt = rmt_param->rx_config.filter_ticks_thresh;
  429. uint16_t threshold = rmt_param->rx_config.idle_threshold;
  430. RMT_ENTER_CRITICAL();
  431. /*Set idle threshold*/
  432. rmt_ll_set_rx_idle_thres(dev, channel, threshold);
  433. /* Set RX filter */
  434. rmt_ll_set_rx_filter_thres(dev, channel, filter_cnt);
  435. rmt_ll_enable_rx_filter(dev, channel, rmt_param->rx_config.filter_en);
  436. RMT_EXIT_CRITICAL();
  437. ESP_LOGD(RMT_TAG, "Rmt Rx Channel %u|Gpio %u|Sclk_Hz %u|Div %u|Thresold %u|Filter %u",
  438. channel, gpio_num, rmt_source_clk_hz, clk_div, threshold, filter_cnt);
  439. }
  440. return ESP_OK;
  441. }
  442. esp_err_t rmt_config(const rmt_config_t *rmt_param)
  443. {
  444. // reset the RMT module at the first time initialize RMT driver
  445. static bool rmt_module_enabled = false;
  446. if (rmt_module_enabled == false) {
  447. periph_module_reset(PERIPH_RMT_MODULE);
  448. rmt_module_enabled = true;
  449. }
  450. periph_module_enable(PERIPH_RMT_MODULE);
  451. RMT_CHECK(rmt_set_pin(rmt_param->channel, rmt_param->rmt_mode, rmt_param->gpio_num) == ESP_OK,
  452. "set gpio for RMT driver failed", ESP_ERR_INVALID_ARG);
  453. RMT_CHECK(rmt_internal_config(&RMT, rmt_param) == ESP_OK,
  454. "initialize RMT driver failed", ESP_ERR_INVALID_ARG);
  455. return ESP_OK;
  456. }
  457. static void IRAM_ATTR rmt_fill_memory(rmt_channel_t channel, const rmt_item32_t *item,
  458. uint16_t item_num, uint16_t mem_offset)
  459. {
  460. RMT_ENTER_CRITICAL();
  461. rmt_ll_set_mem_owner(p_rmt_obj[channel]->hal.regs, channel, RMT_MEM_OWNER_SW);
  462. rmt_ll_write_memory(p_rmt_obj[channel]->hal.mem, channel, item, item_num, mem_offset);
  463. rmt_ll_set_mem_owner(p_rmt_obj[channel]->hal.regs, channel, RMT_MEM_OWNER_HW);
  464. RMT_EXIT_CRITICAL();
  465. }
  466. esp_err_t rmt_fill_tx_items(rmt_channel_t channel, const rmt_item32_t *item, uint16_t item_num, uint16_t mem_offset)
  467. {
  468. RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, (0));
  469. RMT_CHECK((item != NULL), RMT_ADDR_ERROR_STR, ESP_ERR_INVALID_ARG);
  470. RMT_CHECK((item_num > 0), RMT_DRIVER_LENGTH_ERROR_STR, ESP_ERR_INVALID_ARG);
  471. /*Each block has 64 x 32 bits of data*/
  472. uint8_t mem_cnt = rmt_ll_get_mem_blocks(p_rmt_obj[channel]->hal.regs, channel);
  473. RMT_CHECK((mem_cnt * RMT_MEM_ITEM_NUM >= item_num), RMT_WR_MEM_OVF_ERROR_STR, ESP_ERR_INVALID_ARG);
  474. rmt_fill_memory(channel, item, item_num, mem_offset);
  475. return ESP_OK;
  476. }
  477. esp_err_t rmt_isr_register(void (*fn)(void *), void *arg, int intr_alloc_flags, rmt_isr_handle_t *handle)
  478. {
  479. RMT_CHECK((fn != NULL), RMT_ADDR_ERROR_STR, ESP_ERR_INVALID_ARG);
  480. RMT_CHECK(s_rmt_driver_channels == 0, "RMT driver installed, can not install generic ISR handler", ESP_FAIL);
  481. return esp_intr_alloc(ETS_RMT_INTR_SOURCE, intr_alloc_flags, fn, arg, handle);
  482. }
  483. esp_err_t rmt_isr_deregister(rmt_isr_handle_t handle)
  484. {
  485. return esp_intr_free(handle);
  486. }
  487. static int IRAM_ATTR rmt_get_mem_len(rmt_channel_t channel)
  488. {
  489. int block_num = rmt_ll_get_mem_blocks(p_rmt_obj[channel]->hal.regs, channel);
  490. int item_block_len = block_num * RMT_MEM_ITEM_NUM;
  491. volatile rmt_item32_t *data = (rmt_item32_t *)RMTMEM.chan[channel].data32;
  492. int idx;
  493. for (idx = 0; idx < item_block_len; idx++) {
  494. if (data[idx].duration0 == 0) {
  495. return idx;
  496. } else if (data[idx].duration1 == 0) {
  497. return idx + 1;
  498. }
  499. }
  500. return idx;
  501. }
  502. static void IRAM_ATTR rmt_driver_isr_default(void *arg)
  503. {
  504. uint32_t status = 0;
  505. rmt_item32_t volatile *addr = NULL;
  506. uint8_t channel = 0;
  507. rmt_hal_context_t *hal = (rmt_hal_context_t *)arg;
  508. portBASE_TYPE HPTaskAwoken = pdFALSE;
  509. // Tx end interrupt
  510. status = rmt_ll_get_tx_end_interrupt_status(hal->regs);
  511. while (status) {
  512. channel = __builtin_ffs(status) - 1;
  513. status &= ~(1 << channel);
  514. rmt_obj_t *p_rmt = p_rmt_obj[channel];
  515. if (p_rmt) {
  516. xSemaphoreGiveFromISR(p_rmt->tx_sem, &HPTaskAwoken);
  517. rmt_ll_reset_tx_pointer(p_rmt_obj[channel]->hal.regs, channel);
  518. p_rmt->tx_data = NULL;
  519. p_rmt->tx_len_rem = 0;
  520. p_rmt->tx_offset = 0;
  521. p_rmt->tx_sub_len = 0;
  522. p_rmt->sample_cur = NULL;
  523. p_rmt->translator = false;
  524. if (rmt_tx_end_callback.function != NULL) {
  525. rmt_tx_end_callback.function(channel, rmt_tx_end_callback.arg);
  526. }
  527. }
  528. rmt_ll_clear_tx_end_interrupt(hal->regs, channel);
  529. }
  530. // Tx thres interrupt
  531. status = rmt_ll_get_tx_thres_interrupt_status(hal->regs);
  532. while (status) {
  533. channel = __builtin_ffs(status) - 1;
  534. status &= ~(1 << channel);
  535. rmt_obj_t *p_rmt = p_rmt_obj[channel];
  536. if (p_rmt) {
  537. if (p_rmt->translator) {
  538. if (p_rmt->sample_size_remain > 0) {
  539. size_t translated_size = 0;
  540. p_rmt->sample_to_rmt((void *)p_rmt->sample_cur,
  541. p_rmt->tx_buf,
  542. p_rmt->sample_size_remain,
  543. p_rmt->tx_sub_len,
  544. &translated_size,
  545. &p_rmt->tx_len_rem);
  546. p_rmt->sample_size_remain -= translated_size;
  547. p_rmt->sample_cur += translated_size;
  548. p_rmt->tx_data = p_rmt->tx_buf;
  549. } else {
  550. p_rmt->sample_cur = NULL;
  551. p_rmt->translator = false;
  552. }
  553. }
  554. const rmt_item32_t *pdata = p_rmt->tx_data;
  555. int len_rem = p_rmt->tx_len_rem;
  556. if (len_rem >= p_rmt->tx_sub_len) {
  557. rmt_fill_memory(channel, pdata, p_rmt->tx_sub_len, p_rmt->tx_offset);
  558. p_rmt->tx_data += p_rmt->tx_sub_len;
  559. p_rmt->tx_len_rem -= p_rmt->tx_sub_len;
  560. } else if (len_rem == 0) {
  561. rmt_item32_t stop_data = {0};
  562. rmt_ll_write_memory(p_rmt_obj[channel]->hal.mem, channel, &stop_data, 1, p_rmt->tx_offset);
  563. } else {
  564. rmt_fill_memory(channel, pdata, len_rem, p_rmt->tx_offset);
  565. rmt_item32_t stop_data = {0};
  566. rmt_ll_write_memory(p_rmt_obj[channel]->hal.mem, channel, &stop_data, 1, p_rmt->tx_offset + len_rem);
  567. p_rmt->tx_data += len_rem;
  568. p_rmt->tx_len_rem -= len_rem;
  569. }
  570. if (p_rmt->tx_offset == 0) {
  571. p_rmt->tx_offset = p_rmt->tx_sub_len;
  572. } else {
  573. p_rmt->tx_offset = 0;
  574. }
  575. }
  576. rmt_ll_clear_tx_thres_interrupt(hal->regs, channel);
  577. }
  578. // Rx end interrupt
  579. status = rmt_ll_get_rx_end_interrupt_status(hal->regs);
  580. while (status) {
  581. channel = __builtin_ffs(status) - 1;
  582. status &= ~(1 << channel);
  583. rmt_obj_t *p_rmt = p_rmt_obj[channel];
  584. if (p_rmt) {
  585. rmt_ll_enable_rx(p_rmt_obj[channel]->hal.regs, channel, false);
  586. int item_len = rmt_get_mem_len(channel);
  587. rmt_ll_set_mem_owner(p_rmt_obj[channel]->hal.regs, channel, RMT_MEM_OWNER_SW);
  588. if (p_rmt->rx_buf) {
  589. addr = RMTMEM.chan[channel].data32;
  590. BaseType_t res = xRingbufferSendFromISR(p_rmt->rx_buf, (void *)addr, item_len * 4, &HPTaskAwoken);
  591. if (res == pdFALSE) {
  592. ESP_EARLY_LOGE(RMT_TAG, "RMT RX BUFFER FULL");
  593. }
  594. } else {
  595. ESP_EARLY_LOGE(RMT_TAG, "RMT RX BUFFER ERROR");
  596. }
  597. rmt_ll_reset_rx_pointer(p_rmt_obj[channel]->hal.regs, channel);
  598. rmt_ll_set_mem_owner(p_rmt_obj[channel]->hal.regs, channel, RMT_MEM_OWNER_HW);
  599. rmt_ll_enable_rx(p_rmt_obj[channel]->hal.regs, channel, true);
  600. }
  601. rmt_ll_clear_rx_end_interrupt(hal->regs, channel);
  602. }
  603. // Err interrupt
  604. status = rmt_ll_get_err_interrupt_status(hal->regs);
  605. while (status) {
  606. channel = __builtin_ffs(status) - 1;
  607. status &= ~(1 << channel);
  608. rmt_obj_t *p_rmt = p_rmt_obj[channel];
  609. if (p_rmt) {
  610. // Reset the receiver/transmitter's write/read addresses to prevent endless err interrupts.
  611. rmt_ll_reset_tx_pointer(p_rmt_obj[channel]->hal.regs, channel);
  612. rmt_ll_reset_rx_pointer(p_rmt_obj[channel]->hal.regs, channel);
  613. ESP_EARLY_LOGD(RMT_TAG, "RMT[%d] ERR", channel);
  614. ESP_EARLY_LOGD(RMT_TAG, "status: 0x%08x", rmt_ll_get_channel_status(p_rmt_obj[channel]->hal.regs, channel));
  615. }
  616. rmt_ll_clear_err_interrupt(hal->regs, channel);
  617. }
  618. if (HPTaskAwoken == pdTRUE) {
  619. portYIELD_FROM_ISR();
  620. }
  621. }
  622. esp_err_t rmt_driver_uninstall(rmt_channel_t channel)
  623. {
  624. esp_err_t err = ESP_OK;
  625. RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
  626. RMT_CHECK((s_rmt_driver_channels & BIT(channel)) != 0, "No RMT driver for this channel", ESP_ERR_INVALID_STATE);
  627. if (p_rmt_obj[channel] == NULL) {
  628. return ESP_OK;
  629. }
  630. //Avoid blocking here(when the interrupt is disabled and do not wait tx done).
  631. if (p_rmt_obj[channel]->wait_done) {
  632. xSemaphoreTake(p_rmt_obj[channel]->tx_sem, portMAX_DELAY);
  633. }
  634. rmt_set_rx_intr_en(channel, 0);
  635. rmt_set_err_intr_en(channel, 0);
  636. rmt_set_tx_intr_en(channel, 0);
  637. rmt_set_tx_thr_intr_en(channel, 0, 0xffff);
  638. _lock_acquire_recursive(&rmt_driver_isr_lock);
  639. s_rmt_driver_channels &= ~BIT(channel);
  640. if (s_rmt_driver_channels == 0) {
  641. // all channels have driver disabled
  642. err = rmt_isr_deregister(s_rmt_driver_intr_handle);
  643. s_rmt_driver_intr_handle = NULL;
  644. }
  645. _lock_release_recursive(&rmt_driver_isr_lock);
  646. if (err != ESP_OK) {
  647. return err;
  648. }
  649. if (p_rmt_obj[channel]->tx_sem) {
  650. vSemaphoreDelete(p_rmt_obj[channel]->tx_sem);
  651. p_rmt_obj[channel]->tx_sem = NULL;
  652. }
  653. if (p_rmt_obj[channel]->rx_buf) {
  654. vRingbufferDelete(p_rmt_obj[channel]->rx_buf);
  655. p_rmt_obj[channel]->rx_buf = NULL;
  656. }
  657. if (p_rmt_obj[channel]->tx_buf) {
  658. free(p_rmt_obj[channel]->tx_buf);
  659. p_rmt_obj[channel]->tx_buf = NULL;
  660. }
  661. if (p_rmt_obj[channel]->sample_to_rmt) {
  662. p_rmt_obj[channel]->sample_to_rmt = NULL;
  663. }
  664. free(p_rmt_obj[channel]);
  665. p_rmt_obj[channel] = NULL;
  666. return ESP_OK;
  667. }
  668. esp_err_t rmt_driver_install(rmt_channel_t channel, size_t rx_buf_size, int intr_alloc_flags)
  669. {
  670. RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
  671. RMT_CHECK((s_rmt_driver_channels & BIT(channel)) == 0,
  672. "RMT driver already installed for channel", ESP_ERR_INVALID_STATE);
  673. esp_err_t err = ESP_OK;
  674. if (p_rmt_obj[channel] != NULL) {
  675. ESP_LOGD(RMT_TAG, "RMT driver already installed");
  676. return ESP_ERR_INVALID_STATE;
  677. }
  678. #if !CONFIG_SPIRAM_USE_MALLOC
  679. p_rmt_obj[channel] = (rmt_obj_t *)malloc(sizeof(rmt_obj_t));
  680. #else
  681. if (!(intr_alloc_flags & ESP_INTR_FLAG_IRAM)) {
  682. p_rmt_obj[channel] = (rmt_obj_t *)malloc(sizeof(rmt_obj_t));
  683. } else {
  684. p_rmt_obj[channel] = (rmt_obj_t *)heap_caps_calloc(1, sizeof(rmt_obj_t), MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
  685. }
  686. #endif
  687. if (p_rmt_obj[channel] == NULL) {
  688. ESP_LOGE(RMT_TAG, "RMT driver malloc error");
  689. return ESP_ERR_NO_MEM;
  690. }
  691. memset(p_rmt_obj[channel], 0, sizeof(rmt_obj_t));
  692. rmt_hal_init(&p_rmt_obj[channel]->hal);
  693. rmt_hal_channel_reset(&p_rmt_obj[channel]->hal, channel);
  694. p_rmt_obj[channel]->tx_len_rem = 0;
  695. p_rmt_obj[channel]->tx_data = NULL;
  696. p_rmt_obj[channel]->channel = channel;
  697. p_rmt_obj[channel]->tx_offset = 0;
  698. p_rmt_obj[channel]->tx_sub_len = 0;
  699. p_rmt_obj[channel]->wait_done = false;
  700. p_rmt_obj[channel]->translator = false;
  701. p_rmt_obj[channel]->sample_to_rmt = NULL;
  702. if (p_rmt_obj[channel]->tx_sem == NULL) {
  703. #if !CONFIG_SPIRAM_USE_MALLOC
  704. p_rmt_obj[channel]->tx_sem = xSemaphoreCreateBinary();
  705. #else
  706. p_rmt_obj[channel]->intr_alloc_flags = intr_alloc_flags;
  707. if (!(intr_alloc_flags & ESP_INTR_FLAG_IRAM)) {
  708. p_rmt_obj[channel]->tx_sem = xSemaphoreCreateBinary();
  709. } else {
  710. p_rmt_obj[channel]->tx_sem = xSemaphoreCreateBinaryStatic(&p_rmt_obj[channel]->tx_sem_buffer);
  711. }
  712. #endif
  713. xSemaphoreGive(p_rmt_obj[channel]->tx_sem);
  714. }
  715. if (p_rmt_obj[channel]->rx_buf == NULL && rx_buf_size > 0) {
  716. p_rmt_obj[channel]->rx_buf = xRingbufferCreate(rx_buf_size, RINGBUF_TYPE_NOSPLIT);
  717. }
  718. rmt_set_err_intr_en(channel, 1);
  719. _lock_acquire_recursive(&rmt_driver_isr_lock);
  720. if (s_rmt_driver_channels == 0) {
  721. // first RMT channel using driver
  722. err = rmt_isr_register(rmt_driver_isr_default, &p_rmt_obj[channel]->hal, intr_alloc_flags, &s_rmt_driver_intr_handle);
  723. }
  724. if (err == ESP_OK) {
  725. s_rmt_driver_channels |= BIT(channel);
  726. }
  727. _lock_release_recursive(&rmt_driver_isr_lock);
  728. return err;
  729. }
  730. esp_err_t rmt_write_items(rmt_channel_t channel, const rmt_item32_t *rmt_item, int item_num, bool wait_tx_done)
  731. {
  732. RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
  733. RMT_CHECK(p_rmt_obj[channel] != NULL, RMT_DRIVER_ERROR_STR, ESP_FAIL);
  734. RMT_CHECK(rmt_item != NULL, RMT_ADDR_ERROR_STR, ESP_FAIL);
  735. RMT_CHECK(item_num > 0, RMT_DRIVER_LENGTH_ERROR_STR, ESP_ERR_INVALID_ARG);
  736. #if CONFIG_SPIRAM_USE_MALLOC
  737. if (p_rmt_obj[channel]->intr_alloc_flags & ESP_INTR_FLAG_IRAM) {
  738. if (!esp_ptr_internal(rmt_item)) {
  739. ESP_LOGE(RMT_TAG, RMT_PSRAM_BUFFER_WARN_STR);
  740. return ESP_ERR_INVALID_ARG;
  741. }
  742. }
  743. #endif
  744. rmt_obj_t *p_rmt = p_rmt_obj[channel];
  745. int block_num = rmt_ll_get_mem_blocks(p_rmt_obj[channel]->hal.regs, channel);
  746. int item_block_len = block_num * RMT_MEM_ITEM_NUM;
  747. int item_sub_len = block_num * RMT_MEM_ITEM_NUM / 2;
  748. int len_rem = item_num;
  749. xSemaphoreTake(p_rmt->tx_sem, portMAX_DELAY);
  750. // fill the memory block first
  751. if (item_num >= item_block_len) {
  752. rmt_fill_memory(channel, rmt_item, item_block_len, 0);
  753. len_rem -= item_block_len;
  754. rmt_set_tx_loop_mode(channel, false);
  755. rmt_set_tx_thr_intr_en(channel, 1, item_sub_len);
  756. p_rmt->tx_data = rmt_item + item_block_len;
  757. p_rmt->tx_len_rem = len_rem;
  758. p_rmt->tx_offset = 0;
  759. p_rmt->tx_sub_len = item_sub_len;
  760. } else {
  761. rmt_fill_memory(channel, rmt_item, len_rem, 0);
  762. rmt_item32_t stop_data = {0};
  763. rmt_ll_write_memory(p_rmt_obj[channel]->hal.mem, channel, &stop_data, 1, len_rem);
  764. p_rmt->tx_len_rem = 0;
  765. }
  766. rmt_tx_start(channel, true);
  767. p_rmt->wait_done = wait_tx_done;
  768. if (wait_tx_done) {
  769. xSemaphoreTake(p_rmt->tx_sem, portMAX_DELAY);
  770. xSemaphoreGive(p_rmt->tx_sem);
  771. }
  772. return ESP_OK;
  773. }
  774. esp_err_t rmt_wait_tx_done(rmt_channel_t channel, TickType_t wait_time)
  775. {
  776. RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
  777. RMT_CHECK(p_rmt_obj[channel] != NULL, RMT_DRIVER_ERROR_STR, ESP_FAIL);
  778. if (xSemaphoreTake(p_rmt_obj[channel]->tx_sem, wait_time) == pdTRUE) {
  779. p_rmt_obj[channel]->wait_done = false;
  780. xSemaphoreGive(p_rmt_obj[channel]->tx_sem);
  781. return ESP_OK;
  782. } else {
  783. if (wait_time != 0) {
  784. // Don't emit error message if just polling.
  785. ESP_LOGE(RMT_TAG, "Timeout on wait_tx_done");
  786. }
  787. return ESP_ERR_TIMEOUT;
  788. }
  789. }
  790. esp_err_t rmt_get_ringbuf_handle(rmt_channel_t channel, RingbufHandle_t *buf_handle)
  791. {
  792. RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
  793. RMT_CHECK(p_rmt_obj[channel] != NULL, RMT_DRIVER_ERROR_STR, ESP_FAIL);
  794. RMT_CHECK(buf_handle != NULL, RMT_ADDR_ERROR_STR, ESP_ERR_INVALID_ARG);
  795. *buf_handle = p_rmt_obj[channel]->rx_buf;
  796. return ESP_OK;
  797. }
  798. rmt_tx_end_callback_t rmt_register_tx_end_callback(rmt_tx_end_fn_t function, void *arg)
  799. {
  800. rmt_tx_end_callback_t previous = rmt_tx_end_callback;
  801. rmt_tx_end_callback.function = function;
  802. rmt_tx_end_callback.arg = arg;
  803. return previous;
  804. }
  805. esp_err_t rmt_translator_init(rmt_channel_t channel, sample_to_rmt_t fn)
  806. {
  807. RMT_CHECK(fn != NULL, RMT_TRANSLATOR_NULL_STR, ESP_ERR_INVALID_ARG);
  808. RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
  809. RMT_CHECK(p_rmt_obj[channel] != NULL, RMT_DRIVER_ERROR_STR, ESP_FAIL);
  810. const uint32_t block_size = rmt_ll_get_mem_blocks(p_rmt_obj[channel]->hal.regs, channel) *
  811. RMT_MEM_ITEM_NUM * sizeof(rmt_item32_t);
  812. if (p_rmt_obj[channel]->tx_buf == NULL) {
  813. #if !CONFIG_SPIRAM_USE_MALLOC
  814. p_rmt_obj[channel]->tx_buf = (rmt_item32_t *)malloc(block_size);
  815. #else
  816. if (p_rmt_obj[channel]->intr_alloc_flags & ESP_INTR_FLAG_IRAM) {
  817. p_rmt_obj[channel]->tx_buf = (rmt_item32_t *)malloc(block_size);
  818. } else {
  819. p_rmt_obj[channel]->tx_buf = (rmt_item32_t *)heap_caps_calloc(1, block_size, MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
  820. }
  821. #endif
  822. if (p_rmt_obj[channel]->tx_buf == NULL) {
  823. ESP_LOGE(RMT_TAG, "RMT translator buffer create fail");
  824. return ESP_FAIL;
  825. }
  826. }
  827. p_rmt_obj[channel]->sample_to_rmt = fn;
  828. p_rmt_obj[channel]->sample_size_remain = 0;
  829. p_rmt_obj[channel]->sample_cur = NULL;
  830. ESP_LOGD(RMT_TAG, "RMT translator init done");
  831. return ESP_OK;
  832. }
  833. esp_err_t rmt_write_sample(rmt_channel_t channel, const uint8_t *src, size_t src_size, bool wait_tx_done)
  834. {
  835. RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
  836. RMT_CHECK(p_rmt_obj[channel] != NULL, RMT_DRIVER_ERROR_STR, ESP_FAIL);
  837. RMT_CHECK(p_rmt_obj[channel]->sample_to_rmt != NULL, RMT_TRANSLATOR_UNINIT_STR, ESP_FAIL);
  838. #if CONFIG_SPIRAM_USE_MALLOC
  839. if (p_rmt_obj[channel]->intr_alloc_flags & ESP_INTR_FLAG_IRAM) {
  840. if (!esp_ptr_internal(src)) {
  841. ESP_LOGE(RMT_TAG, RMT_PSRAM_BUFFER_WARN_STR);
  842. return ESP_ERR_INVALID_ARG;
  843. }
  844. }
  845. #endif
  846. size_t item_num = 0;
  847. size_t translated_size = 0;
  848. rmt_obj_t *p_rmt = p_rmt_obj[channel];
  849. const uint32_t item_block_len = rmt_ll_get_mem_blocks(p_rmt_obj[channel]->hal.regs, channel) * RMT_MEM_ITEM_NUM;
  850. const uint32_t item_sub_len = item_block_len / 2;
  851. xSemaphoreTake(p_rmt->tx_sem, portMAX_DELAY);
  852. p_rmt->sample_to_rmt((void *)src, p_rmt->tx_buf, src_size, item_block_len, &translated_size, &item_num);
  853. p_rmt->sample_size_remain = src_size - translated_size;
  854. p_rmt->sample_cur = src + translated_size;
  855. rmt_fill_memory(channel, p_rmt->tx_buf, item_num, 0);
  856. if (item_num == item_block_len) {
  857. rmt_set_tx_thr_intr_en(channel, 1, item_sub_len);
  858. p_rmt->tx_data = p_rmt->tx_buf;
  859. p_rmt->tx_offset = 0;
  860. p_rmt->tx_sub_len = item_sub_len;
  861. p_rmt->translator = true;
  862. } else {
  863. rmt_item32_t stop_data = {0};
  864. rmt_ll_write_memory(p_rmt_obj[channel]->hal.mem, channel, &stop_data, 1, item_num);
  865. p_rmt->tx_len_rem = 0;
  866. p_rmt->sample_cur = NULL;
  867. p_rmt->translator = false;
  868. }
  869. rmt_tx_start(channel, true);
  870. p_rmt->wait_done = wait_tx_done;
  871. if (wait_tx_done) {
  872. xSemaphoreTake(p_rmt->tx_sem, portMAX_DELAY);
  873. xSemaphoreGive(p_rmt->tx_sem);
  874. }
  875. return ESP_OK;
  876. }
  877. esp_err_t rmt_get_channel_status(rmt_channel_status_result_t *channel_status)
  878. {
  879. RMT_CHECK(channel_status != NULL, RMT_PARAM_ERR_STR, ESP_ERR_INVALID_ARG);
  880. for (int i = 0; i < RMT_CHANNEL_MAX; i++) {
  881. channel_status->status[i] = RMT_CHANNEL_UNINIT;
  882. if (p_rmt_obj[i] != NULL) {
  883. if (p_rmt_obj[i]->tx_sem != NULL) {
  884. if (xSemaphoreTake(p_rmt_obj[i]->tx_sem, (TickType_t)0) == pdTRUE) {
  885. channel_status->status[i] = RMT_CHANNEL_IDLE;
  886. xSemaphoreGive(p_rmt_obj[i]->tx_sem);
  887. } else {
  888. channel_status->status[i] = RMT_CHANNEL_BUSY;
  889. }
  890. }
  891. }
  892. }
  893. return ESP_OK;
  894. }
  895. esp_err_t rmt_get_counter_clock(rmt_channel_t channel, uint32_t *clock_hz)
  896. {
  897. RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
  898. RMT_CHECK(clock_hz, "parameter clock_hz can't be null", ESP_ERR_INVALID_ARG);
  899. RMT_ENTER_CRITICAL();
  900. *clock_hz = rmt_hal_get_counter_clock(&p_rmt_obj[channel]->hal, channel, RMT_SOURCE_CLK(RMT_BASECLK_APB));
  901. RMT_EXIT_CRITICAL();
  902. return ESP_OK;
  903. }