bt.c 35 KB

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  1. /*
  2. * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. */
  6. #include <stddef.h>
  7. #include <stdlib.h>
  8. #include <stdio.h>
  9. #include <string.h>
  10. #include "esp_random.h"
  11. #include "esp_heap_caps.h"
  12. #include "esp_heap_caps_init.h"
  13. #include <esp_mac.h>
  14. #include "sdkconfig.h"
  15. #include "nimble/nimble_port.h"
  16. #include "nimble/nimble_port_freertos.h"
  17. #ifdef ESP_PLATFORM
  18. #include "esp_log.h"
  19. #endif
  20. #if CONFIG_SW_COEXIST_ENABLE
  21. #include "esp_coexist_internal.h"
  22. #endif
  23. #include "nimble/nimble_npl_os.h"
  24. #include "nimble/ble_hci_trans.h"
  25. #include "os/endian.h"
  26. #include "esp_bt.h"
  27. #include "esp_intr_alloc.h"
  28. #include "esp_sleep.h"
  29. #include "esp_pm.h"
  30. #include "esp_phy_init.h"
  31. #include "soc/syscon_reg.h"
  32. #include "soc/modem_clkrst_reg.h"
  33. #include "esp_private/periph_ctrl.h"
  34. #include "hci_uart.h"
  35. #include "bt_osi_mem.h"
  36. #ifdef CONFIG_BT_BLUEDROID_ENABLED
  37. #include "hci/hci_hal.h"
  38. #endif
  39. #include "freertos/FreeRTOS.h"
  40. #include "freertos/task.h"
  41. #include "esp_private/periph_ctrl.h"
  42. #include "esp_sleep.h"
  43. #include "soc/syscon_reg.h"
  44. #include "soc/dport_access.h"
  45. /* Macro definition
  46. ************************************************************************
  47. */
  48. #define NIMBLE_PORT_LOG_TAG "BLE_INIT"
  49. #define OSI_COEX_VERSION 0x00010006
  50. #define OSI_COEX_MAGIC_VALUE 0xFADEBEAD
  51. #define EXT_FUNC_VERSION 0x20221122
  52. #define EXT_FUNC_MAGIC_VALUE 0xA5A5A5A5
  53. #define BT_ASSERT_PRINT ets_printf
  54. #ifdef CONFIG_BT_BLUEDROID_ENABLED
  55. /* ACL_DATA_MBUF_LEADINGSPCAE: The leadingspace in user info header for ACL data */
  56. #define ACL_DATA_MBUF_LEADINGSPCAE 4
  57. #endif
  58. /* Types definition
  59. ************************************************************************
  60. */
  61. struct osi_coex_funcs_t {
  62. uint32_t _magic;
  63. uint32_t _version;
  64. void (* _coex_wifi_sleep_set)(bool sleep);
  65. int (* _coex_core_ble_conn_dyn_prio_get)(bool *low, bool *high);
  66. void (* _coex_schm_status_bit_set)(uint32_t type, uint32_t status);
  67. void (* _coex_schm_status_bit_clear)(uint32_t type, uint32_t status);
  68. };
  69. struct ext_funcs_t {
  70. uint32_t ext_version;
  71. int (*_esp_intr_alloc)(int source, int flags, intr_handler_t handler, void *arg, void **ret_handle);
  72. int (*_esp_intr_free)(void **ret_handle);
  73. void *(* _malloc)(size_t size);
  74. void (*_free)(void *p);
  75. void (*_hal_uart_start_tx)(int);
  76. int (*_hal_uart_init_cbs)(int, hci_uart_tx_char, hci_uart_tx_done, hci_uart_rx_char, void *);
  77. int (*_hal_uart_config)(int, int32_t, uint8_t, uint8_t, uart_parity_t, uart_hw_flowcontrol_t);
  78. int (*_hal_uart_close)(int);
  79. void (*_hal_uart_blocking_tx)(int, uint8_t);
  80. int (*_hal_uart_init)(int, void *);
  81. int (* _task_create)(void *task_func, const char *name, uint32_t stack_depth, void *param, uint32_t prio, void *task_handle, uint32_t core_id);
  82. void (* _task_delete)(void *task_handle);
  83. void (*_osi_assert)(const uint32_t ln, const char *fn, uint32_t param1, uint32_t param2);
  84. uint32_t (* _os_random)(void);
  85. int (* _ecc_gen_key_pair)(uint8_t *public, uint8_t *priv);
  86. int (* _ecc_gen_dh_key)(const uint8_t *remote_pub_key_x, const uint8_t *remote_pub_key_y, const uint8_t *local_priv_key, uint8_t *dhkey);
  87. void (* _esp_reset_rpa_moudle)(void);
  88. void (* _esp_bt_track_pll_cap)(void);
  89. uint32_t magic;
  90. };
  91. /* External functions or variables
  92. ************************************************************************
  93. */
  94. extern int ble_osi_coex_funcs_register(struct osi_coex_funcs_t *coex_funcs);
  95. extern int coex_core_ble_conn_dyn_prio_get(bool *low, bool *high);
  96. extern int ble_controller_init(esp_bt_controller_config_t *cfg);
  97. extern int ble_controller_deinit(void);
  98. extern int ble_controller_enable(uint8_t mode);
  99. extern int ble_controller_disable(void);
  100. extern int esp_register_ext_funcs (struct ext_funcs_t *);
  101. extern void esp_unregister_ext_funcs (void);
  102. extern int esp_ble_ll_set_public_addr(const uint8_t *addr);
  103. extern int esp_register_npl_funcs (struct npl_funcs_t *p_npl_func);
  104. extern void esp_unregister_npl_funcs (void);
  105. extern void npl_freertos_mempool_deinit(void);
  106. extern void bt_bb_v2_init_cmplx(uint8_t i);
  107. extern int os_msys_buf_alloc(void);
  108. extern uint32_t r_os_cputime_get32(void);
  109. extern uint32_t r_os_cputime_ticks_to_usecs(uint32_t ticks);
  110. extern void r_ble_lll_rfmgmt_set_sleep_cb(void *s_cb, void *w_cb, void *s_arg, void *w_arg, uint32_t us_to_enabled);
  111. extern void r_ble_rtc_wake_up_state_clr(void);
  112. extern int os_msys_init(void);
  113. extern void os_msys_buf_free(void);
  114. extern int ble_sm_alg_gen_dhkey(const uint8_t *peer_pub_key_x,
  115. const uint8_t *peer_pub_key_y,
  116. const uint8_t *our_priv_key, uint8_t *out_dhkey);
  117. extern int ble_sm_alg_gen_key_pair(uint8_t *pub, uint8_t *priv);
  118. extern int ble_txpwr_set(esp_ble_enhanced_power_type_t power_type, uint16_t handle, int power_level);
  119. extern int ble_txpwr_get(esp_ble_enhanced_power_type_t power_type, uint16_t handle);
  120. extern uint32_t _bt_bss_start;
  121. extern uint32_t _bt_bss_end;
  122. extern uint32_t _nimble_bss_start;
  123. extern uint32_t _nimble_bss_end;
  124. extern uint32_t _nimble_data_start;
  125. extern uint32_t _nimble_data_end;
  126. extern uint32_t _bt_data_start;
  127. extern uint32_t _bt_data_end;
  128. /* Local Function Declaration
  129. *********************************************************************
  130. */
  131. static void coex_schm_status_bit_set_wrapper(uint32_t type, uint32_t status);
  132. static void coex_schm_status_bit_clear_wrapper(uint32_t type, uint32_t status);
  133. static int task_create_wrapper(void *task_func, const char *name, uint32_t stack_depth, void *param, uint32_t prio, void *task_handle, uint32_t core_id);
  134. static void task_delete_wrapper(void *task_handle);
  135. #if CONFIG_BT_LE_HCI_INTERFACE_USE_UART
  136. static void hci_uart_start_tx_wrapper(int uart_no);
  137. static int hci_uart_init_cbs_wrapper(int uart_no, hci_uart_tx_char tx_func,
  138. hci_uart_tx_done tx_done, hci_uart_rx_char rx_func, void *arg);
  139. static int hci_uart_config_wrapper(int uart_no, int32_t speed, uint8_t databits, uint8_t stopbits,
  140. uart_parity_t parity, uart_hw_flowcontrol_t flow_ctl);
  141. static int hci_uart_close_wrapper(int uart_no);
  142. static void hci_uart_blocking_tx_wrapper(int port, uint8_t data);
  143. static int hci_uart_init_wrapper(int uart_no, void *cfg);
  144. #endif
  145. static int esp_intr_alloc_wrapper(int source, int flags, intr_handler_t handler, void *arg, void **ret_handle_in);
  146. static int esp_intr_free_wrapper(void **ret_handle);
  147. static void osi_assert_wrapper(const uint32_t ln, const char *fn, uint32_t param1, uint32_t param2);
  148. static uint32_t osi_random_wrapper(void);
  149. static void esp_reset_rpa_moudle(void);
  150. /* Local variable definition
  151. ***************************************************************************
  152. */
  153. /* Static variable declare */
  154. static DRAM_ATTR esp_bt_controller_status_t ble_controller_status = ESP_BT_CONTROLLER_STATUS_IDLE;
  155. /* This variable tells if BLE is running */
  156. static bool s_ble_active = false;
  157. #ifdef CONFIG_PM_ENABLE
  158. static DRAM_ATTR esp_pm_lock_handle_t s_pm_lock = NULL;
  159. #define BTDM_MIN_TIMER_UNCERTAINTY_US (200)
  160. #endif /* #ifdef CONFIG_PM_ENABLE */
  161. #ifdef CONFIG_BT_LE_WAKEUP_SOURCE_BLE_RTC_TIMER
  162. #define BLE_RTC_DELAY_US (1100)
  163. #endif
  164. #ifdef CONFIG_BT_LE_WAKEUP_SOURCE_CPU_RTC_TIMER
  165. #define BLE_RTC_DELAY_US (0)
  166. static void ble_sleep_timer_callback(void *arg);
  167. static DRAM_ATTR esp_timer_handle_t s_ble_sleep_timer = NULL;
  168. #endif
  169. static const struct osi_coex_funcs_t s_osi_coex_funcs_ro = {
  170. ._magic = OSI_COEX_MAGIC_VALUE,
  171. ._version = OSI_COEX_VERSION,
  172. ._coex_wifi_sleep_set = NULL,
  173. ._coex_core_ble_conn_dyn_prio_get = NULL,
  174. ._coex_schm_status_bit_set = coex_schm_status_bit_set_wrapper,
  175. ._coex_schm_status_bit_clear = coex_schm_status_bit_clear_wrapper,
  176. };
  177. struct ext_funcs_t ext_funcs_ro = {
  178. .ext_version = EXT_FUNC_VERSION,
  179. ._esp_intr_alloc = esp_intr_alloc_wrapper,
  180. ._esp_intr_free = esp_intr_free_wrapper,
  181. ._malloc = bt_osi_mem_malloc_internal,
  182. ._free = bt_osi_mem_free,
  183. #if CONFIG_BT_LE_HCI_INTERFACE_USE_UART
  184. ._hal_uart_start_tx = hci_uart_start_tx_wrapper,
  185. ._hal_uart_init_cbs = hci_uart_init_cbs_wrapper,
  186. ._hal_uart_config = hci_uart_config_wrapper,
  187. ._hal_uart_close = hci_uart_close_wrapper,
  188. ._hal_uart_blocking_tx = hci_uart_blocking_tx_wrapper,
  189. ._hal_uart_init = hci_uart_init_wrapper,
  190. #endif //CONFIG_BT_LE_HCI_INTERFACE_USE_UART
  191. ._task_create = task_create_wrapper,
  192. ._task_delete = task_delete_wrapper,
  193. ._osi_assert = osi_assert_wrapper,
  194. ._os_random = osi_random_wrapper,
  195. ._ecc_gen_key_pair = ble_sm_alg_gen_key_pair,
  196. ._ecc_gen_dh_key = ble_sm_alg_gen_dhkey,
  197. ._esp_reset_rpa_moudle = esp_reset_rpa_moudle,
  198. .magic = EXT_FUNC_MAGIC_VALUE,
  199. };
  200. static void IRAM_ATTR esp_reset_rpa_moudle(void)
  201. {
  202. DPORT_SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, BLE_RPA_REST_BIT);
  203. DPORT_CLEAR_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, BLE_RPA_REST_BIT);
  204. }
  205. static void IRAM_ATTR osi_assert_wrapper(const uint32_t ln, const char *fn, uint32_t param1, uint32_t param2)
  206. {
  207. BT_ASSERT_PRINT("BLE assert: line %d in function %s, param: 0x%x, 0x%x", ln, fn, param1, param2);
  208. assert(0);
  209. }
  210. static uint32_t IRAM_ATTR osi_random_wrapper(void)
  211. {
  212. return esp_random();
  213. }
  214. static void coex_schm_status_bit_set_wrapper(uint32_t type, uint32_t status)
  215. {
  216. #if CONFIG_SW_COEXIST_ENABLE
  217. coex_schm_status_bit_set(type, status);
  218. #endif
  219. }
  220. static void coex_schm_status_bit_clear_wrapper(uint32_t type, uint32_t status)
  221. {
  222. #if CONFIG_SW_COEXIST_ENABLE
  223. coex_schm_status_bit_clear(type, status);
  224. #endif
  225. }
  226. #ifdef CONFIG_BT_BLUEDROID_ENABLED
  227. bool esp_vhci_host_check_send_available(void)
  228. {
  229. if (ble_controller_status != ESP_BT_CONTROLLER_STATUS_ENABLED) {
  230. return false;
  231. }
  232. return true;
  233. }
  234. /**
  235. * Allocates an mbuf for use by the nimble host.
  236. */
  237. static struct os_mbuf *ble_hs_mbuf_gen_pkt(uint16_t leading_space)
  238. {
  239. struct os_mbuf *om;
  240. int rc;
  241. om = os_msys_get_pkthdr(0, 0);
  242. if (om == NULL) {
  243. return NULL;
  244. }
  245. if (om->om_omp->omp_databuf_len < leading_space) {
  246. rc = os_mbuf_free_chain(om);
  247. assert(rc == 0);
  248. return NULL;
  249. }
  250. om->om_data += leading_space;
  251. return om;
  252. }
  253. /**
  254. * Allocates an mbuf suitable for an HCI ACL data packet.
  255. *
  256. * @return An empty mbuf on success; null on memory
  257. * exhaustion.
  258. */
  259. struct os_mbuf *ble_hs_mbuf_acl_pkt(void)
  260. {
  261. return ble_hs_mbuf_gen_pkt(4 + 1);
  262. }
  263. void esp_vhci_host_send_packet(uint8_t *data, uint16_t len)
  264. {
  265. if (ble_controller_status != ESP_BT_CONTROLLER_STATUS_ENABLED) {
  266. return;
  267. }
  268. if (*(data) == DATA_TYPE_COMMAND) {
  269. struct ble_hci_cmd *cmd = NULL;
  270. cmd = (struct ble_hci_cmd *) ble_hci_trans_buf_alloc(BLE_HCI_TRANS_BUF_CMD);
  271. memcpy((uint8_t *)cmd, data + 1, len - 1);
  272. ble_hci_trans_hs_cmd_tx((uint8_t *)cmd);
  273. }
  274. if (*(data) == DATA_TYPE_ACL) {
  275. struct os_mbuf *om = os_msys_get_pkthdr(len, ACL_DATA_MBUF_LEADINGSPCAE);
  276. assert(om);
  277. os_mbuf_append(om, &data[1], len - 1);
  278. ble_hci_trans_hs_acl_tx(om);
  279. }
  280. }
  281. esp_err_t esp_vhci_host_register_callback(const esp_vhci_host_callback_t *callback)
  282. {
  283. if (ble_controller_status != ESP_BT_CONTROLLER_STATUS_ENABLED) {
  284. return ESP_FAIL;
  285. }
  286. ble_hci_trans_cfg_hs(ble_hs_hci_rx_evt, NULL, ble_hs_rx_data, NULL);
  287. return ESP_OK;
  288. }
  289. #endif
  290. static int task_create_wrapper(void *task_func, const char *name, uint32_t stack_depth, void *param, uint32_t prio, void *task_handle, uint32_t core_id)
  291. {
  292. return (uint32_t)xTaskCreatePinnedToCore(task_func, name, stack_depth, param, prio, task_handle, (core_id < portNUM_PROCESSORS ? core_id : tskNO_AFFINITY));
  293. }
  294. static void task_delete_wrapper(void *task_handle)
  295. {
  296. vTaskDelete(task_handle);
  297. }
  298. #ifdef CONFIG_BT_LE_HCI_INTERFACE_USE_UART
  299. static void hci_uart_start_tx_wrapper(int uart_no)
  300. {
  301. hci_uart_start_tx(uart_no);
  302. }
  303. static int hci_uart_init_cbs_wrapper(int uart_no, hci_uart_tx_char tx_func,
  304. hci_uart_tx_done tx_done, hci_uart_rx_char rx_func, void *arg)
  305. {
  306. int rc = -1;
  307. rc = hci_uart_init_cbs(uart_no, tx_func, tx_done, rx_func, arg);
  308. return rc;
  309. }
  310. static int hci_uart_config_wrapper(int port_num, int32_t baud_rate, uint8_t data_bits, uint8_t stop_bits,
  311. uart_parity_t parity, uart_hw_flowcontrol_t flow_ctl)
  312. {
  313. int rc = -1;
  314. rc = hci_uart_config(port_num, baud_rate, data_bits, stop_bits, parity, flow_ctl);
  315. return rc;
  316. }
  317. static int hci_uart_close_wrapper(int uart_no)
  318. {
  319. int rc = -1;
  320. rc = hci_uart_close(uart_no);
  321. return rc;
  322. }
  323. static void hci_uart_blocking_tx_wrapper(int port, uint8_t data)
  324. {
  325. //This function is nowhere to use.
  326. }
  327. static int hci_uart_init_wrapper(int uart_no, void *cfg)
  328. {
  329. //This function is nowhere to use.
  330. return 0;
  331. }
  332. #endif //CONFIG_BT_LE_HCI_INTERFACE_USE_UART
  333. static int ble_hci_unregistered_hook(void*, void*)
  334. {
  335. ESP_LOGD(NIMBLE_PORT_LOG_TAG,"%s ble hci rx_evt is not registered.",__func__);
  336. return 0;
  337. }
  338. static int esp_intr_alloc_wrapper(int source, int flags, intr_handler_t handler, void *arg, void **ret_handle_in)
  339. {
  340. int rc = esp_intr_alloc(source, flags | ESP_INTR_FLAG_IRAM, handler, arg, (intr_handle_t *)ret_handle_in);
  341. return rc;
  342. }
  343. static int esp_intr_free_wrapper(void **ret_handle)
  344. {
  345. int rc = 0;
  346. rc = esp_intr_free((intr_handle_t) * ret_handle);
  347. *ret_handle = NULL;
  348. return rc;
  349. }
  350. IRAM_ATTR void controller_sleep_cb(uint32_t enable_tick, void *arg)
  351. {
  352. if (!s_ble_active) {
  353. return;
  354. }
  355. #ifdef CONFIG_PM_ENABLE
  356. #ifdef CONFIG_BT_LE_WAKEUP_SOURCE_CPU_RTC_TIMER
  357. uint32_t delta_tick;
  358. uint32_t us_to_sleep;
  359. uint32_t sleep_tick;
  360. uint32_t tick_invalid = *(uint32_t*)(arg);
  361. assert(arg != NULL);
  362. if (!tick_invalid) {
  363. sleep_tick = r_os_cputime_get32();
  364. // start a timer to wake up and acquire the pm_lock before modem_sleep awakes
  365. delta_tick = enable_tick - sleep_tick;
  366. if (delta_tick & 0x80000000) {
  367. return;
  368. }
  369. us_to_sleep = r_os_cputime_ticks_to_usecs(delta_tick);
  370. if (us_to_sleep <= BTDM_MIN_TIMER_UNCERTAINTY_US) {
  371. return;
  372. }
  373. esp_err_t err = esp_timer_start_once(s_ble_sleep_timer, us_to_sleep - BTDM_MIN_TIMER_UNCERTAINTY_US);
  374. if (err != ESP_OK) {
  375. ESP_LOGW(NIMBLE_PORT_LOG_TAG, "ESP timer start failed\n");
  376. return;
  377. }
  378. }
  379. #endif // CONFIG_BT_LE_WAKEUP_SOURCE_CPU_RTC_TIMER
  380. #ifdef CONFIG_BT_LE_WAKEUP_SOURCE_BLE_RTC_TIMER
  381. r_ble_rtc_wake_up_state_clr();
  382. #endif
  383. esp_pm_lock_release(s_pm_lock);
  384. #endif // CONFIG_PM_ENABLE
  385. esp_phy_disable();
  386. s_ble_active = false;
  387. }
  388. IRAM_ATTR void controller_wakeup_cb(void *arg)
  389. {
  390. if (s_ble_active) {
  391. return;
  392. }
  393. esp_phy_enable();
  394. // need to check if need to call pm lock here
  395. #ifdef CONFIG_PM_ENABLE
  396. esp_pm_lock_acquire(s_pm_lock);
  397. #endif //CONFIG_PM_ENABLE
  398. s_ble_active = true;
  399. }
  400. #ifdef CONFIG_PM_ENABLE
  401. #ifdef CONFIG_BT_LE_WAKEUP_SOURCE_CPU_RTC_TIMER
  402. static void ble_sleep_timer_callback(void * arg)
  403. {
  404. }
  405. #endif // CONFIG_BT_LE_WAKEUP_SOURCE_CPU_RTC_TIMER
  406. #endif // CONFIG_PM_ENABLE
  407. esp_err_t controller_sleep_init(void)
  408. {
  409. esp_err_t rc = 0;
  410. #ifdef CONFIG_BT_LE_SLEEP_ENABLE
  411. ESP_LOGW(NIMBLE_PORT_LOG_TAG, "BLE modem sleep is enabled\n");
  412. r_ble_lll_rfmgmt_set_sleep_cb(controller_sleep_cb, controller_wakeup_cb, 0, 0, 500 + BLE_RTC_DELAY_US);
  413. #ifdef CONFIG_PM_ENABLE
  414. esp_sleep_pd_config(ESP_PD_DOMAIN_XTAL, ESP_PD_OPTION_ON);
  415. #endif // CONFIG_PM_ENABLE
  416. #endif // CONFIG_BT_LE_SLEEP_ENABLE
  417. // enable light sleep
  418. #ifdef CONFIG_PM_ENABLE
  419. rc = esp_pm_lock_create(ESP_PM_CPU_FREQ_MAX, 0, "bt", &s_pm_lock);
  420. if (rc != ESP_OK) {
  421. goto error;
  422. }
  423. esp_pm_lock_acquire(s_pm_lock);
  424. #ifdef CONFIG_BT_LE_WAKEUP_SOURCE_CPU_RTC_TIMER
  425. esp_timer_create_args_t create_args = {
  426. .callback = ble_sleep_timer_callback,
  427. .arg = NULL,
  428. .name = "btSlp"
  429. };
  430. rc = esp_timer_create(&create_args, &s_ble_sleep_timer);
  431. if (rc != ESP_OK) {
  432. goto error;
  433. }
  434. ESP_LOGW(NIMBLE_PORT_LOG_TAG, "Enable light sleep, the wake up source is ESP timer");
  435. #endif //CONFIG_BT_LE_WAKEUP_SOURCE_CPU_RTC_TIMER
  436. #ifdef CONFIG_BT_LE_WAKEUP_SOURCE_BLE_RTC_TIMER
  437. esp_sleep_enable_bt_wakeup();
  438. ESP_LOGW(NIMBLE_PORT_LOG_TAG, "Enable light sleep, the wake up source is BLE timer");
  439. #endif // CONFIG_BT_LE_WAKEUP_SOURCE_BLE_RTC_TIMER
  440. return rc;
  441. error:
  442. /*lock should release first and then delete*/
  443. if (s_pm_lock != NULL) {
  444. esp_pm_lock_release(s_pm_lock);
  445. esp_pm_lock_delete(s_pm_lock);
  446. s_pm_lock = NULL;
  447. }
  448. #ifdef CONFIG_BT_LE_WAKEUP_SOURCE_CPU_RTC_TIMER
  449. if (s_ble_sleep_timer != NULL) {
  450. esp_timer_stop(s_ble_sleep_timer);
  451. esp_timer_delete(s_ble_sleep_timer);
  452. s_ble_sleep_timer = NULL;
  453. }
  454. #endif // CONFIG_BT_LE_WAKEUP_SOURCE_CPU_RTC_TIMER
  455. #ifdef CONFIG_BT_LE_WAKEUP_SOURCE_BLE_RTC_TIMER
  456. esp_sleep_disable_bt_wakeup();
  457. #endif // CONFIG_BT_LE_WAKEUP_SOURCE_BLE_RTC_TIMER
  458. #endif //CONFIG_PM_ENABLE
  459. return rc;
  460. }
  461. void controller_sleep_deinit(void)
  462. {
  463. #ifdef CONFIG_PM_ENABLE
  464. #ifdef CONFIG_BT_LE_WAKEUP_SOURCE_BLE_RTC_TIMER
  465. r_ble_rtc_wake_up_state_clr();
  466. esp_sleep_disable_bt_wakeup();
  467. #endif //CONFIG_BT_LE_WAKEUP_SOURCE_BLE_RTC_TIMER
  468. esp_sleep_pd_config(ESP_PD_DOMAIN_XTAL, ESP_PD_OPTION_AUTO);
  469. /*lock should release first and then delete*/
  470. if (s_ble_active) {
  471. esp_pm_lock_release(s_pm_lock);
  472. }
  473. esp_pm_lock_delete(s_pm_lock);
  474. s_pm_lock = NULL;
  475. #ifdef CONFIG_BT_LE_WAKEUP_SOURCE_CPU_RTC_TIMER
  476. if (s_ble_sleep_timer != NULL) {
  477. esp_timer_stop(s_ble_sleep_timer);
  478. esp_timer_delete(s_ble_sleep_timer);
  479. s_ble_sleep_timer = NULL;
  480. }
  481. #endif //CONFIG_BT_LE_WAKEUP_SOURCE_CPU_RTC_TIMER
  482. #endif //CONFIG_PM_ENABLE
  483. }
  484. void ble_rtc_clk_init(void)
  485. {
  486. // modem_clkrst_reg
  487. // LP_TIMER_SEL_XTAL32K -> 0
  488. // LP_TIMER_SEL_XTAL -> 1
  489. // LP_TIMER_SEL_8M -> 0
  490. // LP_TIMER_SEL_RTC_SLOW -> 0
  491. SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, 1, 0, MODEM_CLKRST_LP_TIMER_SEL_XTAL32K_S);
  492. SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, 1, 1, MODEM_CLKRST_LP_TIMER_SEL_XTAL_S);
  493. SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, 1, 0, MODEM_CLKRST_LP_TIMER_SEL_8M_S);
  494. SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, 1, 0, MODEM_CLKRST_LP_TIMER_SEL_RTC_SLOW_S);
  495. #ifdef CONFIG_XTAL_FREQ_26
  496. // LP_TIMER_CLK_DIV_NUM -> 130
  497. SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM, 129, MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM_S);
  498. #else
  499. // LP_TIMER_CLK_DIV_NUM -> 250
  500. SET_PERI_REG_BITS(MODEM_CLKRST_MODEM_LP_TIMER_CONF_REG, MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM, 249, MODEM_CLKRST_LP_TIMER_CLK_DIV_NUM_S);
  501. #endif // CONFIG_XTAL_FREQ_26
  502. // MODEM_CLKRST_ETM_CLK_ACTIVE -> 1
  503. // MODEM_CLKRST_ETM_CLK_SEL -> 0
  504. SET_PERI_REG_BITS(MODEM_CLKRST_ETM_CLK_CONF_REG, 1, 1, MODEM_CLKRST_ETM_CLK_ACTIVE_S);
  505. SET_PERI_REG_BITS(MODEM_CLKRST_ETM_CLK_CONF_REG, 1, 0, MODEM_CLKRST_ETM_CLK_SEL_S);
  506. }
  507. esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
  508. {
  509. esp_err_t ret = ESP_OK;
  510. if (ble_controller_status != ESP_BT_CONTROLLER_STATUS_IDLE) {
  511. ESP_LOGW(NIMBLE_PORT_LOG_TAG, "invalid controller state");
  512. return ESP_ERR_INVALID_STATE;
  513. }
  514. if (!cfg) {
  515. ESP_LOGW(NIMBLE_PORT_LOG_TAG, "cfg is NULL");
  516. return ESP_ERR_INVALID_ARG;
  517. }
  518. ble_rtc_clk_init();
  519. ret = esp_register_ext_funcs(&ext_funcs_ro);
  520. if (ret != ESP_OK) {
  521. ESP_LOGW(NIMBLE_PORT_LOG_TAG, "register extend functions failed");
  522. return ret;
  523. }
  524. /* Initialize the function pointers for OS porting */
  525. npl_freertos_funcs_init();
  526. struct npl_funcs_t *p_npl_funcs = npl_freertos_funcs_get();
  527. if (!p_npl_funcs) {
  528. ESP_LOGW(NIMBLE_PORT_LOG_TAG, "npl functions get failed");
  529. return ESP_ERR_INVALID_ARG;
  530. }
  531. ret = esp_register_npl_funcs(p_npl_funcs);
  532. if (ret != ESP_OK) {
  533. ESP_LOGW(NIMBLE_PORT_LOG_TAG, "npl functions register failed");
  534. goto free_mem;
  535. }
  536. if (npl_freertos_mempool_init() != 0) {
  537. ESP_LOGW(NIMBLE_PORT_LOG_TAG, "npl mempool init failed");
  538. ret = ESP_ERR_INVALID_ARG;
  539. goto free_mem;
  540. }
  541. /* Initialize the global memory pool */
  542. ret = os_msys_buf_alloc();
  543. if (ret != ESP_OK) {
  544. ESP_LOGW(NIMBLE_PORT_LOG_TAG, "os msys alloc failed");
  545. goto free_mem;
  546. }
  547. os_msys_init();
  548. #if CONFIG_BT_NIMBLE_ENABLED
  549. // ble_npl_eventq_init() need to use npl function in rom and must be called after esp_bt_controller_init()
  550. /* Initialize default event queue */
  551. ble_npl_eventq_init(nimble_port_get_dflt_eventq());
  552. #endif
  553. esp_phy_modem_init();
  554. periph_module_enable(PERIPH_BT_MODULE);
  555. // init phy
  556. esp_phy_enable();
  557. s_ble_active = true;
  558. // init bb
  559. bt_bb_v2_init_cmplx(1);
  560. if (ble_osi_coex_funcs_register((struct osi_coex_funcs_t *)&s_osi_coex_funcs_ro) != 0) {
  561. ESP_LOGW(NIMBLE_PORT_LOG_TAG, "osi coex funcs reg failed");
  562. ret = ESP_ERR_INVALID_ARG;
  563. goto free_controller;
  564. }
  565. #if CONFIG_SW_COEXIST_ENABLE
  566. coex_init();
  567. #endif
  568. ret = ble_controller_init(cfg);
  569. if (ret != ESP_OK) {
  570. ESP_LOGW(NIMBLE_PORT_LOG_TAG, "ble_controller_init failed %d", ret);
  571. goto free_controller;
  572. }
  573. ret = controller_sleep_init();
  574. if (ret != ESP_OK) {
  575. ESP_LOGW(NIMBLE_PORT_LOG_TAG, "controller_sleep_init failed %d", ret);
  576. goto free_controller;
  577. }
  578. uint8_t mac[6];
  579. ESP_ERROR_CHECK(esp_read_mac((uint8_t *)mac, ESP_MAC_BT));
  580. swap_in_place(mac, 6);
  581. esp_ble_ll_set_public_addr(mac);
  582. ble_controller_status = ESP_BT_CONTROLLER_STATUS_INITED;
  583. ble_hci_trans_cfg_hs((ble_hci_trans_rx_cmd_fn *)ble_hci_unregistered_hook,NULL,
  584. (ble_hci_trans_rx_acl_fn *)ble_hci_unregistered_hook,NULL);
  585. return ESP_OK;
  586. free_controller:
  587. controller_sleep_deinit();
  588. ble_controller_deinit();
  589. esp_phy_disable();
  590. esp_phy_modem_deinit();
  591. #if CONFIG_BT_NIMBLE_ENABLED
  592. ble_npl_eventq_deinit(nimble_port_get_dflt_eventq());
  593. #endif // CONFIG_BT_NIMBLE_ENABLED
  594. free_mem:
  595. os_msys_buf_free();
  596. npl_freertos_mempool_deinit();
  597. esp_unregister_npl_funcs();
  598. npl_freertos_funcs_deinit();
  599. esp_unregister_ext_funcs();
  600. return ret;
  601. }
  602. esp_err_t esp_bt_controller_deinit(void)
  603. {
  604. if ((ble_controller_status < ESP_BT_CONTROLLER_STATUS_INITED) || (ble_controller_status >= ESP_BT_CONTROLLER_STATUS_ENABLED)) {
  605. ESP_LOGW(NIMBLE_PORT_LOG_TAG, "invalid controller state");
  606. return ESP_FAIL;
  607. }
  608. controller_sleep_deinit();
  609. if (s_ble_active) {
  610. esp_phy_disable();
  611. s_ble_active = false;
  612. }
  613. ble_controller_deinit();
  614. #if CONFIG_BT_NIMBLE_ENABLED
  615. /* De-initialize default event queue */
  616. ble_npl_eventq_deinit(nimble_port_get_dflt_eventq());
  617. #endif
  618. os_msys_buf_free();
  619. esp_unregister_npl_funcs();
  620. esp_unregister_ext_funcs();
  621. /* De-initialize npl functions */
  622. npl_freertos_funcs_deinit();
  623. npl_freertos_mempool_deinit();
  624. esp_phy_modem_deinit();
  625. ble_controller_status = ESP_BT_CONTROLLER_STATUS_IDLE;
  626. return ESP_OK;
  627. }
  628. esp_err_t esp_bt_controller_enable(esp_bt_mode_t mode)
  629. {
  630. if (mode != ESP_BT_MODE_BLE) {
  631. ESP_LOGW(NIMBLE_PORT_LOG_TAG, "invalid controller mode");
  632. return ESP_FAIL;
  633. }
  634. if (ble_controller_status != ESP_BT_CONTROLLER_STATUS_INITED) {
  635. ESP_LOGW(NIMBLE_PORT_LOG_TAG, "invalid controller state");
  636. return ESP_FAIL;
  637. }
  638. #if CONFIG_SW_COEXIST_ENABLE
  639. coex_enable();
  640. #endif
  641. if (ble_controller_enable(mode) != 0) {
  642. return ESP_FAIL;
  643. }
  644. ble_controller_status = ESP_BT_CONTROLLER_STATUS_ENABLED;
  645. return ESP_OK;
  646. }
  647. esp_err_t esp_bt_controller_disable(void)
  648. {
  649. if (ble_controller_status < ESP_BT_CONTROLLER_STATUS_ENABLED) {
  650. ESP_LOGW(NIMBLE_PORT_LOG_TAG, "invalid controller state");
  651. return ESP_FAIL;
  652. }
  653. if (ble_controller_disable() != 0) {
  654. return ESP_FAIL;
  655. }
  656. ble_controller_status = ESP_BT_CONTROLLER_STATUS_INITED;
  657. return ESP_OK;
  658. }
  659. esp_err_t esp_bt_controller_mem_release(esp_bt_mode_t mode)
  660. {
  661. ESP_LOGD(NIMBLE_PORT_LOG_TAG, "%s not implemented, return OK", __func__);
  662. return ESP_OK;
  663. }
  664. static esp_err_t try_heap_caps_add_region(intptr_t start, intptr_t end)
  665. {
  666. int ret = heap_caps_add_region(start, end);
  667. /* heap_caps_add_region() returns ESP_ERR_INVALID_SIZE if the memory region is
  668. * is too small to fit a heap. This cannot be termed as a fatal error and hence
  669. * we replace it by ESP_OK
  670. */
  671. if (ret == ESP_ERR_INVALID_SIZE) {
  672. return ESP_OK;
  673. }
  674. return ret;
  675. }
  676. esp_err_t esp_bt_mem_release(esp_bt_mode_t mode)
  677. {
  678. intptr_t mem_start, mem_end;
  679. if (mode == ESP_BT_MODE_BLE) {
  680. mem_start = (intptr_t)&_bt_bss_start;
  681. mem_end = (intptr_t)&_bt_bss_end;
  682. if (mem_start != mem_end) {
  683. ESP_LOGD(NIMBLE_PORT_LOG_TAG, "Release BT BSS [0x%08x] - [0x%08x]", mem_start, mem_end);
  684. ESP_ERROR_CHECK(try_heap_caps_add_region(mem_start, mem_end));
  685. }
  686. mem_start = (intptr_t)&_bt_data_start;
  687. mem_end = (intptr_t)&_bt_data_end;
  688. if (mem_start != mem_end) {
  689. ESP_LOGD(NIMBLE_PORT_LOG_TAG, "Release BT Data [0x%08x] - [0x%08x]", mem_start, mem_end);
  690. ESP_ERROR_CHECK(try_heap_caps_add_region(mem_start, mem_end));
  691. }
  692. mem_start = (intptr_t)&_nimble_bss_start;
  693. mem_end = (intptr_t)&_nimble_bss_end;
  694. if (mem_start != mem_end) {
  695. ESP_LOGD(NIMBLE_PORT_LOG_TAG, "Release NimBLE BSS [0x%08x] - [0x%08x]", mem_start, mem_end);
  696. ESP_ERROR_CHECK(try_heap_caps_add_region(mem_start, mem_end));
  697. }
  698. mem_start = (intptr_t)&_nimble_data_start;
  699. mem_end = (intptr_t)&_nimble_data_end;
  700. if (mem_start != mem_end) {
  701. ESP_LOGD(NIMBLE_PORT_LOG_TAG, "Release NimBLE Data [0x%08x] - [0x%08x]", mem_start, mem_end);
  702. ESP_ERROR_CHECK(try_heap_caps_add_region(mem_start, mem_end));
  703. }
  704. }
  705. return ESP_OK;
  706. }
  707. esp_bt_controller_status_t esp_bt_controller_get_status(void)
  708. {
  709. return ble_controller_status;
  710. }
  711. /* extra functions */
  712. esp_err_t esp_ble_tx_power_set(esp_ble_power_type_t power_type, esp_power_level_t power_level)
  713. {
  714. esp_err_t stat = ESP_FAIL;
  715. switch (power_type) {
  716. case ESP_BLE_PWR_TYPE_DEFAULT:
  717. case ESP_BLE_PWR_TYPE_ADV:
  718. case ESP_BLE_PWR_TYPE_SCAN:
  719. if (ble_txpwr_set(ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT, 0, power_level) == 0) {
  720. stat = ESP_OK;
  721. }
  722. break;
  723. case ESP_BLE_PWR_TYPE_CONN_HDL0:
  724. case ESP_BLE_PWR_TYPE_CONN_HDL1:
  725. case ESP_BLE_PWR_TYPE_CONN_HDL2:
  726. case ESP_BLE_PWR_TYPE_CONN_HDL3:
  727. case ESP_BLE_PWR_TYPE_CONN_HDL4:
  728. case ESP_BLE_PWR_TYPE_CONN_HDL5:
  729. case ESP_BLE_PWR_TYPE_CONN_HDL6:
  730. case ESP_BLE_PWR_TYPE_CONN_HDL7:
  731. case ESP_BLE_PWR_TYPE_CONN_HDL8:
  732. if (ble_txpwr_set(ESP_BLE_ENHANCED_PWR_TYPE_CONN, power_type, power_level) == 0) {
  733. stat = ESP_OK;
  734. }
  735. break;
  736. default:
  737. stat = ESP_ERR_NOT_SUPPORTED;
  738. break;
  739. }
  740. return stat;
  741. }
  742. esp_err_t esp_ble_tx_power_set_enhanced(esp_ble_enhanced_power_type_t power_type, uint16_t handle, esp_power_level_t power_level)
  743. {
  744. esp_err_t stat = ESP_FAIL;
  745. switch (power_type) {
  746. case ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT:
  747. case ESP_BLE_ENHANCED_PWR_TYPE_SCAN:
  748. case ESP_BLE_ENHANCED_PWR_TYPE_INIT:
  749. if (ble_txpwr_set(ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT, 0, power_level) == 0) {
  750. stat = ESP_OK;
  751. }
  752. break;
  753. case ESP_BLE_ENHANCED_PWR_TYPE_ADV:
  754. case ESP_BLE_ENHANCED_PWR_TYPE_CONN:
  755. if (ble_txpwr_set(power_type, handle, power_level) == 0) {
  756. stat = ESP_OK;
  757. }
  758. break;
  759. default:
  760. stat = ESP_ERR_NOT_SUPPORTED;
  761. break;
  762. }
  763. return stat;
  764. }
  765. esp_power_level_t esp_ble_tx_power_get(esp_ble_power_type_t power_type)
  766. {
  767. int tx_level = 0;
  768. switch (power_type) {
  769. case ESP_BLE_PWR_TYPE_ADV:
  770. case ESP_BLE_PWR_TYPE_SCAN:
  771. case ESP_BLE_PWR_TYPE_DEFAULT:
  772. tx_level = ble_txpwr_get(ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT, 0);
  773. break;
  774. case ESP_BLE_PWR_TYPE_CONN_HDL0:
  775. case ESP_BLE_PWR_TYPE_CONN_HDL1:
  776. case ESP_BLE_PWR_TYPE_CONN_HDL2:
  777. case ESP_BLE_PWR_TYPE_CONN_HDL3:
  778. case ESP_BLE_PWR_TYPE_CONN_HDL4:
  779. case ESP_BLE_PWR_TYPE_CONN_HDL5:
  780. case ESP_BLE_PWR_TYPE_CONN_HDL6:
  781. case ESP_BLE_PWR_TYPE_CONN_HDL7:
  782. case ESP_BLE_PWR_TYPE_CONN_HDL8:
  783. tx_level = ble_txpwr_get(ESP_BLE_ENHANCED_PWR_TYPE_CONN, power_type);
  784. break;
  785. default:
  786. return ESP_PWR_LVL_INVALID;
  787. }
  788. if (tx_level < 0) {
  789. return ESP_PWR_LVL_INVALID;
  790. }
  791. return (esp_power_level_t)tx_level;
  792. }
  793. esp_power_level_t esp_ble_tx_power_get_enhanced(esp_ble_enhanced_power_type_t power_type, uint16_t handle)
  794. {
  795. int tx_level = 0;
  796. switch (power_type) {
  797. case ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT:
  798. case ESP_BLE_ENHANCED_PWR_TYPE_SCAN:
  799. case ESP_BLE_ENHANCED_PWR_TYPE_INIT:
  800. tx_level = ble_txpwr_get(ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT, 0);
  801. break;
  802. case ESP_BLE_ENHANCED_PWR_TYPE_ADV:
  803. case ESP_BLE_ENHANCED_PWR_TYPE_CONN:
  804. tx_level = ble_txpwr_get(power_type, handle);
  805. break;
  806. default:
  807. return ESP_PWR_LVL_INVALID;
  808. }
  809. if (tx_level < 0) {
  810. return ESP_PWR_LVL_INVALID;
  811. }
  812. return (esp_power_level_t)tx_level;
  813. }
  814. #if (!CONFIG_BT_NIMBLE_ENABLED) && (CONFIG_BT_CONTROLLER_ENABLED == true)
  815. #define BLE_SM_KEY_ERR 0x17
  816. #if CONFIG_BT_LE_CRYPTO_STACK_MBEDTLS
  817. #include "mbedtls/aes.h"
  818. #if CONFIG_BT_LE_SM_SC
  819. #include "mbedtls/cipher.h"
  820. #include "mbedtls/entropy.h"
  821. #include "mbedtls/ctr_drbg.h"
  822. #include "mbedtls/cmac.h"
  823. #include "mbedtls/ecdh.h"
  824. #include "mbedtls/ecp.h"
  825. #endif
  826. #else
  827. #include "tinycrypt/aes.h"
  828. #include "tinycrypt/constants.h"
  829. #include "tinycrypt/utils.h"
  830. #if CONFIG_BT_LE_SM_SC
  831. #include "tinycrypt/cmac_mode.h"
  832. #include "tinycrypt/ecc_dh.h"
  833. #endif
  834. #endif
  835. #if CONFIG_BT_LE_CRYPTO_STACK_MBEDTLS
  836. #if CONFIG_BT_LE_SM_SC
  837. static mbedtls_ecp_keypair keypair;
  838. #endif
  839. #endif
  840. int ble_sm_alg_gen_dhkey(const uint8_t *peer_pub_key_x, const uint8_t *peer_pub_key_y,
  841. const uint8_t *our_priv_key, uint8_t *out_dhkey)
  842. {
  843. uint8_t dh[32];
  844. uint8_t pk[64];
  845. uint8_t priv[32];
  846. int rc = BLE_SM_KEY_ERR;
  847. swap_buf(pk, peer_pub_key_x, 32);
  848. swap_buf(&pk[32], peer_pub_key_y, 32);
  849. swap_buf(priv, our_priv_key, 32);
  850. #if CONFIG_BT_LE_CRYPTO_STACK_MBEDTLS
  851. struct mbedtls_ecp_point pt = {0}, Q = {0};
  852. mbedtls_mpi z = {0}, d = {0};
  853. mbedtls_ctr_drbg_context ctr_drbg = {0};
  854. mbedtls_entropy_context entropy = {0};
  855. uint8_t pub[65] = {0};
  856. /* Hardcoded first byte of pub key for MBEDTLS_ECP_PF_UNCOMPRESSED */
  857. pub[0] = 0x04;
  858. memcpy(&pub[1], pk, 64);
  859. /* Initialize the required structures here */
  860. mbedtls_ecp_point_init(&pt);
  861. mbedtls_ecp_point_init(&Q);
  862. mbedtls_ctr_drbg_init(&ctr_drbg);
  863. mbedtls_entropy_init(&entropy);
  864. mbedtls_mpi_init(&d);
  865. mbedtls_mpi_init(&z);
  866. /* Below 3 steps are to validate public key on curve secp256r1 */
  867. if (mbedtls_ecp_group_load(&keypair.MBEDTLS_PRIVATE(grp), MBEDTLS_ECP_DP_SECP256R1) != 0) {
  868. goto exit;
  869. }
  870. if (mbedtls_ecp_point_read_binary(&keypair.MBEDTLS_PRIVATE(grp), &pt, pub, 65) != 0) {
  871. goto exit;
  872. }
  873. if (mbedtls_ecp_check_pubkey(&keypair.MBEDTLS_PRIVATE(grp), &pt) != 0) {
  874. goto exit;
  875. }
  876. /* Set PRNG */
  877. if ((rc = mbedtls_ctr_drbg_seed(&ctr_drbg, mbedtls_entropy_func, &entropy,
  878. NULL, 0)) != 0) {
  879. goto exit;
  880. }
  881. /* Prepare point Q from pub key */
  882. if (mbedtls_ecp_point_read_binary(&keypair.MBEDTLS_PRIVATE(grp), &Q, pub, 65) != 0) {
  883. goto exit;
  884. }
  885. if (mbedtls_mpi_read_binary(&d, priv, 32) != 0) {
  886. goto exit;
  887. }
  888. rc = mbedtls_ecdh_compute_shared(&keypair.MBEDTLS_PRIVATE(grp), &z, &Q, &d,
  889. mbedtls_ctr_drbg_random, &ctr_drbg);
  890. if (rc != 0) {
  891. goto exit;
  892. }
  893. rc = mbedtls_mpi_write_binary(&z, dh, 32);
  894. if (rc != 0) {
  895. goto exit;
  896. }
  897. exit:
  898. mbedtls_ecp_point_free(&pt);
  899. mbedtls_mpi_free(&z);
  900. mbedtls_mpi_free(&d);
  901. mbedtls_ecp_point_free(&Q);
  902. mbedtls_entropy_free(&entropy);
  903. mbedtls_ctr_drbg_free(&ctr_drbg);
  904. if (rc != 0) {
  905. return BLE_SM_KEY_ERR;
  906. }
  907. #else
  908. if (uECC_valid_public_key(pk, &curve_secp256r1) < 0) {
  909. return BLE_SM_KEY_ERR;
  910. }
  911. rc = uECC_shared_secret(pk, priv, dh, &curve_secp256r1);
  912. if (rc == TC_CRYPTO_FAIL) {
  913. return BLE_SM_KEY_ERR;
  914. }
  915. #endif
  916. swap_buf(out_dhkey, dh, 32);
  917. return 0;
  918. }
  919. /* based on Core Specification 4.2 Vol 3. Part H 2.3.5.6.1 */
  920. static const uint8_t ble_sm_alg_dbg_priv_key[32] = {
  921. 0x3f, 0x49, 0xf6, 0xd4, 0xa3, 0xc5, 0x5f, 0x38, 0x74, 0xc9, 0xb3, 0xe3,
  922. 0xd2, 0x10, 0x3f, 0x50, 0x4a, 0xff, 0x60, 0x7b, 0xeb, 0x40, 0xb7, 0x99,
  923. 0x58, 0x99, 0xb8, 0xa6, 0xcd, 0x3c, 0x1a, 0xbd
  924. };
  925. #if CONFIG_BT_LE_CRYPTO_STACK_MBEDTLS
  926. static int mbedtls_gen_keypair(uint8_t *public_key, uint8_t *private_key)
  927. {
  928. int rc = BLE_SM_KEY_ERR;
  929. mbedtls_entropy_context entropy = {0};
  930. mbedtls_ctr_drbg_context ctr_drbg = {0};
  931. mbedtls_entropy_init(&entropy);
  932. mbedtls_ctr_drbg_init(&ctr_drbg);
  933. mbedtls_ecp_keypair_init(&keypair);
  934. if ((rc = mbedtls_ctr_drbg_seed(&ctr_drbg, mbedtls_entropy_func, &entropy,
  935. NULL, 0)) != 0) {
  936. goto exit;
  937. }
  938. if ((rc = mbedtls_ecp_gen_key(MBEDTLS_ECP_DP_SECP256R1, &keypair,
  939. mbedtls_ctr_drbg_random, &ctr_drbg)) != 0) {
  940. goto exit;
  941. }
  942. if ((rc = mbedtls_mpi_write_binary(&keypair.MBEDTLS_PRIVATE(d), private_key, 32)) != 0) {
  943. goto exit;
  944. }
  945. size_t olen = 0;
  946. uint8_t pub[65] = {0};
  947. if ((rc = mbedtls_ecp_point_write_binary(&keypair.MBEDTLS_PRIVATE(grp), &keypair.MBEDTLS_PRIVATE(Q), MBEDTLS_ECP_PF_UNCOMPRESSED,
  948. &olen, pub, 65)) != 0) {
  949. goto exit;
  950. }
  951. memcpy(public_key, &pub[1], 64);
  952. exit:
  953. mbedtls_ctr_drbg_free(&ctr_drbg);
  954. mbedtls_entropy_free(&entropy);
  955. if (rc != 0) {
  956. mbedtls_ecp_keypair_free(&keypair);
  957. return BLE_SM_KEY_ERR;
  958. }
  959. return 0;
  960. }
  961. #endif
  962. /**
  963. * pub: 64 bytes
  964. * priv: 32 bytes
  965. */
  966. int ble_sm_alg_gen_key_pair(uint8_t *pub, uint8_t *priv)
  967. {
  968. #if CONFIG_BT_LE_SM_SC_DEBUG_KEYS
  969. swap_buf(pub, ble_sm_alg_dbg_pub_key, 32);
  970. swap_buf(&pub[32], &ble_sm_alg_dbg_pub_key[32], 32);
  971. swap_buf(priv, ble_sm_alg_dbg_priv_key, 32);
  972. #else
  973. uint8_t pk[64];
  974. do {
  975. #if CONFIG_BT_LE_CRYPTO_STACK_MBEDTLS
  976. if (mbedtls_gen_keypair(pk, priv) != 0) {
  977. return BLE_SM_KEY_ERR;
  978. }
  979. #else
  980. if (uECC_make_key(pk, priv, &curve_secp256r1) != TC_CRYPTO_SUCCESS) {
  981. return BLE_SM_KEY_ERR;
  982. }
  983. #endif
  984. /* Make sure generated key isn't debug key. */
  985. } while (memcmp(priv, ble_sm_alg_dbg_priv_key, 32) == 0);
  986. swap_buf(pub, pk, 32);
  987. swap_buf(&pub[32], &pk[32], 32);
  988. swap_in_place(priv, 32);
  989. #endif
  990. return 0;
  991. }
  992. #endif