timer_legacy.c 24 KB

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  1. /*
  2. * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. */
  6. #include <string.h>
  7. #include "esp_log.h"
  8. #include "esp_err.h"
  9. #include "esp_check.h"
  10. #include "esp_intr_alloc.h"
  11. #include "freertos/FreeRTOS.h"
  12. #include "driver/timer_types_legacy.h"
  13. #include "hal/timer_hal.h"
  14. #include "hal/timer_ll.h"
  15. #include "hal/check.h"
  16. #include "soc/timer_periph.h"
  17. #include "esp_private/esp_clk.h"
  18. #include "soc/timer_group_reg.h"
  19. #include "esp_private/periph_ctrl.h"
  20. static const char *TIMER_TAG = "timer_group";
  21. #define TIMER_GROUP_NUM_ERROR "TIMER GROUP NUM ERROR"
  22. #define TIMER_NUM_ERROR "HW TIMER NUM ERROR"
  23. #define TIMER_PARAM_ADDR_ERROR "HW TIMER PARAM ADDR ERROR"
  24. #define TIMER_NEVER_INIT_ERROR "HW TIMER NEVER INIT ERROR"
  25. #define TIMER_COUNT_DIR_ERROR "HW TIMER COUNTER DIR ERROR"
  26. #define TIMER_AUTORELOAD_ERROR "HW TIMER AUTORELOAD ERROR"
  27. #define TIMER_SCALE_ERROR "HW TIMER SCALE ERROR"
  28. #define TIMER_ALARM_ERROR "HW TIMER ALARM ERROR"
  29. #define DIVIDER_RANGE_ERROR "HW TIMER divider outside of [2, 65536] range error"
  30. #define TIMER_ENTER_CRITICAL(mux) portENTER_CRITICAL_SAFE(mux);
  31. #define TIMER_EXIT_CRITICAL(mux) portEXIT_CRITICAL_SAFE(mux);
  32. typedef struct {
  33. timer_isr_t fn; /*!< isr function */
  34. void *args; /*!< isr function args */
  35. timer_isr_handle_t timer_isr_handle; /*!< interrupt handle */
  36. timer_group_t isr_timer_group; /*!< timer group of interrupt triggered */
  37. } timer_isr_func_t;
  38. typedef struct {
  39. timer_hal_context_t hal;
  40. timer_isr_func_t timer_isr_fun;
  41. timer_src_clk_t clk_src;
  42. gptimer_count_direction_t direction;
  43. uint32_t divider;
  44. uint64_t alarm_value;
  45. bool alarm_en;
  46. bool auto_reload_en;
  47. bool counter_en;
  48. } timer_obj_t;
  49. static timer_obj_t *p_timer_obj[TIMER_GROUP_MAX][TIMER_MAX] = {0};
  50. static portMUX_TYPE timer_spinlock[TIMER_GROUP_MAX] = { [0 ... TIMER_GROUP_MAX - 1] = portMUX_INITIALIZER_UNLOCKED, };
  51. esp_err_t timer_get_counter_value(timer_group_t group_num, timer_idx_t timer_num, uint64_t *timer_val)
  52. {
  53. ESP_RETURN_ON_FALSE(group_num < TIMER_GROUP_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_GROUP_NUM_ERROR);
  54. ESP_RETURN_ON_FALSE(timer_num < TIMER_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_NUM_ERROR);
  55. ESP_RETURN_ON_FALSE(timer_val != NULL, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_PARAM_ADDR_ERROR);
  56. ESP_RETURN_ON_FALSE(p_timer_obj[group_num][timer_num] != NULL, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_NEVER_INIT_ERROR);
  57. TIMER_ENTER_CRITICAL(&timer_spinlock[group_num]);
  58. *timer_val = timer_hal_capture_and_get_counter_value(&p_timer_obj[group_num][timer_num]->hal);
  59. TIMER_EXIT_CRITICAL(&timer_spinlock[group_num]);
  60. return ESP_OK;
  61. }
  62. esp_err_t timer_get_counter_time_sec(timer_group_t group_num, timer_idx_t timer_num, double *time)
  63. {
  64. ESP_RETURN_ON_FALSE(group_num < TIMER_GROUP_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_GROUP_NUM_ERROR);
  65. ESP_RETURN_ON_FALSE(timer_num < TIMER_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_NUM_ERROR);
  66. ESP_RETURN_ON_FALSE(time != NULL, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_PARAM_ADDR_ERROR);
  67. ESP_RETURN_ON_FALSE(p_timer_obj[group_num][timer_num] != NULL, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_NEVER_INIT_ERROR);
  68. uint64_t timer_val = timer_hal_capture_and_get_counter_value(&p_timer_obj[group_num][timer_num]->hal);
  69. uint32_t div = p_timer_obj[group_num][timer_num]->divider;
  70. // [clk_tree] TODO: replace the following switch table by clk_tree API
  71. switch (p_timer_obj[group_num][timer_num]->clk_src) {
  72. #if SOC_TIMER_GROUP_SUPPORT_APB
  73. case TIMER_SRC_CLK_APB:
  74. *time = (double)timer_val * div / esp_clk_apb_freq();
  75. break;
  76. #endif
  77. #if SOC_TIMER_GROUP_SUPPORT_XTAL
  78. case TIMER_SRC_CLK_XTAL:
  79. *time = (double)timer_val * div / esp_clk_xtal_freq();
  80. break;
  81. #endif
  82. #if SOC_TIMER_GROUP_SUPPORT_AHB
  83. case TIMER_SRC_CLK_AHB:
  84. *time = (double)timer_val * div / (48 * 1000 * 1000);
  85. break;
  86. #endif
  87. #if SOC_TIMER_GROUP_SUPPORT_PLL_F40M
  88. case TIMER_SRC_CLK_PLL_F40M:
  89. *time = (double)timer_val * div / (40 * 1000 * 1000);
  90. break;
  91. #endif
  92. #if SOC_TIMER_GROUP_SUPPORT_PLL_F80M
  93. case TIMER_SRC_CLK_PLL_F80M:
  94. *time = (double)timer_val * div / (80 * 1000 * 1000);
  95. break;
  96. #endif
  97. default:
  98. ESP_RETURN_ON_FALSE(false, ESP_ERR_INVALID_ARG, TIMER_TAG, "invalid clock source");
  99. break;
  100. }
  101. return ESP_OK;
  102. }
  103. esp_err_t timer_set_counter_value(timer_group_t group_num, timer_idx_t timer_num, uint64_t load_val)
  104. {
  105. ESP_RETURN_ON_FALSE(group_num < TIMER_GROUP_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_GROUP_NUM_ERROR);
  106. ESP_RETURN_ON_FALSE(timer_num < TIMER_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_NUM_ERROR);
  107. ESP_RETURN_ON_FALSE(p_timer_obj[group_num][timer_num] != NULL, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_NEVER_INIT_ERROR);
  108. TIMER_ENTER_CRITICAL(&timer_spinlock[group_num]);
  109. timer_hal_set_counter_value(&(p_timer_obj[group_num][timer_num]->hal), load_val);
  110. TIMER_EXIT_CRITICAL(&timer_spinlock[group_num]);
  111. return ESP_OK;
  112. }
  113. esp_err_t timer_start(timer_group_t group_num, timer_idx_t timer_num)
  114. {
  115. ESP_RETURN_ON_FALSE(group_num < TIMER_GROUP_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_GROUP_NUM_ERROR);
  116. ESP_RETURN_ON_FALSE(timer_num < TIMER_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_NUM_ERROR);
  117. ESP_RETURN_ON_FALSE(p_timer_obj[group_num][timer_num] != NULL, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_NEVER_INIT_ERROR);
  118. TIMER_ENTER_CRITICAL(&timer_spinlock[group_num]);
  119. timer_ll_enable_counter(p_timer_obj[group_num][timer_num]->hal.dev, timer_num, true);
  120. p_timer_obj[group_num][timer_num]->counter_en = true;
  121. TIMER_EXIT_CRITICAL(&timer_spinlock[group_num]);
  122. return ESP_OK;
  123. }
  124. esp_err_t timer_pause(timer_group_t group_num, timer_idx_t timer_num)
  125. {
  126. ESP_RETURN_ON_FALSE(group_num < TIMER_GROUP_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_GROUP_NUM_ERROR);
  127. ESP_RETURN_ON_FALSE(timer_num < TIMER_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_NUM_ERROR);
  128. ESP_RETURN_ON_FALSE(p_timer_obj[group_num][timer_num] != NULL, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_NEVER_INIT_ERROR);
  129. TIMER_ENTER_CRITICAL(&timer_spinlock[group_num]);
  130. timer_ll_enable_counter(p_timer_obj[group_num][timer_num]->hal.dev, timer_num, false);
  131. p_timer_obj[group_num][timer_num]->counter_en = false;
  132. TIMER_EXIT_CRITICAL(&timer_spinlock[group_num]);
  133. return ESP_OK;
  134. }
  135. esp_err_t timer_set_counter_mode(timer_group_t group_num, timer_idx_t timer_num, timer_count_dir_t counter_dir)
  136. {
  137. ESP_RETURN_ON_FALSE(group_num < TIMER_GROUP_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_GROUP_NUM_ERROR);
  138. ESP_RETURN_ON_FALSE(timer_num < TIMER_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_NUM_ERROR);
  139. ESP_RETURN_ON_FALSE(counter_dir < TIMER_COUNT_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_COUNT_DIR_ERROR);
  140. ESP_RETURN_ON_FALSE(p_timer_obj[group_num][timer_num] != NULL, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_NEVER_INIT_ERROR);
  141. TIMER_ENTER_CRITICAL(&timer_spinlock[group_num]);
  142. timer_ll_set_count_direction(p_timer_obj[group_num][timer_num]->hal.dev, timer_num, counter_dir);
  143. TIMER_EXIT_CRITICAL(&timer_spinlock[group_num]);
  144. return ESP_OK;
  145. }
  146. esp_err_t timer_set_auto_reload(timer_group_t group_num, timer_idx_t timer_num, timer_autoreload_t reload)
  147. {
  148. ESP_RETURN_ON_FALSE(group_num < TIMER_GROUP_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_GROUP_NUM_ERROR);
  149. ESP_RETURN_ON_FALSE(timer_num < TIMER_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_NUM_ERROR);
  150. ESP_RETURN_ON_FALSE(reload < TIMER_AUTORELOAD_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_AUTORELOAD_ERROR);
  151. ESP_RETURN_ON_FALSE(p_timer_obj[group_num][timer_num] != NULL, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_NEVER_INIT_ERROR);
  152. TIMER_ENTER_CRITICAL(&timer_spinlock[group_num]);
  153. timer_ll_enable_auto_reload(p_timer_obj[group_num][timer_num]->hal.dev, timer_num, reload);
  154. p_timer_obj[group_num][timer_num]->auto_reload_en = reload;
  155. TIMER_EXIT_CRITICAL(&timer_spinlock[group_num]);
  156. return ESP_OK;
  157. }
  158. esp_err_t timer_set_divider(timer_group_t group_num, timer_idx_t timer_num, uint32_t divider)
  159. {
  160. ESP_RETURN_ON_FALSE(group_num < TIMER_GROUP_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_GROUP_NUM_ERROR);
  161. ESP_RETURN_ON_FALSE(timer_num < TIMER_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_NUM_ERROR);
  162. ESP_RETURN_ON_FALSE(divider > 1 && divider < 65537, ESP_ERR_INVALID_ARG, TIMER_TAG, DIVIDER_RANGE_ERROR);
  163. ESP_RETURN_ON_FALSE(p_timer_obj[group_num][timer_num] != NULL, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_NEVER_INIT_ERROR);
  164. TIMER_ENTER_CRITICAL(&timer_spinlock[group_num]);
  165. timer_ll_set_clock_prescale(p_timer_obj[group_num][timer_num]->hal.dev, timer_num, divider);
  166. p_timer_obj[group_num][timer_num]->divider = divider;
  167. TIMER_EXIT_CRITICAL(&timer_spinlock[group_num]);
  168. return ESP_OK;
  169. }
  170. esp_err_t timer_set_alarm_value(timer_group_t group_num, timer_idx_t timer_num, uint64_t alarm_value)
  171. {
  172. ESP_RETURN_ON_FALSE(group_num < TIMER_GROUP_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_GROUP_NUM_ERROR);
  173. ESP_RETURN_ON_FALSE(timer_num < TIMER_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_NUM_ERROR);
  174. ESP_RETURN_ON_FALSE(p_timer_obj[group_num][timer_num] != NULL, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_NEVER_INIT_ERROR);
  175. TIMER_ENTER_CRITICAL(&timer_spinlock[group_num]);
  176. timer_ll_set_alarm_value(p_timer_obj[group_num][timer_num]->hal.dev, timer_num, alarm_value);
  177. p_timer_obj[group_num][timer_num]->alarm_value = alarm_value;
  178. TIMER_EXIT_CRITICAL(&timer_spinlock[group_num]);
  179. return ESP_OK;
  180. }
  181. esp_err_t timer_get_alarm_value(timer_group_t group_num, timer_idx_t timer_num, uint64_t *alarm_value)
  182. {
  183. ESP_RETURN_ON_FALSE(group_num < TIMER_GROUP_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_GROUP_NUM_ERROR);
  184. ESP_RETURN_ON_FALSE(timer_num < TIMER_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_NUM_ERROR);
  185. ESP_RETURN_ON_FALSE(alarm_value != NULL, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_PARAM_ADDR_ERROR);
  186. ESP_RETURN_ON_FALSE(p_timer_obj[group_num][timer_num] != NULL, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_NEVER_INIT_ERROR);
  187. TIMER_ENTER_CRITICAL(&timer_spinlock[group_num]);
  188. *alarm_value = p_timer_obj[group_num][timer_num]->alarm_value;
  189. TIMER_EXIT_CRITICAL(&timer_spinlock[group_num]);
  190. return ESP_OK;
  191. }
  192. esp_err_t timer_set_alarm(timer_group_t group_num, timer_idx_t timer_num, timer_alarm_t alarm_en)
  193. {
  194. ESP_RETURN_ON_FALSE(group_num < TIMER_GROUP_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_GROUP_NUM_ERROR);
  195. ESP_RETURN_ON_FALSE(timer_num < TIMER_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_NUM_ERROR);
  196. ESP_RETURN_ON_FALSE(alarm_en < TIMER_ALARM_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_ALARM_ERROR);
  197. ESP_RETURN_ON_FALSE(p_timer_obj[group_num][timer_num] != NULL, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_NEVER_INIT_ERROR);
  198. TIMER_ENTER_CRITICAL(&timer_spinlock[group_num]);
  199. timer_ll_enable_alarm(p_timer_obj[group_num][timer_num]->hal.dev, timer_num, alarm_en);
  200. TIMER_EXIT_CRITICAL(&timer_spinlock[group_num]);
  201. return ESP_OK;
  202. }
  203. static void IRAM_ATTR timer_isr_default(void *arg)
  204. {
  205. bool is_awoken = false;
  206. timer_obj_t *timer_obj = (timer_obj_t *)arg;
  207. if (timer_obj == NULL || timer_obj->timer_isr_fun.fn == NULL) {
  208. return;
  209. }
  210. uint32_t timer_id = timer_obj->hal.timer_id;
  211. timer_hal_context_t *hal = &timer_obj->hal;
  212. TIMER_ENTER_CRITICAL(&timer_spinlock[timer_obj->timer_isr_fun.isr_timer_group]);
  213. uint32_t intr_status = timer_ll_get_intr_status(hal->dev);
  214. uint64_t old_alarm_value = timer_obj->alarm_value;
  215. if (intr_status & TIMER_LL_EVENT_ALARM(timer_id)) {
  216. // Clear interrupt status
  217. timer_ll_clear_intr_status(hal->dev, TIMER_LL_EVENT_ALARM(timer_id));
  218. // call user registered callback
  219. is_awoken = timer_obj->timer_isr_fun.fn(timer_obj->timer_isr_fun.args);
  220. // reenable alarm if required
  221. uint64_t new_alarm_value = timer_obj->alarm_value;
  222. bool reenable_alarm = (new_alarm_value != old_alarm_value) || timer_obj->auto_reload_en;
  223. timer_ll_enable_alarm(hal->dev, timer_id, reenable_alarm);
  224. }
  225. TIMER_EXIT_CRITICAL(&timer_spinlock[timer_obj->timer_isr_fun.isr_timer_group]);
  226. if (is_awoken) {
  227. portYIELD_FROM_ISR();
  228. }
  229. }
  230. esp_err_t timer_enable_intr(timer_group_t group_num, timer_idx_t timer_num)
  231. {
  232. ESP_RETURN_ON_FALSE(group_num < TIMER_GROUP_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_GROUP_NUM_ERROR);
  233. ESP_RETURN_ON_FALSE(timer_num < TIMER_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_NUM_ERROR);
  234. ESP_RETURN_ON_FALSE(p_timer_obj[group_num][timer_num] != NULL, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_NEVER_INIT_ERROR);
  235. TIMER_ENTER_CRITICAL(&timer_spinlock[group_num]);
  236. timer_ll_enable_intr(p_timer_obj[group_num][timer_num]->hal.dev, TIMER_LL_EVENT_ALARM(timer_num), true);
  237. TIMER_EXIT_CRITICAL(&timer_spinlock[group_num]);
  238. return ESP_OK;
  239. }
  240. esp_err_t timer_disable_intr(timer_group_t group_num, timer_idx_t timer_num)
  241. {
  242. ESP_RETURN_ON_FALSE(group_num < TIMER_GROUP_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_GROUP_NUM_ERROR);
  243. ESP_RETURN_ON_FALSE(timer_num < TIMER_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_NUM_ERROR);
  244. ESP_RETURN_ON_FALSE(p_timer_obj[group_num][timer_num] != NULL, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_NEVER_INIT_ERROR);
  245. TIMER_ENTER_CRITICAL(&timer_spinlock[group_num]);
  246. timer_ll_enable_intr(p_timer_obj[group_num][timer_num]->hal.dev, TIMER_LL_EVENT_ALARM(timer_num), false);
  247. TIMER_EXIT_CRITICAL(&timer_spinlock[group_num]);
  248. return ESP_OK;
  249. }
  250. esp_err_t timer_isr_register(timer_group_t group_num, timer_idx_t timer_num,
  251. void (*fn)(void *), void *arg, int intr_alloc_flags, timer_isr_handle_t *handle)
  252. {
  253. ESP_RETURN_ON_FALSE(group_num < TIMER_GROUP_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_GROUP_NUM_ERROR);
  254. ESP_RETURN_ON_FALSE(timer_num < TIMER_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_NUM_ERROR);
  255. ESP_RETURN_ON_FALSE(fn != NULL, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_PARAM_ADDR_ERROR);
  256. ESP_RETURN_ON_FALSE(p_timer_obj[group_num][timer_num] != NULL, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_NEVER_INIT_ERROR);
  257. timer_hal_context_t *hal = &p_timer_obj[group_num][timer_num]->hal;
  258. return esp_intr_alloc_intrstatus(timer_group_periph_signals.groups[group_num].timer_irq_id[timer_num],
  259. intr_alloc_flags,
  260. (uint32_t)timer_ll_get_intr_status_reg(hal->dev),
  261. TIMER_LL_EVENT_ALARM(timer_num), fn, arg, handle);
  262. }
  263. esp_err_t timer_isr_callback_add(timer_group_t group_num, timer_idx_t timer_num, timer_isr_t isr_handler, void *args, int intr_alloc_flags)
  264. {
  265. ESP_RETURN_ON_FALSE(group_num < TIMER_GROUP_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_GROUP_NUM_ERROR);
  266. ESP_RETURN_ON_FALSE(timer_num < TIMER_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_NUM_ERROR);
  267. ESP_RETURN_ON_FALSE(p_timer_obj[group_num][timer_num] != NULL, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_NEVER_INIT_ERROR);
  268. esp_err_t ret = ESP_OK;
  269. timer_disable_intr(group_num, timer_num);
  270. p_timer_obj[group_num][timer_num]->timer_isr_fun.fn = isr_handler;
  271. p_timer_obj[group_num][timer_num]->timer_isr_fun.args = args;
  272. p_timer_obj[group_num][timer_num]->timer_isr_fun.isr_timer_group = group_num;
  273. ret = timer_isr_register(group_num, timer_num, timer_isr_default, (void *)p_timer_obj[group_num][timer_num],
  274. intr_alloc_flags, &(p_timer_obj[group_num][timer_num]->timer_isr_fun.timer_isr_handle));
  275. ESP_RETURN_ON_ERROR(ret, TIMER_TAG, "register interrupt service failed");
  276. timer_enable_intr(group_num, timer_num);
  277. return ret;
  278. }
  279. esp_err_t timer_isr_callback_remove(timer_group_t group_num, timer_idx_t timer_num)
  280. {
  281. ESP_RETURN_ON_FALSE(group_num < TIMER_GROUP_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_GROUP_NUM_ERROR);
  282. ESP_RETURN_ON_FALSE(timer_num < TIMER_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_NUM_ERROR);
  283. ESP_RETURN_ON_FALSE(p_timer_obj[group_num][timer_num] != NULL, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_NEVER_INIT_ERROR);
  284. timer_disable_intr(group_num, timer_num);
  285. p_timer_obj[group_num][timer_num]->timer_isr_fun.fn = NULL;
  286. p_timer_obj[group_num][timer_num]->timer_isr_fun.args = NULL;
  287. esp_intr_free(p_timer_obj[group_num][timer_num]->timer_isr_fun.timer_isr_handle);
  288. return ESP_OK;
  289. }
  290. esp_err_t timer_init(timer_group_t group_num, timer_idx_t timer_num, const timer_config_t *config)
  291. {
  292. ESP_RETURN_ON_FALSE(group_num < TIMER_GROUP_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_GROUP_NUM_ERROR);
  293. ESP_RETURN_ON_FALSE(timer_num < TIMER_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_NUM_ERROR);
  294. ESP_RETURN_ON_FALSE(config != NULL, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_PARAM_ADDR_ERROR);
  295. ESP_RETURN_ON_FALSE(config->divider > 1 && config->divider < 65537, ESP_ERR_INVALID_ARG, TIMER_TAG, DIVIDER_RANGE_ERROR);
  296. ESP_RETURN_ON_FALSE(config->intr_type < TIMER_INTR_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, "only support Level Interrupt");
  297. if (p_timer_obj[group_num][timer_num] == NULL) {
  298. p_timer_obj[group_num][timer_num] = (timer_obj_t *) heap_caps_calloc(1, sizeof(timer_obj_t), MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
  299. ESP_RETURN_ON_FALSE(p_timer_obj[group_num][timer_num], ESP_ERR_NO_MEM, TIMER_TAG, "no mem for timer object");
  300. }
  301. timer_hal_context_t *hal = &p_timer_obj[group_num][timer_num]->hal;
  302. periph_module_enable(timer_group_periph_signals.groups[group_num].module);
  303. TIMER_ENTER_CRITICAL(&timer_spinlock[group_num]);
  304. timer_hal_init(hal, group_num, timer_num);
  305. timer_hal_set_counter_value(hal, 0);
  306. // although `clk_src` is of `timer_src_clk_t` type, but it's binary compatible with `gptimer_clock_source_t`,
  307. // as the underlying enum entries come from the same `soc_module_clk_t`
  308. timer_ll_set_clock_source(p_timer_obj[group_num][timer_num]->hal.dev, timer_num, (gptimer_clock_source_t)config->clk_src);
  309. timer_ll_set_clock_prescale(hal->dev, timer_num, config->divider);
  310. timer_ll_set_count_direction(p_timer_obj[group_num][timer_num]->hal.dev, timer_num, config->counter_dir);
  311. timer_ll_enable_intr(hal->dev, TIMER_LL_EVENT_ALARM(timer_num), false);
  312. timer_ll_clear_intr_status(hal->dev, TIMER_LL_EVENT_ALARM(timer_num));
  313. timer_ll_enable_alarm(hal->dev, timer_num, config->alarm_en);
  314. timer_ll_enable_auto_reload(hal->dev, timer_num, config->auto_reload);
  315. timer_ll_enable_counter(hal->dev, timer_num, config->counter_en);
  316. p_timer_obj[group_num][timer_num]->clk_src = config->clk_src;
  317. p_timer_obj[group_num][timer_num]->alarm_en = config->alarm_en;
  318. p_timer_obj[group_num][timer_num]->auto_reload_en = config->auto_reload;
  319. p_timer_obj[group_num][timer_num]->direction = config->counter_dir;
  320. p_timer_obj[group_num][timer_num]->counter_en = config->counter_en;
  321. p_timer_obj[group_num][timer_num]->divider = config->divider;
  322. TIMER_EXIT_CRITICAL(&timer_spinlock[group_num]);
  323. return ESP_OK;
  324. }
  325. esp_err_t timer_deinit(timer_group_t group_num, timer_idx_t timer_num)
  326. {
  327. ESP_RETURN_ON_FALSE(group_num < TIMER_GROUP_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_GROUP_NUM_ERROR);
  328. ESP_RETURN_ON_FALSE(timer_num < TIMER_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_NUM_ERROR);
  329. ESP_RETURN_ON_FALSE(p_timer_obj[group_num][timer_num] != NULL, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_NEVER_INIT_ERROR);
  330. timer_hal_context_t *hal = &p_timer_obj[group_num][timer_num]->hal;
  331. TIMER_ENTER_CRITICAL(&timer_spinlock[group_num]);
  332. timer_ll_enable_intr(hal->dev, TIMER_LL_EVENT_ALARM(timer_num), false);
  333. timer_ll_clear_intr_status(hal->dev, TIMER_LL_EVENT_ALARM(timer_num));
  334. timer_hal_deinit(hal);
  335. TIMER_EXIT_CRITICAL(&timer_spinlock[group_num]);
  336. free(p_timer_obj[group_num][timer_num]);
  337. p_timer_obj[group_num][timer_num] = NULL;
  338. return ESP_OK;
  339. }
  340. esp_err_t timer_get_config(timer_group_t group_num, timer_idx_t timer_num, timer_config_t *config)
  341. {
  342. ESP_RETURN_ON_FALSE(group_num < TIMER_GROUP_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_GROUP_NUM_ERROR);
  343. ESP_RETURN_ON_FALSE(timer_num < TIMER_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_NUM_ERROR);
  344. ESP_RETURN_ON_FALSE(config != NULL, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_PARAM_ADDR_ERROR);
  345. ESP_RETURN_ON_FALSE(p_timer_obj[group_num][timer_num] != NULL, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_NEVER_INIT_ERROR);
  346. TIMER_ENTER_CRITICAL(&timer_spinlock[group_num]);
  347. config->alarm_en = p_timer_obj[group_num][timer_num]->alarm_en;
  348. config->auto_reload = p_timer_obj[group_num][timer_num]->auto_reload_en;
  349. config->counter_dir = p_timer_obj[group_num][timer_num]->direction;
  350. config->counter_en = p_timer_obj[group_num][timer_num]->counter_en;
  351. config->divider = p_timer_obj[group_num][timer_num]->divider;
  352. config->intr_type = TIMER_INTR_LEVEL;
  353. TIMER_EXIT_CRITICAL(&timer_spinlock[group_num]);
  354. return ESP_OK;
  355. }
  356. esp_err_t timer_group_intr_enable(timer_group_t group_num, timer_intr_t en_mask)
  357. {
  358. ESP_RETURN_ON_FALSE(group_num < TIMER_GROUP_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_GROUP_NUM_ERROR);
  359. ESP_RETURN_ON_FALSE(p_timer_obj[group_num] != NULL, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_NEVER_INIT_ERROR);
  360. TIMER_ENTER_CRITICAL(&timer_spinlock[group_num]);
  361. timer_ll_enable_intr(p_timer_obj[group_num][0]->hal.dev, en_mask, true);
  362. TIMER_EXIT_CRITICAL(&timer_spinlock[group_num]);
  363. return ESP_OK;
  364. }
  365. esp_err_t timer_group_intr_disable(timer_group_t group_num, timer_intr_t disable_mask)
  366. {
  367. ESP_RETURN_ON_FALSE(group_num < TIMER_GROUP_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_GROUP_NUM_ERROR);
  368. ESP_RETURN_ON_FALSE(p_timer_obj[group_num] != NULL, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_NEVER_INIT_ERROR);
  369. TIMER_ENTER_CRITICAL(&timer_spinlock[group_num]);
  370. timer_ll_enable_intr(p_timer_obj[group_num][0]->hal.dev, disable_mask, false);
  371. TIMER_EXIT_CRITICAL(&timer_spinlock[group_num]);
  372. return ESP_OK;
  373. }
  374. uint32_t IRAM_ATTR timer_group_get_intr_status_in_isr(timer_group_t group_num)
  375. {
  376. uint32_t intr_status = 0;
  377. if (p_timer_obj[group_num][TIMER_0] != NULL) {
  378. intr_status = timer_ll_get_intr_status(TIMER_LL_GET_HW(group_num)) & TIMER_LL_EVENT_ALARM(0);
  379. }
  380. #if SOC_TIMER_GROUP_TIMERS_PER_GROUP > 1
  381. else if (p_timer_obj[group_num][TIMER_1] != NULL) {
  382. intr_status = timer_ll_get_intr_status(TIMER_LL_GET_HW(group_num)) & TIMER_LL_EVENT_ALARM(1);
  383. }
  384. #endif
  385. return intr_status;
  386. }
  387. void IRAM_ATTR timer_group_clr_intr_status_in_isr(timer_group_t group_num, timer_idx_t timer_num)
  388. {
  389. timer_ll_clear_intr_status(p_timer_obj[group_num][timer_num]->hal.dev, TIMER_LL_EVENT_ALARM(timer_num));
  390. }
  391. void IRAM_ATTR timer_group_enable_alarm_in_isr(timer_group_t group_num, timer_idx_t timer_num)
  392. {
  393. timer_ll_enable_alarm(p_timer_obj[group_num][timer_num]->hal.dev, timer_num, true);
  394. }
  395. uint64_t IRAM_ATTR timer_group_get_counter_value_in_isr(timer_group_t group_num, timer_idx_t timer_num)
  396. {
  397. timer_ll_trigger_soft_capture(p_timer_obj[group_num][timer_num]->hal.dev, timer_num);
  398. uint64_t val = timer_ll_get_counter_value(p_timer_obj[group_num][timer_num]->hal.dev, timer_num);
  399. return val;
  400. }
  401. void IRAM_ATTR timer_group_set_alarm_value_in_isr(timer_group_t group_num, timer_idx_t timer_num, uint64_t alarm_val)
  402. {
  403. timer_ll_set_alarm_value(p_timer_obj[group_num][timer_num]->hal.dev, timer_num, alarm_val);
  404. p_timer_obj[group_num][timer_num]->alarm_value = alarm_val;
  405. }
  406. void IRAM_ATTR timer_group_set_counter_enable_in_isr(timer_group_t group_num, timer_idx_t timer_num, timer_start_t counter_en)
  407. {
  408. timer_ll_enable_counter(p_timer_obj[group_num][timer_num]->hal.dev, timer_num, counter_en);
  409. p_timer_obj[group_num][timer_num]->counter_en = counter_en;
  410. }
  411. bool IRAM_ATTR timer_group_get_auto_reload_in_isr(timer_group_t group_num, timer_idx_t timer_num)
  412. {
  413. return p_timer_obj[group_num][timer_num]->auto_reload_en;
  414. }
  415. /**
  416. * @brief This function will be called during start up, to check that this legacy timer group driver is not running along with the gptimer driver
  417. */
  418. __attribute__((constructor))
  419. static void check_legacy_timer_driver_conflict(void)
  420. {
  421. // This function was declared as weak here. gptimer driver has one implementation.
  422. // So if gptimer driver is not linked in, then `gptimer_new_timer()` should be NULL at runtime.
  423. extern __attribute__((weak)) esp_err_t gptimer_new_timer(const void *config, void **ret_timer);
  424. if ((void *)gptimer_new_timer != NULL) {
  425. ESP_EARLY_LOGE(TIMER_TAG, "CONFLICT! driver_ng is not allowed to be used with the legacy driver");
  426. abort();
  427. }
  428. ESP_EARLY_LOGW(TIMER_TAG, "legacy driver is deprecated, please migrate to `driver/gptimer.h`");
  429. }