cpu_start.c 12 KB

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  1. // Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
  2. //
  3. // Licensed under the Apache License, Version 2.0 (the "License");
  4. // you may not use this file except in compliance with the License.
  5. // You may obtain a copy of the License at
  6. //
  7. // http://www.apache.org/licenses/LICENSE-2.0
  8. //
  9. // Unless required by applicable law or agreed to in writing, software
  10. // distributed under the License is distributed on an "AS IS" BASIS,
  11. // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  12. // See the License for the specific language governing permissions and
  13. // limitations under the License.
  14. #include <stdint.h>
  15. #include <string.h>
  16. #include "esp_attr.h"
  17. #include "esp_err.h"
  18. #include "rom/ets_sys.h"
  19. #include "rom/uart.h"
  20. #include "rom/rtc.h"
  21. #include "rom/cache.h"
  22. #include "soc/cpu.h"
  23. #include "soc/rtc.h"
  24. #include "soc/dport_reg.h"
  25. #include "soc/io_mux_reg.h"
  26. #include "soc/rtc_cntl_reg.h"
  27. #include "soc/timer_group_reg.h"
  28. #include "driver/rtc_io.h"
  29. #include "freertos/FreeRTOS.h"
  30. #include "freertos/task.h"
  31. #include "freertos/semphr.h"
  32. #include "freertos/queue.h"
  33. #include "freertos/portmacro.h"
  34. #include "tcpip_adapter.h"
  35. #include "esp_heap_caps_init.h"
  36. #include "sdkconfig.h"
  37. #include "esp_system.h"
  38. #include "esp_spi_flash.h"
  39. #include "nvs_flash.h"
  40. #include "esp_event.h"
  41. #include "esp_spi_flash.h"
  42. #include "esp_ipc.h"
  43. #include "esp_crosscore_int.h"
  44. #include "esp_dport_access.h"
  45. #include "esp_log.h"
  46. #include "esp_vfs_dev.h"
  47. #include "esp_newlib.h"
  48. #include "esp_brownout.h"
  49. #include "esp_int_wdt.h"
  50. #include "esp_task_wdt.h"
  51. #include "esp_phy_init.h"
  52. #include "esp_cache_err_int.h"
  53. #include "esp_coexist.h"
  54. #include "esp_panic.h"
  55. #include "esp_core_dump.h"
  56. #include "esp_app_trace.h"
  57. #include "esp_efuse.h"
  58. #include "esp_spiram.h"
  59. #include "esp_clk.h"
  60. #include "esp_timer.h"
  61. #include "trax.h"
  62. #define STRINGIFY(s) STRINGIFY2(s)
  63. #define STRINGIFY2(s) #s
  64. void start_cpu0(void) __attribute__((weak, alias("start_cpu0_default"))) __attribute__((noreturn));
  65. void start_cpu0_default(void) IRAM_ATTR __attribute__((noreturn));
  66. #if !CONFIG_FREERTOS_UNICORE
  67. static void IRAM_ATTR call_start_cpu1() __attribute__((noreturn));
  68. void start_cpu1(void) __attribute__((weak, alias("start_cpu1_default"))) __attribute__((noreturn));
  69. void start_cpu1_default(void) IRAM_ATTR __attribute__((noreturn));
  70. static bool app_cpu_started = false;
  71. #endif //!CONFIG_FREERTOS_UNICORE
  72. static void do_global_ctors(void);
  73. static void main_task(void* args);
  74. extern void app_main(void);
  75. extern esp_err_t esp_pthread_init(void);
  76. extern int _bss_start;
  77. extern int _bss_end;
  78. extern int _rtc_bss_start;
  79. extern int _rtc_bss_end;
  80. extern int _init_start;
  81. extern void (*__init_array_start)(void);
  82. extern void (*__init_array_end)(void);
  83. extern volatile int port_xSchedulerRunning[2];
  84. static const char* TAG = "cpu_start";
  85. struct object { long placeholder[ 10 ]; };
  86. void __register_frame_info (const void *begin, struct object *ob);
  87. extern char __eh_frame[];
  88. /*
  89. * We arrive here after the bootloader finished loading the program from flash. The hardware is mostly uninitialized,
  90. * and the app CPU is in reset. We do have a stack, so we can do the initialization in C.
  91. */
  92. void IRAM_ATTR call_start_cpu0()
  93. {
  94. #if CONFIG_FREERTOS_UNICORE
  95. RESET_REASON rst_reas[1];
  96. #else
  97. RESET_REASON rst_reas[2];
  98. #endif
  99. cpu_configure_region_protection();
  100. //Move exception vectors to IRAM
  101. asm volatile (\
  102. "wsr %0, vecbase\n" \
  103. ::"r"(&_init_start));
  104. rst_reas[0] = rtc_get_reset_reason(0);
  105. #if !CONFIG_FREERTOS_UNICORE
  106. rst_reas[1] = rtc_get_reset_reason(1);
  107. #endif
  108. // from panic handler we can be reset by RWDT or TG0WDT
  109. if (rst_reas[0] == RTCWDT_SYS_RESET || rst_reas[0] == TG0WDT_SYS_RESET
  110. #if !CONFIG_FREERTOS_UNICORE
  111. || rst_reas[1] == RTCWDT_SYS_RESET || rst_reas[1] == TG0WDT_SYS_RESET
  112. #endif
  113. ) {
  114. esp_panic_wdt_stop();
  115. }
  116. // Temporary workaround for an ugly crash, until we allow > 192KB of static DRAM
  117. if ((intptr_t)&_bss_end > 0x3FFE0000) {
  118. // Can't use assert() or logging here because there's no .bss
  119. ets_printf("ERROR: Static .bss section extends past 0x3FFE0000. IDF cannot boot.\n");
  120. abort();
  121. }
  122. //Clear BSS. Please do not attempt to do any complex stuff (like early logging) before this.
  123. memset(&_bss_start, 0, (&_bss_end - &_bss_start) * sizeof(_bss_start));
  124. /* Unless waking from deep sleep (implying RTC memory is intact), clear RTC bss */
  125. if (rst_reas[0] != DEEPSLEEP_RESET) {
  126. memset(&_rtc_bss_start, 0, (&_rtc_bss_end - &_rtc_bss_start) * sizeof(_rtc_bss_start));
  127. }
  128. #if CONFIG_SPIRAM_BOOT_INIT
  129. if (esp_spiram_init() != ESP_OK) {
  130. ESP_EARLY_LOGE(TAG, "Failed to init external RAM!");
  131. abort();
  132. }
  133. #endif
  134. ESP_EARLY_LOGI(TAG, "Pro cpu up.");
  135. #if !CONFIG_FREERTOS_UNICORE
  136. ESP_EARLY_LOGI(TAG, "Starting app cpu, entry point is %p", call_start_cpu1);
  137. //Flush and enable icache for APP CPU
  138. Cache_Flush(1);
  139. Cache_Read_Enable(1);
  140. esp_cpu_unstall(1);
  141. // Enable clock and reset APP CPU. Note that OpenOCD may have already
  142. // enabled clock and taken APP CPU out of reset. In this case don't reset
  143. // APP CPU again, as that will clear the breakpoints which may have already
  144. // been set.
  145. if (!DPORT_GET_PERI_REG_MASK(DPORT_APPCPU_CTRL_B_REG, DPORT_APPCPU_CLKGATE_EN)) {
  146. DPORT_SET_PERI_REG_MASK(DPORT_APPCPU_CTRL_B_REG, DPORT_APPCPU_CLKGATE_EN);
  147. DPORT_CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_C_REG, DPORT_APPCPU_RUNSTALL);
  148. DPORT_SET_PERI_REG_MASK(DPORT_APPCPU_CTRL_A_REG, DPORT_APPCPU_RESETTING);
  149. DPORT_CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_A_REG, DPORT_APPCPU_RESETTING);
  150. }
  151. ets_set_appcpu_boot_addr((uint32_t)call_start_cpu1);
  152. while (!app_cpu_started) {
  153. ets_delay_us(100);
  154. }
  155. #else
  156. ESP_EARLY_LOGI(TAG, "Single core mode");
  157. DPORT_CLEAR_PERI_REG_MASK(DPORT_APPCPU_CTRL_B_REG, DPORT_APPCPU_CLKGATE_EN);
  158. #endif
  159. #if CONFIG_SPIRAM_MEMTEST
  160. bool ext_ram_ok=esp_spiram_test();
  161. if (!ext_ram_ok) {
  162. ESP_EARLY_LOGE(TAG, "External RAM failed memory test!");
  163. abort();
  164. }
  165. #endif
  166. /* Initialize heap allocator. WARNING: This *needs* to happen *after* the app cpu has booted.
  167. If the heap allocator is initialized first, it will put free memory linked list items into
  168. memory also used by the ROM. Starting the app cpu will let its ROM initialize that memory,
  169. corrupting those linked lists. Initializing the allocator *after* the app cpu has booted
  170. works around this problem.
  171. With SPI RAM enabled, there's a second reason: half of the SPI RAM will be managed by the
  172. app CPU, and when that is not up yet, the memory will be inaccessible and heap_caps_init may
  173. fail initializing it properly. */
  174. heap_caps_init();
  175. ESP_EARLY_LOGI(TAG, "Pro cpu start user code");
  176. start_cpu0();
  177. }
  178. #if !CONFIG_FREERTOS_UNICORE
  179. static void wdt_reset_cpu1_info_enable(void)
  180. {
  181. DPORT_REG_SET_BIT(DPORT_APP_CPU_RECORD_CTRL_REG, DPORT_APP_CPU_PDEBUG_ENABLE | DPORT_APP_CPU_RECORD_ENABLE);
  182. DPORT_REG_CLR_BIT(DPORT_APP_CPU_RECORD_CTRL_REG, DPORT_APP_CPU_RECORD_ENABLE);
  183. }
  184. void IRAM_ATTR call_start_cpu1()
  185. {
  186. asm volatile (\
  187. "wsr %0, vecbase\n" \
  188. ::"r"(&_init_start));
  189. ets_set_appcpu_boot_addr(0);
  190. cpu_configure_region_protection();
  191. #if CONFIG_CONSOLE_UART_NONE
  192. ets_install_putc1(NULL);
  193. ets_install_putc2(NULL);
  194. #else // CONFIG_CONSOLE_UART_NONE
  195. uartAttach();
  196. ets_install_uart_printf();
  197. uart_tx_switch(CONFIG_CONSOLE_UART_NUM);
  198. #endif
  199. wdt_reset_cpu1_info_enable();
  200. ESP_EARLY_LOGI(TAG, "App cpu up.");
  201. app_cpu_started = 1;
  202. start_cpu1();
  203. }
  204. #endif //!CONFIG_FREERTOS_UNICORE
  205. static void intr_matrix_clear(void)
  206. {
  207. //Clear all the interrupt matrix register
  208. for (int i = ETS_WIFI_MAC_INTR_SOURCE; i <= ETS_CACHE_IA_INTR_SOURCE; i++) {
  209. intr_matrix_set(0, i, ETS_INVALID_INUM);
  210. #if !CONFIG_FREERTOS_UNICORE
  211. intr_matrix_set(1, i, ETS_INVALID_INUM);
  212. #endif
  213. }
  214. }
  215. void start_cpu0_default(void)
  216. {
  217. esp_err_t err;
  218. esp_setup_syscall_table();
  219. #if CONFIG_SPIRAM_BOOT_INIT && (CONFIG_SPIRAM_USE_CAPS_ALLOC || CONFIG_SPIRAM_USE_MALLOC)
  220. esp_err_t r=esp_spiram_add_to_heapalloc();
  221. if (r != ESP_OK) {
  222. ESP_EARLY_LOGE(TAG, "External RAM could not be added to heap!");
  223. abort();
  224. }
  225. #endif
  226. //Enable trace memory and immediately start trace.
  227. #if CONFIG_ESP32_TRAX
  228. #if CONFIG_ESP32_TRAX_TWOBANKS
  229. trax_enable(TRAX_ENA_PRO_APP);
  230. #else
  231. trax_enable(TRAX_ENA_PRO);
  232. #endif
  233. trax_start_trace(TRAX_DOWNCOUNT_WORDS);
  234. #endif
  235. esp_clk_init();
  236. esp_perip_clk_init();
  237. intr_matrix_clear();
  238. #ifndef CONFIG_CONSOLE_UART_NONE
  239. uart_div_modify(CONFIG_CONSOLE_UART_NUM, (rtc_clk_apb_freq_get() << 4) / CONFIG_CONSOLE_UART_BAUDRATE);
  240. #endif
  241. #if CONFIG_BROWNOUT_DET
  242. esp_brownout_init();
  243. #endif
  244. #if CONFIG_DISABLE_BASIC_ROM_CONSOLE
  245. esp_efuse_disable_basic_rom_console();
  246. #endif
  247. rtc_gpio_force_hold_dis_all();
  248. esp_vfs_dev_uart_register();
  249. esp_reent_init(_GLOBAL_REENT);
  250. #ifndef CONFIG_CONSOLE_UART_NONE
  251. const char* default_uart_dev = "/dev/uart/" STRINGIFY(CONFIG_CONSOLE_UART_NUM);
  252. _GLOBAL_REENT->_stdin = fopen(default_uart_dev, "r");
  253. _GLOBAL_REENT->_stdout = fopen(default_uart_dev, "w");
  254. _GLOBAL_REENT->_stderr = fopen(default_uart_dev, "w");
  255. #else
  256. _GLOBAL_REENT->_stdin = (FILE*) &__sf_fake_stdin;
  257. _GLOBAL_REENT->_stdout = (FILE*) &__sf_fake_stdout;
  258. _GLOBAL_REENT->_stderr = (FILE*) &__sf_fake_stderr;
  259. #endif
  260. esp_timer_init();
  261. esp_set_time_from_rtc();
  262. #if CONFIG_ESP32_APPTRACE_ENABLE
  263. err = esp_apptrace_init();
  264. assert(err == ESP_OK && "Failed to init apptrace module on PRO CPU!");
  265. #endif
  266. #if CONFIG_SYSVIEW_ENABLE
  267. SEGGER_SYSVIEW_Conf();
  268. #endif
  269. err = esp_pthread_init();
  270. assert(err == ESP_OK && "Failed to init pthread module!");
  271. do_global_ctors();
  272. #if CONFIG_INT_WDT
  273. esp_int_wdt_init();
  274. #endif
  275. #if CONFIG_TASK_WDT
  276. esp_task_wdt_init();
  277. #endif
  278. esp_cache_err_int_init();
  279. esp_crosscore_int_init();
  280. esp_ipc_init();
  281. #ifndef CONFIG_FREERTOS_UNICORE
  282. esp_dport_access_int_init();
  283. #endif
  284. spi_flash_init();
  285. /* init default OS-aware flash access critical section */
  286. spi_flash_guard_set(&g_flash_guard_default_ops);
  287. #if CONFIG_ESP32_ENABLE_COREDUMP
  288. esp_core_dump_init();
  289. #endif
  290. portBASE_TYPE res = xTaskCreatePinnedToCore(&main_task, "main",
  291. ESP_TASK_MAIN_STACK, NULL,
  292. ESP_TASK_MAIN_PRIO, NULL, 0);
  293. assert(res == pdTRUE);
  294. ESP_LOGI(TAG, "Starting scheduler on PRO CPU.");
  295. vTaskStartScheduler();
  296. abort(); /* Only get to here if not enough free heap to start scheduler */
  297. }
  298. #if !CONFIG_FREERTOS_UNICORE
  299. void start_cpu1_default(void)
  300. {
  301. // Wait for FreeRTOS initialization to finish on PRO CPU
  302. while (port_xSchedulerRunning[0] == 0) {
  303. ;
  304. }
  305. #if CONFIG_ESP32_TRAX_TWOBANKS
  306. trax_start_trace(TRAX_DOWNCOUNT_WORDS);
  307. #endif
  308. #if CONFIG_ESP32_APPTRACE_ENABLE
  309. esp_err_t err = esp_apptrace_init();
  310. assert(err == ESP_OK && "Failed to init apptrace module on APP CPU!");
  311. #endif
  312. //Take care putting stuff here: if asked, FreeRTOS will happily tell you the scheduler
  313. //has started, but it isn't active *on this CPU* yet.
  314. esp_cache_err_int_init();
  315. esp_crosscore_int_init();
  316. esp_dport_access_int_init();
  317. ESP_EARLY_LOGI(TAG, "Starting scheduler on APP CPU.");
  318. xPortStartScheduler();
  319. abort(); /* Only get to here if FreeRTOS somehow very broken */
  320. }
  321. #endif //!CONFIG_FREERTOS_UNICORE
  322. static void do_global_ctors(void)
  323. {
  324. static struct object ob;
  325. __register_frame_info( __eh_frame, &ob );
  326. void (**p)(void);
  327. for (p = &__init_array_end - 1; p >= &__init_array_start; --p) {
  328. (*p)();
  329. }
  330. }
  331. static void main_task(void* args)
  332. {
  333. // Now that the application is about to start, disable boot watchdogs
  334. REG_CLR_BIT(TIMG_WDTCONFIG0_REG(0), TIMG_WDT_FLASHBOOT_MOD_EN_S);
  335. REG_CLR_BIT(RTC_CNTL_WDTCONFIG0_REG, RTC_CNTL_WDT_FLASHBOOT_MOD_EN);
  336. #if !CONFIG_FREERTOS_UNICORE
  337. // Wait for FreeRTOS initialization to finish on APP CPU, before replacing its startup stack
  338. while (port_xSchedulerRunning[1] == 0) {
  339. ;
  340. }
  341. #endif
  342. //Enable allocation in region where the startup stacks were located.
  343. heap_caps_enable_nonos_stack_heaps();
  344. app_main();
  345. vTaskDelete(NULL);
  346. }