system_api.c 4.8 KB

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  1. // Copyright 2013-2016 Espressif Systems (Shanghai) PTE LTD
  2. //
  3. // Licensed under the Apache License, Version 2.0 (the "License");
  4. // you may not use this file except in compliance with the License.
  5. // You may obtain a copy of the License at
  6. //
  7. // http://www.apache.org/licenses/LICENSE-2.0
  8. //
  9. // Unless required by applicable law or agreed to in writing, software
  10. // distributed under the License is distributed on an "AS IS" BASIS,
  11. // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  12. // See the License for the specific language governing permissions and
  13. // limitations under the License.
  14. #include "esp_system.h"
  15. #include "esp_attr.h"
  16. #include "esp_wifi.h"
  17. #include "esp_wifi_internal.h"
  18. #include "esp_log.h"
  19. #include "rom/efuse.h"
  20. #include "rom/cache.h"
  21. #include "rom/uart.h"
  22. #include "soc/dport_reg.h"
  23. #include "soc/efuse_reg.h"
  24. #include "soc/rtc_cntl_reg.h"
  25. #include "soc/timer_group_reg.h"
  26. #include "soc/timer_group_struct.h"
  27. #include "soc/cpu.h"
  28. #include "freertos/FreeRTOS.h"
  29. #include "freertos/task.h"
  30. #include "freertos/xtensa_api.h"
  31. #include "rtc.h"
  32. static const char* TAG = "system_api";
  33. void system_init()
  34. {
  35. }
  36. esp_err_t esp_efuse_read_mac(uint8_t* mac)
  37. {
  38. uint8_t efuse_crc;
  39. uint8_t calc_crc;
  40. uint32_t mac_low = REG_READ(EFUSE_BLK0_RDATA1_REG);
  41. uint32_t mac_high = REG_READ(EFUSE_BLK0_RDATA2_REG);
  42. mac[0] = mac_high >> 8;
  43. mac[1] = mac_high;
  44. mac[2] = mac_low >> 24;
  45. mac[3] = mac_low >> 16;
  46. mac[4] = mac_low >> 8;
  47. mac[5] = mac_low;
  48. efuse_crc = mac_high >> 16;
  49. calc_crc = esp_crc8(mac, 6);
  50. if (efuse_crc != calc_crc) {
  51. // Small range of MAC addresses are accepted even if CRC is invalid.
  52. // These addresses are reserved for Espressif internal use.
  53. if ((mac_high & 0xFFFF) == 0x18fe) {
  54. if ((mac_low >= 0x346a85c7) && (mac_low <= 0x346a85f8)) {
  55. return ESP_OK;
  56. }
  57. } else {
  58. ESP_LOGE(TAG, "MAC address CRC error, efuse_crc = 0x%02x; calc_crc = 0x%02x", efuse_crc, calc_crc);
  59. abort();
  60. }
  61. }
  62. return ESP_OK;
  63. }
  64. esp_err_t system_efuse_read_mac(uint8_t mac[6]) __attribute__((alias("esp_efuse_read_mac")));
  65. void IRAM_ATTR esp_restart(void)
  66. {
  67. esp_wifi_stop();
  68. // Disable scheduler on this core.
  69. vTaskSuspendAll();
  70. const uint32_t core_id = xPortGetCoreID();
  71. const uint32_t other_core_id = core_id == 0 ? 1 : 0;
  72. esp_cpu_stall(other_core_id);
  73. // We need to disable TG0/TG1 watchdogs
  74. // First enable RTC watchdog to be on the safe side
  75. REG_WRITE(RTC_CNTL_WDTWPROTECT_REG, RTC_CNTL_WDT_WKEY_VALUE);
  76. REG_WRITE(RTC_CNTL_WDTCONFIG0_REG,
  77. RTC_CNTL_WDT_FLASHBOOT_MOD_EN_M |
  78. (1 << RTC_CNTL_WDT_SYS_RESET_LENGTH_S) |
  79. (1 << RTC_CNTL_WDT_CPU_RESET_LENGTH_S) );
  80. REG_WRITE(RTC_CNTL_WDTCONFIG1_REG, 128000);
  81. // Disable TG0/TG1 watchdogs
  82. TIMERG0.wdt_wprotect=TIMG_WDT_WKEY_VALUE;
  83. TIMERG0.wdt_config0.en = 0;
  84. TIMERG0.wdt_wprotect=0;
  85. TIMERG1.wdt_wprotect=TIMG_WDT_WKEY_VALUE;
  86. TIMERG1.wdt_config0.en = 0;
  87. TIMERG1.wdt_wprotect=0;
  88. // Disable all interrupts
  89. xt_ints_off(0xFFFFFFFF);
  90. // Disable cache
  91. Cache_Read_Disable(0);
  92. Cache_Read_Disable(1);
  93. // Flush any data left in UART FIFOs
  94. uart_tx_wait_idle(0);
  95. uart_tx_wait_idle(1);
  96. uart_tx_wait_idle(2);
  97. // Reset wifi/bluetooth/ethernet/sdio (bb/mac)
  98. SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG,
  99. DPORT_BB_RST | DPORT_FE_RST | DPORT_MAC_RST |
  100. DPORT_BT_RST | DPORT_BTMAC_RST | DPORT_SDIO_RST |
  101. DPORT_SDIO_HOST_RST | DPORT_EMAC_RST | DPORT_MACPWR_RST |
  102. DPROT_RW_BTMAC_RST | DPROT_RW_BTLP_RST);
  103. REG_WRITE(DPORT_CORE_RST_EN_REG, 0);
  104. // Reset timer/spi/uart
  105. SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG,
  106. DPORT_TIMERS_RST | DPORT_SPI_RST_1 | DPORT_UART_RST);
  107. REG_WRITE(DPORT_PERIP_RST_EN_REG, 0);
  108. // Set CPU back to XTAL source, no PLL, same as hard reset
  109. rtc_set_cpu_freq(CPU_XTAL);
  110. // Reset CPUs
  111. if (core_id == 0) {
  112. // Running on PRO CPU: APP CPU is stalled. Can reset both CPUs.
  113. SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG,
  114. RTC_CNTL_SW_PROCPU_RST_M | RTC_CNTL_SW_APPCPU_RST_M);
  115. } else {
  116. // Running on APP CPU: need to reset PRO CPU and unstall it,
  117. // then stall APP CPU
  118. SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_PROCPU_RST_M);
  119. esp_cpu_unstall(0);
  120. esp_cpu_stall(1);
  121. }
  122. while(true) {
  123. ;
  124. }
  125. }
  126. void system_restart(void) __attribute__((alias("esp_restart")));
  127. void system_restore(void)
  128. {
  129. esp_wifi_restore();
  130. }
  131. uint32_t esp_get_free_heap_size(void)
  132. {
  133. return xPortGetFreeHeapSize();
  134. }
  135. uint32_t system_get_free_heap_size(void) __attribute__((alias("esp_get_free_heap_size")));
  136. const char* system_get_sdk_version(void)
  137. {
  138. return "master";
  139. }