rmt.c 36 KB

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  1. // Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
  2. //
  3. // Licensed under the Apache License, Version 2.0 (the "License");
  4. // you may not use this file except in compliance with the License.
  5. // You may obtain a copy of the License at
  6. // http://www.apache.org/licenses/LICENSE-2.0
  7. //
  8. // Unless required by applicable law or agreed to in writing, software
  9. // distributed under the License is distributed on an "AS IS" BASIS,
  10. // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  11. // See the License for the specific language governing permissions and
  12. // limitations under the License.
  13. #include <esp_types.h>
  14. #include <string.h>
  15. #include <stdlib.h>
  16. #include "freertos/FreeRTOS.h"
  17. #include "freertos/semphr.h"
  18. #include "freertos/xtensa_api.h"
  19. #include "freertos/ringbuf.h"
  20. #include "esp_intr_alloc.h"
  21. #include "esp_log.h"
  22. #include "esp_err.h"
  23. #include "soc/gpio_periph.h"
  24. #include "driver/periph_ctrl.h"
  25. #include "driver/rmt.h"
  26. #include "soc/soc_memory_layout.h"
  27. #include <sys/lock.h>
  28. #define RMT_SOUCCE_CLK_APB (APB_CLK_FREQ) /*!< RMT source clock is APB_CLK */
  29. #define RMT_SOURCE_CLK_REF (1 * 1000000) /*!< not used yet */
  30. #define RMT_SOURCE_CLK(select) ((select == RMT_BASECLK_REF) ? (RMT_SOURCE_CLK_REF) : (RMT_SOUCCE_CLK_APB)) /*! RMT source clock frequency */
  31. #define RMT_CHANNEL_ERROR_STR "RMT CHANNEL ERR"
  32. #define RMT_ADDR_ERROR_STR "RMT ADDRESS ERR"
  33. #define RMT_MEM_CNT_ERROR_STR "RMT MEM BLOCK NUM ERR"
  34. #define RMT_CARRIER_ERROR_STR "RMT CARRIER LEVEL ERR"
  35. #define RMT_MEM_OWNER_ERROR_STR "RMT MEM OWNER_ERR"
  36. #define RMT_BASECLK_ERROR_STR "RMT BASECLK ERR"
  37. #define RMT_WR_MEM_OVF_ERROR_STR "RMT WR MEM OVERFLOW"
  38. #define RMT_GPIO_ERROR_STR "RMT GPIO ERROR"
  39. #define RMT_MODE_ERROR_STR "RMT MODE ERROR"
  40. #define RMT_CLK_DIV_ERROR_STR "RMT CLK DIV ERR"
  41. #define RMT_DRIVER_ERROR_STR "RMT DRIVER ERR"
  42. #define RMT_DRIVER_LENGTH_ERROR_STR "RMT PARAM LEN ERROR"
  43. #define RMT_PSRAM_BUFFER_WARN_STR "Using buffer allocated from psram"
  44. #define RMT_TRANSLATOR_NULL_STR "RMT translator is null"
  45. #define RMT_TRANSLATOR_UNINIT_STR "RMT translator not init"
  46. #define RMT_PARAM_ERR_STR "RMT param error"
  47. static const char* RMT_TAG = "rmt";
  48. static uint8_t s_rmt_driver_channels; // Bitmask (bits 0-7) of installed drivers' channels
  49. static rmt_isr_handle_t s_rmt_driver_intr_handle;
  50. #define RMT_CHECK(a, str, ret_val) \
  51. if (!(a)) { \
  52. ESP_LOGE(RMT_TAG,"%s(%d): %s", __FUNCTION__, __LINE__, str); \
  53. return (ret_val); \
  54. }
  55. // Spinlock for protecting concurrent register-level access only
  56. static portMUX_TYPE rmt_spinlock = portMUX_INITIALIZER_UNLOCKED;
  57. // Mutex lock for protecting concurrent register/unregister of RMT channels' ISR
  58. static _lock_t rmt_driver_isr_lock;
  59. typedef struct {
  60. size_t tx_offset;
  61. size_t tx_len_rem;
  62. size_t tx_sub_len;
  63. bool translator;
  64. bool wait_done; //Mark whether wait tx done.
  65. rmt_channel_t channel;
  66. const rmt_item32_t* tx_data;
  67. xSemaphoreHandle tx_sem;
  68. #if CONFIG_SPIRAM_USE_MALLOC
  69. int intr_alloc_flags;
  70. StaticSemaphore_t tx_sem_buffer;
  71. #endif
  72. rmt_item32_t* tx_buf;
  73. RingbufHandle_t rx_buf;
  74. sample_to_rmt_t sample_to_rmt;
  75. size_t sample_size_remain;
  76. const uint8_t *sample_cur;
  77. } rmt_obj_t;
  78. rmt_obj_t* p_rmt_obj[RMT_CHANNEL_MAX] = {0};
  79. // Event called when transmission is ended
  80. static rmt_tx_end_callback_t rmt_tx_end_callback;
  81. static void rmt_set_tx_wrap_en(bool en)
  82. {
  83. portENTER_CRITICAL(&rmt_spinlock);
  84. RMT.apb_conf.mem_tx_wrap_en = en;
  85. portEXIT_CRITICAL(&rmt_spinlock);
  86. }
  87. static void rmt_set_data_mode(rmt_data_mode_t data_mode)
  88. {
  89. portENTER_CRITICAL(&rmt_spinlock);
  90. RMT.apb_conf.fifo_mask = data_mode;
  91. portEXIT_CRITICAL(&rmt_spinlock);
  92. }
  93. esp_err_t rmt_set_clk_div(rmt_channel_t channel, uint8_t div_cnt)
  94. {
  95. RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
  96. RMT.conf_ch[channel].conf0.div_cnt = div_cnt;
  97. return ESP_OK;
  98. }
  99. esp_err_t rmt_get_clk_div(rmt_channel_t channel, uint8_t* div_cnt)
  100. {
  101. RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
  102. RMT_CHECK(div_cnt != NULL, RMT_ADDR_ERROR_STR, ESP_ERR_INVALID_ARG);
  103. *div_cnt = RMT.conf_ch[channel].conf0.div_cnt;
  104. return ESP_OK;
  105. }
  106. esp_err_t rmt_set_rx_idle_thresh(rmt_channel_t channel, uint16_t thresh)
  107. {
  108. RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
  109. RMT.conf_ch[channel].conf0.idle_thres = thresh;
  110. return ESP_OK;
  111. }
  112. esp_err_t rmt_get_rx_idle_thresh(rmt_channel_t channel, uint16_t *thresh)
  113. {
  114. RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
  115. RMT_CHECK(thresh != NULL, RMT_ADDR_ERROR_STR, ESP_ERR_INVALID_ARG);
  116. *thresh = RMT.conf_ch[channel].conf0.idle_thres;
  117. return ESP_OK;
  118. }
  119. esp_err_t rmt_set_mem_block_num(rmt_channel_t channel, uint8_t rmt_mem_num)
  120. {
  121. RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
  122. RMT_CHECK(rmt_mem_num <= RMT_CHANNEL_MAX - channel, RMT_MEM_CNT_ERROR_STR, ESP_ERR_INVALID_ARG);
  123. RMT.conf_ch[channel].conf0.mem_size = rmt_mem_num;
  124. return ESP_OK;
  125. }
  126. esp_err_t rmt_get_mem_block_num(rmt_channel_t channel, uint8_t* rmt_mem_num)
  127. {
  128. RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
  129. RMT_CHECK(rmt_mem_num != NULL, RMT_ADDR_ERROR_STR, ESP_ERR_INVALID_ARG);
  130. *rmt_mem_num = RMT.conf_ch[channel].conf0.mem_size;
  131. return ESP_OK;
  132. }
  133. esp_err_t rmt_set_tx_carrier(rmt_channel_t channel, bool carrier_en, uint16_t high_level, uint16_t low_level,
  134. rmt_carrier_level_t carrier_level)
  135. {
  136. RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
  137. RMT_CHECK(carrier_level < RMT_CARRIER_LEVEL_MAX, RMT_CARRIER_ERROR_STR, ESP_ERR_INVALID_ARG);
  138. RMT.carrier_duty_ch[channel].high = high_level;
  139. RMT.carrier_duty_ch[channel].low = low_level;
  140. RMT.conf_ch[channel].conf0.carrier_out_lv = carrier_level;
  141. RMT.conf_ch[channel].conf0.carrier_en = carrier_en;
  142. return ESP_OK;
  143. }
  144. esp_err_t rmt_set_mem_pd(rmt_channel_t channel, bool pd_en)
  145. {
  146. RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
  147. RMT.conf_ch[channel].conf0.mem_pd = pd_en;
  148. return ESP_OK;
  149. }
  150. esp_err_t rmt_get_mem_pd(rmt_channel_t channel, bool* pd_en)
  151. {
  152. RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
  153. *pd_en = (bool) RMT.conf_ch[channel].conf0.mem_pd;
  154. return ESP_OK;
  155. }
  156. esp_err_t rmt_tx_start(rmt_channel_t channel, bool tx_idx_rst)
  157. {
  158. RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
  159. portENTER_CRITICAL(&rmt_spinlock);
  160. if(tx_idx_rst) {
  161. RMT.conf_ch[channel].conf1.mem_rd_rst = 1;
  162. }
  163. RMT.conf_ch[channel].conf1.mem_owner = RMT_MEM_OWNER_TX;
  164. RMT.conf_ch[channel].conf1.tx_start = 1;
  165. portEXIT_CRITICAL(&rmt_spinlock);
  166. return ESP_OK;
  167. }
  168. esp_err_t rmt_tx_stop(rmt_channel_t channel)
  169. {
  170. RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
  171. portENTER_CRITICAL(&rmt_spinlock);
  172. RMTMEM.chan[channel].data32[0].val = 0;
  173. RMT.conf_ch[channel].conf1.tx_start = 0;
  174. RMT.conf_ch[channel].conf1.mem_rd_rst = 1;
  175. RMT.conf_ch[channel].conf1.mem_rd_rst = 0;
  176. portEXIT_CRITICAL(&rmt_spinlock);
  177. return ESP_OK;
  178. }
  179. esp_err_t rmt_rx_start(rmt_channel_t channel, bool rx_idx_rst)
  180. {
  181. RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
  182. portENTER_CRITICAL(&rmt_spinlock);
  183. if(rx_idx_rst) {
  184. RMT.conf_ch[channel].conf1.mem_wr_rst = 1;
  185. }
  186. RMT.conf_ch[channel].conf1.rx_en = 0;
  187. RMT.conf_ch[channel].conf1.mem_owner = RMT_MEM_OWNER_RX;
  188. RMT.conf_ch[channel].conf1.rx_en = 1;
  189. portEXIT_CRITICAL(&rmt_spinlock);
  190. return ESP_OK;
  191. }
  192. esp_err_t rmt_rx_stop(rmt_channel_t channel)
  193. {
  194. RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
  195. portENTER_CRITICAL(&rmt_spinlock);
  196. RMT.conf_ch[channel].conf1.rx_en = 0;
  197. portEXIT_CRITICAL(&rmt_spinlock);
  198. return ESP_OK;
  199. }
  200. esp_err_t rmt_memory_rw_rst(rmt_channel_t channel)
  201. {
  202. RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
  203. portENTER_CRITICAL(&rmt_spinlock);
  204. RMT.conf_ch[channel].conf1.mem_rd_rst = 1;
  205. RMT.conf_ch[channel].conf1.mem_wr_rst = 1;
  206. portEXIT_CRITICAL(&rmt_spinlock);
  207. return ESP_OK;
  208. }
  209. esp_err_t rmt_set_memory_owner(rmt_channel_t channel, rmt_mem_owner_t owner)
  210. {
  211. RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
  212. RMT_CHECK(owner < RMT_MEM_OWNER_MAX, RMT_MEM_OWNER_ERROR_STR, ESP_ERR_INVALID_ARG);
  213. portENTER_CRITICAL(&rmt_spinlock);
  214. RMT.conf_ch[channel].conf1.mem_owner = owner;
  215. portEXIT_CRITICAL(&rmt_spinlock);
  216. return ESP_OK;
  217. }
  218. esp_err_t rmt_get_memory_owner(rmt_channel_t channel, rmt_mem_owner_t* owner)
  219. {
  220. RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
  221. RMT_CHECK(owner != NULL, RMT_MEM_OWNER_ERROR_STR, ESP_ERR_INVALID_ARG);
  222. *owner = (rmt_mem_owner_t) RMT.conf_ch[channel].conf1.mem_owner;
  223. return ESP_OK;
  224. }
  225. esp_err_t rmt_set_tx_loop_mode(rmt_channel_t channel, bool loop_en)
  226. {
  227. RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
  228. portENTER_CRITICAL(&rmt_spinlock);
  229. RMT.conf_ch[channel].conf1.tx_conti_mode = loop_en;
  230. portEXIT_CRITICAL(&rmt_spinlock);
  231. return ESP_OK;
  232. }
  233. esp_err_t rmt_get_tx_loop_mode(rmt_channel_t channel, bool* loop_en)
  234. {
  235. RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
  236. *loop_en = (bool) RMT.conf_ch[channel].conf1.tx_conti_mode;
  237. return ESP_OK;
  238. }
  239. esp_err_t rmt_set_rx_filter(rmt_channel_t channel, bool rx_filter_en, uint8_t thresh)
  240. {
  241. RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
  242. portENTER_CRITICAL(&rmt_spinlock);
  243. RMT.conf_ch[channel].conf1.rx_filter_en = rx_filter_en;
  244. RMT.conf_ch[channel].conf1.rx_filter_thres = thresh;
  245. portEXIT_CRITICAL(&rmt_spinlock);
  246. return ESP_OK;
  247. }
  248. esp_err_t rmt_set_source_clk(rmt_channel_t channel, rmt_source_clk_t base_clk)
  249. {
  250. RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
  251. RMT_CHECK(base_clk < RMT_BASECLK_MAX, RMT_BASECLK_ERROR_STR, ESP_ERR_INVALID_ARG);
  252. portENTER_CRITICAL(&rmt_spinlock);
  253. RMT.conf_ch[channel].conf1.ref_always_on = base_clk;
  254. portEXIT_CRITICAL(&rmt_spinlock);
  255. return ESP_OK;
  256. }
  257. esp_err_t rmt_get_source_clk(rmt_channel_t channel, rmt_source_clk_t* src_clk)
  258. {
  259. RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
  260. *src_clk = (rmt_source_clk_t) (RMT.conf_ch[channel].conf1.ref_always_on);
  261. return ESP_OK;
  262. }
  263. esp_err_t rmt_set_idle_level(rmt_channel_t channel, bool idle_out_en, rmt_idle_level_t level)
  264. {
  265. RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
  266. RMT_CHECK(level < RMT_IDLE_LEVEL_MAX, "RMT IDLE LEVEL ERR", ESP_ERR_INVALID_ARG);
  267. portENTER_CRITICAL(&rmt_spinlock);
  268. RMT.conf_ch[channel].conf1.idle_out_en = idle_out_en;
  269. RMT.conf_ch[channel].conf1.idle_out_lv = level;
  270. portEXIT_CRITICAL(&rmt_spinlock);
  271. return ESP_OK;
  272. }
  273. esp_err_t rmt_get_idle_level(rmt_channel_t channel, bool* idle_out_en, rmt_idle_level_t* level)
  274. {
  275. RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
  276. *idle_out_en = (bool) (RMT.conf_ch[channel].conf1.idle_out_en);
  277. *level = (rmt_idle_level_t) (RMT.conf_ch[channel].conf1.idle_out_lv);
  278. return ESP_OK;
  279. }
  280. esp_err_t rmt_get_status(rmt_channel_t channel, uint32_t* status)
  281. {
  282. RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
  283. *status = RMT.status_ch[channel];
  284. return ESP_OK;
  285. }
  286. rmt_data_mode_t rmt_get_data_mode()
  287. {
  288. return (rmt_data_mode_t) (RMT.apb_conf.fifo_mask);
  289. }
  290. void rmt_set_intr_enable_mask(uint32_t mask)
  291. {
  292. portENTER_CRITICAL(&rmt_spinlock);
  293. RMT.int_ena.val |= mask;
  294. portEXIT_CRITICAL(&rmt_spinlock);
  295. }
  296. void rmt_clr_intr_enable_mask(uint32_t mask)
  297. {
  298. portENTER_CRITICAL(&rmt_spinlock);
  299. RMT.int_ena.val &= (~mask);
  300. portEXIT_CRITICAL(&rmt_spinlock);
  301. }
  302. esp_err_t rmt_set_rx_intr_en(rmt_channel_t channel, bool en)
  303. {
  304. RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
  305. if(en) {
  306. rmt_set_intr_enable_mask(BIT(channel * 3 + 1));
  307. } else {
  308. rmt_clr_intr_enable_mask(BIT(channel * 3 + 1));
  309. }
  310. return ESP_OK;
  311. }
  312. esp_err_t rmt_set_err_intr_en(rmt_channel_t channel, bool en)
  313. {
  314. RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
  315. if(en) {
  316. rmt_set_intr_enable_mask(BIT(channel * 3 + 2));
  317. } else {
  318. rmt_clr_intr_enable_mask(BIT(channel * 3 + 2));
  319. }
  320. return ESP_OK;
  321. }
  322. esp_err_t rmt_set_tx_intr_en(rmt_channel_t channel, bool en)
  323. {
  324. RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
  325. if(en) {
  326. rmt_set_intr_enable_mask(BIT(channel * 3));
  327. } else {
  328. rmt_clr_intr_enable_mask(BIT(channel * 3));
  329. }
  330. return ESP_OK;
  331. }
  332. esp_err_t rmt_set_tx_thr_intr_en(rmt_channel_t channel, bool en, uint16_t evt_thresh)
  333. {
  334. RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
  335. if(en) {
  336. RMT_CHECK(evt_thresh <= 256, "RMT EVT THRESH ERR", ESP_ERR_INVALID_ARG);
  337. portENTER_CRITICAL(&rmt_spinlock);
  338. RMT.tx_lim_ch[channel].limit = evt_thresh;
  339. portEXIT_CRITICAL(&rmt_spinlock);
  340. rmt_set_tx_wrap_en(true);
  341. rmt_set_intr_enable_mask(BIT(channel + 24));
  342. } else {
  343. rmt_clr_intr_enable_mask(BIT(channel + 24));
  344. }
  345. return ESP_OK;
  346. }
  347. esp_err_t rmt_set_pin(rmt_channel_t channel, rmt_mode_t mode, gpio_num_t gpio_num)
  348. {
  349. RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
  350. RMT_CHECK(mode < RMT_MODE_MAX, RMT_MODE_ERROR_STR, ESP_ERR_INVALID_ARG);
  351. RMT_CHECK(((GPIO_IS_VALID_GPIO(gpio_num) && (mode == RMT_MODE_RX)) || (GPIO_IS_VALID_OUTPUT_GPIO(gpio_num) && (mode == RMT_MODE_TX))),
  352. RMT_GPIO_ERROR_STR, ESP_ERR_INVALID_ARG);
  353. PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[gpio_num], 2);
  354. if(mode == RMT_MODE_TX) {
  355. gpio_set_direction(gpio_num, GPIO_MODE_OUTPUT);
  356. gpio_matrix_out(gpio_num, RMT_SIG_OUT0_IDX + channel, 0, 0);
  357. } else {
  358. gpio_set_direction(gpio_num, GPIO_MODE_INPUT);
  359. gpio_matrix_in(gpio_num, RMT_SIG_IN0_IDX + channel, 0);
  360. }
  361. return ESP_OK;
  362. }
  363. esp_err_t rmt_config(const rmt_config_t* rmt_param)
  364. {
  365. uint8_t mode = rmt_param->rmt_mode;
  366. uint8_t channel = rmt_param->channel;
  367. uint8_t gpio_num = rmt_param->gpio_num;
  368. uint8_t mem_cnt = rmt_param->mem_block_num;
  369. int clk_div = rmt_param->clk_div;
  370. uint32_t carrier_freq_hz = rmt_param->tx_config.carrier_freq_hz;
  371. bool carrier_en = rmt_param->tx_config.carrier_en;
  372. RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
  373. RMT_CHECK(GPIO_IS_VALID_GPIO(gpio_num), RMT_GPIO_ERROR_STR, ESP_ERR_INVALID_ARG);
  374. RMT_CHECK((mem_cnt + channel <= 8 && mem_cnt > 0), RMT_MEM_CNT_ERROR_STR, ESP_ERR_INVALID_ARG);
  375. RMT_CHECK((clk_div > 0), RMT_CLK_DIV_ERROR_STR, ESP_ERR_INVALID_ARG);
  376. if (mode == RMT_MODE_TX) {
  377. RMT_CHECK((!carrier_en || carrier_freq_hz > 0), "RMT carrier frequency can't be zero", ESP_ERR_INVALID_ARG);
  378. }
  379. static bool rmt_enable = false;
  380. if (rmt_enable == false) {
  381. periph_module_reset(PERIPH_RMT_MODULE);
  382. rmt_enable = true;
  383. }
  384. periph_module_enable(PERIPH_RMT_MODULE);
  385. RMT.conf_ch[channel].conf0.div_cnt = clk_div;
  386. /*Visit data use memory not FIFO*/
  387. rmt_set_data_mode(RMT_DATA_MODE_MEM);
  388. /*Reset tx/rx memory index */
  389. portENTER_CRITICAL(&rmt_spinlock);
  390. RMT.conf_ch[channel].conf1.mem_rd_rst = 1;
  391. RMT.conf_ch[channel].conf1.mem_wr_rst = 1;
  392. portEXIT_CRITICAL(&rmt_spinlock);
  393. if(mode == RMT_MODE_TX) {
  394. uint32_t rmt_source_clk_hz = 0;
  395. uint16_t carrier_duty_percent = rmt_param->tx_config.carrier_duty_percent;
  396. uint8_t carrier_level = rmt_param->tx_config.carrier_level;
  397. uint8_t idle_level = rmt_param->tx_config.idle_level;
  398. portENTER_CRITICAL(&rmt_spinlock);
  399. RMT.conf_ch[channel].conf1.tx_conti_mode = rmt_param->tx_config.loop_en;
  400. /*Memory set block number*/
  401. RMT.conf_ch[channel].conf0.mem_size = mem_cnt;
  402. RMT.conf_ch[channel].conf1.mem_owner = RMT_MEM_OWNER_TX;
  403. /*We use APB clock in this version, which is 80Mhz, later we will release system reference clock*/
  404. RMT.conf_ch[channel].conf1.ref_always_on = RMT_BASECLK_APB;
  405. rmt_source_clk_hz = RMT_SOURCE_CLK(RMT_BASECLK_APB);
  406. /*Set idle level */
  407. RMT.conf_ch[channel].conf1.idle_out_en = rmt_param->tx_config.idle_output_en;
  408. RMT.conf_ch[channel].conf1.idle_out_lv = idle_level;
  409. /*Set carrier*/
  410. RMT.conf_ch[channel].conf0.carrier_en = carrier_en;
  411. if (carrier_en) {
  412. uint32_t duty_div, duty_h, duty_l;
  413. duty_div = rmt_source_clk_hz / carrier_freq_hz;
  414. duty_h = duty_div * carrier_duty_percent / 100;
  415. duty_l = duty_div - duty_h;
  416. RMT.conf_ch[channel].conf0.carrier_out_lv = carrier_level;
  417. RMT.carrier_duty_ch[channel].high = duty_h;
  418. RMT.carrier_duty_ch[channel].low = duty_l;
  419. } else {
  420. RMT.conf_ch[channel].conf0.carrier_out_lv = 0;
  421. RMT.carrier_duty_ch[channel].high = 0;
  422. RMT.carrier_duty_ch[channel].low = 0;
  423. }
  424. portEXIT_CRITICAL(&rmt_spinlock);
  425. ESP_LOGD(RMT_TAG, "Rmt Tx Channel %u|Gpio %u|Sclk_Hz %u|Div %u|Carrier_Hz %u|Duty %u",
  426. channel, gpio_num, rmt_source_clk_hz, clk_div, carrier_freq_hz, carrier_duty_percent);
  427. }
  428. else if(RMT_MODE_RX == mode) {
  429. uint8_t filter_cnt = rmt_param->rx_config.filter_ticks_thresh;
  430. uint16_t threshold = rmt_param->rx_config.idle_threshold;
  431. portENTER_CRITICAL(&rmt_spinlock);
  432. /*clock init*/
  433. RMT.conf_ch[channel].conf1.ref_always_on = RMT_BASECLK_APB;
  434. uint32_t rmt_source_clk_hz = RMT_SOURCE_CLK(RMT_BASECLK_APB);
  435. /*memory set block number and owner*/
  436. RMT.conf_ch[channel].conf0.mem_size = mem_cnt;
  437. RMT.conf_ch[channel].conf1.mem_owner = RMT_MEM_OWNER_RX;
  438. /*Set idle threshold*/
  439. RMT.conf_ch[channel].conf0.idle_thres = threshold;
  440. /* Set RX filter */
  441. RMT.conf_ch[channel].conf1.rx_filter_thres = filter_cnt;
  442. RMT.conf_ch[channel].conf1.rx_filter_en = rmt_param->rx_config.filter_en;
  443. portEXIT_CRITICAL(&rmt_spinlock);
  444. ESP_LOGD(RMT_TAG, "Rmt Rx Channel %u|Gpio %u|Sclk_Hz %u|Div %u|Thresold %u|Filter %u",
  445. channel, gpio_num, rmt_source_clk_hz, clk_div, threshold, filter_cnt);
  446. }
  447. rmt_set_pin(channel, mode, gpio_num);
  448. return ESP_OK;
  449. }
  450. static void IRAM_ATTR rmt_fill_memory(rmt_channel_t channel, const rmt_item32_t* item, uint16_t item_num, uint16_t mem_offset)
  451. {
  452. portENTER_CRITICAL_SAFE(&rmt_spinlock);
  453. RMT.apb_conf.fifo_mask = RMT_DATA_MODE_MEM;
  454. portEXIT_CRITICAL_SAFE(&rmt_spinlock);
  455. int i;
  456. for(i = 0; i < item_num; i++) {
  457. RMTMEM.chan[channel].data32[i + mem_offset].val = item[i].val;
  458. }
  459. }
  460. esp_err_t rmt_fill_tx_items(rmt_channel_t channel, const rmt_item32_t* item, uint16_t item_num, uint16_t mem_offset)
  461. {
  462. RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, (0));
  463. RMT_CHECK((item != NULL), RMT_ADDR_ERROR_STR, ESP_ERR_INVALID_ARG);
  464. RMT_CHECK((item_num > 0), RMT_DRIVER_LENGTH_ERROR_STR, ESP_ERR_INVALID_ARG);
  465. /*Each block has 64 x 32 bits of data*/
  466. uint8_t mem_cnt = RMT.conf_ch[channel].conf0.mem_size;
  467. RMT_CHECK((mem_cnt * RMT_MEM_ITEM_NUM >= item_num), RMT_WR_MEM_OVF_ERROR_STR, ESP_ERR_INVALID_ARG);
  468. rmt_fill_memory(channel, item, item_num, mem_offset);
  469. return ESP_OK;
  470. }
  471. esp_err_t rmt_isr_register(void (*fn)(void*), void * arg, int intr_alloc_flags, rmt_isr_handle_t *handle)
  472. {
  473. RMT_CHECK((fn != NULL), RMT_ADDR_ERROR_STR, ESP_ERR_INVALID_ARG);
  474. RMT_CHECK(s_rmt_driver_channels == 0, "RMT driver installed, can not install generic ISR handler", ESP_FAIL);
  475. return esp_intr_alloc(ETS_RMT_INTR_SOURCE, intr_alloc_flags, fn, arg, handle);
  476. }
  477. esp_err_t rmt_isr_deregister(rmt_isr_handle_t handle)
  478. {
  479. return esp_intr_free(handle);
  480. }
  481. static int IRAM_ATTR rmt_get_mem_len(rmt_channel_t channel)
  482. {
  483. int block_num = RMT.conf_ch[channel].conf0.mem_size;
  484. int item_block_len = block_num * RMT_MEM_ITEM_NUM;
  485. volatile rmt_item32_t* data = RMTMEM.chan[channel].data32;
  486. int idx;
  487. for(idx = 0; idx < item_block_len; idx++) {
  488. if(data[idx].duration0 == 0) {
  489. return idx;
  490. } else if(data[idx].duration1 == 0) {
  491. return idx + 1;
  492. }
  493. }
  494. return idx;
  495. }
  496. static void IRAM_ATTR rmt_driver_isr_default(void* arg)
  497. {
  498. const uint32_t intr_st = RMT.int_st.val;
  499. uint32_t status = intr_st;
  500. uint8_t channel;
  501. portBASE_TYPE HPTaskAwoken = 0;
  502. while (status) {
  503. int i = __builtin_ffs(status) - 1;
  504. status &= ~(1 << i);
  505. if(i < 24) {
  506. channel = i / 3;
  507. rmt_obj_t* p_rmt = p_rmt_obj[channel];
  508. if(NULL == p_rmt) {
  509. continue;
  510. }
  511. switch(i % 3) {
  512. //TX END
  513. case 0:
  514. xSemaphoreGiveFromISR(p_rmt->tx_sem, &HPTaskAwoken);
  515. RMT.conf_ch[channel].conf1.mem_rd_rst = 1;
  516. RMT.conf_ch[channel].conf1.mem_rd_rst = 0;
  517. p_rmt->tx_data = NULL;
  518. p_rmt->tx_len_rem = 0;
  519. p_rmt->tx_offset = 0;
  520. p_rmt->tx_sub_len = 0;
  521. p_rmt->sample_cur = NULL;
  522. p_rmt->translator = false;
  523. if(rmt_tx_end_callback.function != NULL) {
  524. rmt_tx_end_callback.function(channel, rmt_tx_end_callback.arg);
  525. }
  526. break;
  527. //RX_END
  528. case 1:
  529. RMT.conf_ch[channel].conf1.rx_en = 0;
  530. int item_len = rmt_get_mem_len(channel);
  531. //change memory owner to protect data.
  532. RMT.conf_ch[channel].conf1.mem_owner = RMT_MEM_OWNER_TX;
  533. if(p_rmt->rx_buf) {
  534. BaseType_t res = xRingbufferSendFromISR(p_rmt->rx_buf, (void*) RMTMEM.chan[channel].data32, item_len * 4, &HPTaskAwoken);
  535. if(res == pdFALSE) {
  536. ESP_EARLY_LOGE(RMT_TAG, "RMT RX BUFFER FULL");
  537. } else {
  538. }
  539. } else {
  540. ESP_EARLY_LOGE(RMT_TAG, "RMT RX BUFFER ERROR\n");
  541. }
  542. RMT.conf_ch[channel].conf1.mem_wr_rst = 1;
  543. RMT.conf_ch[channel].conf1.mem_owner = RMT_MEM_OWNER_RX;
  544. RMT.conf_ch[channel].conf1.rx_en = 1;
  545. break;
  546. //ERR
  547. case 2:
  548. ESP_EARLY_LOGE(RMT_TAG, "RMT[%d] ERR", channel);
  549. ESP_EARLY_LOGE(RMT_TAG, "status: 0x%08x", RMT.status_ch[channel]);
  550. RMT.int_ena.val &= (~(BIT(i)));
  551. break;
  552. default:
  553. break;
  554. }
  555. } else {
  556. channel = i - 24;
  557. rmt_obj_t* p_rmt = p_rmt_obj[channel];
  558. if(p_rmt->tx_data == NULL) {
  559. //skip
  560. } else {
  561. if(p_rmt->translator) {
  562. if(p_rmt->sample_size_remain > 0) {
  563. size_t translated_size = 0;
  564. p_rmt->sample_to_rmt((void *) p_rmt->sample_cur,
  565. p_rmt->tx_buf,
  566. p_rmt->sample_size_remain,
  567. p_rmt->tx_sub_len,
  568. &translated_size,
  569. &p_rmt->tx_len_rem
  570. );
  571. p_rmt->sample_size_remain -= translated_size;
  572. p_rmt->sample_cur += translated_size;
  573. p_rmt->tx_data = p_rmt->tx_buf;
  574. } else {
  575. p_rmt->sample_cur = NULL;
  576. p_rmt->translator = false;
  577. }
  578. }
  579. const rmt_item32_t* pdata = p_rmt->tx_data;
  580. int len_rem = p_rmt->tx_len_rem;
  581. if(len_rem >= p_rmt->tx_sub_len) {
  582. rmt_fill_memory(channel, pdata, p_rmt->tx_sub_len, p_rmt->tx_offset);
  583. p_rmt->tx_data += p_rmt->tx_sub_len;
  584. p_rmt->tx_len_rem -= p_rmt->tx_sub_len;
  585. } else if(len_rem == 0) {
  586. RMTMEM.chan[channel].data32[p_rmt->tx_offset].val = 0;
  587. } else {
  588. rmt_fill_memory(channel, pdata, len_rem, p_rmt->tx_offset);
  589. RMTMEM.chan[channel].data32[p_rmt->tx_offset + len_rem].val = 0;
  590. p_rmt->tx_data += len_rem;
  591. p_rmt->tx_len_rem -= len_rem;
  592. }
  593. if(p_rmt->tx_offset == 0) {
  594. p_rmt->tx_offset = p_rmt->tx_sub_len;
  595. } else {
  596. p_rmt->tx_offset = 0;
  597. }
  598. }
  599. }
  600. }
  601. RMT.int_clr.val = intr_st;
  602. if(HPTaskAwoken == pdTRUE) {
  603. portYIELD_FROM_ISR();
  604. }
  605. }
  606. esp_err_t rmt_driver_uninstall(rmt_channel_t channel)
  607. {
  608. esp_err_t err = ESP_OK;
  609. RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
  610. RMT_CHECK((s_rmt_driver_channels & BIT(channel)) != 0, "No RMT driver for this channel", ESP_ERR_INVALID_STATE);
  611. if(p_rmt_obj[channel] == NULL) {
  612. return ESP_OK;
  613. }
  614. //Avoid blocking here(when the interrupt is disabled and do not wait tx done).
  615. if(p_rmt_obj[channel]->wait_done) {
  616. xSemaphoreTake(p_rmt_obj[channel]->tx_sem, portMAX_DELAY);
  617. }
  618. rmt_set_rx_intr_en(channel, 0);
  619. rmt_set_err_intr_en(channel, 0);
  620. rmt_set_tx_intr_en(channel, 0);
  621. rmt_set_tx_thr_intr_en(channel, 0, 0xffff);
  622. _lock_acquire_recursive(&rmt_driver_isr_lock);
  623. s_rmt_driver_channels &= ~BIT(channel);
  624. if (s_rmt_driver_channels == 0) { // all channels have driver disabled
  625. err = rmt_isr_deregister(s_rmt_driver_intr_handle);
  626. s_rmt_driver_intr_handle = NULL;
  627. }
  628. _lock_release_recursive(&rmt_driver_isr_lock);
  629. if (err != ESP_OK) {
  630. return err;
  631. }
  632. if(p_rmt_obj[channel]->tx_sem) {
  633. vSemaphoreDelete(p_rmt_obj[channel]->tx_sem);
  634. p_rmt_obj[channel]->tx_sem = NULL;
  635. }
  636. if(p_rmt_obj[channel]->rx_buf) {
  637. vRingbufferDelete(p_rmt_obj[channel]->rx_buf);
  638. p_rmt_obj[channel]->rx_buf = NULL;
  639. }
  640. if(p_rmt_obj[channel]->tx_buf) {
  641. free(p_rmt_obj[channel]->tx_buf);
  642. p_rmt_obj[channel]->tx_buf = NULL;
  643. }
  644. if(p_rmt_obj[channel]->sample_to_rmt) {
  645. p_rmt_obj[channel]->sample_to_rmt = NULL;
  646. }
  647. free(p_rmt_obj[channel]);
  648. p_rmt_obj[channel] = NULL;
  649. return ESP_OK;
  650. }
  651. esp_err_t rmt_driver_install(rmt_channel_t channel, size_t rx_buf_size, int intr_alloc_flags)
  652. {
  653. RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
  654. RMT_CHECK((s_rmt_driver_channels & BIT(channel)) == 0, "RMT driver already installed for channel", ESP_ERR_INVALID_STATE);
  655. esp_err_t err = ESP_OK;
  656. if(p_rmt_obj[channel] != NULL) {
  657. ESP_LOGD(RMT_TAG, "RMT driver already installed");
  658. return ESP_ERR_INVALID_STATE;
  659. }
  660. #if !CONFIG_SPIRAM_USE_MALLOC
  661. p_rmt_obj[channel] = (rmt_obj_t*) malloc(sizeof(rmt_obj_t));
  662. #else
  663. if( !(intr_alloc_flags & ESP_INTR_FLAG_IRAM) ) {
  664. p_rmt_obj[channel] = (rmt_obj_t*) malloc(sizeof(rmt_obj_t));
  665. } else {
  666. p_rmt_obj[channel] = (rmt_obj_t*) heap_caps_calloc(1, sizeof(rmt_obj_t), MALLOC_CAP_INTERNAL|MALLOC_CAP_8BIT);
  667. }
  668. #endif
  669. if(p_rmt_obj[channel] == NULL) {
  670. ESP_LOGE(RMT_TAG, "RMT driver malloc error");
  671. return ESP_ERR_NO_MEM;
  672. }
  673. memset(p_rmt_obj[channel], 0, sizeof(rmt_obj_t));
  674. p_rmt_obj[channel]->tx_len_rem = 0;
  675. p_rmt_obj[channel]->tx_data = NULL;
  676. p_rmt_obj[channel]->channel = channel;
  677. p_rmt_obj[channel]->tx_offset = 0;
  678. p_rmt_obj[channel]->tx_sub_len = 0;
  679. p_rmt_obj[channel]->wait_done = false;
  680. p_rmt_obj[channel]->translator = false;
  681. p_rmt_obj[channel]->sample_to_rmt = NULL;
  682. if(p_rmt_obj[channel]->tx_sem == NULL) {
  683. #if !CONFIG_SPIRAM_USE_MALLOC
  684. p_rmt_obj[channel]->tx_sem = xSemaphoreCreateBinary();
  685. #else
  686. p_rmt_obj[channel]->intr_alloc_flags = intr_alloc_flags;
  687. if( !(intr_alloc_flags & ESP_INTR_FLAG_IRAM) ) {
  688. p_rmt_obj[channel]->tx_sem = xSemaphoreCreateBinary();
  689. } else {
  690. p_rmt_obj[channel]->tx_sem = xSemaphoreCreateBinaryStatic(&p_rmt_obj[channel]->tx_sem_buffer);
  691. }
  692. #endif
  693. xSemaphoreGive(p_rmt_obj[channel]->tx_sem);
  694. }
  695. if(p_rmt_obj[channel]->rx_buf == NULL && rx_buf_size > 0) {
  696. p_rmt_obj[channel]->rx_buf = xRingbufferCreate(rx_buf_size, RINGBUF_TYPE_NOSPLIT);
  697. rmt_set_rx_intr_en(channel, 1);
  698. rmt_set_err_intr_en(channel, 1);
  699. }
  700. _lock_acquire_recursive(&rmt_driver_isr_lock);
  701. if(s_rmt_driver_channels == 0) { // first RMT channel using driver
  702. err = rmt_isr_register(rmt_driver_isr_default, NULL, intr_alloc_flags, &s_rmt_driver_intr_handle);
  703. }
  704. if (err == ESP_OK) {
  705. s_rmt_driver_channels |= BIT(channel);
  706. rmt_set_tx_intr_en(channel, 1);
  707. }
  708. _lock_release_recursive(&rmt_driver_isr_lock);
  709. return err;
  710. }
  711. esp_err_t rmt_write_items(rmt_channel_t channel, const rmt_item32_t* rmt_item, int item_num, bool wait_tx_done)
  712. {
  713. RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
  714. RMT_CHECK(p_rmt_obj[channel] != NULL, RMT_DRIVER_ERROR_STR, ESP_FAIL);
  715. RMT_CHECK(rmt_item != NULL, RMT_ADDR_ERROR_STR, ESP_FAIL);
  716. RMT_CHECK(item_num > 0, RMT_DRIVER_LENGTH_ERROR_STR, ESP_ERR_INVALID_ARG);
  717. #if CONFIG_SPIRAM_USE_MALLOC
  718. if( p_rmt_obj[channel]->intr_alloc_flags & ESP_INTR_FLAG_IRAM ) {
  719. if( !esp_ptr_internal(rmt_item) ) {
  720. ESP_LOGE(RMT_TAG, RMT_PSRAM_BUFFER_WARN_STR);
  721. return ESP_ERR_INVALID_ARG;
  722. }
  723. }
  724. #endif
  725. rmt_obj_t* p_rmt = p_rmt_obj[channel];
  726. int block_num = RMT.conf_ch[channel].conf0.mem_size;
  727. int item_block_len = block_num * RMT_MEM_ITEM_NUM;
  728. int item_sub_len = block_num * RMT_MEM_ITEM_NUM / 2;
  729. int len_rem = item_num;
  730. xSemaphoreTake(p_rmt->tx_sem, portMAX_DELAY);
  731. // fill the memory block first
  732. if(item_num >= item_block_len) {
  733. rmt_fill_memory(channel, rmt_item, item_block_len, 0);
  734. len_rem -= item_block_len;
  735. rmt_set_tx_loop_mode(channel, false);
  736. rmt_set_tx_thr_intr_en(channel, 1, item_sub_len);
  737. p_rmt->tx_data = rmt_item + item_block_len;
  738. p_rmt->tx_len_rem = len_rem;
  739. p_rmt->tx_offset = 0;
  740. p_rmt->tx_sub_len = item_sub_len;
  741. } else {
  742. rmt_fill_memory(channel, rmt_item, len_rem, 0);
  743. RMTMEM.chan[channel].data32[len_rem].val = 0;
  744. p_rmt->tx_len_rem = 0;
  745. }
  746. rmt_tx_start(channel, true);
  747. p_rmt->wait_done = wait_tx_done;
  748. if(wait_tx_done) {
  749. xSemaphoreTake(p_rmt->tx_sem, portMAX_DELAY);
  750. xSemaphoreGive(p_rmt->tx_sem);
  751. }
  752. return ESP_OK;
  753. }
  754. esp_err_t rmt_wait_tx_done(rmt_channel_t channel, TickType_t wait_time)
  755. {
  756. RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
  757. RMT_CHECK(p_rmt_obj[channel] != NULL, RMT_DRIVER_ERROR_STR, ESP_FAIL);
  758. if(xSemaphoreTake(p_rmt_obj[channel]->tx_sem, wait_time) == pdTRUE) {
  759. p_rmt_obj[channel]->wait_done = false;
  760. xSemaphoreGive(p_rmt_obj[channel]->tx_sem);
  761. return ESP_OK;
  762. }
  763. else {
  764. if (wait_time != 0) { // Don't emit error message if just polling.
  765. ESP_LOGE(RMT_TAG, "Timeout on wait_tx_done");
  766. }
  767. return ESP_ERR_TIMEOUT;
  768. }
  769. }
  770. esp_err_t rmt_get_ringbuf_handle(rmt_channel_t channel, RingbufHandle_t* buf_handle)
  771. {
  772. RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
  773. RMT_CHECK(p_rmt_obj[channel] != NULL, RMT_DRIVER_ERROR_STR, ESP_FAIL);
  774. RMT_CHECK(buf_handle != NULL, RMT_ADDR_ERROR_STR, ESP_ERR_INVALID_ARG);
  775. *buf_handle = p_rmt_obj[channel]->rx_buf;
  776. return ESP_OK;
  777. }
  778. rmt_tx_end_callback_t rmt_register_tx_end_callback(rmt_tx_end_fn_t function, void *arg)
  779. {
  780. rmt_tx_end_callback_t previous = rmt_tx_end_callback;
  781. rmt_tx_end_callback.function = function;
  782. rmt_tx_end_callback.arg = arg;
  783. return previous;
  784. }
  785. esp_err_t rmt_translator_init(rmt_channel_t channel, sample_to_rmt_t fn)
  786. {
  787. RMT_CHECK(fn != NULL, RMT_TRANSLATOR_NULL_STR, ESP_ERR_INVALID_ARG);
  788. RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
  789. RMT_CHECK(p_rmt_obj[channel] != NULL, RMT_DRIVER_ERROR_STR, ESP_FAIL);
  790. const uint32_t block_size = RMT.conf_ch[channel].conf0.mem_size * RMT_MEM_ITEM_NUM * sizeof(rmt_item32_t);
  791. if (p_rmt_obj[channel]->tx_buf == NULL) {
  792. #if !CONFIG_SPIRAM_USE_MALLOC
  793. p_rmt_obj[channel]->tx_buf = (rmt_item32_t *)malloc(block_size);
  794. #else
  795. if( p_rmt_obj[channel]->intr_alloc_flags & ESP_INTR_FLAG_IRAM ) {
  796. p_rmt_obj[channel]->tx_buf = (rmt_item32_t *)malloc(block_size);
  797. } else {
  798. p_rmt_obj[channel]->tx_buf = (rmt_item32_t *)heap_caps_calloc(1, block_size, MALLOC_CAP_INTERNAL|MALLOC_CAP_8BIT);
  799. }
  800. #endif
  801. if(p_rmt_obj[channel]->tx_buf == NULL) {
  802. ESP_LOGE(RMT_TAG, "RMT translator buffer create fail");
  803. return ESP_FAIL;
  804. }
  805. }
  806. p_rmt_obj[channel]->sample_to_rmt = fn;
  807. p_rmt_obj[channel]->sample_size_remain = 0;
  808. p_rmt_obj[channel]->sample_cur = NULL;
  809. ESP_LOGD(RMT_TAG, "RMT translator init done");
  810. return ESP_OK;
  811. }
  812. esp_err_t rmt_write_sample(rmt_channel_t channel, const uint8_t *src, size_t src_size, bool wait_tx_done)
  813. {
  814. RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG);
  815. RMT_CHECK(p_rmt_obj[channel] != NULL, RMT_DRIVER_ERROR_STR, ESP_FAIL);
  816. RMT_CHECK(p_rmt_obj[channel]->sample_to_rmt != NULL,RMT_TRANSLATOR_UNINIT_STR, ESP_FAIL);
  817. #if CONFIG_SPIRAM_USE_MALLOC
  818. if( p_rmt_obj[channel]->intr_alloc_flags & ESP_INTR_FLAG_IRAM ) {
  819. if( !esp_ptr_internal(src) ) {
  820. ESP_LOGE(RMT_TAG, RMT_PSRAM_BUFFER_WARN_STR);
  821. return ESP_ERR_INVALID_ARG;
  822. }
  823. }
  824. #endif
  825. size_t item_num = 0;
  826. size_t translated_size = 0;
  827. rmt_obj_t* p_rmt = p_rmt_obj[channel];
  828. const uint32_t item_block_len = RMT.conf_ch[channel].conf0.mem_size * RMT_MEM_ITEM_NUM;
  829. const uint32_t item_sub_len = item_block_len / 2;
  830. xSemaphoreTake(p_rmt->tx_sem, portMAX_DELAY);
  831. p_rmt->sample_to_rmt((void *)src, p_rmt->tx_buf, src_size, item_block_len, &translated_size, &item_num);
  832. p_rmt->sample_size_remain = src_size - translated_size;
  833. p_rmt->sample_cur = src + translated_size;
  834. rmt_fill_memory(channel, p_rmt->tx_buf, item_num, 0);
  835. if (item_num == item_block_len) {
  836. rmt_set_tx_thr_intr_en(channel, 1, item_sub_len);
  837. p_rmt->tx_data = p_rmt->tx_buf;
  838. p_rmt->tx_offset = 0;
  839. p_rmt->tx_sub_len = item_sub_len;
  840. p_rmt->translator = true;
  841. } else {
  842. RMTMEM.chan[channel].data32[item_num].val = 0;
  843. p_rmt->tx_len_rem = 0;
  844. p_rmt->sample_cur = NULL;
  845. p_rmt->translator = false;
  846. }
  847. rmt_tx_start(channel, true);
  848. p_rmt->wait_done = wait_tx_done;
  849. if (wait_tx_done) {
  850. xSemaphoreTake(p_rmt->tx_sem, portMAX_DELAY);
  851. xSemaphoreGive(p_rmt->tx_sem);
  852. }
  853. return ESP_OK;
  854. }
  855. esp_err_t rmt_get_channel_status(rmt_channel_status_result_t *channel_status)
  856. {
  857. RMT_CHECK(channel_status != NULL, RMT_PARAM_ERR_STR, ESP_ERR_INVALID_ARG);
  858. for(int i = 0; i < RMT_CHANNEL_MAX; i++) {
  859. channel_status->status[i]= RMT_CHANNEL_UNINIT;
  860. if( p_rmt_obj[i] != NULL ) {
  861. if( p_rmt_obj[i]->tx_sem != NULL ) {
  862. if( xSemaphoreTake(p_rmt_obj[i]->tx_sem, (TickType_t)0) == pdTRUE ) {
  863. channel_status->status[i] = RMT_CHANNEL_IDLE;
  864. xSemaphoreGive(p_rmt_obj[i]->tx_sem);
  865. } else {
  866. channel_status->status[i] = RMT_CHANNEL_BUSY;
  867. }
  868. }
  869. }
  870. }
  871. return ESP_OK;
  872. }