Kconfig 13 KB

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  1. menu "Common ESP-related"
  2. config ESP_ERR_TO_NAME_LOOKUP
  3. bool "Enable lookup of error code strings"
  4. default "y"
  5. help
  6. Functions esp_err_to_name() and esp_err_to_name_r() return string representations of error codes from a
  7. pre-generated lookup table. This option can be used to turn off the use of the look-up table in order to
  8. save memory but this comes at the price of sacrificing distinguishable (meaningful) output string
  9. representations.
  10. config ESP_SYSTEM_EVENT_QUEUE_SIZE
  11. int "System event queue size"
  12. default 32
  13. help
  14. Config system event queue size in different application.
  15. config ESP_SYSTEM_EVENT_TASK_STACK_SIZE
  16. int "Event loop task stack size"
  17. default 2304
  18. help
  19. Config system event task stack size in different application.
  20. config ESP_MAIN_TASK_STACK_SIZE
  21. int "Main task stack size"
  22. default 3584
  23. help
  24. Configure the "main task" stack size. This is the stack of the task
  25. which calls app_main(). If app_main() returns then this task is deleted
  26. and its stack memory is freed.
  27. config ESP_IPC_TASK_STACK_SIZE
  28. int "Inter-Processor Call (IPC) task stack size"
  29. range 512 65536 if !APPTRACE_ENABLE
  30. range 2048 65536 if APPTRACE_ENABLE
  31. default 2048 if APPTRACE_ENABLE
  32. default 1024
  33. help
  34. Configure the IPC tasks stack size. One IPC task runs on each core
  35. (in dual core mode), and allows for cross-core function calls.
  36. See IPC documentation for more details.
  37. The default stack size should be enough for most common use cases.
  38. It can be shrunk if you are sure that you do not use any custom
  39. IPC functionality.
  40. config ESP_IPC_USES_CALLERS_PRIORITY
  41. bool "IPC runs at caller's priority"
  42. default y
  43. depends on !FREERTOS_UNICORE
  44. help
  45. If this option is not enabled then the IPC task will keep behavior
  46. same as prior to that of ESP-IDF v4.0, and hence IPC task will run
  47. at (configMAX_PRIORITIES - 1) priority.
  48. config ESP_MINIMAL_SHARED_STACK_SIZE
  49. int "Minimal allowed size for shared stack"
  50. default 2048
  51. help
  52. Minimal value of size, in bytes, accepted to execute a expression
  53. with shared stack.
  54. choice ESP_CONSOLE_UART
  55. prompt "Channel for console output"
  56. default ESP_CONSOLE_UART_DEFAULT
  57. help
  58. Select where to send console output (through stdout and stderr).
  59. - Default is to use UART0 on pre-defined GPIOs.
  60. - If "Custom" is selected, UART0 or UART1 can be chosen,
  61. and any pins can be selected.
  62. - If "None" is selected, there will be no console output on any UART, except
  63. for initial output from ROM bootloader. This ROM output can be suppressed by
  64. GPIO strapping or EFUSE, refer to chip datasheet for details.
  65. - On chips with USB peripheral, "USB CDC" option redirects output to the
  66. CDC port. This option uses the CDC driver in the chip ROM.
  67. This option is incompatible with TinyUSB stack.
  68. config ESP_CONSOLE_UART_DEFAULT
  69. bool "Default: UART0"
  70. config ESP_CONSOLE_USB_CDC
  71. bool "USB CDC"
  72. # The naming is confusing: USB_ENABLED means that TinyUSB driver is enabled, not USB in general.
  73. # && !USB_ENABLED is because the ROM CDC driver is currently incompatible with TinyUSB.
  74. depends on IDF_TARGET_ESP32S2 && !USB_ENABLED
  75. config ESP_CONSOLE_UART_CUSTOM
  76. bool "Custom UART"
  77. config ESP_CONSOLE_NONE
  78. bool "None"
  79. endchoice
  80. # Internal option, indicates that console UART is used (and not USB, for example)
  81. config ESP_CONSOLE_UART
  82. bool
  83. default y if ESP_CONSOLE_UART_DEFAULT || ESP_CONSOLE_UART_CUSTOM
  84. config ESP_CONSOLE_MULTIPLE_UART
  85. bool
  86. default y if !IDF_TARGET_ESP32C3
  87. choice ESP_CONSOLE_UART_NUM
  88. prompt "UART peripheral to use for console output (0-1)"
  89. depends on ESP_CONSOLE_UART_CUSTOM && ESP_CONSOLE_MULTIPLE_UART
  90. default ESP_CONSOLE_UART_CUSTOM_NUM_0
  91. help
  92. This UART peripheral is used for console output from the ESP-IDF Bootloader and the app.
  93. If the configuration is different in the Bootloader binary compared to the app binary, UART
  94. is reconfigured after the bootloader exits and the app starts.
  95. Due to an ESP32 ROM bug, UART2 is not supported for console output
  96. via esp_rom_printf.
  97. config ESP_CONSOLE_UART_CUSTOM_NUM_0
  98. bool "UART0"
  99. config ESP_CONSOLE_UART_CUSTOM_NUM_1
  100. bool "UART1"
  101. endchoice
  102. config ESP_CONSOLE_UART_NUM
  103. int
  104. default 0 if ESP_CONSOLE_UART_DEFAULT
  105. default 0 if !ESP_CONSOLE_MULTIPLE_UART
  106. default 0 if ESP_CONSOLE_UART_CUSTOM_NUM_0
  107. default 1 if ESP_CONSOLE_UART_CUSTOM_NUM_1
  108. default -1 if !ESP_CONSOLE_UART
  109. config ESP_CONSOLE_UART_TX_GPIO
  110. int "UART TX on GPIO#"
  111. depends on ESP_CONSOLE_UART_CUSTOM
  112. range 0 46
  113. default 1 if IDF_TARGET_ESP32
  114. default 21 if IDF_TARGET_ESP32C3
  115. default 43
  116. help
  117. This GPIO is used for console UART TX output in the ESP-IDF Bootloader and the app (including
  118. boot log output and default standard output and standard error of the app).
  119. If the configuration is different in the Bootloader binary compared to the app binary, UART
  120. is reconfigured after the bootloader exits and the app starts.
  121. config ESP_CONSOLE_UART_RX_GPIO
  122. int "UART RX on GPIO#"
  123. depends on ESP_CONSOLE_UART_CUSTOM
  124. range 0 46
  125. default 3 if IDF_TARGET_ESP32
  126. default 20 if IDF_TARGET_ESP32C3
  127. default 44
  128. help
  129. This GPIO is used for UART RX input in the ESP-IDF Bootloader and the app (including
  130. default default standard input of the app).
  131. Note: The default ESP-IDF Bootloader configures this pin but doesn't read anything from the UART.
  132. If the configuration is different in the Bootloader binary compared to the app binary, UART
  133. is reconfigured after the bootloader exits and the app starts.
  134. config ESP_CONSOLE_UART_BAUDRATE
  135. int
  136. prompt "UART console baud rate" if ESP_CONSOLE_UART_CUSTOM
  137. depends on ESP_CONSOLE_UART
  138. default 115200
  139. range 1200 4000000 if !PM_ENABLE
  140. range 1200 1000000 if PM_ENABLE
  141. help
  142. This baud rate is used by both the ESP-IDF Bootloader and the app (including
  143. boot log output and default standard input/output/error of the app).
  144. The app's maximum baud rate depends on the UART clock source. If Power Management is disabled,
  145. the UART clock source is the APB clock and all baud rates in the available range will be sufficiently
  146. accurate. If Power Management is enabled, REF_TICK clock source is used so the baud rate is divided
  147. from 1MHz. Baud rates above 1Mbps are not possible and values between 500Kbps and 1Mbps may not be
  148. accurate.
  149. If the configuration is different in the Bootloader binary compared to the app binary, UART
  150. is reconfigured after the bootloader exits and the app starts.
  151. config ESP_CONSOLE_USB_CDC_RX_BUF_SIZE
  152. int "Size of USB CDC RX buffer"
  153. depends on ESP_CONSOLE_USB_CDC
  154. default 64
  155. range 4 16384
  156. help
  157. Set the size of USB CDC RX buffer. Increase the buffer size if your application
  158. is often receiving data over USB CDC.
  159. config ESP_CONSOLE_USB_CDC_SUPPORT_ETS_PRINTF
  160. bool "Enable esp_rom_printf / ESP_EARLY_LOG via USB CDC"
  161. depends on ESP_CONSOLE_USB_CDC
  162. default n
  163. help
  164. If enabled, esp_rom_printf and ESP_EARLY_LOG output will also be sent over USB CDC.
  165. Disabling this option saves about 1kB or RAM.
  166. config ESP_INT_WDT
  167. bool "Interrupt watchdog"
  168. default y
  169. help
  170. This watchdog timer can detect if the FreeRTOS tick interrupt has not been called for a certain time,
  171. either because a task turned off interrupts and did not turn them on for a long time, or because an
  172. interrupt handler did not return. It will try to invoke the panic handler first and failing that
  173. reset the SoC.
  174. config ESP_INT_WDT_TIMEOUT_MS
  175. int "Interrupt watchdog timeout (ms)"
  176. depends on ESP_INT_WDT
  177. default 300 if !ESP32_SPIRAM_SUPPORT
  178. default 800 if ESP32_SPIRAM_SUPPORT
  179. range 10 10000
  180. help
  181. The timeout of the watchdog, in miliseconds. Make this higher than the FreeRTOS tick rate.
  182. config ESP_INT_WDT_CHECK_CPU1
  183. bool "Also watch CPU1 tick interrupt"
  184. depends on ESP_INT_WDT && !FREERTOS_UNICORE
  185. default y
  186. help
  187. Also detect if interrupts on CPU 1 are disabled for too long.
  188. config ESP_TASK_WDT
  189. bool "Initialize Task Watchdog Timer on startup"
  190. default y
  191. help
  192. The Task Watchdog Timer can be used to make sure individual tasks are still
  193. running. Enabling this option will cause the Task Watchdog Timer to be
  194. initialized automatically at startup. The Task Watchdog timer can be
  195. initialized after startup as well (see Task Watchdog Timer API Reference)
  196. config ESP_TASK_WDT_PANIC
  197. bool "Invoke panic handler on Task Watchdog timeout"
  198. depends on ESP_TASK_WDT
  199. default n
  200. help
  201. If this option is enabled, the Task Watchdog Timer will be configured to
  202. trigger the panic handler when it times out. This can also be configured
  203. at run time (see Task Watchdog Timer API Reference)
  204. config ESP_TASK_WDT_TIMEOUT_S
  205. int "Task Watchdog timeout period (seconds)"
  206. depends on ESP_TASK_WDT
  207. range 1 60
  208. default 5
  209. help
  210. Timeout period configuration for the Task Watchdog Timer in seconds.
  211. This is also configurable at run time (see Task Watchdog Timer API Reference)
  212. config ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0
  213. bool "Watch CPU0 Idle Task"
  214. depends on ESP_TASK_WDT
  215. default y
  216. help
  217. If this option is enabled, the Task Watchdog Timer will watch the CPU0
  218. Idle Task. Having the Task Watchdog watch the Idle Task allows for detection
  219. of CPU starvation as the Idle Task not being called is usually a symptom of
  220. CPU starvation. Starvation of the Idle Task is detrimental as FreeRTOS household
  221. tasks depend on the Idle Task getting some runtime every now and then.
  222. config ESP_TASK_WDT_CHECK_IDLE_TASK_CPU1
  223. bool "Watch CPU1 Idle Task"
  224. depends on ESP_TASK_WDT && !FREERTOS_UNICORE
  225. default y
  226. help
  227. If this option is enabled, the Task Wtachdog Timer will wach the CPU1
  228. Idle Task.
  229. config ESP_PANIC_HANDLER_IRAM
  230. bool "Place panic handler code in IRAM"
  231. default n
  232. help
  233. If this option is disabled (default), the panic handler code is placed in flash not IRAM.
  234. This means that if ESP-IDF crashes while flash cache is disabled, the panic handler will
  235. automatically re-enable flash cache before running GDB Stub or Core Dump. This adds some minor
  236. risk, if the flash cache status is also corrupted during the crash.
  237. If this option is enabled, the panic handler code is placed in IRAM. This allows the panic
  238. handler to run without needing to re-enable cache first. This may be necessary to debug some
  239. complex issues with crashes while flash cache is disabled (for example, when writing to
  240. SPI flash.)
  241. config ESP_DEBUG_STUBS_ENABLE
  242. bool
  243. default COMPILER_OPTIMIZATION_LEVEL_DEBUG
  244. depends on !ESP32_TRAX && !ESP32S2_TRAX
  245. help
  246. Debug stubs are used by OpenOCD to execute pre-compiled onboard code
  247. which does some useful debugging stuff, e.g. GCOV data dump.
  248. config ESP_MAC_ADDR_UNIVERSE_WIFI_STA
  249. bool
  250. config ESP_MAC_ADDR_UNIVERSE_WIFI_AP
  251. bool
  252. config ESP_MAC_ADDR_UNIVERSE_BT
  253. bool
  254. config ESP_MAC_ADDR_UNIVERSE_BT_OFFSET
  255. int
  256. default 2 if ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR
  257. default 1 if ESP32_UNIVERSAL_MAC_ADDRESSES_TWO
  258. default 1
  259. config ESP_MAC_ADDR_UNIVERSE_ETH
  260. bool
  261. endmenu # Common ESP-related