efuse_struct.h 39 KB

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  1. // Copyright 2020 Espressif Systems (Shanghai) PTE LTD
  2. //
  3. // Licensed under the Apache License, Version 2.0 (the "License");
  4. // you may not use this file except in compliance with the License.
  5. // You may obtain a copy of the License at
  6. //
  7. // http://www.apache.org/licenses/LICENSE-2.0
  8. //
  9. // Unless required by applicable law or agreed to in writing, software
  10. // distributed under the License is distributed on an "AS IS" BASIS,
  11. // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  12. // See the License for the specific language governing permissions and
  13. // limitations under the License.
  14. #ifndef _SOC_EFUSE_STRUCT_H_
  15. #define _SOC_EFUSE_STRUCT_H_
  16. #ifdef __cplusplus
  17. extern "C" {
  18. #endif
  19. typedef volatile struct {
  20. uint32_t pgm_data0; /*Register 0 that stores data to be programmed.*/
  21. union {
  22. struct {
  23. uint32_t rd_dis: 7; /*Set this bit to disable reading from BlOCK4-10.*/
  24. uint32_t dis_rtc_ram_boot: 1; /*Set this bit to disable boot from RTC RAM.*/
  25. uint32_t dis_icache: 1; /*Set this bit to disable Icache.*/
  26. uint32_t dis_usb_jtag: 1; /*Set this bit to disable function of usb switch to jtag in module of usb device.*/
  27. uint32_t dis_download_icache: 1; /*Set this bit to disable Icache in download mode (boot_mode[3:0] is 0 1 2 3 6 7).*/
  28. uint32_t dis_usb_device: 1; /*Set this bit to disable usb device.*/
  29. uint32_t dis_force_download: 1; /*Set this bit to disable the function that forces chip into download mode.*/
  30. uint32_t dis_usb: 1; /*Set this bit to disable USB function.*/
  31. uint32_t dis_can: 1; /*Set this bit to disable CAN function.*/
  32. uint32_t jtag_sel_enable: 1; /*Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0.*/
  33. uint32_t soft_dis_jtag: 3; /*Set these bits to disable JTAG in the soft way (odd number 1 means disable ). JTAG can be enabled in HMAC module.*/
  34. uint32_t dis_pad_jtag: 1; /*Set this bit to disable JTAG in the hard way. JTAG is disabled permanently.*/
  35. uint32_t dis_download_manual_encrypt: 1; /*Set this bit to disable flash encryption when in download boot modes.*/
  36. uint32_t usb_drefh: 2; /*Controls single-end input threshold vrefh 1.76 V to 2 V with step of 80 mV stored in eFuse.*/
  37. uint32_t usb_drefl: 2; /*Controls single-end input threshold vrefl 0.8 V to 1.04 V with step of 80 mV stored in eFuse.*/
  38. uint32_t usb_exchg_pins: 1; /*Set this bit to exchange USB D+ and D- pins.*/
  39. uint32_t vdd_spi_as_gpio: 1; /*Set this bit to vdd spi pin function as gpio.*/
  40. uint32_t btlc_gpio_enable: 2; /*Enable btlc gpio.*/
  41. uint32_t powerglitch_en: 1; /*Set this bit to enable power glitch function.*/
  42. uint32_t power_glitch_dsense: 2; /*Sample delay configuration of power glitch.*/
  43. };
  44. uint32_t val;
  45. } pgm_data1;
  46. union {
  47. struct {
  48. uint32_t rpt4_reserved2: 16; /*Reserved (used for four backups method).*/
  49. uint32_t wat_delay_sel: 2; /*Selects RTC watchdog timeout threshold in unit of slow clock cycle. 0: 40000. 1: 80000. 2: 160000. 3:320000.*/
  50. uint32_t spi_boot_crypt_cnt: 3; /*Set this bit to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even number of 1: disable.*/
  51. uint32_t secure_boot_key_revoke0: 1; /*Set this bit to enable revoking first secure boot key.*/
  52. uint32_t secure_boot_key_revoke1: 1; /*Set this bit to enable revoking second secure boot key.*/
  53. uint32_t secure_boot_key_revoke2: 1; /*Set this bit to enable revoking third secure boot key.*/
  54. uint32_t key_purpose_0: 4; /*Purpose of Key0.*/
  55. uint32_t key_purpose_1: 4; /*Purpose of Key1.*/
  56. };
  57. uint32_t val;
  58. } pgm_data2;
  59. union {
  60. struct {
  61. uint32_t key_purpose_2: 4; /*Purpose of Key2.*/
  62. uint32_t key_purpose_3: 4; /*Purpose of Key3.*/
  63. uint32_t key_purpose_4: 4; /*Purpose of Key4.*/
  64. uint32_t key_purpose_5: 4; /*Purpose of Key5.*/
  65. uint32_t rpt4_reserved3: 4; /*Reserved (used for four backups method).*/
  66. uint32_t secure_boot_en: 1; /*Set this bit to enable secure boot.*/
  67. uint32_t secure_boot_aggressive_revoke: 1; /*Set this bit to enable revoking aggressive secure boot.*/
  68. uint32_t rpt4_reserved0: 6; /*Reserved (used for four backups method).*/
  69. uint32_t flash_tpuw: 4; /*Configures flash waiting time after power-up in unit of ms. If the value is less than 15 the waiting time is the configurable value*/
  70. };
  71. uint32_t val;
  72. } pgm_data3;
  73. union {
  74. struct {
  75. uint32_t dis_download_mode: 1; /*Set this bit to disable download mode (boot_mode[3:0] = 0 1 2 3 6 7).*/
  76. uint32_t dis_legacy_spi_boot: 1; /*Set this bit to disable Legacy SPI boot mode (boot_mode[3:0] = 4).*/
  77. uint32_t uart_print_channel: 1; /*Selectes the default UART print channel. 0: UART0. 1: UART1.*/
  78. uint32_t flash_ecc_mode: 1; /*Set ECC mode in ROM 0: ROM would Enable Flash ECC 16to18 byte mode. 1:ROM would use 16to17 byte mode.*/
  79. uint32_t dis_usb_download_mode: 1; /*Set this bit to disable UART download mode through USB.*/
  80. uint32_t enable_security_download: 1; /*Set this bit to enable secure UART download mode.*/
  81. uint32_t uart_print_control: 2; /*Set the default UARTboot message output mode. 00: Enabled. 01: Enabled when GPIO8 is low at reset. 10: Enabled when GPIO8 is high at reset. 11:disabled.*/
  82. uint32_t pin_power_selection: 1; /*GPIO33-GPIO37 power supply selection in ROM code. 0: VDD3P3_CPU. 1: VDD_SPI.*/
  83. uint32_t flash_type: 1; /*Set the maximum lines of SPI flash. 0: four lines. 1: eight lines.*/
  84. uint32_t flash_page_size: 2; /*Set Flash page size.*/
  85. uint32_t flash_ecc_en: 1; /*Set 1 to enable ECC for flash boot.*/
  86. uint32_t force_send_resume: 1; /*Set this bit to force ROM code to send a resume command during SPI boot.*/
  87. uint32_t secure_version: 16; /*Secure version (used by ESP-IDF anti-rollback feature).*/
  88. uint32_t rpt4_reserved1: 2; /*Reserved (used for four backups method).*/
  89. };
  90. uint32_t val;
  91. } pgm_data4;
  92. union {
  93. struct {
  94. uint32_t rpt4_reserved4:24; /*Reserved (used for four backups method).*/
  95. uint32_t reserved24: 8; /*Reserved.*/
  96. };
  97. uint32_t val;
  98. } pgm_data5;
  99. uint32_t pgm_data6; /*Register 6 that stores data to be programmed.*/
  100. uint32_t pgm_data7; /*Register 7 that stores data to be programmed.*/
  101. uint32_t pgm_check_value0; /*Register 0 that stores the RS code to be programmed.*/
  102. uint32_t pgm_check_value1; /*Register 1 that stores the RS code to be programmed.*/
  103. uint32_t pgm_check_value2; /*Register 2 that stores the RS code to be programmed.*/
  104. uint32_t rd_wr_dis; /*BLOCK0 data register $n.*/
  105. union {
  106. struct {
  107. uint32_t rd_dis: 7; /*The value of RD_DIS.*/
  108. uint32_t dis_rtc_ram_boot: 1; /*The value of DIS_RTC_RAM_BOOT.*/
  109. uint32_t dis_icache: 1; /*The value of DIS_ICACHE.*/
  110. uint32_t dis_usb_jtag: 1; /*The value of DIS_USB_JTAG.*/
  111. uint32_t dis_download_icache: 1; /*The value of DIS_DOWNLOAD_ICACHE.*/
  112. uint32_t dis_usb_device: 1; /*The value of DIS_USB_DEVICE.*/
  113. uint32_t dis_force_download: 1; /*The value of DIS_FORCE_DOWNLOAD.*/
  114. uint32_t dis_usb: 1; /*The value of DIS_USB.*/
  115. uint32_t dis_can: 1; /*The value of DIS_CAN.*/
  116. uint32_t jtag_sel_enable: 1; /*The value of JTAG_SEL_ENABLE.*/
  117. uint32_t soft_dis_jtag: 3; /*The value of SOFT_DIS_JTAG.*/
  118. uint32_t dis_pad_jtag: 1; /*The value of DIS_PAD_JTAG.*/
  119. uint32_t dis_download_manual_encrypt: 1; /*The value of DIS_DOWNLOAD_MANUAL_ENCRYPT.*/
  120. uint32_t usb_drefh: 2; /*The value of USB_DREFH.*/
  121. uint32_t usb_drefl: 2; /*The value of USB_DREFL.*/
  122. uint32_t usb_exchg_pins: 1; /*The value of USB_EXCHG_PINS.*/
  123. uint32_t vdd_spi_as_gpio: 1; /*The value of VDD_SPI_AS_GPIO.*/
  124. uint32_t btlc_gpio_enable: 2; /*The value of BTLC_GPIO_ENABLE.*/
  125. uint32_t powerglitch_en: 1; /*The value of POWERGLITCH_EN.*/
  126. uint32_t power_glitch_dsense: 2; /*The value of POWER_GLITCH_DSENSE.*/
  127. };
  128. uint32_t val;
  129. } rd_repeat_data0;
  130. union {
  131. struct {
  132. uint32_t rpt4_reserved2: 16; /*Reserved.*/
  133. uint32_t wdt_delay_sel: 2; /*The value of WDT_DELAY_SEL.*/
  134. uint32_t spi_boot_crypt_cnt: 3; /*The value of SPI_BOOT_CRYPT_CNT.*/
  135. uint32_t secure_boot_key_revoke0: 1; /*The value of SECURE_BOOT_KEY_REVOKE0.*/
  136. uint32_t secure_boot_key_revoke1: 1; /*The value of SECURE_BOOT_KEY_REVOKE1.*/
  137. uint32_t secure_boot_key_revoke2: 1; /*The value of SECURE_BOOT_KEY_REVOKE2.*/
  138. uint32_t key_purpose_0: 4; /*The value of KEY_PURPOSE_0.*/
  139. uint32_t key_purpose_1: 4; /*The value of KEY_PURPOSE_1.*/
  140. };
  141. uint32_t val;
  142. } rd_repeat_data1;
  143. union {
  144. struct {
  145. uint32_t key_purpose_2: 4; /*The value of KEY_PURPOSE_2.*/
  146. uint32_t key_purpose_3: 4; /*The value of KEY_PURPOSE_3.*/
  147. uint32_t key_purpose_4: 4; /*The value of KEY_PURPOSE_4.*/
  148. uint32_t key_purpose_5: 4; /*The value of KEY_PURPOSE_5.*/
  149. uint32_t rpt4_reserved3: 4; /*Reserved.*/
  150. uint32_t secure_boot_en: 1; /*The value of SECURE_BOOT_EN.*/
  151. uint32_t secure_boot_aggressive_revoke: 1; /*The value of SECURE_BOOT_AGGRESSIVE_REVOKE.*/
  152. uint32_t rpt4_reserved0: 6; /*Reserved.*/
  153. uint32_t flash_tpuw: 4; /*The value of FLASH_TPUW.*/
  154. };
  155. uint32_t val;
  156. } rd_repeat_data2;
  157. union {
  158. struct {
  159. uint32_t dis_download_mode: 1; /*The value of DIS_DOWNLOAD_MODE.*/
  160. uint32_t dis_legacy_spi_boot: 1; /*The value of DIS_LEGACY_SPI_BOOT.*/
  161. uint32_t uart_print_channel: 1; /*The value of UART_PRINT_CHANNEL.*/
  162. uint32_t flash_ecc_mode: 1; /*The value of FLASH_ECC_MODE.*/
  163. uint32_t dis_usb_download_mode: 1; /*The value of DIS_USB_DOWNLOAD_MODE.*/
  164. uint32_t enable_security_download: 1; /*The value of ENABLE_SECURITY_DOWNLOAD.*/
  165. uint32_t uart_print_control: 2; /*The value of UART_PRINT_CONTROL.*/
  166. uint32_t pin_power_selection: 1; /*The value of PIN_POWER_SELECTION.*/
  167. uint32_t flash_type: 1; /*The value of FLASH_TYPE.*/
  168. uint32_t flash_page_size: 2; /*The value of FLASH_PAGE_SIZE.*/
  169. uint32_t flash_ecc_en: 1; /*The value of FLASH_ECC_EN.*/
  170. uint32_t force_send_resume: 1; /*The value of FORCE_SEND_RESUME.*/
  171. uint32_t secure_version: 16; /*The value of SECURE_VERSION.*/
  172. uint32_t rpt4_reserved1: 2; /*Reserved.*/
  173. };
  174. uint32_t val;
  175. } rd_repeat_data3;
  176. union {
  177. struct {
  178. uint32_t rpt4_reserved4:24; /*Reserved.*/
  179. uint32_t reserved24: 8; /*Reserved.*/
  180. };
  181. uint32_t val;
  182. } rd_repeat_data4;
  183. uint32_t rd_mac_spi_sys_0; /*BLOCK1 data register $n.*/
  184. union {
  185. struct {
  186. uint32_t mac_1: 16; /*Stores the high 16 bits of MAC address.*/
  187. uint32_t spi_pad_conf_0:16; /*Stores the zeroth part of SPI_PAD_CONF.*/
  188. };
  189. uint32_t val;
  190. } rd_mac_spi_sys_1;
  191. uint32_t rd_mac_spi_sys_2; /*BLOCK1 data register $n.*/
  192. union {
  193. struct {
  194. uint32_t spi_pad_conf_2: 18; /*Stores the second part of SPI_PAD_CONF.*/
  195. uint32_t sys_data_part0_0:14; /*Stores the fist 14 bits of the zeroth part of system data.*/
  196. };
  197. uint32_t val;
  198. } rd_mac_spi_sys_3;
  199. uint32_t rd_mac_spi_sys_4; /*BLOCK1 data register $n.*/
  200. uint32_t rd_mac_spi_sys_5; /*BLOCK1 data register $n.*/
  201. uint32_t rd_sys_part1_data0; /*Register $n of BLOCK2 (system).*/
  202. uint32_t rd_sys_part1_data1; /*Register $n of BLOCK2 (system).*/
  203. uint32_t rd_sys_part1_data2; /*Register $n of BLOCK2 (system).*/
  204. uint32_t rd_sys_part1_data3; /*Register $n of BLOCK2 (system).*/
  205. uint32_t rd_sys_part1_data4; /*Register $n of BLOCK2 (system).*/
  206. uint32_t rd_sys_part1_data5; /*Register $n of BLOCK2 (system).*/
  207. uint32_t rd_sys_part1_data6; /*Register $n of BLOCK2 (system).*/
  208. uint32_t rd_sys_part1_data7; /*Register $n of BLOCK2 (system).*/
  209. uint32_t rd_usr_data0; /*Register $n of BLOCK3 (user).*/
  210. uint32_t rd_usr_data1; /*Register $n of BLOCK3 (user).*/
  211. uint32_t rd_usr_data2; /*Register $n of BLOCK3 (user).*/
  212. uint32_t rd_usr_data3; /*Register $n of BLOCK3 (user).*/
  213. uint32_t rd_usr_data4; /*Register $n of BLOCK3 (user).*/
  214. uint32_t rd_usr_data5; /*Register $n of BLOCK3 (user).*/
  215. uint32_t rd_usr_data6; /*Register $n of BLOCK3 (user).*/
  216. uint32_t rd_usr_data7; /*Register $n of BLOCK3 (user).*/
  217. uint32_t rd_key0_data0; /*Register $n of BLOCK4 (KEY0).*/
  218. uint32_t rd_key0_data1; /*Register $n of BLOCK4 (KEY0).*/
  219. uint32_t rd_key0_data2; /*Register $n of BLOCK4 (KEY0).*/
  220. uint32_t rd_key0_data3; /*Register $n of BLOCK4 (KEY0).*/
  221. uint32_t rd_key0_data4; /*Register $n of BLOCK4 (KEY0).*/
  222. uint32_t rd_key0_data5; /*Register $n of BLOCK4 (KEY0).*/
  223. uint32_t rd_key0_data6; /*Register $n of BLOCK4 (KEY0).*/
  224. uint32_t rd_key0_data7; /*Register $n of BLOCK4 (KEY0).*/
  225. uint32_t rd_key1_data0; /*Register $n of BLOCK5 (KEY1).*/
  226. uint32_t rd_key1_data1; /*Register $n of BLOCK5 (KEY1).*/
  227. uint32_t rd_key1_data2; /*Register $n of BLOCK5 (KEY1).*/
  228. uint32_t rd_key1_data3; /*Register $n of BLOCK5 (KEY1).*/
  229. uint32_t rd_key1_data4; /*Register $n of BLOCK5 (KEY1).*/
  230. uint32_t rd_key1_data5; /*Register $n of BLOCK5 (KEY1).*/
  231. uint32_t rd_key1_data6; /*Register $n of BLOCK5 (KEY1).*/
  232. uint32_t rd_key1_data7; /*Register $n of BLOCK5 (KEY1).*/
  233. uint32_t rd_key2_data0; /*Register $n of BLOCK6 (KEY2).*/
  234. uint32_t rd_key2_data1; /*Register $n of BLOCK6 (KEY2).*/
  235. uint32_t rd_key2_data2; /*Register $n of BLOCK6 (KEY2).*/
  236. uint32_t rd_key2_data3; /*Register $n of BLOCK6 (KEY2).*/
  237. uint32_t rd_key2_data4; /*Register $n of BLOCK6 (KEY2).*/
  238. uint32_t rd_key2_data5; /*Register $n of BLOCK6 (KEY2).*/
  239. uint32_t rd_key2_data6; /*Register $n of BLOCK6 (KEY2).*/
  240. uint32_t rd_key2_data7; /*Register $n of BLOCK6 (KEY2).*/
  241. uint32_t rd_key3_data0; /*Register $n of BLOCK7 (KEY3).*/
  242. uint32_t rd_key3_data1; /*Register $n of BLOCK7 (KEY3).*/
  243. uint32_t rd_key3_data2; /*Register $n of BLOCK7 (KEY3).*/
  244. uint32_t rd_key3_data3; /*Register $n of BLOCK7 (KEY3).*/
  245. uint32_t rd_key3_data4; /*Register $n of BLOCK7 (KEY3).*/
  246. uint32_t rd_key3_data5; /*Register $n of BLOCK7 (KEY3).*/
  247. uint32_t rd_key3_data6; /*Register $n of BLOCK7 (KEY3).*/
  248. uint32_t rd_key3_data7; /*Register $n of BLOCK7 (KEY3).*/
  249. uint32_t rd_key4_data0; /*Register $n of BLOCK8 (KEY4).*/
  250. uint32_t rd_key4_data1; /*Register $n of BLOCK8 (KEY4).*/
  251. uint32_t rd_key4_data2; /*Register $n of BLOCK8 (KEY4).*/
  252. uint32_t rd_key4_data3; /*Register $n of BLOCK8 (KEY4).*/
  253. uint32_t rd_key4_data4; /*Register $n of BLOCK8 (KEY4).*/
  254. uint32_t rd_key4_data5; /*Register $n of BLOCK8 (KEY4).*/
  255. uint32_t rd_key4_data6; /*Register $n of BLOCK8 (KEY4).*/
  256. uint32_t rd_key4_data7; /*Register $n of BLOCK8 (KEY4).*/
  257. uint32_t rd_key5_data0; /*Register $n of BLOCK9 (KEY5).*/
  258. uint32_t rd_key5_data1; /*Register $n of BLOCK9 (KEY5).*/
  259. uint32_t rd_key5_data2; /*Register $n of BLOCK9 (KEY5).*/
  260. uint32_t rd_key5_data3; /*Register $n of BLOCK9 (KEY5).*/
  261. uint32_t rd_key5_data4; /*Register $n of BLOCK9 (KEY5).*/
  262. uint32_t rd_key5_data5; /*Register $n of BLOCK9 (KEY5).*/
  263. uint32_t rd_key5_data6; /*Register $n of BLOCK9 (KEY5).*/
  264. uint32_t rd_key5_data7; /*Register $n of BLOCK9 (KEY5).*/
  265. uint32_t rd_sys_part2_data0; /*Register $n of BLOCK10 (system).*/
  266. uint32_t rd_sys_part2_data1; /*Register $n of BLOCK9 (KEY5).*/
  267. uint32_t rd_sys_part2_data2; /*Register $n of BLOCK10 (system).*/
  268. uint32_t rd_sys_part2_data3; /*Register $n of BLOCK10 (system).*/
  269. uint32_t rd_sys_part2_data4; /*Register $n of BLOCK10 (system).*/
  270. uint32_t rd_sys_part2_data5; /*Register $n of BLOCK10 (system).*/
  271. uint32_t rd_sys_part2_data6; /*Register $n of BLOCK10 (system).*/
  272. uint32_t rd_sys_part2_data7; /*Register $n of BLOCK10 (system).*/
  273. union {
  274. struct {
  275. uint32_t rd_dis_err: 7; /*If any bit in RD_DIS is 1 then it indicates a programming error.*/
  276. uint32_t dis_rtc_ram_boot_err: 1; /*If DIS_RTC_RAM_BOOT is 1 then it indicates a programming error.*/
  277. uint32_t dis_icache_err: 1; /*If DIS_ICACHE is 1 then it indicates a programming error.*/
  278. uint32_t dis_usb_jtag_err: 1; /*If DIS_USB_JTAG is 1 then it indicates a programming error.*/
  279. uint32_t dis_download_icache: 1; /*If DIS_DOWNLOAD_ICACHE is 1 then it indicates a programming error.*/
  280. uint32_t dis_usb_device_err: 1; /*If DIS_USB_DEVICE is 1 then it indicates a programming error.*/
  281. uint32_t dis_force_download_err: 1; /*If DIS_FORCE_DOWNLOAD is 1 then it indicates a programming error.*/
  282. uint32_t dis_usb_err: 1; /*If DIS_USB is 1 then it indicates a programming error.*/
  283. uint32_t dis_can_err: 1; /*If DIS_CAN is 1 then it indicates a programming error.*/
  284. uint32_t jtag_sel_enable_err: 1; /*If JTAG_SEL_ENABLE is 1 then it indicates a programming error.*/
  285. uint32_t soft_dis_jtag_err: 3; /*If SOFT_DIS_JTAG is 1 then it indicates a programming error.*/
  286. uint32_t dis_pad_jtag_err: 1; /*If DIS_PAD_JTAG is 1 then it indicates a programming error.*/
  287. uint32_t dis_download_manual_encrypt_err: 1; /*If DIS_DOWNLOAD_MANUAL_ENCRYPT is 1 then it indicates a programming error.*/
  288. uint32_t usb_drefh_err: 2; /*If any bit in USB_DREFH is 1 then it indicates a programming error.*/
  289. uint32_t usb_drefl_err: 2; /*If any bit in USB_DREFL is 1 then it indicates a programming error.*/
  290. uint32_t usb_exchg_pins_err: 1; /*If USB_EXCHG_PINS is 1 then it indicates a programming error.*/
  291. uint32_t vdd_spi_as_gpio_err: 1; /*If VDD_SPI_AS_GPIO is 1 then it indicates a programming error.*/
  292. uint32_t btlc_gpio_enable_err: 2; /*If any bit in BTLC_GPIO_ENABLE is 1 then it indicates a programming error.*/
  293. uint32_t powerglitch_en_err: 1; /*If POWERGLITCH_EN is 1 then it indicates a programming error.*/
  294. uint32_t power_glitch_dsense_err: 2; /*If any bit in POWER_GLITCH_DSENSE is 1 then it indicates a programming error.*/
  295. };
  296. uint32_t val;
  297. } rd_repeat_err0;
  298. union {
  299. struct {
  300. uint32_t rpt4_reserved2_err: 16; /*Reserved.*/
  301. uint32_t wdt_delay_sel_err: 2; /*If any bit in WDT_DELAY_SEL is 1 then it indicates a programming error.*/
  302. uint32_t spi_boot_crypt_cnt_err: 3; /*If any bit in SPI_BOOT_CRYPT_CNT is 1 then it indicates a programming error.*/
  303. uint32_t secure_boot_key_revoke0_err: 1; /*If SECURE_BOOT_KEY_REVOKE0 is 1 then it indicates a programming error.*/
  304. uint32_t secure_boot_key_revoke1_err: 1; /*If SECURE_BOOT_KEY_REVOKE1 is 1 then it indicates a programming error.*/
  305. uint32_t secure_boot_key_revoke2_err: 1; /*If SECURE_BOOT_KEY_REVOKE2 is 1 then it indicates a programming error.*/
  306. uint32_t key_purpose_0_err: 4; /*If any bit in KEY_PURPOSE_0 is 1 then it indicates a programming error.*/
  307. uint32_t key_purpose_1_err: 4; /*If any bit in KEY_PURPOSE_1 is 1 then it indicates a programming error.*/
  308. };
  309. uint32_t val;
  310. } rd_repeat_err1;
  311. union {
  312. struct {
  313. uint32_t key_purpose_2_err: 4; /*If any bit in KEY_PURPOSE_2 is 1 then it indicates a programming error.*/
  314. uint32_t key_purpose_3_err: 4; /*If any bit in KEY_PURPOSE_3 is 1 then it indicates a programming error.*/
  315. uint32_t key_purpose_4_err: 4; /*If any bit in KEY_PURPOSE_4 is 1 then it indicates a programming error.*/
  316. uint32_t key_purpose_5_err: 4; /*If any bit in KEY_PURPOSE_5 is 1 then it indicates a programming error.*/
  317. uint32_t rpt4_reserved3_err: 4; /*Reserved.*/
  318. uint32_t secure_boot_en_err: 1; /*If SECURE_BOOT_EN is 1 then it indicates a programming error.*/
  319. uint32_t secure_boot_aggressive_revoke_err: 1; /*If SECURE_BOOT_AGGRESSIVE_REVOKE is 1 then it indicates a programming error.*/
  320. uint32_t rpt4_reserved0_err: 6; /*Reserved.*/
  321. uint32_t flash_tpuw_err: 4; /*If any bit in FLASH_TPUM is 1 then it indicates a programming error.*/
  322. };
  323. uint32_t val;
  324. } rd_repeat_err2;
  325. union {
  326. struct {
  327. uint32_t dis_download_mode_err: 1; /*If DIS_DOWNLOAD_MODE is 1 then it indicates a programming error.*/
  328. uint32_t dis_legacy_spi_boot_err: 1; /*If DIS_LEGACY_SPI_BOOT is 1 then it indicates a programming error.*/
  329. uint32_t uart_print_channel_err: 1; /*If UART_PRINT_CHANNEL is 1 then it indicates a programming error.*/
  330. uint32_t flash_ecc_mode_err: 1; /*If FLASH_ECC_MODE is 1 then it indicates a programming error.*/
  331. uint32_t dis_usb_download_mode_err: 1; /*If DIS_USB_DOWNLOAD_MODE is 1 then it indicates a programming error.*/
  332. uint32_t enable_security_download_err: 1; /*If ENABLE_SECURITY_DOWNLOAD is 1 then it indicates a programming error.*/
  333. uint32_t uart_print_control_err: 2; /*If any bit in UART_PRINT_CONTROL is 1 then it indicates a programming error.*/
  334. uint32_t pin_power_selection_err: 1; /*If PIN_POWER_SELECTION is 1 then it indicates a programming error.*/
  335. uint32_t flash_type_err: 1; /*If FLASH_TYPE is 1 then it indicates a programming error.*/
  336. uint32_t flash_page_size: 2; /*If any bits in FLASH_PAGE_SIZE is 1 then it indicates a programming error.*/
  337. uint32_t flash_ecc_en: 1; /*If FLASH_ECC_EN_ERR is 1 then it indicates a programming error.*/
  338. uint32_t force_send_resume_err: 1; /*If FORCE_SEND_RESUME is 1 then it indicates a programming error.*/
  339. uint32_t secure_version_err: 16; /*If any bit in SECURE_VERSION is 1 then it indicates a programming error.*/
  340. uint32_t rpt4_reserved1_err: 2; /*Reserved.*/
  341. };
  342. uint32_t val;
  343. } rd_repeat_err3;
  344. uint32_t reserved_18c;
  345. union {
  346. struct {
  347. uint32_t rpt4_reserved4_err:24; /*Reserved.*/
  348. uint32_t reserved24: 8; /*Reserved.*/
  349. };
  350. uint32_t val;
  351. } rd_repeat_err4;
  352. uint32_t reserved_194;
  353. uint32_t reserved_198;
  354. uint32_t reserved_19c;
  355. uint32_t reserved_1a0;
  356. uint32_t reserved_1a4;
  357. uint32_t reserved_1a8;
  358. uint32_t reserved_1ac;
  359. uint32_t reserved_1b0;
  360. uint32_t reserved_1b4;
  361. uint32_t reserved_1b8;
  362. uint32_t reserved_1bc;
  363. union {
  364. struct {
  365. uint32_t mac_spi_8m_err_num: 3; /*The value of this signal means the number of error bytes.*/
  366. uint32_t mac_spi_8m_fail: 1; /*0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that programming user data failed and the number of error bytes is over 6.*/
  367. uint32_t sys_part1_num: 3; /*The value of this signal means the number of error bytes.*/
  368. uint32_t sys_part1_fail: 1; /*0: Means no failure and that the data of system part1 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.*/
  369. uint32_t usr_data_err_num: 3; /*The value of this signal means the number of error bytes.*/
  370. uint32_t usr_data_fail: 1; /*0: Means no failure and that the user data is reliable 1: Means that programming user data failed and the number of error bytes is over 6.*/
  371. uint32_t key0_err_num: 3; /*The value of this signal means the number of error bytes.*/
  372. uint32_t key0_fail: 1; /*0: Means no failure and that the data of key$n is reliable 1: Means that programming key$n failed and the number of error bytes is over 6.*/
  373. uint32_t key1_err_num: 3; /*The value of this signal means the number of error bytes.*/
  374. uint32_t key1_fail: 1; /*0: Means no failure and that the data of key$n is reliable 1: Means that programming key$n failed and the number of error bytes is over 6.*/
  375. uint32_t key2_err_num: 3; /*The value of this signal means the number of error bytes.*/
  376. uint32_t key2_fail: 1; /*0: Means no failure and that the data of key$n is reliable 1: Means that programming key$n failed and the number of error bytes is over 6.*/
  377. uint32_t key3_err_num: 3; /*The value of this signal means the number of error bytes.*/
  378. uint32_t key3_fail: 1; /*0: Means no failure and that the data of key$n is reliable 1: Means that programming key$n failed and the number of error bytes is over 6.*/
  379. uint32_t key4_err_num: 3; /*The value of this signal means the number of error bytes.*/
  380. uint32_t key4_fail: 1; /*0: Means no failure and that the data of key$n is reliable 1: Means that programming key$n failed and the number of error bytes is over 6.*/
  381. };
  382. uint32_t val;
  383. } rd_rs_err0;
  384. union {
  385. struct {
  386. uint32_t key5_err_num: 3; /*The value of this signal means the number of error bytes.*/
  387. uint32_t key5_fail: 1; /*0: Means no failure and that the data of KEY5 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.*/
  388. uint32_t sys_part2_err_num: 3; /*The value of this signal means the number of error bytes.*/
  389. uint32_t sys_part2_fail: 1; /*0: Means no failure and that the data of system part2 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.*/
  390. uint32_t reserved8: 24; /*Reserved.*/
  391. };
  392. uint32_t val;
  393. } rd_rs_err1;
  394. union {
  395. struct {
  396. uint32_t mem_force_pd: 1; /*Set this bit to force eFuse SRAM into power-saving mode.*/
  397. uint32_t mem_clk_force_on: 1; /*Set this bit and force to activate clock signal of eFuse SRAM.*/
  398. uint32_t mem_force_pu: 1; /*Set this bit to force eFuse SRAM into working mode.*/
  399. uint32_t reserved3: 13; /*Reserved.*/
  400. uint32_t clk_en: 1; /*Set this bit and force to enable clock signal of eFuse memory.*/
  401. uint32_t reserved17: 15; /*Reserved.*/
  402. };
  403. uint32_t val;
  404. } clk;
  405. union {
  406. struct {
  407. uint32_t op_code: 16; /*0x5A5A: Operate programming command 0x5AA5: Operate read command.*/
  408. uint32_t reserved16:16; /*Reserved.*/
  409. };
  410. uint32_t val;
  411. } conf;
  412. union {
  413. struct {
  414. uint32_t state: 4; /*Indicates the state of the eFuse state machine.*/
  415. uint32_t otp_load_sw: 1; /*The value of OTP_LOAD_SW.*/
  416. uint32_t otp_vddq_c_sync2: 1; /*The value of OTP_VDDQ_C_SYNC2.*/
  417. uint32_t otp_strobe_sw: 1; /*The value of OTP_STROBE_SW.*/
  418. uint32_t otp_csb_sw: 1; /*The value of OTP_CSB_SW.*/
  419. uint32_t otp_pgenb_sw: 1; /*The value of OTP_PGENB_SW.*/
  420. uint32_t otp_vddq_is_sw: 1; /*The value of OTP_VDDQ_IS_SW.*/
  421. uint32_t repeat_err_cnt: 8; /*Indicates the number of error bits during programming BLOCK0.*/
  422. uint32_t reserved18: 14; /*Reserved.*/
  423. };
  424. uint32_t val;
  425. } status;
  426. union {
  427. struct {
  428. uint32_t read_cmd: 1; /*Set this bit to send read command.*/
  429. uint32_t pgm_cmd: 1; /*Set this bit to send programming command.*/
  430. uint32_t blk_num: 4; /*The serial number of the block to be programmed. Value 0-10 corresponds to block number 0-10 respectively.*/
  431. uint32_t reserved6: 26; /*Reserved.*/
  432. };
  433. uint32_t val;
  434. } cmd;
  435. union {
  436. struct {
  437. uint32_t read_done: 1; /*The raw bit signal for read_done interrupt.*/
  438. uint32_t pgm_done: 1; /*The raw bit signal for pgm_done interrupt.*/
  439. uint32_t reserved2: 30; /*Reserved.*/
  440. };
  441. uint32_t val;
  442. } int_raw;
  443. union {
  444. struct {
  445. uint32_t read_done: 1; /*The status signal for read_done interrupt.*/
  446. uint32_t pgm_done: 1; /*The status signal for pgm_done interrupt.*/
  447. uint32_t reserved2: 30; /*Reserved.*/
  448. };
  449. uint32_t val;
  450. } int_st;
  451. union {
  452. struct {
  453. uint32_t read_done: 1; /*The enable signal for read_done interrupt.*/
  454. uint32_t pgm_done: 1; /*The enable signal for pgm_done interrupt.*/
  455. uint32_t reserved2: 30; /*Reserved.*/
  456. };
  457. uint32_t val;
  458. } int_ena;
  459. union {
  460. struct {
  461. uint32_t read_done: 1; /*The clear signal for read_done interrupt.*/
  462. uint32_t pgm_done: 1; /*The clear signal for pgm_done interrupt.*/
  463. uint32_t reserved2: 30; /*Reserved.*/
  464. };
  465. uint32_t val;
  466. } int_clr;
  467. union {
  468. struct {
  469. uint32_t dac_clk_div: 8; /*Controls the division factor of the rising clock of the programming voltage.*/
  470. uint32_t dac_clk_pad_sel: 1; /*Don't care.*/
  471. uint32_t dac_num: 8; /*Controls the rising period of the programming voltage.*/
  472. uint32_t oe_clr: 1; /*Reduces the power supply of the programming voltage.*/
  473. uint32_t reserved18: 14; /*Reserved.*/
  474. };
  475. uint32_t val;
  476. } dac_conf;
  477. union {
  478. struct {
  479. uint32_t reserved0: 24; /*Configures the setup time of read operation.*/
  480. uint32_t read_init_num: 8; /*Configures the initial read time of eFuse.*/
  481. };
  482. uint32_t val;
  483. } rd_tim_conf;
  484. union {
  485. struct {
  486. uint32_t reserved0: 8; /*Configures the setup time of programming operation.*/
  487. uint32_t pwr_on_num:16; /*Configures the power up time for VDDQ.*/
  488. uint32_t reserved24: 8; /*Reserved.*/
  489. };
  490. uint32_t val;
  491. } wr_tim_conf1;
  492. union {
  493. struct {
  494. uint32_t pwr_off_num:16; /*Configures the power outage time for VDDQ.*/
  495. uint32_t reserved16: 16; /*Reserved.*/
  496. };
  497. uint32_t val;
  498. } wr_tim_conf2;
  499. uint32_t reserved_1f8;
  500. union {
  501. struct {
  502. uint32_t date: 28; /*Stores eFuse version.*/
  503. uint32_t reserved28: 4; /*Reserved.*/
  504. };
  505. uint32_t val;
  506. } date;
  507. } efuse_dev_t;
  508. extern efuse_dev_t EFUSE;
  509. #ifdef __cplusplus
  510. }
  511. #endif
  512. #endif /* _SOC_EFUSE_STRUCT_H_ */