esp-idf/components/hal/ledc_hal.c

/*
 * SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */

// The HAL layer for LEDC (common part)

#include "esp_attr.h"
#include "hal/ledc_hal.h"
#include "soc/soc_caps.h"

void ledc_hal_init(ledc_hal_context_t *hal, ledc_mode_t speed_mode)
{
    //Get hardware instance.
    hal->dev = LEDC_LL_GET_HW();
    hal->speed_mode = speed_mode;
}

static inline ledc_clk_cfg_t ledc_hal_get_slow_clock_helper(ledc_hal_context_t *hal)
{
    ledc_slow_clk_sel_t slow_clk = LEDC_SLOW_CLK_APB;

    ledc_hal_get_slow_clk_sel(hal, &slow_clk);

    switch (slow_clk) {
        case LEDC_SLOW_CLK_RTC8M:
            return LEDC_USE_RTC8M_CLK;
#if SOC_LEDC_SUPPORT_XTAL_CLOCK
        case LEDC_SLOW_CLK_XTAL:
            return LEDC_USE_XTAL_CLK;
#endif
        default:
            return LEDC_USE_APB_CLK;
    }
}

void ledc_hal_get_clk_cfg(ledc_hal_context_t *hal, ledc_timer_t timer_sel, ledc_clk_cfg_t *clk_cfg)
{
    /* Use the following variable to retrieve the clock source used by the LEDC
     * hardware controler. */
    ledc_clk_src_t clk_src;

    /* Clock configuration to return to the driver. */
    ledc_clk_cfg_t driver_clk = LEDC_USE_APB_CLK;

    /* Get the timer-specific mux value. */
    ledc_hal_get_clock_source(hal, timer_sel, &clk_src);
#if SOC_LEDC_SUPPORT_REF_TICK
    if (clk_src == LEDC_REF_TICK) {
        driver_clk = LEDC_USE_REF_TICK;
    } else
#endif
    /* If the timer-specific mux is not set to REF_TICK, it either means that:
     * - The controler is in fast mode, and thus using APB clock (driver_clk
     *   variable's default value)
     * - The controler is in slow mode and so, using a global clock,
     *   so we have to retrieve that clock here.
     */
    if (hal->speed_mode == LEDC_LOW_SPEED_MODE) {
        /* If the source clock used by LEDC hardware is not REF_TICKS, it is
         * necessary to retrieve the global clock source used. */
        driver_clk = ledc_hal_get_slow_clock_helper(hal);
    }

    *clk_cfg = driver_clk;
}

void ledc_hal_set_slow_clk(ledc_hal_context_t *hal, ledc_clk_cfg_t clk_cfg)
{
    // For low speed channels, if RTC_8MCLK is used as the source clock, the `slow_clk_sel` register should be cleared, otherwise it should be set.
    ledc_slow_clk_sel_t slow_clk_sel;

    switch (clk_cfg) {
        case LEDC_USE_RTC8M_CLK:
            slow_clk_sel = LEDC_SLOW_CLK_RTC8M;
            break;
#if SOC_LEDC_SUPPORT_XTAL_CLOCK
        case LEDC_USE_XTAL_CLK:
            slow_clk_sel = LEDC_SLOW_CLK_XTAL;
            break;
#endif
        default:
            slow_clk_sel = LEDC_SLOW_CLK_APB;
            break;
    }

    ledc_hal_set_slow_clk_sel(hal, slow_clk_sel);
}