bt.c 46 KB

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  1. /*
  2. * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. */
  6. #include <stddef.h>
  7. #include <stdlib.h>
  8. #include <stdio.h>
  9. #include <string.h>
  10. #include "esp_random.h"
  11. #include "esp_heap_caps.h"
  12. #include "esp_heap_caps_init.h"
  13. #include <esp_mac.h>
  14. #include "sdkconfig.h"
  15. #include "nimble/nimble_port.h"
  16. #include "nimble/nimble_port_freertos.h"
  17. #include "esp_private/esp_modem_clock.h"
  18. #ifdef ESP_PLATFORM
  19. #include "esp_log.h"
  20. #endif // ESP_PLATFORM
  21. #if CONFIG_SW_COEXIST_ENABLE
  22. #include "private/esp_coexist_internal.h"
  23. #endif // CONFIG_SW_COEXIST_ENABLE
  24. #include "nimble/nimble_npl_os.h"
  25. #include "nimble/ble_hci_trans.h"
  26. #include "os/endian.h"
  27. #include "esp_bt.h"
  28. #include "esp_intr_alloc.h"
  29. #include "esp_sleep.h"
  30. #include "esp_pm.h"
  31. #include "esp_phy_init.h"
  32. #include "esp_private/periph_ctrl.h"
  33. #include "hci_uart.h"
  34. #include "bt_osi_mem.h"
  35. #if SOC_PM_RETENTION_HAS_CLOCK_BUG
  36. #include "esp_private/sleep_retention.h"
  37. #endif // SOC_PM_RETENTION_HAS_CLOCK_BUG
  38. #if CONFIG_FREERTOS_USE_TICKLESS_IDLE
  39. #include "esp_private/sleep_modem.h"
  40. #endif // CONFIG_FREERTOS_USE_TICKLESS_IDLE
  41. #ifdef CONFIG_BT_BLUEDROID_ENABLED
  42. #include "hci/hci_hal.h"
  43. #endif // CONFIG_BT_BLUEDROID_ENABLED
  44. #include "freertos/FreeRTOS.h"
  45. #include "freertos/task.h"
  46. #include "esp_private/periph_ctrl.h"
  47. #include "esp_sleep.h"
  48. #include "hal/efuse_hal.h"
  49. #include "soc/rtc.h"
  50. /* Macro definition
  51. ************************************************************************
  52. */
  53. #define NIMBLE_PORT_LOG_TAG "BLE_INIT"
  54. #define OSI_COEX_VERSION 0x00010006
  55. #define OSI_COEX_MAGIC_VALUE 0xFADEBEAD
  56. #define EXT_FUNC_VERSION 0x20221122
  57. #define EXT_FUNC_MAGIC_VALUE 0xA5A5A5A5
  58. #define BT_ASSERT_PRINT ets_printf
  59. #ifdef CONFIG_BT_BLUEDROID_ENABLED
  60. /* ACL_DATA_MBUF_LEADINGSPCAE: The leadingspace in user info header for ACL data */
  61. #define ACL_DATA_MBUF_LEADINGSPCAE 4
  62. #endif // CONFIG_BT_BLUEDROID_ENABLED
  63. /* Types definition
  64. ************************************************************************
  65. */
  66. struct osi_coex_funcs_t {
  67. uint32_t _magic;
  68. uint32_t _version;
  69. void (* _coex_wifi_sleep_set)(bool sleep);
  70. int (* _coex_core_ble_conn_dyn_prio_get)(bool *low, bool *high);
  71. void (* _coex_schm_status_bit_set)(uint32_t type, uint32_t status);
  72. void (* _coex_schm_status_bit_clear)(uint32_t type, uint32_t status);
  73. };
  74. struct ext_funcs_t {
  75. uint32_t ext_version;
  76. int (*_esp_intr_alloc)(int source, int flags, intr_handler_t handler, void *arg, void **ret_handle);
  77. int (*_esp_intr_free)(void **ret_handle);
  78. void *(* _malloc)(size_t size);
  79. void (*_free)(void *p);
  80. void (*_hal_uart_start_tx)(int);
  81. int (*_hal_uart_init_cbs)(int, hci_uart_tx_char, hci_uart_tx_done, hci_uart_rx_char, void *);
  82. int (*_hal_uart_config)(int, int32_t, uint8_t, uint8_t, uart_parity_t, uart_hw_flowcontrol_t);
  83. int (*_hal_uart_close)(int);
  84. void (*_hal_uart_blocking_tx)(int, uint8_t);
  85. int (*_hal_uart_init)(int, void *);
  86. int (* _task_create)(void *task_func, const char *name, uint32_t stack_depth, void *param,
  87. uint32_t prio, void *task_handle, uint32_t core_id);
  88. void (* _task_delete)(void *task_handle);
  89. void (*_osi_assert)(const uint32_t ln, const char *fn, uint32_t param1, uint32_t param2);
  90. uint32_t (* _os_random)(void);
  91. int (* _ecc_gen_key_pair)(uint8_t *public, uint8_t *priv);
  92. int (* _ecc_gen_dh_key)(const uint8_t *remote_pub_key_x, const uint8_t *remote_pub_key_y,
  93. const uint8_t *local_priv_key, uint8_t *dhkey);
  94. void (* _esp_reset_rpa_moudle)(void);
  95. uint32_t magic;
  96. };
  97. #if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
  98. typedef void (*interface_func_t) (uint32_t len, const uint8_t*addr, bool end);
  99. #endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
  100. /* External functions or variables
  101. ************************************************************************
  102. */
  103. extern int ble_osi_coex_funcs_register(struct osi_coex_funcs_t *coex_funcs);
  104. extern int ble_controller_init(esp_bt_controller_config_t *cfg);
  105. #if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
  106. extern int ble_log_init_async(interface_func_t bt_controller_log_interface, bool task_create, uint8_t buffers, uint32_t *bufs_size);
  107. extern int ble_log_deinit_async(void);
  108. extern void ble_log_async_select_dump_buffers(uint8_t buffers);
  109. extern void ble_log_async_output_dump_all(bool output);
  110. #endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
  111. extern int ble_controller_deinit(void);
  112. extern int ble_controller_enable(uint8_t mode);
  113. extern int ble_controller_disable(void);
  114. extern int esp_register_ext_funcs (struct ext_funcs_t *);
  115. extern void esp_unregister_ext_funcs (void);
  116. extern int esp_ble_ll_set_public_addr(const uint8_t *addr);
  117. extern int esp_register_npl_funcs (struct npl_funcs_t *p_npl_func);
  118. extern void esp_unregister_npl_funcs (void);
  119. extern void npl_freertos_mempool_deinit(void);
  120. extern uint32_t r_os_cputime_get32(void);
  121. extern uint32_t r_os_cputime_ticks_to_usecs(uint32_t ticks);
  122. extern void ble_lll_rfmgmt_set_sleep_cb(void *s_cb, void *w_cb, void *s_arg,
  123. void *w_arg, uint32_t us_to_enabled);
  124. extern void r_ble_rtc_wake_up_state_clr(void);
  125. extern int os_msys_init(void);
  126. extern void os_msys_deinit(void);
  127. #if CONFIG_FREERTOS_USE_TICKLESS_IDLE
  128. extern const sleep_retention_entries_config_t *esp_ble_mac_retention_link_get(uint8_t *size, uint8_t extra);
  129. extern void esp_ble_set_wakeup_overhead(uint32_t overhead);
  130. #endif /* CONFIG_FREERTOS_USE_TICKLESS_IDLE */
  131. extern void esp_ble_change_rtc_freq(uint32_t freq);
  132. extern int ble_sm_alg_gen_dhkey(const uint8_t *peer_pub_key_x,
  133. const uint8_t *peer_pub_key_y,
  134. const uint8_t *our_priv_key, uint8_t *out_dhkey);
  135. extern int ble_sm_alg_gen_key_pair(uint8_t *pub, uint8_t *priv);
  136. extern int ble_txpwr_set(esp_ble_enhanced_power_type_t power_type, uint16_t handle, int power_level);
  137. extern int ble_txpwr_get(esp_ble_enhanced_power_type_t power_type, uint16_t handle);
  138. extern int ble_get_npl_element_info(esp_bt_controller_config_t *cfg, ble_npl_count_info_t * npl_info);
  139. extern uint32_t _bt_bss_start;
  140. extern uint32_t _bt_bss_end;
  141. extern uint32_t _bt_controller_bss_start;
  142. extern uint32_t _bt_controller_bss_end;
  143. extern uint32_t _bt_data_start;
  144. extern uint32_t _bt_data_end;
  145. extern uint32_t _bt_controller_data_start;
  146. extern uint32_t _bt_controller_data_end;
  147. /* Local Function Declaration
  148. *********************************************************************
  149. */
  150. static void coex_schm_status_bit_set_wrapper(uint32_t type, uint32_t status);
  151. static void coex_schm_status_bit_clear_wrapper(uint32_t type, uint32_t status);
  152. static int task_create_wrapper(void *task_func, const char *name, uint32_t stack_depth,
  153. void *param, uint32_t prio, void *task_handle, uint32_t core_id);
  154. static void task_delete_wrapper(void *task_handle);
  155. #if CONFIG_BT_LE_HCI_INTERFACE_USE_UART
  156. static void hci_uart_start_tx_wrapper(int uart_no);
  157. static int hci_uart_init_cbs_wrapper(int uart_no, hci_uart_tx_char tx_func,
  158. hci_uart_tx_done tx_done, hci_uart_rx_char rx_func, void *arg);
  159. static int hci_uart_config_wrapper(int uart_no, int32_t speed, uint8_t databits, uint8_t stopbits,
  160. uart_parity_t parity, uart_hw_flowcontrol_t flow_ctl);
  161. static int hci_uart_close_wrapper(int uart_no);
  162. static void hci_uart_blocking_tx_wrapper(int port, uint8_t data);
  163. static int hci_uart_init_wrapper(int uart_no, void *cfg);
  164. #endif // CONFIG_BT_LE_HCI_INTERFACE_USE_UART
  165. static int esp_intr_alloc_wrapper(int source, int flags, intr_handler_t handler,
  166. void *arg, void **ret_handle_in);
  167. static int esp_intr_free_wrapper(void **ret_handle);
  168. static void osi_assert_wrapper(const uint32_t ln, const char *fn, uint32_t param1, uint32_t param2);
  169. static uint32_t osi_random_wrapper(void);
  170. static void esp_reset_rpa_moudle(void);
  171. static int esp_ecc_gen_key_pair(uint8_t *pub, uint8_t *priv);
  172. static int esp_ecc_gen_dh_key(const uint8_t *peer_pub_key_x, const uint8_t *peer_pub_key_y,
  173. const uint8_t *our_priv_key, uint8_t *out_dhkey);
  174. #if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
  175. static void esp_bt_controller_log_interface(uint32_t len, const uint8_t *addr, bool end);
  176. #endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
  177. /* Local variable definition
  178. ***************************************************************************
  179. */
  180. /* Static variable declare */
  181. static DRAM_ATTR esp_bt_controller_status_t ble_controller_status = ESP_BT_CONTROLLER_STATUS_IDLE;
  182. #if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
  183. const static uint32_t log_bufs_size[] = {6144, 1024, 2048};
  184. #endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
  185. /* This variable tells if BLE is running */
  186. static bool s_ble_active = false;
  187. #ifdef CONFIG_PM_ENABLE
  188. static DRAM_ATTR esp_pm_lock_handle_t s_pm_lock = NULL;
  189. #define BTDM_MIN_TIMER_UNCERTAINTY_US (200)
  190. #endif // CONFIG_PM_ENABLE
  191. #define BLE_RTC_DELAY_US_LIGHT_SLEEP (2500)
  192. #define BLE_RTC_DELAY_US_MODEM_SLEEP (500)
  193. static const struct osi_coex_funcs_t s_osi_coex_funcs_ro = {
  194. ._magic = OSI_COEX_MAGIC_VALUE,
  195. ._version = OSI_COEX_VERSION,
  196. ._coex_wifi_sleep_set = NULL,
  197. ._coex_core_ble_conn_dyn_prio_get = NULL,
  198. ._coex_schm_status_bit_set = coex_schm_status_bit_set_wrapper,
  199. ._coex_schm_status_bit_clear = coex_schm_status_bit_clear_wrapper,
  200. };
  201. struct ext_funcs_t ext_funcs_ro = {
  202. .ext_version = EXT_FUNC_VERSION,
  203. ._esp_intr_alloc = esp_intr_alloc_wrapper,
  204. ._esp_intr_free = esp_intr_free_wrapper,
  205. ._malloc = bt_osi_mem_malloc_internal,
  206. ._free = bt_osi_mem_free,
  207. #if CONFIG_BT_LE_HCI_INTERFACE_USE_UART
  208. ._hal_uart_start_tx = hci_uart_start_tx_wrapper,
  209. ._hal_uart_init_cbs = hci_uart_init_cbs_wrapper,
  210. ._hal_uart_config = hci_uart_config_wrapper,
  211. ._hal_uart_close = hci_uart_close_wrapper,
  212. ._hal_uart_blocking_tx = hci_uart_blocking_tx_wrapper,
  213. ._hal_uart_init = hci_uart_init_wrapper,
  214. #endif //CONFIG_BT_LE_HCI_INTERFACE_USE_UART
  215. ._task_create = task_create_wrapper,
  216. ._task_delete = task_delete_wrapper,
  217. ._osi_assert = osi_assert_wrapper,
  218. ._os_random = osi_random_wrapper,
  219. ._ecc_gen_key_pair = esp_ecc_gen_key_pair,
  220. ._ecc_gen_dh_key = esp_ecc_gen_dh_key,
  221. ._esp_reset_rpa_moudle = esp_reset_rpa_moudle,
  222. .magic = EXT_FUNC_MAGIC_VALUE,
  223. };
  224. static void IRAM_ATTR esp_reset_rpa_moudle(void)
  225. {
  226. }
  227. static void IRAM_ATTR osi_assert_wrapper(const uint32_t ln, const char *fn,
  228. uint32_t param1, uint32_t param2)
  229. {
  230. BT_ASSERT_PRINT("BLE assert: line %d in function %s, param: 0x%x, 0x%x", ln, fn, param1, param2);
  231. #if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
  232. esp_ble_controller_log_dump_all(true);
  233. #endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
  234. assert(0);
  235. }
  236. static uint32_t IRAM_ATTR osi_random_wrapper(void)
  237. {
  238. return esp_random();
  239. }
  240. static void coex_schm_status_bit_set_wrapper(uint32_t type, uint32_t status)
  241. {
  242. #if CONFIG_SW_COEXIST_ENABLE
  243. coex_schm_status_bit_set(type, status);
  244. #endif // CONFIG_SW_COEXIST_ENABLE
  245. }
  246. static void coex_schm_status_bit_clear_wrapper(uint32_t type, uint32_t status)
  247. {
  248. #if CONFIG_SW_COEXIST_ENABLE
  249. coex_schm_status_bit_clear(type, status);
  250. #endif // CONFIG_SW_COEXIST_ENABLE
  251. }
  252. #ifdef CONFIG_BT_BLUEDROID_ENABLED
  253. bool esp_vhci_host_check_send_available(void)
  254. {
  255. if (ble_controller_status != ESP_BT_CONTROLLER_STATUS_ENABLED) {
  256. return false;
  257. }
  258. return true;
  259. }
  260. static struct os_mbuf *ble_hs_mbuf_gen_pkt(uint16_t leading_space)
  261. {
  262. struct os_mbuf *om;
  263. int rc;
  264. om = os_msys_get_pkthdr(0, 0);
  265. if (om == NULL) {
  266. return NULL;
  267. }
  268. if (om->om_omp->omp_databuf_len < leading_space) {
  269. rc = os_mbuf_free_chain(om);
  270. assert(rc == 0);
  271. return NULL;
  272. }
  273. om->om_data += leading_space;
  274. return om;
  275. }
  276. struct os_mbuf *ble_hs_mbuf_acl_pkt(void)
  277. {
  278. return ble_hs_mbuf_gen_pkt(4 + 1);
  279. }
  280. void esp_vhci_host_send_packet(uint8_t *data, uint16_t len)
  281. {
  282. if (ble_controller_status != ESP_BT_CONTROLLER_STATUS_ENABLED) {
  283. return;
  284. }
  285. if (*(data) == DATA_TYPE_COMMAND) {
  286. struct ble_hci_cmd *cmd = NULL;
  287. cmd = (struct ble_hci_cmd *) ble_hci_trans_buf_alloc(BLE_HCI_TRANS_BUF_CMD);
  288. assert(cmd);
  289. memcpy((uint8_t *)cmd, data + 1, len - 1);
  290. ble_hci_trans_hs_cmd_tx((uint8_t *)cmd);
  291. }
  292. if (*(data) == DATA_TYPE_ACL) {
  293. struct os_mbuf *om = os_msys_get_pkthdr(len, ACL_DATA_MBUF_LEADINGSPCAE);
  294. assert(om);
  295. assert(os_mbuf_append(om, &data[1], len - 1) == 0);
  296. ble_hci_trans_hs_acl_tx(om);
  297. }
  298. }
  299. esp_err_t esp_vhci_host_register_callback(const esp_vhci_host_callback_t *callback)
  300. {
  301. if (ble_controller_status != ESP_BT_CONTROLLER_STATUS_ENABLED) {
  302. return ESP_FAIL;
  303. }
  304. ble_hci_trans_cfg_hs(ble_hs_hci_rx_evt, NULL, ble_hs_rx_data, NULL);
  305. return ESP_OK;
  306. }
  307. #endif // CONFIG_BT_BLUEDROID_ENABLED
  308. static int task_create_wrapper(void *task_func, const char *name, uint32_t stack_depth,
  309. void *param, uint32_t prio, void *task_handle, uint32_t core_id)
  310. {
  311. return (uint32_t)xTaskCreatePinnedToCore(task_func, name, stack_depth, param, prio, task_handle,
  312. (core_id < portNUM_PROCESSORS ? core_id : tskNO_AFFINITY));
  313. }
  314. static void task_delete_wrapper(void *task_handle)
  315. {
  316. vTaskDelete(task_handle);
  317. }
  318. static int esp_ecc_gen_key_pair(uint8_t *pub, uint8_t *priv)
  319. {
  320. int rc = -1;
  321. #if CONFIG_BT_LE_SM_LEGACY || CONFIG_BT_LE_SM_SC
  322. rc = ble_sm_alg_gen_key_pair(pub, priv);
  323. #endif // CONFIG_BT_LE_SM_LEGACY || CONFIG_BT_LE_SM_SC
  324. return rc;
  325. }
  326. static int esp_ecc_gen_dh_key(const uint8_t *peer_pub_key_x, const uint8_t *peer_pub_key_y,
  327. const uint8_t *our_priv_key, uint8_t *out_dhkey)
  328. {
  329. int rc = -1;
  330. #if CONFIG_BT_LE_SM_LEGACY || CONFIG_BT_LE_SM_SC
  331. rc = ble_sm_alg_gen_dhkey(peer_pub_key_x, peer_pub_key_y, our_priv_key, out_dhkey);
  332. #endif // CONFIG_BT_LE_SM_LEGACY || CONFIG_BT_LE_SM_SC
  333. return rc;
  334. }
  335. #ifdef CONFIG_BT_LE_HCI_INTERFACE_USE_UART
  336. static void hci_uart_start_tx_wrapper(int uart_no)
  337. {
  338. hci_uart_start_tx(uart_no);
  339. }
  340. static int hci_uart_init_cbs_wrapper(int uart_no, hci_uart_tx_char tx_func,
  341. hci_uart_tx_done tx_done, hci_uart_rx_char rx_func, void *arg)
  342. {
  343. int rc = -1;
  344. rc = hci_uart_init_cbs(uart_no, tx_func, tx_done, rx_func, arg);
  345. return rc;
  346. }
  347. static int hci_uart_config_wrapper(int port_num, int32_t baud_rate, uint8_t data_bits,
  348. uint8_t stop_bits, uart_parity_t parity,
  349. uart_hw_flowcontrol_t flow_ctl)
  350. {
  351. int rc = -1;
  352. rc = hci_uart_config(port_num, baud_rate, data_bits, stop_bits, parity, flow_ctl);
  353. return rc;
  354. }
  355. static int hci_uart_close_wrapper(int uart_no)
  356. {
  357. int rc = -1;
  358. rc = hci_uart_close(uart_no);
  359. return rc;
  360. }
  361. static void hci_uart_blocking_tx_wrapper(int port, uint8_t data)
  362. {
  363. //This function is nowhere to use.
  364. }
  365. static int hci_uart_init_wrapper(int uart_no, void *cfg)
  366. {
  367. //This function is nowhere to use.
  368. return 0;
  369. }
  370. #endif //CONFIG_BT_LE_HCI_INTERFACE_USE_UART
  371. static int ble_hci_unregistered_hook(void*, void*)
  372. {
  373. ESP_LOGD(NIMBLE_PORT_LOG_TAG,"%s ble hci rx_evt is not registered.",__func__);
  374. return 0;
  375. }
  376. static int esp_intr_alloc_wrapper(int source, int flags, intr_handler_t handler,
  377. void *arg, void **ret_handle_in)
  378. {
  379. int rc = esp_intr_alloc(source, flags | ESP_INTR_FLAG_IRAM, handler,
  380. arg, (intr_handle_t *)ret_handle_in);
  381. return rc;
  382. }
  383. static int esp_intr_free_wrapper(void **ret_handle)
  384. {
  385. int rc = 0;
  386. rc = esp_intr_free((intr_handle_t) * ret_handle);
  387. *ret_handle = NULL;
  388. return rc;
  389. }
  390. void esp_bt_rtc_slow_clk_select(uint8_t slow_clk_src)
  391. {
  392. /* Select slow clock source for BT momdule */
  393. switch (slow_clk_src) {
  394. case MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL:
  395. ESP_LOGI(NIMBLE_PORT_LOG_TAG, "Using main XTAL as clock source");
  396. uint32_t chip_version = efuse_hal_chip_revision();
  397. if (chip_version == 0) {
  398. modem_clock_select_lp_clock_source(PERIPH_BT_MODULE, slow_clk_src, (400 - 1));
  399. } else{
  400. modem_clock_select_lp_clock_source(PERIPH_BT_MODULE, slow_clk_src, (5 - 1));
  401. }
  402. break;
  403. case MODEM_CLOCK_LPCLK_SRC_RC_SLOW:
  404. ESP_LOGI(NIMBLE_PORT_LOG_TAG, "Using 136 kHz RC as clock source, can only run legacy ADV or SCAN due to low clock accuracy!");
  405. modem_clock_select_lp_clock_source(PERIPH_BT_MODULE, slow_clk_src, (5 - 1));
  406. break;
  407. case MODEM_CLOCK_LPCLK_SRC_XTAL32K:
  408. ESP_LOGI(NIMBLE_PORT_LOG_TAG, "Using external 32.768 kHz XTAL as clock source");
  409. modem_clock_select_lp_clock_source(PERIPH_BT_MODULE, slow_clk_src, (1 - 1));
  410. break;
  411. case MODEM_CLOCK_LPCLK_SRC_RC32K:
  412. ESP_LOGI(NIMBLE_PORT_LOG_TAG, "Using 32 kHz RC as clock source, can only run legacy ADV or SCAN due to low clock accuracy!");
  413. modem_clock_select_lp_clock_source(PERIPH_BT_MODULE, slow_clk_src, (1 - 1));
  414. break;
  415. case MODEM_CLOCK_LPCLK_SRC_EXT32K:
  416. ESP_LOGI(NIMBLE_PORT_LOG_TAG, "Using 32 kHz oscillator as clock source, can only run legacy ADV or SCAN due to low clock accuracy!");
  417. modem_clock_select_lp_clock_source(PERIPH_BT_MODULE, slow_clk_src, (1 - 1));
  418. break;
  419. default:
  420. }
  421. }
  422. IRAM_ATTR void controller_sleep_cb(uint32_t enable_tick, void *arg)
  423. {
  424. if (!s_ble_active) {
  425. return;
  426. }
  427. #if CONFIG_FREERTOS_USE_TICKLESS_IDLE
  428. r_ble_rtc_wake_up_state_clr();
  429. #if SOC_PM_RETENTION_HAS_CLOCK_BUG
  430. sleep_retention_do_extra_retention(true);
  431. #endif // SOC_PM_RETENTION_HAS_CLOCK_BUG
  432. #endif /* CONFIG_FREERTOS_USE_TICKLESS_IDLE */
  433. esp_phy_disable(PHY_MODEM_BT);
  434. #ifdef CONFIG_PM_ENABLE
  435. esp_pm_lock_release(s_pm_lock);
  436. #endif // CONFIG_PM_ENABLE
  437. s_ble_active = false;
  438. }
  439. IRAM_ATTR void controller_wakeup_cb(void *arg)
  440. {
  441. if (s_ble_active) {
  442. return;
  443. }
  444. #ifdef CONFIG_PM_ENABLE
  445. esp_pm_lock_acquire(s_pm_lock);
  446. r_ble_rtc_wake_up_state_clr();
  447. #if CONFIG_FREERTOS_USE_TICKLESS_IDLE && SOC_PM_RETENTION_HAS_CLOCK_BUG
  448. sleep_retention_do_extra_retention(false);
  449. #endif /* CONFIG_FREERTOS_USE_TICKLESS_IDLE && SOC_PM_RETENTION_HAS_CLOCK_BUG */
  450. #endif //CONFIG_PM_ENABLE
  451. esp_phy_enable(PHY_MODEM_BT);
  452. s_ble_active = true;
  453. }
  454. #if CONFIG_FREERTOS_USE_TICKLESS_IDLE
  455. static esp_err_t sleep_modem_ble_mac_modem_state_init(uint8_t extra)
  456. {
  457. uint8_t size;
  458. const sleep_retention_entries_config_t *ble_mac_modem_config = esp_ble_mac_retention_link_get(&size, extra);
  459. esp_err_t err = sleep_retention_entries_create(ble_mac_modem_config, size, REGDMA_LINK_PRI_5, SLEEP_RETENTION_MODULE_BLE_MAC);
  460. if (err == ESP_OK) {
  461. ESP_LOGI(NIMBLE_PORT_LOG_TAG, "Modem BLE MAC retention initialization");
  462. }
  463. return err;
  464. }
  465. static void sleep_modem_ble_mac_modem_state_deinit(void)
  466. {
  467. sleep_retention_entries_destroy(SLEEP_RETENTION_MODULE_BLE_MAC);
  468. }
  469. void sleep_modem_light_sleep_overhead_set(uint32_t overhead)
  470. {
  471. esp_ble_set_wakeup_overhead(overhead);
  472. }
  473. #endif /* CONFIG_FREERTOS_USE_TICKLESS_IDLE */
  474. esp_err_t controller_sleep_init(void)
  475. {
  476. esp_err_t rc = 0;
  477. #ifdef CONFIG_BT_LE_SLEEP_ENABLE
  478. ESP_LOGW(NIMBLE_PORT_LOG_TAG, "BLE modem sleep is enabled");
  479. #if CONFIG_FREERTOS_USE_TICKLESS_IDLE
  480. ble_lll_rfmgmt_set_sleep_cb(controller_sleep_cb, controller_wakeup_cb, 0, 0,
  481. BLE_RTC_DELAY_US_LIGHT_SLEEP);
  482. #else
  483. ble_lll_rfmgmt_set_sleep_cb(controller_sleep_cb, controller_wakeup_cb, 0, 0,
  484. BLE_RTC_DELAY_US_MODEM_SLEEP);
  485. #endif /* FREERTOS_USE_TICKLESS_IDLE */
  486. #endif // CONFIG_BT_LE_SLEEP_ENABLE
  487. #ifdef CONFIG_PM_ENABLE
  488. rc = esp_pm_lock_create(ESP_PM_CPU_FREQ_MAX, 0, "bt", &s_pm_lock);
  489. if (rc != ESP_OK) {
  490. goto error;
  491. }
  492. #if CONFIG_FREERTOS_USE_TICKLESS_IDLE
  493. /* Create a new regdma link for BLE related register restoration */
  494. rc = sleep_modem_ble_mac_modem_state_init(1);
  495. assert(rc == 0);
  496. esp_sleep_enable_bt_wakeup();
  497. ESP_LOGW(NIMBLE_PORT_LOG_TAG, "Enable light sleep, the wake up source is BLE timer");
  498. rc = esp_pm_register_inform_out_light_sleep_overhead_callback(sleep_modem_light_sleep_overhead_set);
  499. if (rc != ESP_OK) {
  500. goto error;
  501. }
  502. #endif /* CONFIG_FREERTOS_USE_TICKLESS_IDLE */
  503. return rc;
  504. error:
  505. #if CONFIG_FREERTOS_USE_TICKLESS_IDLE
  506. esp_sleep_disable_bt_wakeup();
  507. esp_pm_unregister_inform_out_light_sleep_overhead_callback(sleep_modem_light_sleep_overhead_set);
  508. #endif /* CONFIG_FREERTOS_USE_TICKLESS_IDLE */
  509. /*lock should release first and then delete*/
  510. if (s_pm_lock != NULL) {
  511. esp_pm_lock_delete(s_pm_lock);
  512. s_pm_lock = NULL;
  513. }
  514. #endif // CONFIG_PM_ENABLE
  515. return rc;
  516. }
  517. void controller_sleep_deinit(void)
  518. {
  519. #if CONFIG_FREERTOS_USE_TICKLESS_IDLE
  520. r_ble_rtc_wake_up_state_clr();
  521. esp_sleep_disable_bt_wakeup();
  522. sleep_modem_ble_mac_modem_state_deinit();
  523. esp_pm_unregister_inform_out_light_sleep_overhead_callback(sleep_modem_light_sleep_overhead_set);
  524. #endif /* CONFIG_FREERTOS_USE_TICKLESS_IDLE */
  525. #ifdef CONFIG_PM_ENABLE
  526. /* lock should be released first */
  527. esp_pm_lock_delete(s_pm_lock);
  528. s_pm_lock = NULL;
  529. #endif //CONFIG_PM_ENABLE
  530. }
  531. typedef enum {
  532. FILTER_DUPLICATE_PDUTYPE = BIT(0),
  533. FILTER_DUPLICATE_LENGTH = BIT(1),
  534. FILTER_DUPLICATE_ADDRESS = BIT(2),
  535. FILTER_DUPLICATE_ADVDATA = BIT(3),
  536. FILTER_DUPLICATE_DEFAULT = FILTER_DUPLICATE_PDUTYPE | FILTER_DUPLICATE_ADDRESS,
  537. FILTER_DUPLICATE_PDU_ALL = 0xF,
  538. FILTER_DUPLICATE_EXCEPTION_FOR_MESH = BIT(4),
  539. FILTER_DUPLICATE_AD_TYPE = BIT(5),
  540. }disc_duplicate_mode_t;
  541. extern void filter_duplicate_mode_enable(disc_duplicate_mode_t mode);
  542. extern void filter_duplicate_mode_disable(disc_duplicate_mode_t mode);
  543. extern void filter_duplicate_set_ring_list_max_num(uint32_t max_num);
  544. extern void scan_duplicate_cache_refresh_set_time(uint32_t period_time);
  545. int
  546. ble_vhci_disc_duplicate_mode_enable(int mode)
  547. {
  548. // TODO: use vendor hci to update
  549. filter_duplicate_mode_enable(mode);
  550. return true;
  551. }
  552. int
  553. ble_vhci_disc_duplicate_mode_disable(int mode)
  554. {
  555. // TODO: use vendor hci to update
  556. filter_duplicate_mode_disable(mode);
  557. return true;
  558. }
  559. int ble_vhci_disc_duplicate_set_max_cache_size(int max_cache_size){
  560. // TODO: use vendor hci to update
  561. filter_duplicate_set_ring_list_max_num(max_cache_size);
  562. return true;
  563. }
  564. int ble_vhci_disc_duplicate_set_period_refresh_time(int refresh_period_time){
  565. // TODO: use vendor hci to update
  566. scan_duplicate_cache_refresh_set_time(refresh_period_time);
  567. return true;
  568. }
  569. /**
  570. * @brief Config scan duplicate option mode from menuconfig (Adapt to the old configuration method.)
  571. */
  572. void ble_controller_scan_duplicate_config(void)
  573. {
  574. uint32_t duplicate_mode = FILTER_DUPLICATE_DEFAULT;
  575. uint32_t cache_size = 100;
  576. #if CONFIG_BT_LE_SCAN_DUPL == true
  577. cache_size = CONFIG_BT_LE_SCAN_DUPL_CACHE_SIZE;
  578. if (CONFIG_BT_LE_SCAN_DUPL_TYPE == 0) {
  579. duplicate_mode = FILTER_DUPLICATE_ADDRESS | FILTER_DUPLICATE_PDUTYPE;
  580. } else if (CONFIG_BT_LE_SCAN_DUPL_TYPE == 1) {
  581. duplicate_mode = FILTER_DUPLICATE_ADVDATA;
  582. } else if (CONFIG_BT_LE_SCAN_DUPL_TYPE == 2) {
  583. duplicate_mode = FILTER_DUPLICATE_ADDRESS | FILTER_DUPLICATE_ADVDATA;
  584. }
  585. duplicate_mode |= FILTER_DUPLICATE_EXCEPTION_FOR_MESH;
  586. ble_vhci_disc_duplicate_set_period_refresh_time(CONFIG_BT_LE_SCAN_DUPL_CACHE_REFRESH_PERIOD);
  587. #endif
  588. ble_vhci_disc_duplicate_mode_disable(0xFFFFFFFF);
  589. ble_vhci_disc_duplicate_mode_enable(duplicate_mode);
  590. ble_vhci_disc_duplicate_set_max_cache_size(cache_size);
  591. }
  592. esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
  593. {
  594. uint8_t mac[6];
  595. esp_err_t ret = ESP_OK;
  596. ble_npl_count_info_t npl_info;
  597. uint32_t slow_clk_freq = 0;
  598. memset(&npl_info, 0, sizeof(ble_npl_count_info_t));
  599. if (ble_controller_status != ESP_BT_CONTROLLER_STATUS_IDLE) {
  600. ESP_LOGW(NIMBLE_PORT_LOG_TAG, "invalid controller state");
  601. return ESP_ERR_INVALID_STATE;
  602. }
  603. if (!cfg) {
  604. ESP_LOGW(NIMBLE_PORT_LOG_TAG, "cfg is NULL");
  605. return ESP_ERR_INVALID_ARG;
  606. }
  607. ret = esp_register_ext_funcs(&ext_funcs_ro);
  608. if (ret != ESP_OK) {
  609. ESP_LOGW(NIMBLE_PORT_LOG_TAG, "register extend functions failed");
  610. return ret;
  611. }
  612. /* Initialize the function pointers for OS porting */
  613. npl_freertos_funcs_init();
  614. struct npl_funcs_t *p_npl_funcs = npl_freertos_funcs_get();
  615. if (!p_npl_funcs) {
  616. ESP_LOGW(NIMBLE_PORT_LOG_TAG, "npl functions get failed");
  617. return ESP_ERR_INVALID_ARG;
  618. }
  619. ret = esp_register_npl_funcs(p_npl_funcs);
  620. if (ret != ESP_OK) {
  621. ESP_LOGW(NIMBLE_PORT_LOG_TAG, "npl functions register failed");
  622. goto free_mem;
  623. }
  624. ble_get_npl_element_info(cfg, &npl_info);
  625. npl_freertos_set_controller_npl_info(&npl_info);
  626. if (npl_freertos_mempool_init() != 0) {
  627. ESP_LOGW(NIMBLE_PORT_LOG_TAG, "npl mempool init failed");
  628. ret = ESP_ERR_INVALID_ARG;
  629. goto free_mem;
  630. }
  631. #if CONFIG_BT_NIMBLE_ENABLED
  632. /* ble_npl_eventq_init() needs to use npl functions in rom and
  633. * must be called after esp_bt_controller_init().
  634. */
  635. ble_npl_eventq_init(nimble_port_get_dflt_eventq());
  636. #endif // CONFIG_BT_NIMBLE_ENABLED
  637. /* Enable BT-related clocks */
  638. modem_clock_module_enable(PERIPH_BT_MODULE);
  639. modem_clock_module_mac_reset(PERIPH_BT_MODULE);
  640. /* Select slow clock source for BT momdule */
  641. #if CONFIG_BT_LE_LP_CLK_SRC_MAIN_XTAL
  642. esp_bt_rtc_slow_clk_select(MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL);
  643. slow_clk_freq = 100000;
  644. #else
  645. #if CONFIG_RTC_CLK_SRC_INT_RC
  646. esp_bt_rtc_slow_clk_select(MODEM_CLOCK_LPCLK_SRC_RC_SLOW);
  647. slow_clk_freq = 30000;
  648. #elif CONFIG_RTC_CLK_SRC_EXT_CRYS
  649. if (rtc_clk_slow_src_get() == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
  650. esp_bt_rtc_slow_clk_select(MODEM_CLOCK_LPCLK_SRC_XTAL32K);
  651. slow_clk_freq = 32768;
  652. } else {
  653. ESP_LOGW(NIMBLE_PORT_LOG_TAG, "32.768kHz XTAL not detected, fall back to main XTAL as Bluetooth sleep clock");
  654. esp_bt_rtc_slow_clk_select(MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL);
  655. slow_clk_freq = 100000;
  656. }
  657. #elif CONFIG_RTC_CLK_SRC_INT_RC32K
  658. esp_bt_rtc_slow_clk_select(MODEM_CLOCK_LPCLK_SRC_RC32K);
  659. slow_clk_freq = 32000;
  660. #elif CONFIG_RTC_CLK_SRC_EXT_OSC
  661. esp_bt_rtc_slow_clk_select(MODEM_CLOCK_LPCLK_SRC_EXT32K);
  662. slow_clk_freq = 32000;
  663. #else
  664. ESP_LOGE(NIMBLE_PORT_LOG_TAG, "Unsupported clock source");
  665. assert(0);
  666. #endif
  667. #endif /* CONFIG_BT_LE_LP_CLK_SRC_MAIN_XTAL */
  668. esp_phy_modem_init();
  669. if (ble_osi_coex_funcs_register((struct osi_coex_funcs_t *)&s_osi_coex_funcs_ro) != 0) {
  670. ESP_LOGW(NIMBLE_PORT_LOG_TAG, "osi coex funcs reg failed");
  671. ret = ESP_ERR_INVALID_ARG;
  672. goto modem_deint;
  673. }
  674. #if CONFIG_SW_COEXIST_ENABLE
  675. coex_init();
  676. #endif // CONFIG_SW_COEXIST_ENABLE
  677. #if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
  678. interface_func_t bt_controller_log_interface;
  679. bt_controller_log_interface = esp_bt_controller_log_interface;
  680. uint8_t buffers = 0;
  681. #if CONFIG_BT_LE_CONTROLLER_LOG_CTRL_ENABLED
  682. buffers |= ESP_BLE_LOG_BUF_CONTROLLER;
  683. #endif // CONFIG_BT_LE_CONTROLLER_LOG_CTRL_ENABLED
  684. #if CONFIG_BT_LE_CONTROLLER_LOG_HCI_ENABLED
  685. buffers |= ESP_BLE_LOG_BUF_HCI;
  686. #endif // CONFIG_BT_LE_CONTROLLER_LOG_HCI_ENABLED
  687. #if CONFIG_BT_LE_CONTROLLER_LOG_DUMP_ONLY
  688. ret = ble_log_init_async(bt_controller_log_interface, false, buffers, (uint32_t *)log_bufs_size);
  689. #else
  690. ret = ble_log_init_async(bt_controller_log_interface, true, buffers, (uint32_t *)log_bufs_size);
  691. #endif // CONFIG_BT_CONTROLLER_LOG_DUMP
  692. if (ret != ESP_OK) {
  693. ESP_LOGW(NIMBLE_PORT_LOG_TAG, "ble_controller_log_init failed %d", ret);
  694. goto modem_deint;
  695. }
  696. #endif // CONFIG_BT_CONTROLLER_LOG_ENABLED
  697. ret = ble_controller_init(cfg);
  698. if (ret != ESP_OK) {
  699. ESP_LOGW(NIMBLE_PORT_LOG_TAG, "ble_controller_init failed %d", ret);
  700. goto modem_deint;
  701. }
  702. esp_ble_change_rtc_freq(slow_clk_freq);
  703. ble_controller_scan_duplicate_config();
  704. ret = os_msys_init();
  705. if (ret != ESP_OK) {
  706. ESP_LOGW(NIMBLE_PORT_LOG_TAG, "msys_init failed %d", ret);
  707. goto free_controller;
  708. }
  709. ret = controller_sleep_init();
  710. if (ret != ESP_OK) {
  711. ESP_LOGW(NIMBLE_PORT_LOG_TAG, "controller_sleep_init failed %d", ret);
  712. goto free_controller;
  713. }
  714. ESP_ERROR_CHECK(esp_read_mac((uint8_t *)mac, ESP_MAC_BT));
  715. swap_in_place(mac, 6);
  716. esp_ble_ll_set_public_addr(mac);
  717. ble_controller_status = ESP_BT_CONTROLLER_STATUS_INITED;
  718. ble_hci_trans_cfg_hs((ble_hci_trans_rx_cmd_fn *)ble_hci_unregistered_hook,NULL,
  719. (ble_hci_trans_rx_acl_fn *)ble_hci_unregistered_hook,NULL);
  720. return ESP_OK;
  721. free_controller:
  722. controller_sleep_deinit();
  723. os_msys_deinit();
  724. ble_controller_deinit();
  725. modem_deint:
  726. #if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
  727. ble_log_deinit_async();
  728. #endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
  729. esp_phy_modem_deinit();
  730. modem_clock_deselect_lp_clock_source(PERIPH_BT_MODULE);
  731. modem_clock_module_disable(PERIPH_BT_MODULE);
  732. #if CONFIG_BT_NIMBLE_ENABLED
  733. ble_npl_eventq_deinit(nimble_port_get_dflt_eventq());
  734. #endif // CONFIG_BT_NIMBLE_ENABLED
  735. free_mem:
  736. npl_freertos_mempool_deinit();
  737. esp_unregister_npl_funcs();
  738. npl_freertos_funcs_deinit();
  739. esp_unregister_ext_funcs();
  740. return ret;
  741. }
  742. esp_err_t esp_bt_controller_deinit(void)
  743. {
  744. if ((ble_controller_status < ESP_BT_CONTROLLER_STATUS_INITED) ||
  745. (ble_controller_status >= ESP_BT_CONTROLLER_STATUS_ENABLED)) {
  746. ESP_LOGW(NIMBLE_PORT_LOG_TAG, "invalid controller state");
  747. return ESP_FAIL;
  748. }
  749. controller_sleep_deinit();
  750. os_msys_deinit();
  751. esp_phy_modem_deinit();
  752. modem_clock_deselect_lp_clock_source(PERIPH_BT_MODULE);
  753. modem_clock_module_disable(PERIPH_BT_MODULE);
  754. #if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
  755. ble_log_deinit_async();
  756. #endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
  757. ble_controller_deinit();
  758. #if CONFIG_BT_NIMBLE_ENABLED
  759. /* De-initialize default event queue */
  760. ble_npl_eventq_deinit(nimble_port_get_dflt_eventq());
  761. #endif // CONFIG_BT_NIMBLE_ENABLED
  762. esp_unregister_npl_funcs();
  763. esp_unregister_ext_funcs();
  764. /* De-initialize npl functions */
  765. npl_freertos_funcs_deinit();
  766. npl_freertos_mempool_deinit();
  767. ble_controller_status = ESP_BT_CONTROLLER_STATUS_IDLE;
  768. return ESP_OK;
  769. }
  770. esp_err_t esp_bt_controller_enable(esp_bt_mode_t mode)
  771. {
  772. esp_err_t ret = ESP_OK;
  773. if (mode != ESP_BT_MODE_BLE) {
  774. ESP_LOGW(NIMBLE_PORT_LOG_TAG, "invalid controller mode");
  775. return ESP_FAIL;
  776. }
  777. if (ble_controller_status != ESP_BT_CONTROLLER_STATUS_INITED) {
  778. ESP_LOGW(NIMBLE_PORT_LOG_TAG, "invalid controller state");
  779. return ESP_FAIL;
  780. }
  781. if (!s_ble_active) {
  782. #if CONFIG_PM_ENABLE
  783. esp_pm_lock_acquire(s_pm_lock);
  784. #endif // CONFIG_PM_ENABLE
  785. esp_phy_enable(PHY_MODEM_BT);
  786. esp_btbb_enable();
  787. s_ble_active = true;
  788. }
  789. #if CONFIG_SW_COEXIST_ENABLE
  790. coex_enable();
  791. #endif // CONFIG_SW_COEXIST_ENABLE
  792. if (ble_controller_enable(mode) != 0) {
  793. ret = ESP_FAIL;
  794. goto error;
  795. }
  796. ble_controller_status = ESP_BT_CONTROLLER_STATUS_ENABLED;
  797. return ESP_OK;
  798. error:
  799. #if CONFIG_SW_COEXIST_ENABLE
  800. coex_disable();
  801. #endif
  802. if (s_ble_active) {
  803. esp_btbb_disable();
  804. esp_phy_disable(PHY_MODEM_BT);
  805. #if CONFIG_PM_ENABLE
  806. esp_pm_lock_release(s_pm_lock);
  807. #endif // CONFIG_PM_ENABLE
  808. s_ble_active = false;
  809. }
  810. return ret;
  811. }
  812. esp_err_t esp_bt_controller_disable(void)
  813. {
  814. if (ble_controller_status < ESP_BT_CONTROLLER_STATUS_ENABLED) {
  815. ESP_LOGW(NIMBLE_PORT_LOG_TAG, "invalid controller state");
  816. return ESP_FAIL;
  817. }
  818. if (ble_controller_disable() != 0) {
  819. return ESP_FAIL;
  820. }
  821. #if CONFIG_SW_COEXIST_ENABLE
  822. coex_disable();
  823. #endif
  824. if (s_ble_active) {
  825. esp_btbb_disable();
  826. esp_phy_disable(PHY_MODEM_BT);
  827. #if CONFIG_PM_ENABLE
  828. esp_pm_lock_release(s_pm_lock);
  829. #endif // CONFIG_PM_ENABLE
  830. s_ble_active = false;
  831. } else {
  832. #if CONFIG_FREERTOS_USE_TICKLESS_IDLE
  833. /* Avoid consecutive backup of register cause assertion */
  834. sleep_retention_module_deinit();
  835. #endif // CONFIG_FREERTOS_USE_TICKLESS_IDLE
  836. }
  837. ble_controller_status = ESP_BT_CONTROLLER_STATUS_INITED;
  838. return ESP_OK;
  839. }
  840. esp_err_t esp_bt_controller_mem_release(esp_bt_mode_t mode)
  841. {
  842. ESP_LOGD(NIMBLE_PORT_LOG_TAG, "%s not implemented, return OK", __func__);
  843. return ESP_OK;
  844. }
  845. static esp_err_t try_heap_caps_add_region(intptr_t start, intptr_t end)
  846. {
  847. int ret = heap_caps_add_region(start, end);
  848. /* heap_caps_add_region() returns ESP_ERR_INVALID_SIZE if the memory region is
  849. * is too small to fit a heap. This cannot be termed as a fatal error and hence
  850. * we replace it by ESP_OK
  851. */
  852. if (ret == ESP_ERR_INVALID_SIZE) {
  853. return ESP_OK;
  854. }
  855. return ret;
  856. }
  857. esp_err_t esp_bt_mem_release(esp_bt_mode_t mode)
  858. {
  859. intptr_t mem_start, mem_end;
  860. if (mode & ESP_BT_MODE_BLE) {
  861. /* If the addresses of btdm .bss and bt .bss are consecutive,
  862. * they are registered in the system heap as a piece of memory
  863. */
  864. if(_bt_bss_end == _bt_controller_bss_start) {
  865. mem_start = (intptr_t)&_bt_bss_start;
  866. mem_end = (intptr_t)&_bt_controller_bss_end;
  867. if (mem_start != mem_end) {
  868. ESP_LOGD(NIMBLE_PORT_LOG_TAG, "Release BSS [0x%08x] - [0x%08x], len %d",
  869. mem_start, mem_end, mem_end - mem_start);
  870. ESP_ERROR_CHECK(try_heap_caps_add_region(mem_start, mem_end));
  871. }
  872. } else {
  873. mem_start = (intptr_t)&_bt_bss_start;
  874. mem_end = (intptr_t)&_bt_bss_end;
  875. if (mem_start != mem_end) {
  876. ESP_LOGD(NIMBLE_PORT_LOG_TAG, "Release BT BSS [0x%08x] - [0x%08x], len %d",
  877. mem_start, mem_end, mem_end - mem_start);
  878. ESP_ERROR_CHECK(try_heap_caps_add_region(mem_start, mem_end));
  879. }
  880. mem_start = (intptr_t)&_bt_controller_bss_start;
  881. mem_end = (intptr_t)&_bt_controller_bss_end;
  882. if (mem_start != mem_end) {
  883. ESP_LOGD(NIMBLE_PORT_LOG_TAG, "Release Controller BSS [0x%08x] - [0x%08x], len %d",
  884. mem_start, mem_end, mem_end - mem_start);
  885. ESP_ERROR_CHECK(try_heap_caps_add_region(mem_start, mem_end));
  886. }
  887. }
  888. /* If the addresses of btdm .data and bt .data are consecutive,
  889. * they are registered in the system heap as a piece of memory
  890. */
  891. if(_bt_data_end == _bt_controller_data_start) {
  892. mem_start = (intptr_t)&_bt_data_start;
  893. mem_end = (intptr_t)&_bt_controller_data_end;
  894. if (mem_start != mem_end) {
  895. ESP_LOGD(NIMBLE_PORT_LOG_TAG, "Release data [0x%08x] - [0x%08x], len %d",
  896. mem_start, mem_end, mem_end - mem_start);
  897. ESP_ERROR_CHECK(try_heap_caps_add_region(mem_start, mem_end));
  898. }
  899. } else {
  900. mem_start = (intptr_t)&_bt_data_start;
  901. mem_end = (intptr_t)&_bt_data_end;
  902. if (mem_start != mem_end) {
  903. ESP_LOGD(NIMBLE_PORT_LOG_TAG, "Release BT Data [0x%08x] - [0x%08x], len %d",
  904. mem_start, mem_end, mem_end - mem_start);
  905. ESP_ERROR_CHECK(try_heap_caps_add_region(mem_start, mem_end));
  906. }
  907. mem_start = (intptr_t)&_bt_controller_data_start;
  908. mem_end = (intptr_t)&_bt_controller_data_end;
  909. if (mem_start != mem_end) {
  910. ESP_LOGD(NIMBLE_PORT_LOG_TAG, "Release Controller Data [0x%08x] - [0x%08x], len %d",
  911. mem_start, mem_end, mem_end - mem_start);
  912. ESP_ERROR_CHECK(try_heap_caps_add_region(mem_start, mem_end));
  913. }
  914. }
  915. }
  916. return ESP_OK;
  917. }
  918. esp_bt_controller_status_t esp_bt_controller_get_status(void)
  919. {
  920. return ble_controller_status;
  921. }
  922. esp_err_t esp_ble_tx_power_set(esp_ble_power_type_t power_type, esp_power_level_t power_level)
  923. {
  924. esp_err_t stat = ESP_FAIL;
  925. switch (power_type) {
  926. case ESP_BLE_PWR_TYPE_DEFAULT:
  927. case ESP_BLE_PWR_TYPE_ADV:
  928. case ESP_BLE_PWR_TYPE_SCAN:
  929. if (ble_txpwr_set(ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT, 0, power_level) == 0) {
  930. stat = ESP_OK;
  931. }
  932. break;
  933. case ESP_BLE_PWR_TYPE_CONN_HDL0:
  934. case ESP_BLE_PWR_TYPE_CONN_HDL1:
  935. case ESP_BLE_PWR_TYPE_CONN_HDL2:
  936. case ESP_BLE_PWR_TYPE_CONN_HDL3:
  937. case ESP_BLE_PWR_TYPE_CONN_HDL4:
  938. case ESP_BLE_PWR_TYPE_CONN_HDL5:
  939. case ESP_BLE_PWR_TYPE_CONN_HDL6:
  940. case ESP_BLE_PWR_TYPE_CONN_HDL7:
  941. case ESP_BLE_PWR_TYPE_CONN_HDL8:
  942. if (ble_txpwr_set(ESP_BLE_ENHANCED_PWR_TYPE_CONN, power_type, power_level) == 0) {
  943. stat = ESP_OK;
  944. }
  945. break;
  946. default:
  947. stat = ESP_ERR_NOT_SUPPORTED;
  948. break;
  949. }
  950. return stat;
  951. }
  952. esp_err_t esp_ble_tx_power_set_enhanced(esp_ble_enhanced_power_type_t power_type, uint16_t handle,
  953. esp_power_level_t power_level)
  954. {
  955. esp_err_t stat = ESP_FAIL;
  956. switch (power_type) {
  957. case ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT:
  958. case ESP_BLE_ENHANCED_PWR_TYPE_SCAN:
  959. case ESP_BLE_ENHANCED_PWR_TYPE_INIT:
  960. if (ble_txpwr_set(ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT, 0, power_level) == 0) {
  961. stat = ESP_OK;
  962. }
  963. break;
  964. case ESP_BLE_ENHANCED_PWR_TYPE_ADV:
  965. case ESP_BLE_ENHANCED_PWR_TYPE_CONN:
  966. if (ble_txpwr_set(power_type, handle, power_level) == 0) {
  967. stat = ESP_OK;
  968. }
  969. break;
  970. default:
  971. stat = ESP_ERR_NOT_SUPPORTED;
  972. break;
  973. }
  974. return stat;
  975. }
  976. esp_power_level_t esp_ble_tx_power_get(esp_ble_power_type_t power_type)
  977. {
  978. int tx_level = 0;
  979. switch (power_type) {
  980. case ESP_BLE_PWR_TYPE_ADV:
  981. case ESP_BLE_PWR_TYPE_SCAN:
  982. case ESP_BLE_PWR_TYPE_DEFAULT:
  983. tx_level = ble_txpwr_get(ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT, 0);
  984. break;
  985. case ESP_BLE_PWR_TYPE_CONN_HDL0:
  986. case ESP_BLE_PWR_TYPE_CONN_HDL1:
  987. case ESP_BLE_PWR_TYPE_CONN_HDL2:
  988. case ESP_BLE_PWR_TYPE_CONN_HDL3:
  989. case ESP_BLE_PWR_TYPE_CONN_HDL4:
  990. case ESP_BLE_PWR_TYPE_CONN_HDL5:
  991. case ESP_BLE_PWR_TYPE_CONN_HDL6:
  992. case ESP_BLE_PWR_TYPE_CONN_HDL7:
  993. case ESP_BLE_PWR_TYPE_CONN_HDL8:
  994. tx_level = ble_txpwr_get(ESP_BLE_ENHANCED_PWR_TYPE_CONN, power_type);
  995. break;
  996. default:
  997. return ESP_PWR_LVL_INVALID;
  998. }
  999. if (tx_level < 0) {
  1000. return ESP_PWR_LVL_INVALID;
  1001. }
  1002. return (esp_power_level_t)tx_level;
  1003. }
  1004. esp_power_level_t esp_ble_tx_power_get_enhanced(esp_ble_enhanced_power_type_t power_type,
  1005. uint16_t handle)
  1006. {
  1007. int tx_level = 0;
  1008. switch (power_type) {
  1009. case ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT:
  1010. case ESP_BLE_ENHANCED_PWR_TYPE_SCAN:
  1011. case ESP_BLE_ENHANCED_PWR_TYPE_INIT:
  1012. tx_level = ble_txpwr_get(ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT, 0);
  1013. break;
  1014. case ESP_BLE_ENHANCED_PWR_TYPE_ADV:
  1015. case ESP_BLE_ENHANCED_PWR_TYPE_CONN:
  1016. tx_level = ble_txpwr_get(power_type, handle);
  1017. break;
  1018. default:
  1019. return ESP_PWR_LVL_INVALID;
  1020. }
  1021. if (tx_level < 0) {
  1022. return ESP_PWR_LVL_INVALID;
  1023. }
  1024. return (esp_power_level_t)tx_level;
  1025. }
  1026. #if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
  1027. static void esp_bt_controller_log_interface(uint32_t len, const uint8_t *addr, bool end)
  1028. {
  1029. for (int i = 0; i < len; i++) {
  1030. esp_rom_printf("%02x ", addr[i]);
  1031. }
  1032. if (end) {
  1033. esp_rom_printf("\n");
  1034. }
  1035. }
  1036. void esp_ble_controller_log_dump_all(bool output)
  1037. {
  1038. portMUX_TYPE spinlock;
  1039. portENTER_CRITICAL_SAFE(&spinlock);
  1040. BT_ASSERT_PRINT("\r\n[DUMP_START:");
  1041. ble_log_async_output_dump_all(output);
  1042. BT_ASSERT_PRINT("]\r\n");
  1043. portEXIT_CRITICAL_SAFE(&spinlock);
  1044. }
  1045. #endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
  1046. #if (!CONFIG_BT_NIMBLE_ENABLED) && (CONFIG_BT_CONTROLLER_ENABLED == true)
  1047. #define BLE_SM_KEY_ERR 0x17
  1048. #if CONFIG_BT_LE_CRYPTO_STACK_MBEDTLS
  1049. #include "mbedtls/aes.h"
  1050. #if CONFIG_BT_LE_SM_SC
  1051. #include "mbedtls/cipher.h"
  1052. #include "mbedtls/entropy.h"
  1053. #include "mbedtls/ctr_drbg.h"
  1054. #include "mbedtls/cmac.h"
  1055. #include "mbedtls/ecdh.h"
  1056. #include "mbedtls/ecp.h"
  1057. #endif // CONFIG_BT_LE_SM_SC
  1058. #else
  1059. #include "tinycrypt/aes.h"
  1060. #include "tinycrypt/constants.h"
  1061. #include "tinycrypt/utils.h"
  1062. #if CONFIG_BT_LE_SM_SC
  1063. #include "tinycrypt/cmac_mode.h"
  1064. #include "tinycrypt/ecc_dh.h"
  1065. #endif // CONFIG_BT_LE_SM_SC
  1066. #endif // CONFIG_BT_LE_CRYPTO_STACK_MBEDTLS
  1067. #if CONFIG_BT_LE_CRYPTO_STACK_MBEDTLS
  1068. #if CONFIG_BT_LE_SM_SC
  1069. static mbedtls_ecp_keypair keypair;
  1070. #endif // CONFIG_BT_LE_SM_SC
  1071. #endif// CONFIG_BT_LE_CRYPTO_STACK_MBEDTLS
  1072. int ble_sm_alg_gen_dhkey(const uint8_t *peer_pub_key_x, const uint8_t *peer_pub_key_y,
  1073. const uint8_t *our_priv_key, uint8_t *out_dhkey)
  1074. {
  1075. uint8_t dh[32];
  1076. uint8_t pk[64];
  1077. uint8_t priv[32];
  1078. int rc = BLE_SM_KEY_ERR;
  1079. swap_buf(pk, peer_pub_key_x, 32);
  1080. swap_buf(&pk[32], peer_pub_key_y, 32);
  1081. swap_buf(priv, our_priv_key, 32);
  1082. #if CONFIG_BT_LE_CRYPTO_STACK_MBEDTLS
  1083. struct mbedtls_ecp_point pt = {0}, Q = {0};
  1084. mbedtls_mpi z = {0}, d = {0};
  1085. mbedtls_ctr_drbg_context ctr_drbg = {0};
  1086. mbedtls_entropy_context entropy = {0};
  1087. uint8_t pub[65] = {0};
  1088. /* Hardcoded first byte of pub key for MBEDTLS_ECP_PF_UNCOMPRESSED */
  1089. pub[0] = 0x04;
  1090. memcpy(&pub[1], pk, 64);
  1091. /* Initialize the required structures here */
  1092. mbedtls_ecp_point_init(&pt);
  1093. mbedtls_ecp_point_init(&Q);
  1094. mbedtls_ctr_drbg_init(&ctr_drbg);
  1095. mbedtls_entropy_init(&entropy);
  1096. mbedtls_mpi_init(&d);
  1097. mbedtls_mpi_init(&z);
  1098. /* Below 3 steps are to validate public key on curve secp256r1 */
  1099. if (mbedtls_ecp_group_load(&keypair.MBEDTLS_PRIVATE(grp), MBEDTLS_ECP_DP_SECP256R1) != 0) {
  1100. goto exit;
  1101. }
  1102. if (mbedtls_ecp_point_read_binary(&keypair.MBEDTLS_PRIVATE(grp), &pt, pub, 65) != 0) {
  1103. goto exit;
  1104. }
  1105. if (mbedtls_ecp_check_pubkey(&keypair.MBEDTLS_PRIVATE(grp), &pt) != 0) {
  1106. goto exit;
  1107. }
  1108. /* Set PRNG */
  1109. if ((rc = mbedtls_ctr_drbg_seed(&ctr_drbg, mbedtls_entropy_func, &entropy,
  1110. NULL, 0)) != 0) {
  1111. goto exit;
  1112. }
  1113. /* Prepare point Q from pub key */
  1114. if (mbedtls_ecp_point_read_binary(&keypair.MBEDTLS_PRIVATE(grp), &Q, pub, 65) != 0) {
  1115. goto exit;
  1116. }
  1117. if (mbedtls_mpi_read_binary(&d, priv, 32) != 0) {
  1118. goto exit;
  1119. }
  1120. rc = mbedtls_ecdh_compute_shared(&keypair.MBEDTLS_PRIVATE(grp), &z, &Q, &d,
  1121. mbedtls_ctr_drbg_random, &ctr_drbg);
  1122. if (rc != 0) {
  1123. goto exit;
  1124. }
  1125. rc = mbedtls_mpi_write_binary(&z, dh, 32);
  1126. if (rc != 0) {
  1127. goto exit;
  1128. }
  1129. exit:
  1130. mbedtls_ecp_point_free(&pt);
  1131. mbedtls_mpi_free(&z);
  1132. mbedtls_mpi_free(&d);
  1133. mbedtls_ecp_point_free(&Q);
  1134. mbedtls_entropy_free(&entropy);
  1135. mbedtls_ctr_drbg_free(&ctr_drbg);
  1136. if (rc != 0) {
  1137. return BLE_SM_KEY_ERR;
  1138. }
  1139. #else
  1140. if (uECC_valid_public_key(pk, &curve_secp256r1) < 0) {
  1141. return BLE_SM_KEY_ERR;
  1142. }
  1143. rc = uECC_shared_secret(pk, priv, dh, &curve_secp256r1);
  1144. if (rc == TC_CRYPTO_FAIL) {
  1145. return BLE_SM_KEY_ERR;
  1146. }
  1147. #endif // CONFIG_BT_LE_CRYPTO_STACK_MBEDTLS
  1148. swap_buf(out_dhkey, dh, 32);
  1149. return 0;
  1150. }
  1151. /* based on Core Specification 4.2 Vol 3. Part H 2.3.5.6.1 */
  1152. static const uint8_t ble_sm_alg_dbg_priv_key[32] = {
  1153. 0x3f, 0x49, 0xf6, 0xd4, 0xa3, 0xc5, 0x5f, 0x38, 0x74, 0xc9, 0xb3, 0xe3,
  1154. 0xd2, 0x10, 0x3f, 0x50, 0x4a, 0xff, 0x60, 0x7b, 0xeb, 0x40, 0xb7, 0x99,
  1155. 0x58, 0x99, 0xb8, 0xa6, 0xcd, 0x3c, 0x1a, 0xbd
  1156. };
  1157. #if CONFIG_BT_LE_CRYPTO_STACK_MBEDTLS
  1158. static int mbedtls_gen_keypair(uint8_t *public_key, uint8_t *private_key)
  1159. {
  1160. int rc = BLE_SM_KEY_ERR;
  1161. size_t olen = 0;
  1162. uint8_t pub[65] = {0};
  1163. mbedtls_entropy_context entropy = {0};
  1164. mbedtls_ctr_drbg_context ctr_drbg = {0};
  1165. mbedtls_entropy_init(&entropy);
  1166. mbedtls_ctr_drbg_init(&ctr_drbg);
  1167. mbedtls_ecp_keypair_init(&keypair);
  1168. if ((rc = mbedtls_ctr_drbg_seed(&ctr_drbg, mbedtls_entropy_func, &entropy,
  1169. NULL, 0)) != 0) {
  1170. goto exit;
  1171. }
  1172. if ((rc = mbedtls_ecp_gen_key(MBEDTLS_ECP_DP_SECP256R1, &keypair,
  1173. mbedtls_ctr_drbg_random, &ctr_drbg)) != 0) {
  1174. goto exit;
  1175. }
  1176. if ((rc = mbedtls_mpi_write_binary(&keypair.MBEDTLS_PRIVATE(d), private_key, 32)) != 0) {
  1177. goto exit;
  1178. }
  1179. if ((rc = mbedtls_ecp_point_write_binary(&keypair.MBEDTLS_PRIVATE(grp),
  1180. &keypair.MBEDTLS_PRIVATE(Q),
  1181. MBEDTLS_ECP_PF_UNCOMPRESSED,
  1182. &olen, pub, 65)) != 0) {
  1183. goto exit;
  1184. }
  1185. memcpy(public_key, &pub[1], 64);
  1186. exit:
  1187. mbedtls_ctr_drbg_free(&ctr_drbg);
  1188. mbedtls_entropy_free(&entropy);
  1189. if (rc != 0) {
  1190. mbedtls_ecp_keypair_free(&keypair);
  1191. return BLE_SM_KEY_ERR;
  1192. }
  1193. return 0;
  1194. }
  1195. #endif // CONFIG_BT_LE_CRYPTO_STACK_MBEDTLS
  1196. /**
  1197. * pub: 64 bytes
  1198. * priv: 32 bytes
  1199. */
  1200. int ble_sm_alg_gen_key_pair(uint8_t *pub, uint8_t *priv)
  1201. {
  1202. #if CONFIG_BT_LE_SM_SC_DEBUG_KEYS
  1203. swap_buf(pub, ble_sm_alg_dbg_pub_key, 32);
  1204. swap_buf(&pub[32], &ble_sm_alg_dbg_pub_key[32], 32);
  1205. swap_buf(priv, ble_sm_alg_dbg_priv_key, 32);
  1206. #else
  1207. uint8_t pk[64];
  1208. do {
  1209. #if CONFIG_BT_LE_CRYPTO_STACK_MBEDTLS
  1210. if (mbedtls_gen_keypair(pk, priv) != 0) {
  1211. return BLE_SM_KEY_ERR;
  1212. }
  1213. #else
  1214. if (uECC_make_key(pk, priv, &curve_secp256r1) != TC_CRYPTO_SUCCESS) {
  1215. return BLE_SM_KEY_ERR;
  1216. }
  1217. #endif // CONFIG_BT_LE_CRYPTO_STACK_MBEDTLS
  1218. /* Make sure generated key isn't debug key. */
  1219. } while (memcmp(priv, ble_sm_alg_dbg_priv_key, 32) == 0);
  1220. swap_buf(pub, pk, 32);
  1221. swap_buf(&pub[32], &pk[32], 32);
  1222. swap_in_place(priv, 32);
  1223. #endif // CONFIG_BT_LE_SM_SC_DEBUG_KEYS
  1224. return 0;
  1225. }
  1226. #endif // (!CONFIG_BT_NIMBLE_ENABLED) && (CONFIG_BT_CONTROLLER_ENABLED == true)