timer_legacy.c 25 KB

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  1. /*
  2. * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. */
  6. #include <string.h>
  7. #include "esp_log.h"
  8. #include "esp_err.h"
  9. #include "esp_check.h"
  10. #include "esp_intr_alloc.h"
  11. #include "freertos/FreeRTOS.h"
  12. #include "driver/timer_types_legacy.h"
  13. #include "hal/timer_hal.h"
  14. #include "hal/timer_ll.h"
  15. #include "hal/check.h"
  16. #include "soc/timer_periph.h"
  17. #include "esp_clk_tree.h"
  18. #include "soc/timer_group_reg.h"
  19. #include "esp_private/periph_ctrl.h"
  20. static const char *TIMER_TAG = "timer_group";
  21. #define TIMER_GROUP_NUM_ERROR "TIMER GROUP NUM ERROR"
  22. #define TIMER_NUM_ERROR "HW TIMER NUM ERROR"
  23. #define TIMER_PARAM_ADDR_ERROR "HW TIMER PARAM ADDR ERROR"
  24. #define TIMER_NEVER_INIT_ERROR "HW TIMER NEVER INIT ERROR"
  25. #define TIMER_COUNT_DIR_ERROR "HW TIMER COUNTER DIR ERROR"
  26. #define TIMER_AUTORELOAD_ERROR "HW TIMER AUTORELOAD ERROR"
  27. #define TIMER_SCALE_ERROR "HW TIMER SCALE ERROR"
  28. #define TIMER_ALARM_ERROR "HW TIMER ALARM ERROR"
  29. #define DIVIDER_RANGE_ERROR "HW TIMER divider outside of [2, 65536] range error"
  30. #define TIMER_ENTER_CRITICAL(mux) portENTER_CRITICAL_SAFE(mux);
  31. #define TIMER_EXIT_CRITICAL(mux) portEXIT_CRITICAL_SAFE(mux);
  32. #if SOC_PERIPH_CLK_CTRL_SHARED
  33. #define GPTIMER_CLOCK_SRC_ATOMIC() PERIPH_RCC_ATOMIC()
  34. #else
  35. #define GPTIMER_CLOCK_SRC_ATOMIC()
  36. #endif
  37. typedef struct {
  38. timer_isr_t fn; /*!< isr function */
  39. void *args; /*!< isr function args */
  40. timer_isr_handle_t timer_isr_handle; /*!< interrupt handle */
  41. timer_group_t isr_timer_group; /*!< timer group of interrupt triggered */
  42. } timer_isr_func_t;
  43. typedef struct {
  44. timer_hal_context_t hal;
  45. timer_isr_func_t timer_isr_fun;
  46. timer_src_clk_t clk_src;
  47. gptimer_count_direction_t direction;
  48. uint32_t divider;
  49. uint64_t alarm_value;
  50. bool alarm_en;
  51. bool auto_reload_en;
  52. bool counter_en;
  53. } timer_obj_t;
  54. static timer_obj_t *p_timer_obj[TIMER_GROUP_MAX][TIMER_MAX] = {0};
  55. static portMUX_TYPE timer_spinlock[TIMER_GROUP_MAX] = { [0 ... TIMER_GROUP_MAX - 1] = portMUX_INITIALIZER_UNLOCKED, };
  56. esp_err_t timer_get_counter_value(timer_group_t group_num, timer_idx_t timer_num, uint64_t *timer_val)
  57. {
  58. ESP_RETURN_ON_FALSE(group_num < TIMER_GROUP_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_GROUP_NUM_ERROR);
  59. ESP_RETURN_ON_FALSE(timer_num < TIMER_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_NUM_ERROR);
  60. ESP_RETURN_ON_FALSE(timer_val != NULL, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_PARAM_ADDR_ERROR);
  61. ESP_RETURN_ON_FALSE(p_timer_obj[group_num][timer_num] != NULL, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_NEVER_INIT_ERROR);
  62. TIMER_ENTER_CRITICAL(&timer_spinlock[group_num]);
  63. *timer_val = timer_hal_capture_and_get_counter_value(&p_timer_obj[group_num][timer_num]->hal);
  64. TIMER_EXIT_CRITICAL(&timer_spinlock[group_num]);
  65. return ESP_OK;
  66. }
  67. esp_err_t timer_get_counter_time_sec(timer_group_t group_num, timer_idx_t timer_num, double *time)
  68. {
  69. ESP_RETURN_ON_FALSE(group_num < TIMER_GROUP_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_GROUP_NUM_ERROR);
  70. ESP_RETURN_ON_FALSE(timer_num < TIMER_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_NUM_ERROR);
  71. ESP_RETURN_ON_FALSE(time != NULL, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_PARAM_ADDR_ERROR);
  72. ESP_RETURN_ON_FALSE(p_timer_obj[group_num][timer_num] != NULL, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_NEVER_INIT_ERROR);
  73. uint64_t timer_val = timer_hal_capture_and_get_counter_value(&p_timer_obj[group_num][timer_num]->hal);
  74. uint32_t div = p_timer_obj[group_num][timer_num]->divider;
  75. // get clock source frequency
  76. uint32_t counter_src_hz = 0;
  77. ESP_RETURN_ON_ERROR(esp_clk_tree_src_get_freq_hz((soc_module_clk_t)p_timer_obj[group_num][timer_num]->clk_src,
  78. ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &counter_src_hz),
  79. TIMER_TAG, "get clock source frequency failed");
  80. *time = (double)timer_val * div / counter_src_hz;
  81. return ESP_OK;
  82. }
  83. esp_err_t timer_set_counter_value(timer_group_t group_num, timer_idx_t timer_num, uint64_t load_val)
  84. {
  85. ESP_RETURN_ON_FALSE(group_num < TIMER_GROUP_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_GROUP_NUM_ERROR);
  86. ESP_RETURN_ON_FALSE(timer_num < TIMER_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_NUM_ERROR);
  87. ESP_RETURN_ON_FALSE(p_timer_obj[group_num][timer_num] != NULL, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_NEVER_INIT_ERROR);
  88. TIMER_ENTER_CRITICAL(&timer_spinlock[group_num]);
  89. timer_hal_set_counter_value(&(p_timer_obj[group_num][timer_num]->hal), load_val);
  90. TIMER_EXIT_CRITICAL(&timer_spinlock[group_num]);
  91. return ESP_OK;
  92. }
  93. esp_err_t timer_start(timer_group_t group_num, timer_idx_t timer_num)
  94. {
  95. ESP_RETURN_ON_FALSE(group_num < TIMER_GROUP_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_GROUP_NUM_ERROR);
  96. ESP_RETURN_ON_FALSE(timer_num < TIMER_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_NUM_ERROR);
  97. ESP_RETURN_ON_FALSE(p_timer_obj[group_num][timer_num] != NULL, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_NEVER_INIT_ERROR);
  98. TIMER_ENTER_CRITICAL(&timer_spinlock[group_num]);
  99. timer_ll_enable_counter(p_timer_obj[group_num][timer_num]->hal.dev, timer_num, true);
  100. p_timer_obj[group_num][timer_num]->counter_en = true;
  101. TIMER_EXIT_CRITICAL(&timer_spinlock[group_num]);
  102. return ESP_OK;
  103. }
  104. esp_err_t timer_pause(timer_group_t group_num, timer_idx_t timer_num)
  105. {
  106. ESP_RETURN_ON_FALSE(group_num < TIMER_GROUP_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_GROUP_NUM_ERROR);
  107. ESP_RETURN_ON_FALSE(timer_num < TIMER_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_NUM_ERROR);
  108. ESP_RETURN_ON_FALSE(p_timer_obj[group_num][timer_num] != NULL, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_NEVER_INIT_ERROR);
  109. TIMER_ENTER_CRITICAL(&timer_spinlock[group_num]);
  110. timer_ll_enable_counter(p_timer_obj[group_num][timer_num]->hal.dev, timer_num, false);
  111. p_timer_obj[group_num][timer_num]->counter_en = false;
  112. TIMER_EXIT_CRITICAL(&timer_spinlock[group_num]);
  113. return ESP_OK;
  114. }
  115. esp_err_t timer_set_counter_mode(timer_group_t group_num, timer_idx_t timer_num, timer_count_dir_t counter_dir)
  116. {
  117. ESP_RETURN_ON_FALSE(group_num < TIMER_GROUP_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_GROUP_NUM_ERROR);
  118. ESP_RETURN_ON_FALSE(timer_num < TIMER_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_NUM_ERROR);
  119. ESP_RETURN_ON_FALSE(counter_dir < TIMER_COUNT_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_COUNT_DIR_ERROR);
  120. ESP_RETURN_ON_FALSE(p_timer_obj[group_num][timer_num] != NULL, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_NEVER_INIT_ERROR);
  121. TIMER_ENTER_CRITICAL(&timer_spinlock[group_num]);
  122. timer_ll_set_count_direction(p_timer_obj[group_num][timer_num]->hal.dev, timer_num, counter_dir);
  123. TIMER_EXIT_CRITICAL(&timer_spinlock[group_num]);
  124. return ESP_OK;
  125. }
  126. esp_err_t timer_set_auto_reload(timer_group_t group_num, timer_idx_t timer_num, timer_autoreload_t reload)
  127. {
  128. ESP_RETURN_ON_FALSE(group_num < TIMER_GROUP_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_GROUP_NUM_ERROR);
  129. ESP_RETURN_ON_FALSE(timer_num < TIMER_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_NUM_ERROR);
  130. ESP_RETURN_ON_FALSE(reload < TIMER_AUTORELOAD_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_AUTORELOAD_ERROR);
  131. ESP_RETURN_ON_FALSE(p_timer_obj[group_num][timer_num] != NULL, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_NEVER_INIT_ERROR);
  132. TIMER_ENTER_CRITICAL(&timer_spinlock[group_num]);
  133. timer_ll_enable_auto_reload(p_timer_obj[group_num][timer_num]->hal.dev, timer_num, reload);
  134. p_timer_obj[group_num][timer_num]->auto_reload_en = reload;
  135. TIMER_EXIT_CRITICAL(&timer_spinlock[group_num]);
  136. return ESP_OK;
  137. }
  138. esp_err_t timer_set_divider(timer_group_t group_num, timer_idx_t timer_num, uint32_t divider)
  139. {
  140. ESP_RETURN_ON_FALSE(group_num < TIMER_GROUP_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_GROUP_NUM_ERROR);
  141. ESP_RETURN_ON_FALSE(timer_num < TIMER_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_NUM_ERROR);
  142. ESP_RETURN_ON_FALSE(divider > 1 && divider < 65537, ESP_ERR_INVALID_ARG, TIMER_TAG, DIVIDER_RANGE_ERROR);
  143. ESP_RETURN_ON_FALSE(p_timer_obj[group_num][timer_num] != NULL, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_NEVER_INIT_ERROR);
  144. TIMER_ENTER_CRITICAL(&timer_spinlock[group_num]);
  145. timer_ll_set_clock_prescale(p_timer_obj[group_num][timer_num]->hal.dev, timer_num, divider);
  146. p_timer_obj[group_num][timer_num]->divider = divider;
  147. TIMER_EXIT_CRITICAL(&timer_spinlock[group_num]);
  148. return ESP_OK;
  149. }
  150. esp_err_t timer_set_alarm_value(timer_group_t group_num, timer_idx_t timer_num, uint64_t alarm_value)
  151. {
  152. ESP_RETURN_ON_FALSE(group_num < TIMER_GROUP_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_GROUP_NUM_ERROR);
  153. ESP_RETURN_ON_FALSE(timer_num < TIMER_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_NUM_ERROR);
  154. ESP_RETURN_ON_FALSE(p_timer_obj[group_num][timer_num] != NULL, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_NEVER_INIT_ERROR);
  155. TIMER_ENTER_CRITICAL(&timer_spinlock[group_num]);
  156. timer_ll_set_alarm_value(p_timer_obj[group_num][timer_num]->hal.dev, timer_num, alarm_value);
  157. p_timer_obj[group_num][timer_num]->alarm_value = alarm_value;
  158. TIMER_EXIT_CRITICAL(&timer_spinlock[group_num]);
  159. return ESP_OK;
  160. }
  161. esp_err_t timer_get_alarm_value(timer_group_t group_num, timer_idx_t timer_num, uint64_t *alarm_value)
  162. {
  163. ESP_RETURN_ON_FALSE(group_num < TIMER_GROUP_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_GROUP_NUM_ERROR);
  164. ESP_RETURN_ON_FALSE(timer_num < TIMER_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_NUM_ERROR);
  165. ESP_RETURN_ON_FALSE(alarm_value != NULL, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_PARAM_ADDR_ERROR);
  166. ESP_RETURN_ON_FALSE(p_timer_obj[group_num][timer_num] != NULL, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_NEVER_INIT_ERROR);
  167. TIMER_ENTER_CRITICAL(&timer_spinlock[group_num]);
  168. *alarm_value = p_timer_obj[group_num][timer_num]->alarm_value;
  169. TIMER_EXIT_CRITICAL(&timer_spinlock[group_num]);
  170. return ESP_OK;
  171. }
  172. esp_err_t timer_set_alarm(timer_group_t group_num, timer_idx_t timer_num, timer_alarm_t alarm_en)
  173. {
  174. ESP_RETURN_ON_FALSE(group_num < TIMER_GROUP_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_GROUP_NUM_ERROR);
  175. ESP_RETURN_ON_FALSE(timer_num < TIMER_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_NUM_ERROR);
  176. ESP_RETURN_ON_FALSE(alarm_en < TIMER_ALARM_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_ALARM_ERROR);
  177. ESP_RETURN_ON_FALSE(p_timer_obj[group_num][timer_num] != NULL, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_NEVER_INIT_ERROR);
  178. TIMER_ENTER_CRITICAL(&timer_spinlock[group_num]);
  179. timer_ll_enable_alarm(p_timer_obj[group_num][timer_num]->hal.dev, timer_num, alarm_en);
  180. TIMER_EXIT_CRITICAL(&timer_spinlock[group_num]);
  181. return ESP_OK;
  182. }
  183. static void IRAM_ATTR timer_isr_default(void *arg)
  184. {
  185. bool is_awoken = false;
  186. timer_obj_t *timer_obj = (timer_obj_t *)arg;
  187. if (timer_obj == NULL || timer_obj->timer_isr_fun.fn == NULL) {
  188. return;
  189. }
  190. uint32_t timer_id = timer_obj->hal.timer_id;
  191. timer_hal_context_t *hal = &timer_obj->hal;
  192. TIMER_ENTER_CRITICAL(&timer_spinlock[timer_obj->timer_isr_fun.isr_timer_group]);
  193. uint32_t intr_status = timer_ll_get_intr_status(hal->dev);
  194. uint64_t old_alarm_value = timer_obj->alarm_value;
  195. if (intr_status & TIMER_LL_EVENT_ALARM(timer_id)) {
  196. // Clear interrupt status
  197. timer_ll_clear_intr_status(hal->dev, TIMER_LL_EVENT_ALARM(timer_id));
  198. // call user registered callback
  199. is_awoken = timer_obj->timer_isr_fun.fn(timer_obj->timer_isr_fun.args);
  200. // reenable alarm if required
  201. uint64_t new_alarm_value = timer_obj->alarm_value;
  202. bool reenable_alarm = (new_alarm_value != old_alarm_value) || timer_obj->auto_reload_en;
  203. timer_ll_enable_alarm(hal->dev, timer_id, reenable_alarm);
  204. }
  205. TIMER_EXIT_CRITICAL(&timer_spinlock[timer_obj->timer_isr_fun.isr_timer_group]);
  206. if (is_awoken) {
  207. portYIELD_FROM_ISR();
  208. }
  209. }
  210. esp_err_t timer_enable_intr(timer_group_t group_num, timer_idx_t timer_num)
  211. {
  212. ESP_RETURN_ON_FALSE(group_num < TIMER_GROUP_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_GROUP_NUM_ERROR);
  213. ESP_RETURN_ON_FALSE(timer_num < TIMER_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_NUM_ERROR);
  214. ESP_RETURN_ON_FALSE(p_timer_obj[group_num][timer_num] != NULL, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_NEVER_INIT_ERROR);
  215. TIMER_ENTER_CRITICAL(&timer_spinlock[group_num]);
  216. timer_ll_enable_intr(p_timer_obj[group_num][timer_num]->hal.dev, TIMER_LL_EVENT_ALARM(timer_num), true);
  217. TIMER_EXIT_CRITICAL(&timer_spinlock[group_num]);
  218. return ESP_OK;
  219. }
  220. esp_err_t timer_disable_intr(timer_group_t group_num, timer_idx_t timer_num)
  221. {
  222. ESP_RETURN_ON_FALSE(group_num < TIMER_GROUP_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_GROUP_NUM_ERROR);
  223. ESP_RETURN_ON_FALSE(timer_num < TIMER_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_NUM_ERROR);
  224. ESP_RETURN_ON_FALSE(p_timer_obj[group_num][timer_num] != NULL, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_NEVER_INIT_ERROR);
  225. TIMER_ENTER_CRITICAL(&timer_spinlock[group_num]);
  226. timer_ll_enable_intr(p_timer_obj[group_num][timer_num]->hal.dev, TIMER_LL_EVENT_ALARM(timer_num), false);
  227. TIMER_EXIT_CRITICAL(&timer_spinlock[group_num]);
  228. return ESP_OK;
  229. }
  230. esp_err_t timer_isr_register(timer_group_t group_num, timer_idx_t timer_num,
  231. void (*fn)(void *), void *arg, int intr_alloc_flags, timer_isr_handle_t *handle)
  232. {
  233. ESP_RETURN_ON_FALSE(group_num < TIMER_GROUP_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_GROUP_NUM_ERROR);
  234. ESP_RETURN_ON_FALSE(timer_num < TIMER_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_NUM_ERROR);
  235. ESP_RETURN_ON_FALSE(fn != NULL, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_PARAM_ADDR_ERROR);
  236. ESP_RETURN_ON_FALSE(p_timer_obj[group_num][timer_num] != NULL, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_NEVER_INIT_ERROR);
  237. timer_hal_context_t *hal = &p_timer_obj[group_num][timer_num]->hal;
  238. return esp_intr_alloc_intrstatus(timer_group_periph_signals.groups[group_num].timer_irq_id[timer_num],
  239. intr_alloc_flags,
  240. (uint32_t)timer_ll_get_intr_status_reg(hal->dev),
  241. TIMER_LL_EVENT_ALARM(timer_num), fn, arg, handle);
  242. }
  243. esp_err_t timer_isr_callback_add(timer_group_t group_num, timer_idx_t timer_num, timer_isr_t isr_handler, void *args, int intr_alloc_flags)
  244. {
  245. ESP_RETURN_ON_FALSE(group_num < TIMER_GROUP_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_GROUP_NUM_ERROR);
  246. ESP_RETURN_ON_FALSE(timer_num < TIMER_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_NUM_ERROR);
  247. ESP_RETURN_ON_FALSE(p_timer_obj[group_num][timer_num] != NULL, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_NEVER_INIT_ERROR);
  248. esp_err_t ret = ESP_OK;
  249. timer_disable_intr(group_num, timer_num);
  250. p_timer_obj[group_num][timer_num]->timer_isr_fun.fn = isr_handler;
  251. p_timer_obj[group_num][timer_num]->timer_isr_fun.args = args;
  252. p_timer_obj[group_num][timer_num]->timer_isr_fun.isr_timer_group = group_num;
  253. ret = timer_isr_register(group_num, timer_num, timer_isr_default, (void *)p_timer_obj[group_num][timer_num],
  254. intr_alloc_flags, &(p_timer_obj[group_num][timer_num]->timer_isr_fun.timer_isr_handle));
  255. ESP_RETURN_ON_ERROR(ret, TIMER_TAG, "register interrupt service failed");
  256. timer_enable_intr(group_num, timer_num);
  257. return ret;
  258. }
  259. esp_err_t timer_isr_callback_remove(timer_group_t group_num, timer_idx_t timer_num)
  260. {
  261. ESP_RETURN_ON_FALSE(group_num < TIMER_GROUP_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_GROUP_NUM_ERROR);
  262. ESP_RETURN_ON_FALSE(timer_num < TIMER_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_NUM_ERROR);
  263. ESP_RETURN_ON_FALSE(p_timer_obj[group_num][timer_num] != NULL, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_NEVER_INIT_ERROR);
  264. timer_disable_intr(group_num, timer_num);
  265. p_timer_obj[group_num][timer_num]->timer_isr_fun.fn = NULL;
  266. p_timer_obj[group_num][timer_num]->timer_isr_fun.args = NULL;
  267. esp_intr_free(p_timer_obj[group_num][timer_num]->timer_isr_fun.timer_isr_handle);
  268. return ESP_OK;
  269. }
  270. esp_err_t timer_init(timer_group_t group_num, timer_idx_t timer_num, const timer_config_t *config)
  271. {
  272. ESP_RETURN_ON_FALSE(group_num < TIMER_GROUP_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_GROUP_NUM_ERROR);
  273. ESP_RETURN_ON_FALSE(timer_num < TIMER_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_NUM_ERROR);
  274. ESP_RETURN_ON_FALSE(config != NULL, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_PARAM_ADDR_ERROR);
  275. ESP_RETURN_ON_FALSE(config->divider > 1 && config->divider < 65537, ESP_ERR_INVALID_ARG, TIMER_TAG, DIVIDER_RANGE_ERROR);
  276. ESP_RETURN_ON_FALSE(config->intr_type < TIMER_INTR_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, "only support Level Interrupt");
  277. if (p_timer_obj[group_num][timer_num] == NULL) {
  278. p_timer_obj[group_num][timer_num] = (timer_obj_t *) heap_caps_calloc(1, sizeof(timer_obj_t), MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
  279. ESP_RETURN_ON_FALSE(p_timer_obj[group_num][timer_num], ESP_ERR_NO_MEM, TIMER_TAG, "no mem for timer object");
  280. }
  281. timer_hal_context_t *hal = &p_timer_obj[group_num][timer_num]->hal;
  282. PERIPH_RCC_ACQUIRE_ATOMIC(timer_group_periph_signals.groups[group_num].module, ref_count) {
  283. if (ref_count == 0) {
  284. timer_ll_enable_bus_clock(group_num, true);
  285. timer_ll_reset_register(group_num);
  286. }
  287. }
  288. TIMER_ENTER_CRITICAL(&timer_spinlock[group_num]);
  289. timer_hal_init(hal, group_num, timer_num);
  290. timer_hal_set_counter_value(hal, 0);
  291. timer_src_clk_t clk_src = TIMER_SRC_CLK_DEFAULT;
  292. if (config->clk_src) {
  293. clk_src = config->clk_src;
  294. }
  295. GPTIMER_CLOCK_SRC_ATOMIC() {
  296. // although `clk_src` is of `timer_src_clk_t` type, but it's binary compatible with `gptimer_clock_source_t`,
  297. // as the underlying enum entries come from the same `soc_module_clk_t`
  298. timer_ll_set_clock_source(p_timer_obj[group_num][timer_num]->hal.dev, timer_num, (gptimer_clock_source_t)clk_src);
  299. timer_ll_enable_clock(hal->dev, timer_num, true);
  300. }
  301. timer_ll_set_clock_prescale(hal->dev, timer_num, config->divider);
  302. timer_ll_set_count_direction(p_timer_obj[group_num][timer_num]->hal.dev, timer_num, config->counter_dir);
  303. timer_ll_enable_intr(hal->dev, TIMER_LL_EVENT_ALARM(timer_num), false);
  304. timer_ll_clear_intr_status(hal->dev, TIMER_LL_EVENT_ALARM(timer_num));
  305. timer_ll_enable_alarm(hal->dev, timer_num, config->alarm_en);
  306. timer_ll_enable_auto_reload(hal->dev, timer_num, config->auto_reload);
  307. timer_ll_enable_counter(hal->dev, timer_num, config->counter_en);
  308. p_timer_obj[group_num][timer_num]->clk_src = clk_src;
  309. p_timer_obj[group_num][timer_num]->alarm_en = config->alarm_en;
  310. p_timer_obj[group_num][timer_num]->auto_reload_en = config->auto_reload;
  311. p_timer_obj[group_num][timer_num]->direction = config->counter_dir;
  312. p_timer_obj[group_num][timer_num]->counter_en = config->counter_en;
  313. p_timer_obj[group_num][timer_num]->divider = config->divider;
  314. TIMER_EXIT_CRITICAL(&timer_spinlock[group_num]);
  315. return ESP_OK;
  316. }
  317. esp_err_t timer_deinit(timer_group_t group_num, timer_idx_t timer_num)
  318. {
  319. ESP_RETURN_ON_FALSE(group_num < TIMER_GROUP_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_GROUP_NUM_ERROR);
  320. ESP_RETURN_ON_FALSE(timer_num < TIMER_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_NUM_ERROR);
  321. ESP_RETURN_ON_FALSE(p_timer_obj[group_num][timer_num] != NULL, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_NEVER_INIT_ERROR);
  322. timer_hal_context_t *hal = &p_timer_obj[group_num][timer_num]->hal;
  323. // disable the source clock
  324. GPTIMER_CLOCK_SRC_ATOMIC() {
  325. timer_ll_enable_clock(hal->dev, hal->timer_id, false);
  326. }
  327. TIMER_ENTER_CRITICAL(&timer_spinlock[group_num]);
  328. timer_ll_enable_intr(hal->dev, TIMER_LL_EVENT_ALARM(timer_num), false);
  329. timer_ll_clear_intr_status(hal->dev, TIMER_LL_EVENT_ALARM(timer_num));
  330. timer_hal_deinit(hal);
  331. TIMER_EXIT_CRITICAL(&timer_spinlock[group_num]);
  332. PERIPH_RCC_RELEASE_ATOMIC(timer_group_periph_signals.groups[group_num].module, ref_count) {
  333. if (ref_count == 0) {
  334. timer_ll_enable_bus_clock(group_num, false);
  335. }
  336. }
  337. free(p_timer_obj[group_num][timer_num]);
  338. p_timer_obj[group_num][timer_num] = NULL;
  339. return ESP_OK;
  340. }
  341. esp_err_t timer_get_config(timer_group_t group_num, timer_idx_t timer_num, timer_config_t *config)
  342. {
  343. ESP_RETURN_ON_FALSE(group_num < TIMER_GROUP_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_GROUP_NUM_ERROR);
  344. ESP_RETURN_ON_FALSE(timer_num < TIMER_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_NUM_ERROR);
  345. ESP_RETURN_ON_FALSE(config != NULL, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_PARAM_ADDR_ERROR);
  346. ESP_RETURN_ON_FALSE(p_timer_obj[group_num][timer_num] != NULL, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_NEVER_INIT_ERROR);
  347. TIMER_ENTER_CRITICAL(&timer_spinlock[group_num]);
  348. config->alarm_en = p_timer_obj[group_num][timer_num]->alarm_en;
  349. config->auto_reload = p_timer_obj[group_num][timer_num]->auto_reload_en;
  350. config->counter_dir = p_timer_obj[group_num][timer_num]->direction;
  351. config->counter_en = p_timer_obj[group_num][timer_num]->counter_en;
  352. config->divider = p_timer_obj[group_num][timer_num]->divider;
  353. config->intr_type = TIMER_INTR_LEVEL;
  354. TIMER_EXIT_CRITICAL(&timer_spinlock[group_num]);
  355. return ESP_OK;
  356. }
  357. esp_err_t timer_group_intr_enable(timer_group_t group_num, timer_intr_t en_mask)
  358. {
  359. ESP_RETURN_ON_FALSE(group_num < TIMER_GROUP_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_GROUP_NUM_ERROR);
  360. ESP_RETURN_ON_FALSE(p_timer_obj[group_num] != NULL, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_NEVER_INIT_ERROR);
  361. TIMER_ENTER_CRITICAL(&timer_spinlock[group_num]);
  362. timer_ll_enable_intr(p_timer_obj[group_num][0]->hal.dev, en_mask, true);
  363. TIMER_EXIT_CRITICAL(&timer_spinlock[group_num]);
  364. return ESP_OK;
  365. }
  366. esp_err_t timer_group_intr_disable(timer_group_t group_num, timer_intr_t disable_mask)
  367. {
  368. ESP_RETURN_ON_FALSE(group_num < TIMER_GROUP_MAX, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_GROUP_NUM_ERROR);
  369. ESP_RETURN_ON_FALSE(p_timer_obj[group_num] != NULL, ESP_ERR_INVALID_ARG, TIMER_TAG, TIMER_NEVER_INIT_ERROR);
  370. TIMER_ENTER_CRITICAL(&timer_spinlock[group_num]);
  371. timer_ll_enable_intr(p_timer_obj[group_num][0]->hal.dev, disable_mask, false);
  372. TIMER_EXIT_CRITICAL(&timer_spinlock[group_num]);
  373. return ESP_OK;
  374. }
  375. uint32_t IRAM_ATTR timer_group_get_intr_status_in_isr(timer_group_t group_num)
  376. {
  377. uint32_t intr_status = 0;
  378. if (p_timer_obj[group_num][TIMER_0] != NULL) {
  379. intr_status = timer_ll_get_intr_status(TIMER_LL_GET_HW(group_num)) & TIMER_LL_EVENT_ALARM(0);
  380. }
  381. #if SOC_TIMER_GROUP_TIMERS_PER_GROUP > 1
  382. else if (p_timer_obj[group_num][TIMER_1] != NULL) {
  383. intr_status = timer_ll_get_intr_status(TIMER_LL_GET_HW(group_num)) & TIMER_LL_EVENT_ALARM(1);
  384. }
  385. #endif
  386. return intr_status;
  387. }
  388. void IRAM_ATTR timer_group_clr_intr_status_in_isr(timer_group_t group_num, timer_idx_t timer_num)
  389. {
  390. timer_ll_clear_intr_status(p_timer_obj[group_num][timer_num]->hal.dev, TIMER_LL_EVENT_ALARM(timer_num));
  391. }
  392. void IRAM_ATTR timer_group_enable_alarm_in_isr(timer_group_t group_num, timer_idx_t timer_num)
  393. {
  394. timer_ll_enable_alarm(p_timer_obj[group_num][timer_num]->hal.dev, timer_num, true);
  395. }
  396. uint64_t IRAM_ATTR timer_group_get_counter_value_in_isr(timer_group_t group_num, timer_idx_t timer_num)
  397. {
  398. timer_ll_trigger_soft_capture(p_timer_obj[group_num][timer_num]->hal.dev, timer_num);
  399. uint64_t val = timer_ll_get_counter_value(p_timer_obj[group_num][timer_num]->hal.dev, timer_num);
  400. return val;
  401. }
  402. void IRAM_ATTR timer_group_set_alarm_value_in_isr(timer_group_t group_num, timer_idx_t timer_num, uint64_t alarm_val)
  403. {
  404. timer_ll_set_alarm_value(p_timer_obj[group_num][timer_num]->hal.dev, timer_num, alarm_val);
  405. p_timer_obj[group_num][timer_num]->alarm_value = alarm_val;
  406. }
  407. void IRAM_ATTR timer_group_set_counter_enable_in_isr(timer_group_t group_num, timer_idx_t timer_num, timer_start_t counter_en)
  408. {
  409. timer_ll_enable_counter(p_timer_obj[group_num][timer_num]->hal.dev, timer_num, counter_en);
  410. p_timer_obj[group_num][timer_num]->counter_en = counter_en;
  411. }
  412. bool IRAM_ATTR timer_group_get_auto_reload_in_isr(timer_group_t group_num, timer_idx_t timer_num)
  413. {
  414. return p_timer_obj[group_num][timer_num]->auto_reload_en;
  415. }
  416. /**
  417. * @brief This function will be called during start up, to check that this legacy timer group driver is not running along with the gptimer driver
  418. */
  419. __attribute__((constructor))
  420. static void check_legacy_timer_driver_conflict(void)
  421. {
  422. // This function was declared as weak here. gptimer driver has one implementation.
  423. // So if gptimer driver is not linked in, then `gptimer_new_timer()` should be NULL at runtime.
  424. extern __attribute__((weak)) esp_err_t gptimer_new_timer(const void *config, void **ret_timer);
  425. if ((void *)gptimer_new_timer != NULL) {
  426. ESP_EARLY_LOGE(TIMER_TAG, "CONFLICT! driver_ng is not allowed to be used with the legacy driver");
  427. abort();
  428. }
  429. ESP_EARLY_LOGW(TIMER_TAG, "legacy driver is deprecated, please migrate to `driver/gptimer.h`");
  430. }