esp_efuse_table.c 50 KB

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  1. /*
  2. * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. */
  6. #include "sdkconfig.h"
  7. #include "esp_efuse.h"
  8. #include <assert.h>
  9. #include "esp_efuse_table.h"
  10. // md5_digest_table e3fb625011fff48d5d8b7569075d0bb3
  11. // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
  12. // If you want to change some fields, you need to change esp_efuse_table.csv file
  13. // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
  14. // To show efuse_table run the command 'show_efuse_table'.
  15. static const esp_efuse_desc_t WR_DIS[] = {
  16. {EFUSE_BLK0, 0, 32}, // [] Disable programming of individual eFuses,
  17. };
  18. static const esp_efuse_desc_t WR_DIS_RD_DIS[] = {
  19. {EFUSE_BLK0, 0, 1}, // [] wr_dis of RD_DIS,
  20. };
  21. static const esp_efuse_desc_t WR_DIS_DIS_ICACHE[] = {
  22. {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_ICACHE,
  23. };
  24. static const esp_efuse_desc_t WR_DIS_DIS_USB_JTAG[] = {
  25. {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_USB_JTAG,
  26. };
  27. static const esp_efuse_desc_t WR_DIS_POWERGLITCH_EN[] = {
  28. {EFUSE_BLK0, 2, 1}, // [] wr_dis of POWERGLITCH_EN,
  29. };
  30. static const esp_efuse_desc_t WR_DIS_DIS_FORCE_DOWNLOAD[] = {
  31. {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_FORCE_DOWNLOAD,
  32. };
  33. static const esp_efuse_desc_t WR_DIS_SPI_DOWNLOAD_MSPI_DIS[] = {
  34. {EFUSE_BLK0, 2, 1}, // [] wr_dis of SPI_DOWNLOAD_MSPI_DIS,
  35. };
  36. static const esp_efuse_desc_t WR_DIS_DIS_TWAI[] = {
  37. {EFUSE_BLK0, 2, 1}, // [WR_DIS.DIS_CAN] wr_dis of DIS_TWAI,
  38. };
  39. static const esp_efuse_desc_t WR_DIS_JTAG_SEL_ENABLE[] = {
  40. {EFUSE_BLK0, 2, 1}, // [] wr_dis of JTAG_SEL_ENABLE,
  41. };
  42. static const esp_efuse_desc_t WR_DIS_DIS_PAD_JTAG[] = {
  43. {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_PAD_JTAG,
  44. };
  45. static const esp_efuse_desc_t WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[] = {
  46. {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT,
  47. };
  48. static const esp_efuse_desc_t WR_DIS_WDT_DELAY_SEL[] = {
  49. {EFUSE_BLK0, 3, 1}, // [] wr_dis of WDT_DELAY_SEL,
  50. };
  51. static const esp_efuse_desc_t WR_DIS_SPI_BOOT_CRYPT_CNT[] = {
  52. {EFUSE_BLK0, 4, 1}, // [] wr_dis of SPI_BOOT_CRYPT_CNT,
  53. };
  54. static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_KEY_REVOKE0[] = {
  55. {EFUSE_BLK0, 5, 1}, // [] wr_dis of SECURE_BOOT_KEY_REVOKE0,
  56. };
  57. static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_KEY_REVOKE1[] = {
  58. {EFUSE_BLK0, 6, 1}, // [] wr_dis of SECURE_BOOT_KEY_REVOKE1,
  59. };
  60. static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_KEY_REVOKE2[] = {
  61. {EFUSE_BLK0, 7, 1}, // [] wr_dis of SECURE_BOOT_KEY_REVOKE2,
  62. };
  63. static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_0[] = {
  64. {EFUSE_BLK0, 8, 1}, // [WR_DIS.KEY0_PURPOSE] wr_dis of KEY_PURPOSE_0,
  65. };
  66. static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_1[] = {
  67. {EFUSE_BLK0, 9, 1}, // [WR_DIS.KEY1_PURPOSE] wr_dis of KEY_PURPOSE_1,
  68. };
  69. static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_2[] = {
  70. {EFUSE_BLK0, 10, 1}, // [WR_DIS.KEY2_PURPOSE] wr_dis of KEY_PURPOSE_2,
  71. };
  72. static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_3[] = {
  73. {EFUSE_BLK0, 11, 1}, // [WR_DIS.KEY3_PURPOSE] wr_dis of KEY_PURPOSE_3,
  74. };
  75. static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_4[] = {
  76. {EFUSE_BLK0, 12, 1}, // [WR_DIS.KEY4_PURPOSE] wr_dis of KEY_PURPOSE_4,
  77. };
  78. static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_5[] = {
  79. {EFUSE_BLK0, 13, 1}, // [WR_DIS.KEY5_PURPOSE] wr_dis of KEY_PURPOSE_5,
  80. };
  81. static const esp_efuse_desc_t WR_DIS_SEC_DPA_LEVEL[] = {
  82. {EFUSE_BLK0, 14, 1}, // [] wr_dis of SEC_DPA_LEVEL,
  83. };
  84. static const esp_efuse_desc_t WR_DIS_CRYPT_DPA_ENABLE[] = {
  85. {EFUSE_BLK0, 14, 1}, // [] wr_dis of CRYPT_DPA_ENABLE,
  86. };
  87. static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_EN[] = {
  88. {EFUSE_BLK0, 15, 1}, // [] wr_dis of SECURE_BOOT_EN,
  89. };
  90. static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[] = {
  91. {EFUSE_BLK0, 16, 1}, // [] wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE,
  92. };
  93. static const esp_efuse_desc_t WR_DIS_ECDSA_FORCE_USE_HARDWARE_K[] = {
  94. {EFUSE_BLK0, 17, 1}, // [] wr_dis of ECDSA_FORCE_USE_HARDWARE_K,
  95. };
  96. static const esp_efuse_desc_t WR_DIS_FLASH_TPUW[] = {
  97. {EFUSE_BLK0, 18, 1}, // [] wr_dis of FLASH_TPUW,
  98. };
  99. static const esp_efuse_desc_t WR_DIS_DIS_DOWNLOAD_MODE[] = {
  100. {EFUSE_BLK0, 18, 1}, // [] wr_dis of DIS_DOWNLOAD_MODE,
  101. };
  102. static const esp_efuse_desc_t WR_DIS_DIS_DIRECT_BOOT[] = {
  103. {EFUSE_BLK0, 18, 1}, // [] wr_dis of DIS_DIRECT_BOOT,
  104. };
  105. static const esp_efuse_desc_t WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT[] = {
  106. {EFUSE_BLK0, 18, 1}, // [WR_DIS.DIS_USB_PRINT] wr_dis of DIS_USB_SERIAL_JTAG_ROM_PRINT,
  107. };
  108. static const esp_efuse_desc_t WR_DIS_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[] = {
  109. {EFUSE_BLK0, 18, 1}, // [] wr_dis of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE,
  110. };
  111. static const esp_efuse_desc_t WR_DIS_ENABLE_SECURITY_DOWNLOAD[] = {
  112. {EFUSE_BLK0, 18, 1}, // [] wr_dis of ENABLE_SECURITY_DOWNLOAD,
  113. };
  114. static const esp_efuse_desc_t WR_DIS_UART_PRINT_CONTROL[] = {
  115. {EFUSE_BLK0, 18, 1}, // [] wr_dis of UART_PRINT_CONTROL,
  116. };
  117. static const esp_efuse_desc_t WR_DIS_FORCE_SEND_RESUME[] = {
  118. {EFUSE_BLK0, 18, 1}, // [] wr_dis of FORCE_SEND_RESUME,
  119. };
  120. static const esp_efuse_desc_t WR_DIS_SECURE_VERSION[] = {
  121. {EFUSE_BLK0, 18, 1}, // [] wr_dis of SECURE_VERSION,
  122. };
  123. static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_DISABLE_FAST_WAKE[] = {
  124. {EFUSE_BLK0, 18, 1}, // [] wr_dis of SECURE_BOOT_DISABLE_FAST_WAKE,
  125. };
  126. static const esp_efuse_desc_t WR_DIS_HYS_EN_PAD0[] = {
  127. {EFUSE_BLK0, 19, 1}, // [] wr_dis of HYS_EN_PAD0,
  128. };
  129. static const esp_efuse_desc_t WR_DIS_HYS_EN_PAD1[] = {
  130. {EFUSE_BLK0, 19, 1}, // [] wr_dis of HYS_EN_PAD1,
  131. };
  132. static const esp_efuse_desc_t WR_DIS_BLK1[] = {
  133. {EFUSE_BLK0, 20, 1}, // [] wr_dis of BLOCK1,
  134. };
  135. static const esp_efuse_desc_t WR_DIS_MAC[] = {
  136. {EFUSE_BLK0, 20, 1}, // [WR_DIS.MAC_FACTORY] wr_dis of MAC,
  137. };
  138. static const esp_efuse_desc_t WR_DIS_MAC_EXT[] = {
  139. {EFUSE_BLK0, 20, 1}, // [] wr_dis of MAC_EXT,
  140. };
  141. static const esp_efuse_desc_t WR_DIS_RXIQ_VERSION[] = {
  142. {EFUSE_BLK0, 20, 1}, // [] wr_dis of RXIQ_VERSION,
  143. };
  144. static const esp_efuse_desc_t WR_DIS_RXIQ_0[] = {
  145. {EFUSE_BLK0, 20, 1}, // [] wr_dis of RXIQ_0,
  146. };
  147. static const esp_efuse_desc_t WR_DIS_RXIQ_1[] = {
  148. {EFUSE_BLK0, 20, 1}, // [] wr_dis of RXIQ_1,
  149. };
  150. static const esp_efuse_desc_t WR_DIS_WAFER_VERSION_MINOR[] = {
  151. {EFUSE_BLK0, 20, 1}, // [] wr_dis of WAFER_VERSION_MINOR,
  152. };
  153. static const esp_efuse_desc_t WR_DIS_WAFER_VERSION_MAJOR[] = {
  154. {EFUSE_BLK0, 20, 1}, // [] wr_dis of WAFER_VERSION_MAJOR,
  155. };
  156. static const esp_efuse_desc_t WR_DIS_DISABLE_WAFER_VERSION_MAJOR[] = {
  157. {EFUSE_BLK0, 20, 1}, // [] wr_dis of DISABLE_WAFER_VERSION_MAJOR,
  158. };
  159. static const esp_efuse_desc_t WR_DIS_FLASH_CAP[] = {
  160. {EFUSE_BLK0, 20, 1}, // [] wr_dis of FLASH_CAP,
  161. };
  162. static const esp_efuse_desc_t WR_DIS_FLASH_TEMP[] = {
  163. {EFUSE_BLK0, 20, 1}, // [] wr_dis of FLASH_TEMP,
  164. };
  165. static const esp_efuse_desc_t WR_DIS_FLASH_VENDOR[] = {
  166. {EFUSE_BLK0, 20, 1}, // [] wr_dis of FLASH_VENDOR,
  167. };
  168. static const esp_efuse_desc_t WR_DIS_PKG_VERSION[] = {
  169. {EFUSE_BLK0, 20, 1}, // [] wr_dis of PKG_VERSION,
  170. };
  171. static const esp_efuse_desc_t WR_DIS_SYS_DATA_PART1[] = {
  172. {EFUSE_BLK0, 21, 1}, // [] wr_dis of BLOCK2,
  173. };
  174. static const esp_efuse_desc_t WR_DIS_OPTIONAL_UNIQUE_ID[] = {
  175. {EFUSE_BLK0, 21, 1}, // [] wr_dis of OPTIONAL_UNIQUE_ID,
  176. };
  177. static const esp_efuse_desc_t WR_DIS_BLK_VERSION_MINOR[] = {
  178. {EFUSE_BLK0, 21, 1}, // [] wr_dis of BLK_VERSION_MINOR,
  179. };
  180. static const esp_efuse_desc_t WR_DIS_BLK_VERSION_MAJOR[] = {
  181. {EFUSE_BLK0, 21, 1}, // [] wr_dis of BLK_VERSION_MAJOR,
  182. };
  183. static const esp_efuse_desc_t WR_DIS_DISABLE_BLK_VERSION_MAJOR[] = {
  184. {EFUSE_BLK0, 21, 1}, // [] wr_dis of DISABLE_BLK_VERSION_MAJOR,
  185. };
  186. static const esp_efuse_desc_t WR_DIS_TEMP_CALIB[] = {
  187. {EFUSE_BLK0, 21, 1}, // [] wr_dis of TEMP_CALIB,
  188. };
  189. static const esp_efuse_desc_t WR_DIS_ADC1_AVE_INITCODE_ATTEN0[] = {
  190. {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_AVE_INITCODE_ATTEN0,
  191. };
  192. static const esp_efuse_desc_t WR_DIS_ADC1_AVE_INITCODE_ATTEN1[] = {
  193. {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_AVE_INITCODE_ATTEN1,
  194. };
  195. static const esp_efuse_desc_t WR_DIS_ADC1_AVE_INITCODE_ATTEN2[] = {
  196. {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_AVE_INITCODE_ATTEN2,
  197. };
  198. static const esp_efuse_desc_t WR_DIS_ADC1_AVE_INITCODE_ATTEN3[] = {
  199. {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_AVE_INITCODE_ATTEN3,
  200. };
  201. static const esp_efuse_desc_t WR_DIS_ADC1_HI_DOUT_ATTEN0[] = {
  202. {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_HI_DOUT_ATTEN0,
  203. };
  204. static const esp_efuse_desc_t WR_DIS_ADC1_HI_DOUT_ATTEN1[] = {
  205. {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_HI_DOUT_ATTEN1,
  206. };
  207. static const esp_efuse_desc_t WR_DIS_ADC1_HI_DOUT_ATTEN2[] = {
  208. {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_HI_DOUT_ATTEN2,
  209. };
  210. static const esp_efuse_desc_t WR_DIS_ADC1_HI_DOUT_ATTEN3[] = {
  211. {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_HI_DOUT_ATTEN3,
  212. };
  213. static const esp_efuse_desc_t WR_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[] = {
  214. {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_CH0_ATTEN0_INITCODE_DIFF,
  215. };
  216. static const esp_efuse_desc_t WR_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[] = {
  217. {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_CH1_ATTEN0_INITCODE_DIFF,
  218. };
  219. static const esp_efuse_desc_t WR_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[] = {
  220. {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_CH2_ATTEN0_INITCODE_DIFF,
  221. };
  222. static const esp_efuse_desc_t WR_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[] = {
  223. {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_CH3_ATTEN0_INITCODE_DIFF,
  224. };
  225. static const esp_efuse_desc_t WR_DIS_ADC1_CH4_ATTEN0_INITCODE_DIFF[] = {
  226. {EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_CH4_ATTEN0_INITCODE_DIFF,
  227. };
  228. static const esp_efuse_desc_t WR_DIS_BLOCK_USR_DATA[] = {
  229. {EFUSE_BLK0, 22, 1}, // [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA,
  230. };
  231. static const esp_efuse_desc_t WR_DIS_CUSTOM_MAC[] = {
  232. {EFUSE_BLK0, 22, 1}, // [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC,
  233. };
  234. static const esp_efuse_desc_t WR_DIS_BLOCK_KEY0[] = {
  235. {EFUSE_BLK0, 23, 1}, // [WR_DIS.KEY0] wr_dis of BLOCK_KEY0,
  236. };
  237. static const esp_efuse_desc_t WR_DIS_BLOCK_KEY1[] = {
  238. {EFUSE_BLK0, 24, 1}, // [WR_DIS.KEY1] wr_dis of BLOCK_KEY1,
  239. };
  240. static const esp_efuse_desc_t WR_DIS_BLOCK_KEY2[] = {
  241. {EFUSE_BLK0, 25, 1}, // [WR_DIS.KEY2] wr_dis of BLOCK_KEY2,
  242. };
  243. static const esp_efuse_desc_t WR_DIS_BLOCK_KEY3[] = {
  244. {EFUSE_BLK0, 26, 1}, // [WR_DIS.KEY3] wr_dis of BLOCK_KEY3,
  245. };
  246. static const esp_efuse_desc_t WR_DIS_BLOCK_KEY4[] = {
  247. {EFUSE_BLK0, 27, 1}, // [WR_DIS.KEY4] wr_dis of BLOCK_KEY4,
  248. };
  249. static const esp_efuse_desc_t WR_DIS_BLOCK_KEY5[] = {
  250. {EFUSE_BLK0, 28, 1}, // [WR_DIS.KEY5] wr_dis of BLOCK_KEY5,
  251. };
  252. static const esp_efuse_desc_t WR_DIS_BLOCK_SYS_DATA2[] = {
  253. {EFUSE_BLK0, 29, 1}, // [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2,
  254. };
  255. static const esp_efuse_desc_t WR_DIS_USB_EXCHG_PINS[] = {
  256. {EFUSE_BLK0, 30, 1}, // [] wr_dis of USB_EXCHG_PINS,
  257. };
  258. static const esp_efuse_desc_t WR_DIS_VDD_SPI_AS_GPIO[] = {
  259. {EFUSE_BLK0, 30, 1}, // [] wr_dis of VDD_SPI_AS_GPIO,
  260. };
  261. static const esp_efuse_desc_t WR_DIS_SOFT_DIS_JTAG[] = {
  262. {EFUSE_BLK0, 31, 1}, // [] wr_dis of SOFT_DIS_JTAG,
  263. };
  264. static const esp_efuse_desc_t RD_DIS[] = {
  265. {EFUSE_BLK0, 32, 7}, // [] Disable reading from BlOCK4-10,
  266. };
  267. static const esp_efuse_desc_t RD_DIS_BLOCK_KEY0[] = {
  268. {EFUSE_BLK0, 32, 1}, // [RD_DIS.KEY0] rd_dis of BLOCK_KEY0,
  269. };
  270. static const esp_efuse_desc_t RD_DIS_BLOCK_KEY1[] = {
  271. {EFUSE_BLK0, 33, 1}, // [RD_DIS.KEY1] rd_dis of BLOCK_KEY1,
  272. };
  273. static const esp_efuse_desc_t RD_DIS_BLOCK_KEY2[] = {
  274. {EFUSE_BLK0, 34, 1}, // [RD_DIS.KEY2] rd_dis of BLOCK_KEY2,
  275. };
  276. static const esp_efuse_desc_t RD_DIS_BLOCK_KEY3[] = {
  277. {EFUSE_BLK0, 35, 1}, // [RD_DIS.KEY3] rd_dis of BLOCK_KEY3,
  278. };
  279. static const esp_efuse_desc_t RD_DIS_BLOCK_KEY4[] = {
  280. {EFUSE_BLK0, 36, 1}, // [RD_DIS.KEY4] rd_dis of BLOCK_KEY4,
  281. };
  282. static const esp_efuse_desc_t RD_DIS_BLOCK_KEY5[] = {
  283. {EFUSE_BLK0, 37, 1}, // [RD_DIS.KEY5] rd_dis of BLOCK_KEY5,
  284. };
  285. static const esp_efuse_desc_t RD_DIS_BLOCK_SYS_DATA2[] = {
  286. {EFUSE_BLK0, 38, 1}, // [RD_DIS.SYS_DATA_PART2] rd_dis of BLOCK_SYS_DATA2,
  287. };
  288. static const esp_efuse_desc_t DIS_ICACHE[] = {
  289. {EFUSE_BLK0, 40, 1}, // [] Represents whether icache is disabled or enabled. 1: disabled. 0: enabled,
  290. };
  291. static const esp_efuse_desc_t DIS_USB_JTAG[] = {
  292. {EFUSE_BLK0, 41, 1}, // [] Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled. 0: enabled,
  293. };
  294. static const esp_efuse_desc_t POWERGLITCH_EN[] = {
  295. {EFUSE_BLK0, 42, 1}, // [] Represents whether power glitch function is enabled. 1: enabled. 0: disabled,
  296. };
  297. static const esp_efuse_desc_t DIS_FORCE_DOWNLOAD[] = {
  298. {EFUSE_BLK0, 44, 1}, // [] Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled. 0: enabled,
  299. };
  300. static const esp_efuse_desc_t SPI_DOWNLOAD_MSPI_DIS[] = {
  301. {EFUSE_BLK0, 45, 1}, // [] Represents whether SPI0 controller during boot_mode_download is disabled or enabled. 1: disabled. 0: enabled,
  302. };
  303. static const esp_efuse_desc_t DIS_TWAI[] = {
  304. {EFUSE_BLK0, 46, 1}, // [DIS_CAN] Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled,
  305. };
  306. static const esp_efuse_desc_t JTAG_SEL_ENABLE[] = {
  307. {EFUSE_BLK0, 47, 1}, // [] Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio25 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0,
  308. };
  309. static const esp_efuse_desc_t SOFT_DIS_JTAG[] = {
  310. {EFUSE_BLK0, 48, 3}, // [] Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: enabled,
  311. };
  312. static const esp_efuse_desc_t DIS_PAD_JTAG[] = {
  313. {EFUSE_BLK0, 51, 1}, // [] Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: enabled,
  314. };
  315. static const esp_efuse_desc_t DIS_DOWNLOAD_MANUAL_ENCRYPT[] = {
  316. {EFUSE_BLK0, 52, 1}, // [] Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled. 0: enabled,
  317. };
  318. static const esp_efuse_desc_t USB_EXCHG_PINS[] = {
  319. {EFUSE_BLK0, 57, 1}, // [] Represents whether the D+ and D- pins is exchanged. 1: exchanged. 0: not exchanged,
  320. };
  321. static const esp_efuse_desc_t VDD_SPI_AS_GPIO[] = {
  322. {EFUSE_BLK0, 58, 1}, // [] Represents whether vdd spi pin is functioned as gpio. 1: functioned. 0: not functioned,
  323. };
  324. static const esp_efuse_desc_t WDT_DELAY_SEL[] = {
  325. {EFUSE_BLK0, 80, 2}, // [] Represents whether RTC watchdog timeout threshold is selected at startup. 1: selected. 0: not selected,
  326. };
  327. static const esp_efuse_desc_t SPI_BOOT_CRYPT_CNT[] = {
  328. {EFUSE_BLK0, 82, 3}, // [] Enables flash encryption when 1 or 3 bits are set and disables otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"},
  329. };
  330. static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE0[] = {
  331. {EFUSE_BLK0, 85, 1}, // [] Revoke 1st secure boot key,
  332. };
  333. static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE1[] = {
  334. {EFUSE_BLK0, 86, 1}, // [] Revoke 2nd secure boot key,
  335. };
  336. static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE2[] = {
  337. {EFUSE_BLK0, 87, 1}, // [] Revoke 3rd secure boot key,
  338. };
  339. static const esp_efuse_desc_t KEY_PURPOSE_0[] = {
  340. {EFUSE_BLK0, 88, 4}, // [KEY0_PURPOSE] Represents the purpose of Key0,
  341. };
  342. static const esp_efuse_desc_t KEY_PURPOSE_1[] = {
  343. {EFUSE_BLK0, 92, 4}, // [KEY1_PURPOSE] Represents the purpose of Key1,
  344. };
  345. static const esp_efuse_desc_t KEY_PURPOSE_2[] = {
  346. {EFUSE_BLK0, 96, 4}, // [KEY2_PURPOSE] Represents the purpose of Key2,
  347. };
  348. static const esp_efuse_desc_t KEY_PURPOSE_3[] = {
  349. {EFUSE_BLK0, 100, 4}, // [KEY3_PURPOSE] Represents the purpose of Key3,
  350. };
  351. static const esp_efuse_desc_t KEY_PURPOSE_4[] = {
  352. {EFUSE_BLK0, 104, 4}, // [KEY4_PURPOSE] Represents the purpose of Key4,
  353. };
  354. static const esp_efuse_desc_t KEY_PURPOSE_5[] = {
  355. {EFUSE_BLK0, 108, 4}, // [KEY5_PURPOSE] Represents the purpose of Key5,
  356. };
  357. static const esp_efuse_desc_t SEC_DPA_LEVEL[] = {
  358. {EFUSE_BLK0, 112, 2}, // [] Represents the spa secure level by configuring the clock random divide mode,
  359. };
  360. static const esp_efuse_desc_t ECDSA_FORCE_USE_HARDWARE_K[] = {
  361. {EFUSE_BLK0, 114, 1}, // [] Represents whether hardware random number k is forced used in ESDCA. 1: force used. 0: not force used,
  362. };
  363. static const esp_efuse_desc_t CRYPT_DPA_ENABLE[] = {
  364. {EFUSE_BLK0, 115, 1}, // [] Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled,
  365. };
  366. static const esp_efuse_desc_t SECURE_BOOT_EN[] = {
  367. {EFUSE_BLK0, 116, 1}, // [] Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled,
  368. };
  369. static const esp_efuse_desc_t SECURE_BOOT_AGGRESSIVE_REVOKE[] = {
  370. {EFUSE_BLK0, 117, 1}, // [] Represents whether revoking aggressive secure boot is enabled or disabled. 1: enabled. 0: disabled,
  371. };
  372. static const esp_efuse_desc_t FLASH_TPUW[] = {
  373. {EFUSE_BLK0, 124, 4}, // [] Represents the flash waiting time after power-up; in unit of ms. When the value less than 15; the waiting time is the programmed value. Otherwise; the waiting time is 2 times the programmed value,
  374. };
  375. static const esp_efuse_desc_t DIS_DOWNLOAD_MODE[] = {
  376. {EFUSE_BLK0, 128, 1}, // [] Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled,
  377. };
  378. static const esp_efuse_desc_t DIS_DIRECT_BOOT[] = {
  379. {EFUSE_BLK0, 129, 1}, // [] Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled,
  380. };
  381. static const esp_efuse_desc_t DIS_USB_SERIAL_JTAG_ROM_PRINT[] = {
  382. {EFUSE_BLK0, 130, 1}, // [DIS_USB_PRINT] Set this bit to disable USB-Serial-JTAG print during rom boot,
  383. };
  384. static const esp_efuse_desc_t DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[] = {
  385. {EFUSE_BLK0, 132, 1}, // [] Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: disabled. 0: enabled,
  386. };
  387. static const esp_efuse_desc_t ENABLE_SECURITY_DOWNLOAD[] = {
  388. {EFUSE_BLK0, 133, 1}, // [] Represents whether security download is enabled or disabled. 1: enabled. 0: disabled,
  389. };
  390. static const esp_efuse_desc_t UART_PRINT_CONTROL[] = {
  391. {EFUSE_BLK0, 134, 2}, // [] Set the default UARTboot message output mode {0: "Enable"; 1: "Enable when GPIO8 is low at reset"; 2: "Enable when GPIO8 is high at reset"; 3: "Disable"},
  392. };
  393. static const esp_efuse_desc_t FORCE_SEND_RESUME[] = {
  394. {EFUSE_BLK0, 136, 1}, // [] Represents whether ROM code is forced to send a resume command during SPI boot. 1: forced. 0:not forced,
  395. };
  396. static const esp_efuse_desc_t SECURE_VERSION[] = {
  397. {EFUSE_BLK0, 137, 16}, // [] Represents the version used by ESP-IDF anti-rollback feature,
  398. };
  399. static const esp_efuse_desc_t SECURE_BOOT_DISABLE_FAST_WAKE[] = {
  400. {EFUSE_BLK0, 153, 1}, // [] Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled. 1: disabled. 0: enabled,
  401. };
  402. static const esp_efuse_desc_t HYS_EN_PAD0[] = {
  403. {EFUSE_BLK0, 154, 6}, // [] Set bits to enable hysteresis function of PAD0~5,
  404. };
  405. static const esp_efuse_desc_t HYS_EN_PAD1[] = {
  406. {EFUSE_BLK0, 160, 22}, // [] Set bits to enable hysteresis function of PAD6~27,
  407. };
  408. static const esp_efuse_desc_t MAC[] = {
  409. {EFUSE_BLK1, 40, 8}, // [MAC_FACTORY] MAC address,
  410. {EFUSE_BLK1, 32, 8}, // [MAC_FACTORY] MAC address,
  411. {EFUSE_BLK1, 24, 8}, // [MAC_FACTORY] MAC address,
  412. {EFUSE_BLK1, 16, 8}, // [MAC_FACTORY] MAC address,
  413. {EFUSE_BLK1, 8, 8}, // [MAC_FACTORY] MAC address,
  414. {EFUSE_BLK1, 0, 8}, // [MAC_FACTORY] MAC address,
  415. };
  416. static const esp_efuse_desc_t MAC_EXT[] = {
  417. {EFUSE_BLK1, 56, 8}, // [] Stores the extended bits of MAC address,
  418. {EFUSE_BLK1, 48, 8}, // [] Stores the extended bits of MAC address,
  419. };
  420. static const esp_efuse_desc_t RXIQ_VERSION[] = {
  421. {EFUSE_BLK1, 64, 3}, // [] RF Calibration data. RXIQ version,
  422. };
  423. static const esp_efuse_desc_t RXIQ_0[] = {
  424. {EFUSE_BLK1, 67, 7}, // [] RF Calibration data. RXIQ data 0,
  425. };
  426. static const esp_efuse_desc_t RXIQ_1[] = {
  427. {EFUSE_BLK1, 74, 7}, // [] RF Calibration data. RXIQ data 1,
  428. };
  429. static const esp_efuse_desc_t WAFER_VERSION_MINOR[] = {
  430. {EFUSE_BLK1, 114, 3}, // [],
  431. };
  432. static const esp_efuse_desc_t WAFER_VERSION_MAJOR[] = {
  433. {EFUSE_BLK1, 117, 2}, // [],
  434. };
  435. static const esp_efuse_desc_t DISABLE_WAFER_VERSION_MAJOR[] = {
  436. {EFUSE_BLK1, 119, 1}, // [] Disables check of wafer version major,
  437. };
  438. static const esp_efuse_desc_t FLASH_CAP[] = {
  439. {EFUSE_BLK1, 120, 3}, // [],
  440. };
  441. static const esp_efuse_desc_t FLASH_TEMP[] = {
  442. {EFUSE_BLK1, 123, 2}, // [],
  443. };
  444. static const esp_efuse_desc_t FLASH_VENDOR[] = {
  445. {EFUSE_BLK1, 125, 3}, // [],
  446. };
  447. static const esp_efuse_desc_t PKG_VERSION[] = {
  448. {EFUSE_BLK1, 128, 3}, // [] Package version,
  449. };
  450. static const esp_efuse_desc_t OPTIONAL_UNIQUE_ID[] = {
  451. {EFUSE_BLK2, 0, 128}, // [] Optional unique 128-bit ID,
  452. };
  453. static const esp_efuse_desc_t BLK_VERSION_MINOR[] = {
  454. {EFUSE_BLK2, 130, 3}, // [] BLK_VERSION_MINOR of BLOCK2. 1: RF Calibration data in BLOCK1,
  455. };
  456. static const esp_efuse_desc_t BLK_VERSION_MAJOR[] = {
  457. {EFUSE_BLK2, 133, 2}, // [] BLK_VERSION_MAJOR of BLOCK2,
  458. };
  459. static const esp_efuse_desc_t DISABLE_BLK_VERSION_MAJOR[] = {
  460. {EFUSE_BLK2, 135, 1}, // [] Disables check of blk version major,
  461. };
  462. static const esp_efuse_desc_t TEMP_CALIB[] = {
  463. {EFUSE_BLK2, 136, 9}, // [] Temperature calibration data,
  464. };
  465. static const esp_efuse_desc_t ADC1_AVE_INITCODE_ATTEN0[] = {
  466. {EFUSE_BLK2, 145, 10}, // [] ADC1 calibration data,
  467. };
  468. static const esp_efuse_desc_t ADC1_AVE_INITCODE_ATTEN1[] = {
  469. {EFUSE_BLK2, 155, 10}, // [] ADC1 calibration data,
  470. };
  471. static const esp_efuse_desc_t ADC1_AVE_INITCODE_ATTEN2[] = {
  472. {EFUSE_BLK2, 165, 10}, // [] ADC1 calibration data,
  473. };
  474. static const esp_efuse_desc_t ADC1_AVE_INITCODE_ATTEN3[] = {
  475. {EFUSE_BLK2, 175, 10}, // [] ADC1 calibration data,
  476. };
  477. static const esp_efuse_desc_t ADC1_HI_DOUT_ATTEN0[] = {
  478. {EFUSE_BLK2, 185, 10}, // [] ADC1 calibration data,
  479. };
  480. static const esp_efuse_desc_t ADC1_HI_DOUT_ATTEN1[] = {
  481. {EFUSE_BLK2, 195, 10}, // [] ADC1 calibration data,
  482. };
  483. static const esp_efuse_desc_t ADC1_HI_DOUT_ATTEN2[] = {
  484. {EFUSE_BLK2, 205, 10}, // [] ADC1 calibration data,
  485. };
  486. static const esp_efuse_desc_t ADC1_HI_DOUT_ATTEN3[] = {
  487. {EFUSE_BLK2, 215, 10}, // [] ADC1 calibration data,
  488. };
  489. static const esp_efuse_desc_t ADC1_CH0_ATTEN0_INITCODE_DIFF[] = {
  490. {EFUSE_BLK2, 225, 4}, // [] ADC1 calibration data,
  491. };
  492. static const esp_efuse_desc_t ADC1_CH1_ATTEN0_INITCODE_DIFF[] = {
  493. {EFUSE_BLK2, 229, 4}, // [] ADC1 calibration data,
  494. };
  495. static const esp_efuse_desc_t ADC1_CH2_ATTEN0_INITCODE_DIFF[] = {
  496. {EFUSE_BLK2, 233, 4}, // [] ADC1 calibration data,
  497. };
  498. static const esp_efuse_desc_t ADC1_CH3_ATTEN0_INITCODE_DIFF[] = {
  499. {EFUSE_BLK2, 237, 4}, // [] ADC1 calibration data,
  500. };
  501. static const esp_efuse_desc_t ADC1_CH4_ATTEN0_INITCODE_DIFF[] = {
  502. {EFUSE_BLK2, 241, 4}, // [] ADC1 calibration data,
  503. };
  504. static const esp_efuse_desc_t USER_DATA[] = {
  505. {EFUSE_BLK3, 0, 256}, // [BLOCK_USR_DATA] User data,
  506. };
  507. static const esp_efuse_desc_t USER_DATA_MAC_CUSTOM[] = {
  508. {EFUSE_BLK3, 200, 48}, // [MAC_CUSTOM CUSTOM_MAC] Custom MAC,
  509. };
  510. static const esp_efuse_desc_t KEY0[] = {
  511. {EFUSE_BLK4, 0, 256}, // [BLOCK_KEY0] Key0 or user data,
  512. };
  513. static const esp_efuse_desc_t KEY1[] = {
  514. {EFUSE_BLK5, 0, 256}, // [BLOCK_KEY1] Key1 or user data,
  515. };
  516. static const esp_efuse_desc_t KEY2[] = {
  517. {EFUSE_BLK6, 0, 256}, // [BLOCK_KEY2] Key2 or user data,
  518. };
  519. static const esp_efuse_desc_t KEY3[] = {
  520. {EFUSE_BLK7, 0, 256}, // [BLOCK_KEY3] Key3 or user data,
  521. };
  522. static const esp_efuse_desc_t KEY4[] = {
  523. {EFUSE_BLK8, 0, 256}, // [BLOCK_KEY4] Key4 or user data,
  524. };
  525. static const esp_efuse_desc_t KEY5[] = {
  526. {EFUSE_BLK9, 0, 256}, // [BLOCK_KEY5] Key5 or user data,
  527. };
  528. static const esp_efuse_desc_t SYS_DATA_PART2[] = {
  529. {EFUSE_BLK10, 0, 256}, // [BLOCK_SYS_DATA2] System data part 2 (reserved),
  530. };
  531. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS[] = {
  532. &WR_DIS[0], // [] Disable programming of individual eFuses
  533. NULL
  534. };
  535. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[] = {
  536. &WR_DIS_RD_DIS[0], // [] wr_dis of RD_DIS
  537. NULL
  538. };
  539. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_ICACHE[] = {
  540. &WR_DIS_DIS_ICACHE[0], // [] wr_dis of DIS_ICACHE
  541. NULL
  542. };
  543. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_JTAG[] = {
  544. &WR_DIS_DIS_USB_JTAG[0], // [] wr_dis of DIS_USB_JTAG
  545. NULL
  546. };
  547. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_POWERGLITCH_EN[] = {
  548. &WR_DIS_POWERGLITCH_EN[0], // [] wr_dis of POWERGLITCH_EN
  549. NULL
  550. };
  551. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_FORCE_DOWNLOAD[] = {
  552. &WR_DIS_DIS_FORCE_DOWNLOAD[0], // [] wr_dis of DIS_FORCE_DOWNLOAD
  553. NULL
  554. };
  555. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_DOWNLOAD_MSPI_DIS[] = {
  556. &WR_DIS_SPI_DOWNLOAD_MSPI_DIS[0], // [] wr_dis of SPI_DOWNLOAD_MSPI_DIS
  557. NULL
  558. };
  559. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_TWAI[] = {
  560. &WR_DIS_DIS_TWAI[0], // [WR_DIS.DIS_CAN] wr_dis of DIS_TWAI
  561. NULL
  562. };
  563. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_JTAG_SEL_ENABLE[] = {
  564. &WR_DIS_JTAG_SEL_ENABLE[0], // [] wr_dis of JTAG_SEL_ENABLE
  565. NULL
  566. };
  567. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_PAD_JTAG[] = {
  568. &WR_DIS_DIS_PAD_JTAG[0], // [] wr_dis of DIS_PAD_JTAG
  569. NULL
  570. };
  571. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[] = {
  572. &WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[0], // [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT
  573. NULL
  574. };
  575. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WDT_DELAY_SEL[] = {
  576. &WR_DIS_WDT_DELAY_SEL[0], // [] wr_dis of WDT_DELAY_SEL
  577. NULL
  578. };
  579. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[] = {
  580. &WR_DIS_SPI_BOOT_CRYPT_CNT[0], // [] wr_dis of SPI_BOOT_CRYPT_CNT
  581. NULL
  582. };
  583. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0[] = {
  584. &WR_DIS_SECURE_BOOT_KEY_REVOKE0[0], // [] wr_dis of SECURE_BOOT_KEY_REVOKE0
  585. NULL
  586. };
  587. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1[] = {
  588. &WR_DIS_SECURE_BOOT_KEY_REVOKE1[0], // [] wr_dis of SECURE_BOOT_KEY_REVOKE1
  589. NULL
  590. };
  591. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE2[] = {
  592. &WR_DIS_SECURE_BOOT_KEY_REVOKE2[0], // [] wr_dis of SECURE_BOOT_KEY_REVOKE2
  593. NULL
  594. };
  595. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_0[] = {
  596. &WR_DIS_KEY_PURPOSE_0[0], // [WR_DIS.KEY0_PURPOSE] wr_dis of KEY_PURPOSE_0
  597. NULL
  598. };
  599. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_1[] = {
  600. &WR_DIS_KEY_PURPOSE_1[0], // [WR_DIS.KEY1_PURPOSE] wr_dis of KEY_PURPOSE_1
  601. NULL
  602. };
  603. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_2[] = {
  604. &WR_DIS_KEY_PURPOSE_2[0], // [WR_DIS.KEY2_PURPOSE] wr_dis of KEY_PURPOSE_2
  605. NULL
  606. };
  607. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_3[] = {
  608. &WR_DIS_KEY_PURPOSE_3[0], // [WR_DIS.KEY3_PURPOSE] wr_dis of KEY_PURPOSE_3
  609. NULL
  610. };
  611. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_4[] = {
  612. &WR_DIS_KEY_PURPOSE_4[0], // [WR_DIS.KEY4_PURPOSE] wr_dis of KEY_PURPOSE_4
  613. NULL
  614. };
  615. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_5[] = {
  616. &WR_DIS_KEY_PURPOSE_5[0], // [WR_DIS.KEY5_PURPOSE] wr_dis of KEY_PURPOSE_5
  617. NULL
  618. };
  619. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SEC_DPA_LEVEL[] = {
  620. &WR_DIS_SEC_DPA_LEVEL[0], // [] wr_dis of SEC_DPA_LEVEL
  621. NULL
  622. };
  623. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CRYPT_DPA_ENABLE[] = {
  624. &WR_DIS_CRYPT_DPA_ENABLE[0], // [] wr_dis of CRYPT_DPA_ENABLE
  625. NULL
  626. };
  627. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[] = {
  628. &WR_DIS_SECURE_BOOT_EN[0], // [] wr_dis of SECURE_BOOT_EN
  629. NULL
  630. };
  631. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[] = {
  632. &WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[0], // [] wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE
  633. NULL
  634. };
  635. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ECDSA_FORCE_USE_HARDWARE_K[] = {
  636. &WR_DIS_ECDSA_FORCE_USE_HARDWARE_K[0], // [] wr_dis of ECDSA_FORCE_USE_HARDWARE_K
  637. NULL
  638. };
  639. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TPUW[] = {
  640. &WR_DIS_FLASH_TPUW[0], // [] wr_dis of FLASH_TPUW
  641. NULL
  642. };
  643. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MODE[] = {
  644. &WR_DIS_DIS_DOWNLOAD_MODE[0], // [] wr_dis of DIS_DOWNLOAD_MODE
  645. NULL
  646. };
  647. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DIRECT_BOOT[] = {
  648. &WR_DIS_DIS_DIRECT_BOOT[0], // [] wr_dis of DIS_DIRECT_BOOT
  649. NULL
  650. };
  651. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT[] = {
  652. &WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT[0], // [WR_DIS.DIS_USB_PRINT] wr_dis of DIS_USB_SERIAL_JTAG_ROM_PRINT
  653. NULL
  654. };
  655. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[] = {
  656. &WR_DIS_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[0], // [] wr_dis of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE
  657. NULL
  658. };
  659. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ENABLE_SECURITY_DOWNLOAD[] = {
  660. &WR_DIS_ENABLE_SECURITY_DOWNLOAD[0], // [] wr_dis of ENABLE_SECURITY_DOWNLOAD
  661. NULL
  662. };
  663. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_UART_PRINT_CONTROL[] = {
  664. &WR_DIS_UART_PRINT_CONTROL[0], // [] wr_dis of UART_PRINT_CONTROL
  665. NULL
  666. };
  667. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_SEND_RESUME[] = {
  668. &WR_DIS_FORCE_SEND_RESUME[0], // [] wr_dis of FORCE_SEND_RESUME
  669. NULL
  670. };
  671. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_VERSION[] = {
  672. &WR_DIS_SECURE_VERSION[0], // [] wr_dis of SECURE_VERSION
  673. NULL
  674. };
  675. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_DISABLE_FAST_WAKE[] = {
  676. &WR_DIS_SECURE_BOOT_DISABLE_FAST_WAKE[0], // [] wr_dis of SECURE_BOOT_DISABLE_FAST_WAKE
  677. NULL
  678. };
  679. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HYS_EN_PAD0[] = {
  680. &WR_DIS_HYS_EN_PAD0[0], // [] wr_dis of HYS_EN_PAD0
  681. NULL
  682. };
  683. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HYS_EN_PAD1[] = {
  684. &WR_DIS_HYS_EN_PAD1[0], // [] wr_dis of HYS_EN_PAD1
  685. NULL
  686. };
  687. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[] = {
  688. &WR_DIS_BLK1[0], // [] wr_dis of BLOCK1
  689. NULL
  690. };
  691. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC[] = {
  692. &WR_DIS_MAC[0], // [WR_DIS.MAC_FACTORY] wr_dis of MAC
  693. NULL
  694. };
  695. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC_EXT[] = {
  696. &WR_DIS_MAC_EXT[0], // [] wr_dis of MAC_EXT
  697. NULL
  698. };
  699. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RXIQ_VERSION[] = {
  700. &WR_DIS_RXIQ_VERSION[0], // [] wr_dis of RXIQ_VERSION
  701. NULL
  702. };
  703. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RXIQ_0[] = {
  704. &WR_DIS_RXIQ_0[0], // [] wr_dis of RXIQ_0
  705. NULL
  706. };
  707. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RXIQ_1[] = {
  708. &WR_DIS_RXIQ_1[0], // [] wr_dis of RXIQ_1
  709. NULL
  710. };
  711. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR[] = {
  712. &WR_DIS_WAFER_VERSION_MINOR[0], // [] wr_dis of WAFER_VERSION_MINOR
  713. NULL
  714. };
  715. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MAJOR[] = {
  716. &WR_DIS_WAFER_VERSION_MAJOR[0], // [] wr_dis of WAFER_VERSION_MAJOR
  717. NULL
  718. };
  719. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_WAFER_VERSION_MAJOR[] = {
  720. &WR_DIS_DISABLE_WAFER_VERSION_MAJOR[0], // [] wr_dis of DISABLE_WAFER_VERSION_MAJOR
  721. NULL
  722. };
  723. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_CAP[] = {
  724. &WR_DIS_FLASH_CAP[0], // [] wr_dis of FLASH_CAP
  725. NULL
  726. };
  727. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TEMP[] = {
  728. &WR_DIS_FLASH_TEMP[0], // [] wr_dis of FLASH_TEMP
  729. NULL
  730. };
  731. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_VENDOR[] = {
  732. &WR_DIS_FLASH_VENDOR[0], // [] wr_dis of FLASH_VENDOR
  733. NULL
  734. };
  735. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PKG_VERSION[] = {
  736. &WR_DIS_PKG_VERSION[0], // [] wr_dis of PKG_VERSION
  737. NULL
  738. };
  739. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[] = {
  740. &WR_DIS_SYS_DATA_PART1[0], // [] wr_dis of BLOCK2
  741. NULL
  742. };
  743. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[] = {
  744. &WR_DIS_OPTIONAL_UNIQUE_ID[0], // [] wr_dis of OPTIONAL_UNIQUE_ID
  745. NULL
  746. };
  747. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MINOR[] = {
  748. &WR_DIS_BLK_VERSION_MINOR[0], // [] wr_dis of BLK_VERSION_MINOR
  749. NULL
  750. };
  751. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MAJOR[] = {
  752. &WR_DIS_BLK_VERSION_MAJOR[0], // [] wr_dis of BLK_VERSION_MAJOR
  753. NULL
  754. };
  755. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_BLK_VERSION_MAJOR[] = {
  756. &WR_DIS_DISABLE_BLK_VERSION_MAJOR[0], // [] wr_dis of DISABLE_BLK_VERSION_MAJOR
  757. NULL
  758. };
  759. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMP_CALIB[] = {
  760. &WR_DIS_TEMP_CALIB[0], // [] wr_dis of TEMP_CALIB
  761. NULL
  762. };
  763. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN0[] = {
  764. &WR_DIS_ADC1_AVE_INITCODE_ATTEN0[0], // [] wr_dis of ADC1_AVE_INITCODE_ATTEN0
  765. NULL
  766. };
  767. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN1[] = {
  768. &WR_DIS_ADC1_AVE_INITCODE_ATTEN1[0], // [] wr_dis of ADC1_AVE_INITCODE_ATTEN1
  769. NULL
  770. };
  771. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN2[] = {
  772. &WR_DIS_ADC1_AVE_INITCODE_ATTEN2[0], // [] wr_dis of ADC1_AVE_INITCODE_ATTEN2
  773. NULL
  774. };
  775. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN3[] = {
  776. &WR_DIS_ADC1_AVE_INITCODE_ATTEN3[0], // [] wr_dis of ADC1_AVE_INITCODE_ATTEN3
  777. NULL
  778. };
  779. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN0[] = {
  780. &WR_DIS_ADC1_HI_DOUT_ATTEN0[0], // [] wr_dis of ADC1_HI_DOUT_ATTEN0
  781. NULL
  782. };
  783. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN1[] = {
  784. &WR_DIS_ADC1_HI_DOUT_ATTEN1[0], // [] wr_dis of ADC1_HI_DOUT_ATTEN1
  785. NULL
  786. };
  787. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN2[] = {
  788. &WR_DIS_ADC1_HI_DOUT_ATTEN2[0], // [] wr_dis of ADC1_HI_DOUT_ATTEN2
  789. NULL
  790. };
  791. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN3[] = {
  792. &WR_DIS_ADC1_HI_DOUT_ATTEN3[0], // [] wr_dis of ADC1_HI_DOUT_ATTEN3
  793. NULL
  794. };
  795. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[] = {
  796. &WR_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[0], // [] wr_dis of ADC1_CH0_ATTEN0_INITCODE_DIFF
  797. NULL
  798. };
  799. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[] = {
  800. &WR_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[0], // [] wr_dis of ADC1_CH1_ATTEN0_INITCODE_DIFF
  801. NULL
  802. };
  803. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[] = {
  804. &WR_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[0], // [] wr_dis of ADC1_CH2_ATTEN0_INITCODE_DIFF
  805. NULL
  806. };
  807. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[] = {
  808. &WR_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[0], // [] wr_dis of ADC1_CH3_ATTEN0_INITCODE_DIFF
  809. NULL
  810. };
  811. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH4_ATTEN0_INITCODE_DIFF[] = {
  812. &WR_DIS_ADC1_CH4_ATTEN0_INITCODE_DIFF[0], // [] wr_dis of ADC1_CH4_ATTEN0_INITCODE_DIFF
  813. NULL
  814. };
  815. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_USR_DATA[] = {
  816. &WR_DIS_BLOCK_USR_DATA[0], // [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA
  817. NULL
  818. };
  819. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CUSTOM_MAC[] = {
  820. &WR_DIS_CUSTOM_MAC[0], // [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC
  821. NULL
  822. };
  823. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY0[] = {
  824. &WR_DIS_BLOCK_KEY0[0], // [WR_DIS.KEY0] wr_dis of BLOCK_KEY0
  825. NULL
  826. };
  827. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY1[] = {
  828. &WR_DIS_BLOCK_KEY1[0], // [WR_DIS.KEY1] wr_dis of BLOCK_KEY1
  829. NULL
  830. };
  831. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY2[] = {
  832. &WR_DIS_BLOCK_KEY2[0], // [WR_DIS.KEY2] wr_dis of BLOCK_KEY2
  833. NULL
  834. };
  835. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY3[] = {
  836. &WR_DIS_BLOCK_KEY3[0], // [WR_DIS.KEY3] wr_dis of BLOCK_KEY3
  837. NULL
  838. };
  839. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY4[] = {
  840. &WR_DIS_BLOCK_KEY4[0], // [WR_DIS.KEY4] wr_dis of BLOCK_KEY4
  841. NULL
  842. };
  843. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY5[] = {
  844. &WR_DIS_BLOCK_KEY5[0], // [WR_DIS.KEY5] wr_dis of BLOCK_KEY5
  845. NULL
  846. };
  847. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2[] = {
  848. &WR_DIS_BLOCK_SYS_DATA2[0], // [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2
  849. NULL
  850. };
  851. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_EXCHG_PINS[] = {
  852. &WR_DIS_USB_EXCHG_PINS[0], // [] wr_dis of USB_EXCHG_PINS
  853. NULL
  854. };
  855. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_VDD_SPI_AS_GPIO[] = {
  856. &WR_DIS_VDD_SPI_AS_GPIO[0], // [] wr_dis of VDD_SPI_AS_GPIO
  857. NULL
  858. };
  859. const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SOFT_DIS_JTAG[] = {
  860. &WR_DIS_SOFT_DIS_JTAG[0], // [] wr_dis of SOFT_DIS_JTAG
  861. NULL
  862. };
  863. const esp_efuse_desc_t* ESP_EFUSE_RD_DIS[] = {
  864. &RD_DIS[0], // [] Disable reading from BlOCK4-10
  865. NULL
  866. };
  867. const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY0[] = {
  868. &RD_DIS_BLOCK_KEY0[0], // [RD_DIS.KEY0] rd_dis of BLOCK_KEY0
  869. NULL
  870. };
  871. const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY1[] = {
  872. &RD_DIS_BLOCK_KEY1[0], // [RD_DIS.KEY1] rd_dis of BLOCK_KEY1
  873. NULL
  874. };
  875. const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY2[] = {
  876. &RD_DIS_BLOCK_KEY2[0], // [RD_DIS.KEY2] rd_dis of BLOCK_KEY2
  877. NULL
  878. };
  879. const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY3[] = {
  880. &RD_DIS_BLOCK_KEY3[0], // [RD_DIS.KEY3] rd_dis of BLOCK_KEY3
  881. NULL
  882. };
  883. const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY4[] = {
  884. &RD_DIS_BLOCK_KEY4[0], // [RD_DIS.KEY4] rd_dis of BLOCK_KEY4
  885. NULL
  886. };
  887. const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY5[] = {
  888. &RD_DIS_BLOCK_KEY5[0], // [RD_DIS.KEY5] rd_dis of BLOCK_KEY5
  889. NULL
  890. };
  891. const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2[] = {
  892. &RD_DIS_BLOCK_SYS_DATA2[0], // [RD_DIS.SYS_DATA_PART2] rd_dis of BLOCK_SYS_DATA2
  893. NULL
  894. };
  895. const esp_efuse_desc_t* ESP_EFUSE_DIS_ICACHE[] = {
  896. &DIS_ICACHE[0], // [] Represents whether icache is disabled or enabled. 1: disabled. 0: enabled
  897. NULL
  898. };
  899. const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_JTAG[] = {
  900. &DIS_USB_JTAG[0], // [] Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled. 0: enabled
  901. NULL
  902. };
  903. const esp_efuse_desc_t* ESP_EFUSE_POWERGLITCH_EN[] = {
  904. &POWERGLITCH_EN[0], // [] Represents whether power glitch function is enabled. 1: enabled. 0: disabled
  905. NULL
  906. };
  907. const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[] = {
  908. &DIS_FORCE_DOWNLOAD[0], // [] Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled. 0: enabled
  909. NULL
  910. };
  911. const esp_efuse_desc_t* ESP_EFUSE_SPI_DOWNLOAD_MSPI_DIS[] = {
  912. &SPI_DOWNLOAD_MSPI_DIS[0], // [] Represents whether SPI0 controller during boot_mode_download is disabled or enabled. 1: disabled. 0: enabled
  913. NULL
  914. };
  915. const esp_efuse_desc_t* ESP_EFUSE_DIS_TWAI[] = {
  916. &DIS_TWAI[0], // [DIS_CAN] Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled
  917. NULL
  918. };
  919. const esp_efuse_desc_t* ESP_EFUSE_JTAG_SEL_ENABLE[] = {
  920. &JTAG_SEL_ENABLE[0], // [] Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio25 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0
  921. NULL
  922. };
  923. const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[] = {
  924. &SOFT_DIS_JTAG[0], // [] Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: enabled
  925. NULL
  926. };
  927. const esp_efuse_desc_t* ESP_EFUSE_DIS_PAD_JTAG[] = {
  928. &DIS_PAD_JTAG[0], // [] Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: enabled
  929. NULL
  930. };
  931. const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[] = {
  932. &DIS_DOWNLOAD_MANUAL_ENCRYPT[0], // [] Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled. 0: enabled
  933. NULL
  934. };
  935. const esp_efuse_desc_t* ESP_EFUSE_USB_EXCHG_PINS[] = {
  936. &USB_EXCHG_PINS[0], // [] Represents whether the D+ and D- pins is exchanged. 1: exchanged. 0: not exchanged
  937. NULL
  938. };
  939. const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_AS_GPIO[] = {
  940. &VDD_SPI_AS_GPIO[0], // [] Represents whether vdd spi pin is functioned as gpio. 1: functioned. 0: not functioned
  941. NULL
  942. };
  943. const esp_efuse_desc_t* ESP_EFUSE_WDT_DELAY_SEL[] = {
  944. &WDT_DELAY_SEL[0], // [] Represents whether RTC watchdog timeout threshold is selected at startup. 1: selected. 0: not selected
  945. NULL
  946. };
  947. const esp_efuse_desc_t* ESP_EFUSE_SPI_BOOT_CRYPT_CNT[] = {
  948. &SPI_BOOT_CRYPT_CNT[0], // [] Enables flash encryption when 1 or 3 bits are set and disables otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"}
  949. NULL
  950. };
  951. const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE0[] = {
  952. &SECURE_BOOT_KEY_REVOKE0[0], // [] Revoke 1st secure boot key
  953. NULL
  954. };
  955. const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE1[] = {
  956. &SECURE_BOOT_KEY_REVOKE1[0], // [] Revoke 2nd secure boot key
  957. NULL
  958. };
  959. const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE2[] = {
  960. &SECURE_BOOT_KEY_REVOKE2[0], // [] Revoke 3rd secure boot key
  961. NULL
  962. };
  963. const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_0[] = {
  964. &KEY_PURPOSE_0[0], // [KEY0_PURPOSE] Represents the purpose of Key0
  965. NULL
  966. };
  967. const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_1[] = {
  968. &KEY_PURPOSE_1[0], // [KEY1_PURPOSE] Represents the purpose of Key1
  969. NULL
  970. };
  971. const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_2[] = {
  972. &KEY_PURPOSE_2[0], // [KEY2_PURPOSE] Represents the purpose of Key2
  973. NULL
  974. };
  975. const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_3[] = {
  976. &KEY_PURPOSE_3[0], // [KEY3_PURPOSE] Represents the purpose of Key3
  977. NULL
  978. };
  979. const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_4[] = {
  980. &KEY_PURPOSE_4[0], // [KEY4_PURPOSE] Represents the purpose of Key4
  981. NULL
  982. };
  983. const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_5[] = {
  984. &KEY_PURPOSE_5[0], // [KEY5_PURPOSE] Represents the purpose of Key5
  985. NULL
  986. };
  987. const esp_efuse_desc_t* ESP_EFUSE_SEC_DPA_LEVEL[] = {
  988. &SEC_DPA_LEVEL[0], // [] Represents the spa secure level by configuring the clock random divide mode
  989. NULL
  990. };
  991. const esp_efuse_desc_t* ESP_EFUSE_ECDSA_FORCE_USE_HARDWARE_K[] = {
  992. &ECDSA_FORCE_USE_HARDWARE_K[0], // [] Represents whether hardware random number k is forced used in ESDCA. 1: force used. 0: not force used
  993. NULL
  994. };
  995. const esp_efuse_desc_t* ESP_EFUSE_CRYPT_DPA_ENABLE[] = {
  996. &CRYPT_DPA_ENABLE[0], // [] Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled
  997. NULL
  998. };
  999. const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[] = {
  1000. &SECURE_BOOT_EN[0], // [] Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled
  1001. NULL
  1002. };
  1003. const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[] = {
  1004. &SECURE_BOOT_AGGRESSIVE_REVOKE[0], // [] Represents whether revoking aggressive secure boot is enabled or disabled. 1: enabled. 0: disabled
  1005. NULL
  1006. };
  1007. const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[] = {
  1008. &FLASH_TPUW[0], // [] Represents the flash waiting time after power-up; in unit of ms. When the value less than 15; the waiting time is the programmed value. Otherwise; the waiting time is 2 times the programmed value
  1009. NULL
  1010. };
  1011. const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MODE[] = {
  1012. &DIS_DOWNLOAD_MODE[0], // [] Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled
  1013. NULL
  1014. };
  1015. const esp_efuse_desc_t* ESP_EFUSE_DIS_DIRECT_BOOT[] = {
  1016. &DIS_DIRECT_BOOT[0], // [] Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled
  1017. NULL
  1018. };
  1019. const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT[] = {
  1020. &DIS_USB_SERIAL_JTAG_ROM_PRINT[0], // [DIS_USB_PRINT] Set this bit to disable USB-Serial-JTAG print during rom boot
  1021. NULL
  1022. };
  1023. const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[] = {
  1024. &DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[0], // [] Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: disabled. 0: enabled
  1025. NULL
  1026. };
  1027. const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[] = {
  1028. &ENABLE_SECURITY_DOWNLOAD[0], // [] Represents whether security download is enabled or disabled. 1: enabled. 0: disabled
  1029. NULL
  1030. };
  1031. const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[] = {
  1032. &UART_PRINT_CONTROL[0], // [] Set the default UARTboot message output mode {0: "Enable"; 1: "Enable when GPIO8 is low at reset"; 2: "Enable when GPIO8 is high at reset"; 3: "Disable"}
  1033. NULL
  1034. };
  1035. const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[] = {
  1036. &FORCE_SEND_RESUME[0], // [] Represents whether ROM code is forced to send a resume command during SPI boot. 1: forced. 0:not forced
  1037. NULL
  1038. };
  1039. const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[] = {
  1040. &SECURE_VERSION[0], // [] Represents the version used by ESP-IDF anti-rollback feature
  1041. NULL
  1042. };
  1043. const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE[] = {
  1044. &SECURE_BOOT_DISABLE_FAST_WAKE[0], // [] Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled. 1: disabled. 0: enabled
  1045. NULL
  1046. };
  1047. const esp_efuse_desc_t* ESP_EFUSE_HYS_EN_PAD0[] = {
  1048. &HYS_EN_PAD0[0], // [] Set bits to enable hysteresis function of PAD0~5
  1049. NULL
  1050. };
  1051. const esp_efuse_desc_t* ESP_EFUSE_HYS_EN_PAD1[] = {
  1052. &HYS_EN_PAD1[0], // [] Set bits to enable hysteresis function of PAD6~27
  1053. NULL
  1054. };
  1055. const esp_efuse_desc_t* ESP_EFUSE_MAC[] = {
  1056. &MAC[0], // [MAC_FACTORY] MAC address
  1057. &MAC[1], // [MAC_FACTORY] MAC address
  1058. &MAC[2], // [MAC_FACTORY] MAC address
  1059. &MAC[3], // [MAC_FACTORY] MAC address
  1060. &MAC[4], // [MAC_FACTORY] MAC address
  1061. &MAC[5], // [MAC_FACTORY] MAC address
  1062. NULL
  1063. };
  1064. const esp_efuse_desc_t* ESP_EFUSE_MAC_EXT[] = {
  1065. &MAC_EXT[0], // [] Stores the extended bits of MAC address
  1066. &MAC_EXT[1], // [] Stores the extended bits of MAC address
  1067. NULL
  1068. };
  1069. const esp_efuse_desc_t* ESP_EFUSE_RXIQ_VERSION[] = {
  1070. &RXIQ_VERSION[0], // [] RF Calibration data. RXIQ version
  1071. NULL
  1072. };
  1073. const esp_efuse_desc_t* ESP_EFUSE_RXIQ_0[] = {
  1074. &RXIQ_0[0], // [] RF Calibration data. RXIQ data 0
  1075. NULL
  1076. };
  1077. const esp_efuse_desc_t* ESP_EFUSE_RXIQ_1[] = {
  1078. &RXIQ_1[0], // [] RF Calibration data. RXIQ data 1
  1079. NULL
  1080. };
  1081. const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[] = {
  1082. &WAFER_VERSION_MINOR[0], // []
  1083. NULL
  1084. };
  1085. const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[] = {
  1086. &WAFER_VERSION_MAJOR[0], // []
  1087. NULL
  1088. };
  1089. const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[] = {
  1090. &DISABLE_WAFER_VERSION_MAJOR[0], // [] Disables check of wafer version major
  1091. NULL
  1092. };
  1093. const esp_efuse_desc_t* ESP_EFUSE_FLASH_CAP[] = {
  1094. &FLASH_CAP[0], // []
  1095. NULL
  1096. };
  1097. const esp_efuse_desc_t* ESP_EFUSE_FLASH_TEMP[] = {
  1098. &FLASH_TEMP[0], // []
  1099. NULL
  1100. };
  1101. const esp_efuse_desc_t* ESP_EFUSE_FLASH_VENDOR[] = {
  1102. &FLASH_VENDOR[0], // []
  1103. NULL
  1104. };
  1105. const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[] = {
  1106. &PKG_VERSION[0], // [] Package version
  1107. NULL
  1108. };
  1109. const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[] = {
  1110. &OPTIONAL_UNIQUE_ID[0], // [] Optional unique 128-bit ID
  1111. NULL
  1112. };
  1113. const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[] = {
  1114. &BLK_VERSION_MINOR[0], // [] BLK_VERSION_MINOR of BLOCK2. 1: RF Calibration data in BLOCK1
  1115. NULL
  1116. };
  1117. const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[] = {
  1118. &BLK_VERSION_MAJOR[0], // [] BLK_VERSION_MAJOR of BLOCK2
  1119. NULL
  1120. };
  1121. const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[] = {
  1122. &DISABLE_BLK_VERSION_MAJOR[0], // [] Disables check of blk version major
  1123. NULL
  1124. };
  1125. const esp_efuse_desc_t* ESP_EFUSE_TEMP_CALIB[] = {
  1126. &TEMP_CALIB[0], // [] Temperature calibration data
  1127. NULL
  1128. };
  1129. const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN0[] = {
  1130. &ADC1_AVE_INITCODE_ATTEN0[0], // [] ADC1 calibration data
  1131. NULL
  1132. };
  1133. const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN1[] = {
  1134. &ADC1_AVE_INITCODE_ATTEN1[0], // [] ADC1 calibration data
  1135. NULL
  1136. };
  1137. const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN2[] = {
  1138. &ADC1_AVE_INITCODE_ATTEN2[0], // [] ADC1 calibration data
  1139. NULL
  1140. };
  1141. const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN3[] = {
  1142. &ADC1_AVE_INITCODE_ATTEN3[0], // [] ADC1 calibration data
  1143. NULL
  1144. };
  1145. const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN0[] = {
  1146. &ADC1_HI_DOUT_ATTEN0[0], // [] ADC1 calibration data
  1147. NULL
  1148. };
  1149. const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN1[] = {
  1150. &ADC1_HI_DOUT_ATTEN1[0], // [] ADC1 calibration data
  1151. NULL
  1152. };
  1153. const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN2[] = {
  1154. &ADC1_HI_DOUT_ATTEN2[0], // [] ADC1 calibration data
  1155. NULL
  1156. };
  1157. const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN3[] = {
  1158. &ADC1_HI_DOUT_ATTEN3[0], // [] ADC1 calibration data
  1159. NULL
  1160. };
  1161. const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF[] = {
  1162. &ADC1_CH0_ATTEN0_INITCODE_DIFF[0], // [] ADC1 calibration data
  1163. NULL
  1164. };
  1165. const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF[] = {
  1166. &ADC1_CH1_ATTEN0_INITCODE_DIFF[0], // [] ADC1 calibration data
  1167. NULL
  1168. };
  1169. const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF[] = {
  1170. &ADC1_CH2_ATTEN0_INITCODE_DIFF[0], // [] ADC1 calibration data
  1171. NULL
  1172. };
  1173. const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF[] = {
  1174. &ADC1_CH3_ATTEN0_INITCODE_DIFF[0], // [] ADC1 calibration data
  1175. NULL
  1176. };
  1177. const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF[] = {
  1178. &ADC1_CH4_ATTEN0_INITCODE_DIFF[0], // [] ADC1 calibration data
  1179. NULL
  1180. };
  1181. const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[] = {
  1182. &USER_DATA[0], // [BLOCK_USR_DATA] User data
  1183. NULL
  1184. };
  1185. const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[] = {
  1186. &USER_DATA_MAC_CUSTOM[0], // [MAC_CUSTOM CUSTOM_MAC] Custom MAC
  1187. NULL
  1188. };
  1189. const esp_efuse_desc_t* ESP_EFUSE_KEY0[] = {
  1190. &KEY0[0], // [BLOCK_KEY0] Key0 or user data
  1191. NULL
  1192. };
  1193. const esp_efuse_desc_t* ESP_EFUSE_KEY1[] = {
  1194. &KEY1[0], // [BLOCK_KEY1] Key1 or user data
  1195. NULL
  1196. };
  1197. const esp_efuse_desc_t* ESP_EFUSE_KEY2[] = {
  1198. &KEY2[0], // [BLOCK_KEY2] Key2 or user data
  1199. NULL
  1200. };
  1201. const esp_efuse_desc_t* ESP_EFUSE_KEY3[] = {
  1202. &KEY3[0], // [BLOCK_KEY3] Key3 or user data
  1203. NULL
  1204. };
  1205. const esp_efuse_desc_t* ESP_EFUSE_KEY4[] = {
  1206. &KEY4[0], // [BLOCK_KEY4] Key4 or user data
  1207. NULL
  1208. };
  1209. const esp_efuse_desc_t* ESP_EFUSE_KEY5[] = {
  1210. &KEY5[0], // [BLOCK_KEY5] Key5 or user data
  1211. NULL
  1212. };
  1213. const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART2[] = {
  1214. &SYS_DATA_PART2[0], // [BLOCK_SYS_DATA2] System data part 2 (reserved)
  1215. NULL
  1216. };