esp32c2.rom.ld 85 KB

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  1. /*
  2. * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. */
  6. /* ROM function interface esp32c2.rom.ld for esp32c2
  7. *
  8. *
  9. * Generated from ./interface-esp32c2.yml md5sum c679b6ed5e9f0a9c3e7b93e5e0f2a1a3
  10. *
  11. * Compatible with ROM where ECO version equal or greater to 1.
  12. *
  13. * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
  14. */
  15. /***************************************
  16. Group common
  17. ***************************************/
  18. /* Functions */
  19. rtc_get_reset_reason = 0x40000018;
  20. analog_super_wdt_reset_happened = 0x4000001c;
  21. rtc_get_wakeup_cause = 0x40000020;
  22. rtc_select_apb_bridge = 0x40000024;
  23. rtc_unhold_all_pads = 0x40000028;
  24. ets_is_print_boot = 0x4000002c;
  25. ets_vprintf = 0x40000030;
  26. ets_printf = 0x40000034;
  27. ets_install_putc1 = 0x40000038;
  28. ets_install_uart_printf = 0x4000003c;
  29. ets_install_putc2 = 0x40000040;
  30. ets_delay_us = 0x40000044;
  31. ets_get_stack_info = 0x40000048;
  32. ets_install_lock = 0x4000004c;
  33. UartRxString = 0x40000050;
  34. UartGetCmdLn = 0x40000054;
  35. uart_tx_one_char = 0x40000058;
  36. uart_tx_one_char2 = 0x4000005c;
  37. uart_rx_one_char = 0x40000060;
  38. uart_rx_one_char_block = 0x40000064;
  39. uart_rx_readbuff = 0x40000068;
  40. uartAttach = 0x4000006c;
  41. uart_tx_flush = 0x40000070;
  42. uart_tx_wait_idle = 0x40000074;
  43. uart_div_modify = 0x40000078;
  44. ets_write_char_uart = 0x4000007c;
  45. uart_tx_switch = 0x40000080;
  46. multofup = 0x40000084;
  47. software_reset = 0x40000088;
  48. software_reset_cpu = 0x4000008c;
  49. assist_debug_clock_enable = 0x40000090;
  50. assist_debug_record_enable = 0x40000094;
  51. clear_super_wdt_reset_flag = 0x40000098;
  52. disable_default_watchdog = 0x4000009c;
  53. send_packet = 0x400000a0;
  54. recv_packet = 0x400000a4;
  55. GetUartDevice = 0x400000a8;
  56. UartDwnLdProc = 0x400000ac;
  57. GetSecurityInfoProc = 0x400000b0;
  58. Uart_Init = 0x400000b4;
  59. ets_set_user_start = 0x400000b8;
  60. /* Data (.data, .bss, .rodata) */
  61. ets_rom_layout_p = 0x3ff4fffc;
  62. ets_ops_table_ptr = 0x3fcdfffc;
  63. /***************************************
  64. Group miniz
  65. ***************************************/
  66. /* Functions */
  67. mz_adler32 = 0x400000bc;
  68. mz_free = 0x400000c0;
  69. tdefl_compress = 0x400000c4;
  70. tdefl_compress_buffer = 0x400000c8;
  71. tdefl_compress_mem_to_heap = 0x400000cc;
  72. tdefl_compress_mem_to_mem = 0x400000d0;
  73. tdefl_compress_mem_to_output = 0x400000d4;
  74. tdefl_get_adler32 = 0x400000d8;
  75. tdefl_get_prev_return_status = 0x400000dc;
  76. tdefl_init = 0x400000e0;
  77. tdefl_write_image_to_png_file_in_memory = 0x400000e4;
  78. tdefl_write_image_to_png_file_in_memory_ex = 0x400000e8;
  79. tinfl_decompress = 0x400000ec;
  80. tinfl_decompress_mem_to_callback = 0x400000f0;
  81. tinfl_decompress_mem_to_heap = 0x400000f4;
  82. tinfl_decompress_mem_to_mem = 0x400000f8;
  83. /***************************************
  84. Group spiflash_legacy
  85. ***************************************/
  86. /* Functions */
  87. PROVIDE( esp_rom_spiflash_wait_idle = 0x400000fc );
  88. PROVIDE( esp_rom_spiflash_write_encrypted = 0x40000100 );
  89. PROVIDE( esp_rom_spiflash_write_encrypted_dest = 0x40000104 );
  90. PROVIDE( esp_rom_spiflash_write_encrypted_enable = 0x40000108 );
  91. PROVIDE( esp_rom_spiflash_write_encrypted_disable = 0x4000010c );
  92. PROVIDE( esp_rom_spiflash_erase_chip = 0x40000110 );
  93. PROVIDE( _esp_rom_spiflash_erase_sector = 0x40000114 );
  94. PROVIDE( _esp_rom_spiflash_erase_block = 0x40000118 );
  95. PROVIDE( _esp_rom_spiflash_write = 0x4000011c );
  96. PROVIDE( _esp_rom_spiflash_read = 0x40000120 );
  97. PROVIDE( _esp_rom_spiflash_unlock = 0x40000124 );
  98. PROVIDE( _SPIEraseArea = 0x40000128 );
  99. PROVIDE( _SPI_write_enable = 0x4000012c );
  100. PROVIDE( esp_rom_spiflash_erase_sector = 0x40000130 );
  101. PROVIDE( esp_rom_spiflash_erase_block = 0x40000134 );
  102. PROVIDE( esp_rom_spiflash_write = 0x40000138 );
  103. PROVIDE( esp_rom_spiflash_read = 0x4000013c );
  104. PROVIDE( esp_rom_spiflash_unlock = 0x40000140 );
  105. PROVIDE( SPIEraseArea = 0x40000144 );
  106. PROVIDE( SPI_write_enable = 0x40000148 );
  107. PROVIDE( esp_rom_spiflash_config_param = 0x4000014c );
  108. PROVIDE( esp_rom_spiflash_read_user_cmd = 0x40000150 );
  109. PROVIDE( esp_rom_spiflash_select_qio_pins = 0x40000154 );
  110. PROVIDE( esp_rom_spi_flash_auto_sus_res = 0x40000158 );
  111. PROVIDE( esp_rom_spi_flash_send_resume = 0x4000015c );
  112. PROVIDE( esp_rom_spi_flash_update_id = 0x40000160 );
  113. PROVIDE( esp_rom_spiflash_config_clk = 0x40000164 );
  114. PROVIDE( esp_rom_spiflash_config_readmode = 0x40000168 );
  115. PROVIDE( esp_rom_spiflash_read_status = 0x4000016c );
  116. PROVIDE( esp_rom_spiflash_read_statushigh = 0x40000170 );
  117. PROVIDE( esp_rom_spiflash_write_status = 0x40000174 );
  118. PROVIDE( spi_flash_attach = 0x40000178 );
  119. PROVIDE( spi_flash_get_chip_size = 0x4000017c );
  120. PROVIDE( spi_flash_guard_set = 0x40000180 );
  121. PROVIDE( spi_flash_guard_get = 0x40000184 );
  122. PROVIDE( spi_flash_read_encrypted = 0x40000188 );
  123. PROVIDE( spi_flash_mmap_os_func_set = 0x4000018c );
  124. PROVIDE( spi_flash_mmap_page_num_init = 0x40000190 );
  125. PROVIDE( spi_flash_mmap = 0x40000194 );
  126. PROVIDE( spi_flash_mmap_pages = 0x40000198 );
  127. PROVIDE( spi_flash_munmap = 0x4000019c );
  128. PROVIDE( spi_flash_mmap_dump = 0x400001a0 );
  129. PROVIDE( spi_flash_check_and_flush_cache = 0x400001a4 );
  130. PROVIDE( spi_flash_mmap_get_free_pages = 0x400001a8 );
  131. PROVIDE( spi_flash_cache2phys = 0x400001ac );
  132. PROVIDE( spi_flash_phys2cache = 0x400001b0 );
  133. PROVIDE( spi_flash_disable_cache = 0x400001b4 );
  134. PROVIDE( spi_flash_restore_cache = 0x400001b8 );
  135. PROVIDE( spi_flash_cache_enabled = 0x400001bc );
  136. PROVIDE( spi_flash_enable_cache = 0x400001c0 );
  137. PROVIDE( spi_cache_mode_switch = 0x400001c4 );
  138. PROVIDE( spi_common_set_dummy_output = 0x400001c8 );
  139. PROVIDE( spi_common_set_flash_cs_timing = 0x400001cc );
  140. PROVIDE( esp_rom_spi_set_address_bit_len = 0x400001d0 );
  141. PROVIDE( esp_enable_cache_flash_wrap = 0x400001d4 );
  142. PROVIDE( SPILock = 0x400001d8 );
  143. PROVIDE( SPIMasterReadModeCnfig = 0x400001dc );
  144. PROVIDE( SPI_Common_Command = 0x400001e0 );
  145. PROVIDE( SPI_WakeUp = 0x400001e4 );
  146. PROVIDE( SPI_block_erase = 0x400001e8 );
  147. PROVIDE( SPI_chip_erase = 0x400001ec );
  148. PROVIDE( SPI_init = 0x400001f0 );
  149. PROVIDE( SPI_page_program = 0x400001f4 );
  150. PROVIDE( SPI_read_data = 0x400001f8 );
  151. PROVIDE( SPI_sector_erase = 0x400001fc );
  152. PROVIDE( SelectSpiFunction = 0x40000200 );
  153. PROVIDE( SetSpiDrvs = 0x40000204 );
  154. PROVIDE( Wait_SPI_Idle = 0x40000208 );
  155. PROVIDE( spi_dummy_len_fix = 0x4000020c );
  156. PROVIDE( Disable_QMode = 0x40000210 );
  157. PROVIDE( Enable_QMode = 0x40000214 );
  158. /* Data (.data, .bss, .rodata) */
  159. PROVIDE( rom_spiflash_legacy_funcs = 0x3fcdfff4 );
  160. PROVIDE( rom_spiflash_legacy_data = 0x3fcdfff0 );
  161. PROVIDE( g_flash_guard_ops = 0x3fcdfff8 );
  162. /***************************************
  163. Group hal_soc
  164. ***************************************/
  165. /* Functions */
  166. PROVIDE( spi_flash_hal_poll_cmd_done = 0x40000218 );
  167. PROVIDE( spi_flash_hal_device_config = 0x4000021c );
  168. PROVIDE( spi_flash_hal_configure_host_io_mode = 0x40000220 );
  169. PROVIDE( spi_flash_hal_common_command = 0x40000224 );
  170. PROVIDE( spi_flash_hal_read = 0x40000228 );
  171. PROVIDE( spi_flash_hal_erase_chip = 0x4000022c );
  172. PROVIDE( spi_flash_hal_erase_sector = 0x40000230 );
  173. PROVIDE( spi_flash_hal_erase_block = 0x40000234 );
  174. PROVIDE( spi_flash_hal_program_page = 0x40000238 );
  175. PROVIDE( spi_flash_hal_set_write_protect = 0x4000023c );
  176. PROVIDE( spi_flash_hal_host_idle = 0x40000240 );
  177. PROVIDE( spi_flash_hal_check_status = 0x40000244 );
  178. PROVIDE( spi_flash_hal_setup_read_suspend = 0x40000248 );
  179. PROVIDE( spi_flash_hal_setup_auto_suspend_mode = 0x4000024c );
  180. PROVIDE( spi_flash_hal_setup_auto_resume_mode = 0x40000250 );
  181. PROVIDE( spi_flash_hal_disable_auto_suspend_mode = 0x40000254 );
  182. PROVIDE( spi_flash_hal_disable_auto_resume_mode = 0x40000258 );
  183. PROVIDE( spi_flash_hal_resume = 0x4000025c );
  184. PROVIDE( spi_flash_hal_suspend = 0x40000260 );
  185. PROVIDE( spi_flash_encryption_hal_enable = 0x40000264 );
  186. PROVIDE( spi_flash_encryption_hal_disable = 0x40000268 );
  187. PROVIDE( spi_flash_encryption_hal_prepare = 0x4000026c );
  188. PROVIDE( spi_flash_encryption_hal_done = 0x40000270 );
  189. PROVIDE( spi_flash_encryption_hal_destroy = 0x40000274 );
  190. PROVIDE( spi_flash_encryption_hal_check = 0x40000278 );
  191. PROVIDE( wdt_hal_init = 0x4000027c );
  192. PROVIDE( wdt_hal_deinit = 0x40000280 );
  193. PROVIDE( wdt_hal_config_stage = 0x40000284 );
  194. PROVIDE( wdt_hal_write_protect_disable = 0x40000288 );
  195. PROVIDE( wdt_hal_write_protect_enable = 0x4000028c );
  196. PROVIDE( wdt_hal_enable = 0x40000290 );
  197. PROVIDE( wdt_hal_disable = 0x40000294 );
  198. PROVIDE( wdt_hal_handle_intr = 0x40000298 );
  199. PROVIDE( wdt_hal_feed = 0x4000029c );
  200. PROVIDE( wdt_hal_set_flashboot_en = 0x400002a0 );
  201. PROVIDE( wdt_hal_is_enabled = 0x400002a4 );
  202. PROVIDE( systimer_hal_get_counter_value = 0x400002ac );
  203. PROVIDE( systimer_hal_get_alarm_value = 0x400002bc );
  204. PROVIDE( systimer_hal_enable_alarm_int = 0x400002c0 );
  205. PROVIDE( systimer_hal_enable_counter = 0x400002cc );
  206. PROVIDE( systimer_hal_select_alarm_mode = 0x400002d0 );
  207. PROVIDE( systimer_hal_connect_alarm_counter = 0x400002d4 );
  208. PROVIDE( systimer_hal_counter_can_stall_by_cpu = 0x400002d8 );
  209. /* The following ROM functions are commented out because they're patched in the esp_rom_systimer.c */
  210. /* PROVIDE( systimer_hal_init = 0x400002a8 ); */
  211. /* PROVIDE( systimer_hal_get_time = 0x400002b0 ); */
  212. /* PROVIDE( systimer_hal_set_alarm_target = 0x400002b4 ); */
  213. /* PROVIDE( systimer_hal_set_alarm_period = 0x400002b8 ); */
  214. /* PROVIDE( systimer_hal_counter_value_advance = 0x400002c8 ); */
  215. /***************************************
  216. Group heap
  217. ***************************************/
  218. /* Functions */
  219. PROVIDE( tlsf_create = 0x400002dc );
  220. PROVIDE( tlsf_create_with_pool = 0x400002e0 );
  221. PROVIDE( tlsf_get_pool = 0x400002e4 );
  222. PROVIDE( tlsf_add_pool = 0x400002e8 );
  223. PROVIDE( tlsf_remove_pool = 0x400002ec );
  224. PROVIDE( tlsf_malloc = 0x400002f0 );
  225. PROVIDE( tlsf_memalign = 0x400002f4 );
  226. PROVIDE( tlsf_memalign_offs = 0x400002f8 );
  227. PROVIDE( tlsf_realloc = 0x400002fc );
  228. PROVIDE( tlsf_free = 0x40000300 );
  229. PROVIDE( tlsf_block_size = 0x40000304 );
  230. PROVIDE( tlsf_size = 0x40000308 );
  231. PROVIDE( tlsf_align_size = 0x4000030c );
  232. PROVIDE( tlsf_block_size_min = 0x40000310 );
  233. PROVIDE( tlsf_block_size_max = 0x40000314 );
  234. PROVIDE( tlsf_pool_overhead = 0x40000318 );
  235. PROVIDE( tlsf_alloc_overhead = 0x4000031c );
  236. PROVIDE( tlsf_walk_pool = 0x40000320 );
  237. PROVIDE( tlsf_check = 0x40000324 );
  238. PROVIDE( tlsf_check_pool = 0x40000328 );
  239. PROVIDE( tlsf_poison_fill_pfunc_set = 0x4000032c );
  240. PROVIDE( multi_heap_get_block_address_impl = 0x40000330 );
  241. PROVIDE( multi_heap_get_allocated_size_impl = 0x40000334 );
  242. PROVIDE( multi_heap_register_impl = 0x40000338 );
  243. PROVIDE( multi_heap_set_lock = 0x4000033c );
  244. PROVIDE( multi_heap_os_funcs_init = 0x40000340 );
  245. PROVIDE( multi_heap_internal_lock = 0x40000344 );
  246. PROVIDE( multi_heap_internal_unlock = 0x40000348 );
  247. PROVIDE( multi_heap_get_first_block = 0x4000034c );
  248. PROVIDE( multi_heap_get_next_block = 0x40000350 );
  249. PROVIDE( multi_heap_is_free = 0x40000354 );
  250. PROVIDE( multi_heap_malloc_impl = 0x40000358 );
  251. PROVIDE( multi_heap_free_impl = 0x4000035c );
  252. PROVIDE( multi_heap_realloc_impl = 0x40000360 );
  253. PROVIDE( multi_heap_aligned_alloc_impl_offs = 0x40000364 );
  254. PROVIDE( multi_heap_aligned_alloc_impl = 0x40000368 );
  255. PROVIDE( multi_heap_check = 0x4000036c );
  256. PROVIDE( multi_heap_dump = 0x40000370 );
  257. PROVIDE( multi_heap_free_size_impl = 0x40000374 );
  258. PROVIDE( multi_heap_minimum_free_size_impl = 0x40000378 );
  259. PROVIDE( multi_heap_get_info_impl = 0x4000037c );
  260. /* Data (.data, .bss, .rodata) */
  261. PROVIDE( heap_tlsf_table_ptr = 0x3fcdffec );
  262. /***************************************
  263. Group spi_flash_chips
  264. ***************************************/
  265. /* Functions */
  266. PROVIDE( spi_flash_chip_generic_probe = 0x40000380 );
  267. PROVIDE( spi_flash_chip_generic_detect_size = 0x40000384 );
  268. PROVIDE( spi_flash_chip_generic_write = 0x40000388 );
  269. PROVIDE( spi_flash_chip_generic_write_encrypted = 0x4000038c );
  270. PROVIDE( spi_flash_chip_generic_set_write_protect = 0x40000390 );
  271. PROVIDE( spi_flash_common_write_status_16b_wrsr = 0x40000394 );
  272. PROVIDE( spi_flash_chip_generic_reset = 0x40000398 );
  273. PROVIDE( spi_flash_chip_generic_erase_chip = 0x4000039c );
  274. PROVIDE( spi_flash_chip_generic_erase_sector = 0x400003a0 );
  275. PROVIDE( spi_flash_chip_generic_erase_block = 0x400003a4 );
  276. PROVIDE( spi_flash_chip_generic_page_program = 0x400003a8 );
  277. PROVIDE( spi_flash_chip_generic_get_write_protect = 0x400003ac );
  278. PROVIDE( spi_flash_common_read_status_16b_rdsr_rdsr2 = 0x400003b0 );
  279. PROVIDE( spi_flash_chip_generic_read_reg = 0x400003b4 );
  280. PROVIDE( spi_flash_chip_generic_yield = 0x400003b8 );
  281. PROVIDE( spi_flash_generic_wait_host_idle = 0x400003bc );
  282. PROVIDE( spi_flash_chip_generic_wait_idle = 0x400003c0 );
  283. PROVIDE( spi_flash_chip_generic_config_host_io_mode = 0x400003c4 );
  284. PROVIDE( spi_flash_chip_generic_read = 0x400003c8 );
  285. PROVIDE( spi_flash_common_read_status_8b_rdsr2 = 0x400003cc );
  286. PROVIDE( spi_flash_chip_generic_get_io_mode = 0x400003d0 );
  287. PROVIDE( spi_flash_common_read_status_8b_rdsr = 0x400003d4 );
  288. PROVIDE( spi_flash_common_write_status_8b_wrsr = 0x400003d8 );
  289. PROVIDE( spi_flash_common_write_status_8b_wrsr2 = 0x400003dc );
  290. PROVIDE( spi_flash_common_set_io_mode = 0x400003e0 );
  291. PROVIDE( spi_flash_chip_generic_set_io_mode = 0x400003e4 );
  292. PROVIDE( spi_flash_chip_generic_read_unique_id = 0x400003e8 );
  293. PROVIDE( spi_flash_chip_generic_get_caps = 0x400003ec );
  294. PROVIDE( spi_flash_chip_generic_suspend_cmd_conf = 0x400003f0 );
  295. PROVIDE( spi_flash_chip_gd_get_io_mode = 0x400003f4 );
  296. PROVIDE( spi_flash_chip_gd_probe = 0x400003f8 );
  297. PROVIDE( spi_flash_chip_gd_set_io_mode = 0x400003fc );
  298. /* Data (.data, .bss, .rodata) */
  299. PROVIDE( spi_flash_chip_generic_config_data = 0x3fcdffe8 );
  300. PROVIDE( spi_flash_encryption = 0x3fcdffe4 );
  301. /***************************************
  302. Group memspi_host
  303. ***************************************/
  304. /* Functions */
  305. PROVIDE( memspi_host_read_id_hs = 0x40000400 );
  306. PROVIDE( memspi_host_read_status_hs = 0x40000404 );
  307. PROVIDE( memspi_host_flush_cache = 0x40000408 );
  308. PROVIDE( memspi_host_erase_chip = 0x4000040c );
  309. PROVIDE( memspi_host_erase_sector = 0x40000410 );
  310. PROVIDE( memspi_host_erase_block = 0x40000414 );
  311. PROVIDE( memspi_host_program_page = 0x40000418 );
  312. PROVIDE( memspi_host_read = 0x4000041c );
  313. PROVIDE( memspi_host_set_write_protect = 0x40000420 );
  314. PROVIDE( memspi_host_set_max_read_len = 0x40000424 );
  315. PROVIDE( memspi_host_read_data_slicer = 0x40000428 );
  316. PROVIDE( memspi_host_write_data_slicer = 0x4000042c );
  317. /***************************************
  318. Group esp_flash
  319. ***************************************/
  320. /* Functions */
  321. PROVIDE( esp_flash_chip_driver_initialized = 0x40000430 );
  322. PROVIDE( esp_flash_read_id = 0x40000434 );
  323. PROVIDE( esp_flash_get_size = 0x40000438 );
  324. PROVIDE( esp_flash_erase_chip = 0x4000043c );
  325. PROVIDE( esp_flash_erase_region = 0x40000440 );
  326. PROVIDE( esp_flash_get_chip_write_protect = 0x40000444 );
  327. PROVIDE( esp_flash_set_chip_write_protect = 0x40000448 );
  328. PROVIDE( esp_flash_get_protectable_regions = 0x4000044c );
  329. PROVIDE( esp_flash_get_protected_region = 0x40000450 );
  330. PROVIDE( esp_flash_set_protected_region = 0x40000454 );
  331. PROVIDE( esp_flash_read = 0x40000458 );
  332. PROVIDE( esp_flash_write = 0x4000045c );
  333. PROVIDE( esp_flash_write_encrypted = 0x40000460 );
  334. PROVIDE( esp_flash_read_encrypted = 0x40000464 );
  335. PROVIDE( esp_flash_get_io_mode = 0x40000468 );
  336. PROVIDE( esp_flash_set_io_mode = 0x4000046c );
  337. PROVIDE( spi_flash_boot_attach = 0x40000470 );
  338. PROVIDE( esp_flash_read_chip_id = 0x40000474 );
  339. PROVIDE( detect_spi_flash_chip = 0x40000478 );
  340. PROVIDE( esp_rom_spiflash_write_disable = 0x4000047c );
  341. PROVIDE( esp_flash_suspend_cmd_init = 0x40000480 );
  342. /* Data (.data, .bss, .rodata) */
  343. PROVIDE( esp_flash_default_chip = 0x3fcdffe0 );
  344. PROVIDE( esp_flash_api_funcs = 0x3fcdffdc );
  345. /***************************************
  346. Group cache
  347. ***************************************/
  348. /* Functions */
  349. PROVIDE( Cache_Get_ICache_Line_Size = 0x400006e0 );
  350. PROVIDE( Cache_Get_Mode = 0x400006e4 );
  351. PROVIDE( Cache_Address_Through_IBus = 0x400006e8 );
  352. PROVIDE( Cache_Address_Through_DBus = 0x400006ec );
  353. PROVIDE( Cache_Set_Default_Mode = 0x400006f0 );
  354. PROVIDE( Cache_Enable_Defalut_ICache_Mode = 0x400006f4 );
  355. PROVIDE( ROM_Boot_Cache_Init = 0x400006f8 );
  356. PROVIDE( MMU_Set_Page_Mode = 0x400006fc );
  357. PROVIDE( MMU_Get_Page_Mode = 0x40000700 );
  358. PROVIDE( Cache_Invalidate_ICache_Items = 0x40000704 );
  359. PROVIDE( Cache_Op_Addr = 0x40000708 );
  360. PROVIDE( Cache_Invalidate_Addr = 0x4000070c );
  361. PROVIDE( Cache_Invalidate_ICache_All = 0x40000710 );
  362. PROVIDE( Cache_Mask_All = 0x40000714 );
  363. PROVIDE( Cache_UnMask_Dram0 = 0x40000718 );
  364. PROVIDE( Cache_Disable_ICache = 0x4000071c );
  365. PROVIDE( Cache_Enable_ICache = 0x40000720 );
  366. PROVIDE( Cache_Suspend_ICache = 0x40000724 );
  367. PROVIDE( Cache_Resume_ICache = 0x40000728 );
  368. PROVIDE( Cache_Freeze_ICache_Enable = 0x4000072c );
  369. PROVIDE( Cache_Freeze_ICache_Disable = 0x40000730 );
  370. PROVIDE( Cache_Set_IDROM_MMU_Size = 0x40000734 );
  371. PROVIDE( Cache_Get_IROM_MMU_End = 0x40000738 );
  372. PROVIDE( Cache_Get_DROM_MMU_End = 0x4000073c );
  373. PROVIDE( Cache_Owner_Init = 0x40000740 );
  374. PROVIDE( Cache_Occupy_ICache_MEMORY = 0x40000744 );
  375. PROVIDE( Cache_MMU_Init = 0x40000748 );
  376. PROVIDE( Cache_Ibus_MMU_Set = 0x4000074c );
  377. PROVIDE( Cache_Dbus_MMU_Set = 0x40000750 );
  378. PROVIDE( Cache_Count_Flash_Pages = 0x40000754 );
  379. PROVIDE( Cache_Travel_Tag_Memory = 0x40000758 );
  380. PROVIDE( Cache_Get_Virtual_Addr = 0x4000075c );
  381. PROVIDE( Cache_Get_Memory_BaseAddr = 0x40000760 );
  382. PROVIDE( Cache_Get_Memory_Addr = 0x40000764 );
  383. PROVIDE( Cache_Get_Memory_value = 0x40000768 );
  384. /* Data (.data, .bss, .rodata) */
  385. PROVIDE( rom_cache_op_cb = 0x3fcdffd0 );
  386. PROVIDE( rom_cache_internal_table_ptr = 0x3fcdffcc );
  387. /***************************************
  388. Group clock
  389. ***************************************/
  390. /* Functions */
  391. ets_get_apb_freq = 0x4000076c;
  392. ets_get_cpu_frequency = 0x40000770;
  393. ets_update_cpu_frequency = 0x40000774;
  394. ets_get_printf_channel = 0x40000778;
  395. ets_get_xtal_div = 0x4000077c;
  396. ets_set_xtal_div = 0x40000780;
  397. ets_get_xtal_freq = 0x40000784;
  398. /***************************************
  399. Group gpio
  400. ***************************************/
  401. /* Functions */
  402. gpio_input_get = 0x40000788;
  403. gpio_matrix_in = 0x4000078c;
  404. gpio_matrix_out = 0x40000790;
  405. gpio_output_disable = 0x40000794;
  406. gpio_output_enable = 0x40000798;
  407. gpio_output_set = 0x4000079c;
  408. gpio_pad_hold = 0x400007a0;
  409. gpio_pad_input_disable = 0x400007a4;
  410. gpio_pad_input_enable = 0x400007a8;
  411. gpio_pad_pulldown = 0x400007ac;
  412. gpio_pad_pullup = 0x400007b0;
  413. gpio_pad_select_gpio = 0x400007b4;
  414. gpio_pad_set_drv = 0x400007b8;
  415. gpio_pad_unhold = 0x400007bc;
  416. gpio_pin_wakeup_disable = 0x400007c0;
  417. gpio_pin_wakeup_enable = 0x400007c4;
  418. gpio_bypass_matrix_in = 0x400007c8;
  419. /***************************************
  420. Group interrupts
  421. ***************************************/
  422. /* Functions */
  423. esprv_intc_int_set_priority = 0x400007cc;
  424. esprv_intc_int_set_threshold = 0x400007d0;
  425. esprv_intc_int_enable = 0x400007d4;
  426. esprv_intc_int_disable = 0x400007d8;
  427. esprv_intc_int_set_type = 0x400007dc;
  428. PROVIDE( intr_handler_set = 0x400007e0 );
  429. intr_matrix_set = 0x400007e4;
  430. ets_intr_lock = 0x400007e8;
  431. ets_intr_unlock = 0x400007ec;
  432. ets_isr_attach = 0x400007f0;
  433. ets_isr_mask = 0x400007f4;
  434. ets_isr_unmask = 0x400007f8;
  435. /***************************************
  436. Group crypto
  437. ***************************************/
  438. /* Functions */
  439. crc32_le = 0x400007fc;
  440. crc16_le = 0x40000800;
  441. crc8_le = 0x40000804;
  442. crc32_be = 0x40000808;
  443. crc16_be = 0x4000080c;
  444. crc8_be = 0x40000810;
  445. esp_crc8 = 0x40000814;
  446. ets_sha_enable = 0x40000818;
  447. ets_sha_disable = 0x4000081c;
  448. ets_sha_get_state = 0x40000820;
  449. ets_sha_init = 0x40000824;
  450. ets_sha_process = 0x40000828;
  451. ets_sha_starts = 0x4000082c;
  452. ets_sha_update = 0x40000830;
  453. ets_sha_finish = 0x40000834;
  454. ets_sha_clone = 0x40000838;
  455. /* Data (.data, .bss, .rodata) */
  456. crc32_le_table_ptr = 0x3ff4fff8;
  457. crc16_le_table_ptr = 0x3ff4fff4;
  458. crc8_le_table_ptr = 0x3ff4fff0;
  459. crc32_be_table_ptr = 0x3ff4ffec;
  460. crc16_be_table_ptr = 0x3ff4ffe8;
  461. crc8_be_table_ptr = 0x3ff4ffe4;
  462. /***************************************
  463. Group efuse
  464. ***************************************/
  465. /* Functions */
  466. ets_efuse_read = 0x4000083c;
  467. ets_efuse_program = 0x40000840;
  468. ets_efuse_clear_program_registers = 0x40000844;
  469. ets_efuse_write_key = 0x40000848;
  470. ets_efuse_get_read_register_address = 0x4000084c;
  471. ets_efuse_get_key_purpose = 0x40000850;
  472. ets_efuse_key_block_unused = 0x40000854;
  473. ets_efuse_find_unused_key_block = 0x40000858;
  474. ets_efuse_rs_calculate = 0x4000085c;
  475. ets_efuse_count_unused_key_blocks = 0x40000860;
  476. ets_efuse_secure_boot_enabled = 0x40000864;
  477. ets_efuse_secure_boot_aggressive_revoke_enabled = 0x40000868;
  478. ets_efuse_cache_encryption_enabled = 0x4000086c;
  479. ets_efuse_download_modes_disabled = 0x40000870;
  480. ets_efuse_find_purpose = 0x40000874;
  481. ets_efuse_force_send_resume = 0x40000878;
  482. ets_efuse_get_flash_delay_us = 0x4000087c;
  483. ets_efuse_get_mac = 0x40000880;
  484. ets_efuse_get_uart_print_control = 0x40000884;
  485. ets_efuse_direct_boot_mode_disabled = 0x40000888;
  486. ets_efuse_security_download_modes_enabled = 0x4000088c;
  487. ets_efuse_set_timing = 0x40000890;
  488. ets_efuse_jtag_disabled = 0x40000894;
  489. /***************************************
  490. Group secureboot
  491. ***************************************/
  492. /* Functions */
  493. ets_ecdsa_verify = 0x40000898;
  494. ets_secure_boot_verify_bootloader_with_keys = 0x4000089c;
  495. ets_secure_boot_verify_signature = 0x400008a0;
  496. ets_secure_boot_read_key_digests = 0x400008a4;
  497. /***************************************
  498. Group usb_uart
  499. ***************************************/
  500. /* Data (.data, .bss, .rodata) */
  501. g_uart_print = 0x3fcdffc9;
  502. g_usb_print = 0x3fcdffc8;
  503. /***************************************
  504. Group bluetooth
  505. ***************************************/
  506. /* Functions */
  507. ble_controller_rom_data_init = 0x40000aa8;
  508. ble_osi_coex_funcs_register = 0x40000aac;
  509. bt_rf_coex_cfg_get_default = 0x40000ab0;
  510. bt_rf_coex_dft_pti_get_default = 0x40000ab4;
  511. bt_rf_coex_hooks_p_set = 0x40000ab8;
  512. r__os_mbuf_copypkthdr = 0x40000abc;
  513. r_ble_controller_get_rom_compile_version = 0x40000ac4;
  514. r_ble_hci_ram_reset = 0x40000ad8;
  515. r_ble_hci_ram_set_acl_free_cb = 0x40000adc;
  516. r_ble_hci_trans_acl_buf_alloc = 0x40000ae0;
  517. r_ble_hci_trans_buf_alloc = 0x40000ae4;
  518. r_ble_hci_trans_buf_free = 0x40000ae8;
  519. r_ble_hci_trans_cfg_hs = 0x40000aec;
  520. r_ble_hci_trans_cfg_ll = 0x40000af0;
  521. r_ble_hci_trans_init = 0x40000afc;
  522. r_ble_hci_uart_acl_tx = 0x40000b00;
  523. r_ble_hci_uart_cmdevt_tx = 0x40000b04;
  524. r_ble_hci_uart_config = 0x40000b08;
  525. r_ble_hci_uart_free_pkt = 0x40000b0c;
  526. r_ble_hci_uart_rx_acl = 0x40000b20;
  527. r_ble_hci_uart_rx_char = 0x40000b24;
  528. r_ble_hci_uart_rx_cmd = 0x40000b28;
  529. r_ble_hci_uart_rx_evt = 0x40000b2c;
  530. r_ble_hci_uart_rx_evt_cb = 0x40000b30;
  531. r_ble_hci_uart_rx_le_evt = 0x40000b34;
  532. r_ble_hci_uart_rx_pkt_type = 0x40000b38;
  533. r_ble_hci_uart_rx_skip_acl = 0x40000b3c;
  534. r_ble_hci_uart_rx_skip_cmd = 0x40000b40;
  535. r_ble_hci_uart_rx_skip_evt = 0x40000b44;
  536. r_ble_hci_uart_rx_sync_loss = 0x40000b48;
  537. r_ble_hci_uart_set_acl_free_cb = 0x40000b4c;
  538. r_ble_hci_uart_sync_lost = 0x40000b50;
  539. r_ble_hci_uart_trans_reset = 0x40000b54;
  540. r_ble_hci_uart_tx_char = 0x40000b58;
  541. r_ble_hci_uart_tx_pkt_type = 0x40000b5c;
  542. r_ble_hw_encrypt_block = 0x40000b68;
  543. r_ble_hw_get_public_addr = 0x40000b6c;
  544. r_ble_hw_get_static_addr = 0x40000b70;
  545. r_ble_hw_periodiclist_add = 0x40000b74;
  546. r_ble_hw_periodiclist_clear = 0x40000b78;
  547. r_ble_hw_periodiclist_rmv = 0x40000b7c;
  548. r_ble_hw_resolv_list_cur_entry = 0x40000b80;
  549. r_ble_hw_resolv_list_set = 0x40000b88;
  550. r_ble_hw_rng_init = 0x40000b8c;
  551. r_ble_hw_rng_start = 0x40000b90;
  552. r_ble_hw_rng_stop = 0x40000b94;
  553. r_ble_hw_rx_local_is_resolved = 0x40000b98;
  554. r_ble_hw_rx_local_is_rpa = 0x40000b9c;
  555. r_ble_hw_whitelist_add = 0x40000ba0;
  556. r_ble_hw_whitelist_dev_num = 0x40000ba8;
  557. r_ble_hw_whitelist_get_base = 0x40000bac;
  558. r_ble_hw_whitelist_search = 0x40000bb4;
  559. r_ble_hw_whitelist_sort = 0x40000bb8;
  560. r_ble_ll_acl_data_in = 0x40000bbc;
  561. r_ble_ll_addr_is_id = 0x40000bc0;
  562. r_ble_ll_addr_subtype = 0x40000bc4;
  563. r_ble_ll_adv_active_chanset_clear = 0x40000bc8;
  564. r_ble_ll_adv_active_chanset_is_pri = 0x40000bcc;
  565. r_ble_ll_adv_active_chanset_is_sec = 0x40000bd0;
  566. r_ble_ll_adv_active_chanset_set_pri = 0x40000bd4;
  567. r_ble_ll_adv_active_chanset_set_sec = 0x40000bd8;
  568. r_ble_ll_adv_aux_calculate = 0x40000bdc;
  569. r_ble_ll_adv_aux_conn_rsp_pdu_make = 0x40000be0;
  570. r_ble_ll_adv_aux_pdu_make = 0x40000be4;
  571. r_ble_ll_adv_aux_scannable_pdu_make = 0x40000be8;
  572. r_ble_ll_adv_aux_txed = 0x40000bec;
  573. r_ble_ll_adv_can_chg_whitelist = 0x40000bf0;
  574. r_ble_ll_adv_chk_rpa_timeout = 0x40000bf4;
  575. r_ble_ll_adv_clear_all = 0x40000bf8;
  576. r_ble_ll_adv_conn_req_rxd = 0x40000bfc;
  577. r_ble_ll_adv_enabled = 0x40000c04;
  578. r_ble_ll_adv_ext_set_adv_data = 0x40000c0c;
  579. r_ble_ll_adv_ext_set_scan_rsp = 0x40000c18;
  580. r_ble_ll_adv_final_chan = 0x40000c1c;
  581. r_ble_ll_adv_first_chan = 0x40000c20;
  582. r_ble_ll_adv_flags_clear = 0x40000c24;
  583. r_ble_ll_adv_flags_set = 0x40000c28;
  584. r_ble_ll_adv_get_chan_num = 0x40000c2c;
  585. r_ble_ll_adv_get_local_rpa = 0x40000c30;
  586. r_ble_ll_adv_get_peer_rpa = 0x40000c34;
  587. r_ble_ll_adv_hci_set_random_addr = 0x40000c38;
  588. r_ble_ll_adv_init = 0x40000c3c;
  589. r_ble_ll_adv_legacy_pdu_make = 0x40000c40;
  590. r_ble_ll_adv_next_chan = 0x40000c44;
  591. r_ble_ll_adv_pdu_make = 0x40000c48;
  592. r_ble_ll_adv_periodic_check_data_itvl = 0x40000c4c;
  593. r_ble_ll_adv_periodic_estimate_data_itvl = 0x40000c54;
  594. r_ble_ll_adv_periodic_send_sync_ind = 0x40000c58;
  595. r_ble_ll_adv_periodic_set_info_transfer = 0x40000c60;
  596. r_ble_ll_adv_periodic_set_param = 0x40000c64;
  597. r_ble_ll_adv_pre_process = 0x40000c68;
  598. r_ble_ll_adv_put_acad_chM_update_ind = 0x40000c6c;
  599. r_ble_ll_adv_put_aux_ptr = 0x40000c70;
  600. r_ble_ll_adv_put_syncinfo = 0x40000c74;
  601. r_ble_ll_adv_rd_max_adv_data_len = 0x40000c78;
  602. r_ble_ll_adv_rd_sup_adv_sets = 0x40000c7c;
  603. r_ble_ll_adv_read_txpwr = 0x40000c80;
  604. r_ble_ll_adv_rpa_timeout = 0x40000c8c;
  605. r_ble_ll_adv_rpa_update = 0x40000c90;
  606. r_ble_ll_adv_scan_req_rxd = 0x40000c98;
  607. r_ble_ll_adv_scan_rsp_legacy_pdu_make = 0x40000c9c;
  608. r_ble_ll_adv_scan_rsp_pdu_make = 0x40000ca0;
  609. r_ble_ll_adv_scheduled = 0x40000ca4;
  610. r_ble_ll_adv_send_conn_comp_ev = 0x40000ca8;
  611. r_ble_ll_adv_set_adv_params = 0x40000cb0;
  612. r_ble_ll_adv_set_enable = 0x40000cb4;
  613. r_ble_ll_adv_set_random_addr = 0x40000cb8;
  614. r_ble_ll_adv_sm_deinit = 0x40000cc4;
  615. r_ble_ll_adv_sm_event_init = 0x40000cc8;
  616. r_ble_ll_adv_sm_find_configured = 0x40000ccc;
  617. r_ble_ll_adv_sm_get = 0x40000cd0;
  618. r_ble_ll_adv_sm_reset = 0x40000cd8;
  619. r_ble_ll_adv_sm_start = 0x40000cdc;
  620. r_ble_ll_adv_sm_start_periodic = 0x40000ce0;
  621. r_ble_ll_adv_sm_stop = 0x40000ce4;
  622. r_ble_ll_adv_sm_stop_limit_reached = 0x40000ce8;
  623. r_ble_ll_adv_sm_stop_periodic = 0x40000cec;
  624. r_ble_ll_adv_sm_stop_timeout = 0x40000cf0;
  625. r_ble_ll_adv_sync_get_pdu_len = 0x40000cf8;
  626. r_ble_ll_adv_update_adv_scan_rsp_data = 0x40000d00;
  627. r_ble_ll_adv_update_data_mbuf = 0x40000d04;
  628. r_ble_ll_adv_update_did = 0x40000d08;
  629. r_ble_ll_adv_update_periodic_data = 0x40000d0c;
  630. r_ble_ll_auth_pyld_tmo_event_send = 0x40000d14;
  631. r_ble_ll_calc_offset_ticks_us_for_rampup = 0x40000d18;
  632. r_ble_ll_calc_session_key = 0x40000d1c;
  633. r_ble_ll_calc_ticks_per_slot = 0x40000d20;
  634. r_ble_ll_check_scan_params = 0x40000d24;
  635. r_ble_ll_chk_txrx_octets = 0x40000d28;
  636. r_ble_ll_chk_txrx_time = 0x40000d2c;
  637. r_ble_ll_conn_adjust_pyld_len = 0x40000d30;
  638. r_ble_ll_conn_auth_pyld_timer_cb = 0x40000d34;
  639. r_ble_ll_conn_auth_pyld_timer_start = 0x40000d38;
  640. r_ble_ll_conn_calc_dci = 0x40000d3c;
  641. r_ble_ll_conn_calc_dci_csa1 = 0x40000d40;
  642. r_ble_ll_conn_calc_itvl_ticks = 0x40000d44;
  643. r_ble_ll_conn_chk_csm_flags = 0x40000d48;
  644. r_ble_ll_conn_chk_phy_upd_start = 0x40000d4c;
  645. r_ble_ll_conn_comp_event_send = 0x40000d50;
  646. r_ble_ll_conn_connect_ind_pdu_make = 0x40000d54;
  647. r_ble_ll_conn_create_cancel = 0x40000d5c;
  648. r_ble_ll_conn_cth_flow_enable = 0x40000d64;
  649. r_ble_ll_conn_cth_flow_error_fn = 0x40000d68;
  650. r_ble_ll_conn_cth_flow_have_credit = 0x40000d6c;
  651. r_ble_ll_conn_cth_flow_is_enabled = 0x40000d70;
  652. r_ble_ll_conn_cth_flow_process_cmd = 0x40000d74;
  653. r_ble_ll_conn_cth_flow_set_buffers = 0x40000d78;
  654. r_ble_ll_conn_ext_master_init = 0x40000d84;
  655. r_ble_ll_conn_find_active_conn = 0x40000d88;
  656. r_ble_ll_conn_get_active_conn = 0x40000d8c;
  657. r_ble_ll_conn_get_anchor = 0x40000d90;
  658. r_ble_ll_conn_hcc_params_set_fallback = 0x40000d94;
  659. r_ble_ll_conn_hci_cancel_conn_complete_event = 0x40000d98;
  660. r_ble_ll_conn_hci_chk_conn_params = 0x40000d9c;
  661. r_ble_ll_conn_hci_chk_scan_params = 0x40000da0;
  662. r_ble_ll_conn_hci_disconnect_cmd = 0x40000da4;
  663. r_ble_ll_conn_hci_le_ltk_neg_reply = 0x40000da8;
  664. r_ble_ll_conn_hci_le_ltk_reply = 0x40000dac;
  665. r_ble_ll_conn_hci_le_rd_phy = 0x40000db0;
  666. r_ble_ll_conn_hci_le_start_encrypt = 0x40000db8;
  667. r_ble_ll_conn_hci_param_nrr = 0x40000dbc;
  668. r_ble_ll_conn_hci_param_rr = 0x40000dc0;
  669. r_ble_ll_conn_hci_rd_auth_pyld_tmo = 0x40000dc4;
  670. r_ble_ll_conn_hci_rd_chan_map = 0x40000dc8;
  671. r_ble_ll_conn_hci_rd_rem_ver_cmd = 0x40000dcc;
  672. r_ble_ll_conn_hci_rd_rssi = 0x40000dd0;
  673. r_ble_ll_conn_hci_read_rem_features = 0x40000dd4;
  674. r_ble_ll_conn_hci_set_data_len = 0x40000ddc;
  675. r_ble_ll_conn_hci_update = 0x40000de0;
  676. r_ble_ll_conn_hci_wr_auth_pyld_tmo = 0x40000de4;
  677. r_ble_ll_conn_init_phy = 0x40000de8;
  678. r_ble_ll_conn_is_empty_pdu = 0x40000df0;
  679. r_ble_ll_conn_is_lru = 0x40000df4;
  680. r_ble_ll_conn_master_init = 0x40000df8;
  681. r_ble_ll_conn_module_reset = 0x40000e04;
  682. r_ble_ll_conn_num_comp_pkts_event_send = 0x40000e0c;
  683. r_ble_ll_conn_process_conn_params = 0x40000e14;
  684. r_ble_ll_conn_req_peer_sca = 0x40000e18;
  685. r_ble_ll_conn_rx_data_pdu = 0x40000e1c;
  686. r_ble_ll_conn_set_csa = 0x40000e20;
  687. r_ble_ll_conn_set_ext_con_params = 0x40000e24;
  688. r_ble_ll_conn_set_global_chanmap = 0x40000e28;
  689. r_ble_ll_conn_set_phy = 0x40000e2c;
  690. r_ble_ll_conn_set_txpwr_by_handle = 0x40000e30;
  691. r_ble_ll_conn_set_unknown_rx_octets = 0x40000e34;
  692. r_ble_ll_conn_sm_get = 0x40000e3c;
  693. r_ble_ll_conn_tx_pkt_in = 0x40000e4c;
  694. r_ble_ll_conn_update_eff_data_len = 0x40000e50;
  695. r_ble_ll_ctrl_chanmap_req_make = 0x40000e54;
  696. r_ble_ll_ctrl_conn_param_pdu_make = 0x40000e5c;
  697. r_ble_ll_ctrl_conn_param_pdu_proc = 0x40000e60;
  698. r_ble_ll_ctrl_conn_param_reply = 0x40000e64;
  699. r_ble_ll_ctrl_datalen_upd_make = 0x40000e6c;
  700. r_ble_ll_ctrl_enc_allowed_pdu = 0x40000e70;
  701. r_ble_ll_ctrl_enc_allowed_pdu_rx = 0x40000e74;
  702. r_ble_ll_ctrl_enc_req_make = 0x40000e7c;
  703. r_ble_ll_ctrl_find_new_phy = 0x40000e80;
  704. r_ble_ll_ctrl_initiate_dle = 0x40000e84;
  705. r_ble_ll_ctrl_len_proc = 0x40000e88;
  706. r_ble_ll_ctrl_min_used_chan_rsp = 0x40000e8c;
  707. r_ble_ll_ctrl_phy_from_phy_mask = 0x40000e90;
  708. r_ble_ll_ctrl_phy_req_rsp_make = 0x40000e94;
  709. r_ble_ll_ctrl_phy_tx_transition_get = 0x40000e98;
  710. r_ble_ll_ctrl_phy_update_cancel = 0x40000e9c;
  711. r_ble_ll_ctrl_phy_update_ind_make = 0x40000ea0;
  712. r_ble_ll_ctrl_phy_update_proc_complete = 0x40000ea4;
  713. r_ble_ll_ctrl_proc_rsp_timer_cb = 0x40000eac;
  714. r_ble_ll_ctrl_proc_stop = 0x40000eb4;
  715. r_ble_ll_ctrl_proc_with_instant_initiated = 0x40000ebc;
  716. r_ble_ll_ctrl_rej_ext_ind_make = 0x40000ec0;
  717. r_ble_ll_ctrl_reject_ind_send = 0x40000ec4;
  718. r_ble_ll_ctrl_rx_chanmap_req = 0x40000ec8;
  719. r_ble_ll_ctrl_rx_conn_param_req = 0x40000ecc;
  720. r_ble_ll_ctrl_rx_conn_param_rsp = 0x40000ed0;
  721. r_ble_ll_ctrl_rx_conn_update = 0x40000ed4;
  722. r_ble_ll_ctrl_rx_enc_req = 0x40000ed8;
  723. r_ble_ll_ctrl_rx_enc_rsp = 0x40000edc;
  724. r_ble_ll_ctrl_rx_feature_req = 0x40000ee0;
  725. r_ble_ll_ctrl_rx_pause_enc_req = 0x40000ee8;
  726. r_ble_ll_ctrl_rx_pause_enc_rsp = 0x40000eec;
  727. r_ble_ll_ctrl_rx_periodic_sync_ind = 0x40000ef4;
  728. r_ble_ll_ctrl_rx_phy_req = 0x40000ef8;
  729. r_ble_ll_ctrl_rx_phy_rsp = 0x40000efc;
  730. r_ble_ll_ctrl_rx_phy_update_ind = 0x40000f00;
  731. r_ble_ll_ctrl_rx_ping_rsp = 0x40000f04;
  732. r_ble_ll_ctrl_rx_reject_ind = 0x40000f08;
  733. r_ble_ll_ctrl_rx_sca_req = 0x40000f0c;
  734. r_ble_ll_ctrl_rx_sca_rsp = 0x40000f10;
  735. r_ble_ll_ctrl_rx_start_enc_req = 0x40000f14;
  736. r_ble_ll_ctrl_rx_start_enc_rsp = 0x40000f18;
  737. r_ble_ll_ctrl_rx_version_ind = 0x40000f1c;
  738. r_ble_ll_ctrl_sca_req_rsp_make = 0x40000f20;
  739. r_ble_ll_ctrl_start_enc_send = 0x40000f24;
  740. r_ble_ll_ctrl_start_rsp_timer = 0x40000f28;
  741. r_ble_ll_ctrl_terminate_start = 0x40000f2c;
  742. r_ble_ll_ctrl_update_features = 0x40000f34;
  743. r_ble_ll_ctrl_version_ind_make = 0x40000f38;
  744. r_ble_ll_data_buffer_overflow = 0x40000f3c;
  745. r_ble_ll_disconn_comp_event_send = 0x40000f44;
  746. r_ble_ll_event_comp_pkts = 0x40000f4c;
  747. r_ble_ll_event_dbuf_overflow = 0x40000f50;
  748. r_ble_ll_event_send = 0x40000f54;
  749. r_ble_ll_event_tx_pkt = 0x40000f58;
  750. r_ble_ll_ext_adv_phy_mode_to_local_phy = 0x40000f5c;
  751. r_ble_ll_ext_scan_parse_adv_info = 0x40000f64;
  752. r_ble_ll_ext_scan_parse_aux_ptr = 0x40000f68;
  753. r_ble_ll_flush_pkt_queue = 0x40000f6c;
  754. r_ble_ll_generate_dh_key_v1 = 0x40000f70;
  755. r_ble_ll_generate_dh_key_v2 = 0x40000f74;
  756. r_ble_ll_get_addr_type = 0x40000f7c;
  757. r_ble_ll_get_our_devaddr = 0x40000f84;
  758. r_ble_ll_get_tx_pwr_compensation = 0x40000f88;
  759. r_ble_ll_hci_acl_rx = 0x40000f8c;
  760. r_ble_ll_hci_adv_mode_ext = 0x40000f90;
  761. r_ble_ll_hci_adv_set_enable = 0x40000f94;
  762. r_ble_ll_hci_cb_set_ctrlr_to_host_fc = 0x40000f9c;
  763. r_ble_ll_hci_cb_set_event_mask = 0x40000fa0;
  764. r_ble_ll_hci_cb_set_event_mask2 = 0x40000fa4;
  765. r_ble_ll_hci_chk_phy_masks = 0x40000fa8;
  766. r_ble_ll_hci_cmd_rx = 0x40000fb0;
  767. r_ble_ll_hci_disconnect = 0x40000fbc;
  768. r_ble_ll_hci_ev_conn_update = 0x40000fc4;
  769. r_ble_ll_hci_ev_databuf_overflow = 0x40000fc8;
  770. r_ble_ll_hci_ev_datalen_chg = 0x40000fcc;
  771. r_ble_ll_hci_ev_encrypt_chg = 0x40000fd0;
  772. r_ble_ll_hci_ev_hw_err = 0x40000fd4;
  773. r_ble_ll_hci_ev_le_csa = 0x40000fd8;
  774. r_ble_ll_hci_ev_ltk_req = 0x40000fdc;
  775. r_ble_ll_hci_ev_phy_update = 0x40000fe0;
  776. r_ble_ll_hci_ev_rd_rem_used_feat = 0x40000fe4;
  777. r_ble_ll_hci_ev_rd_rem_ver = 0x40000fe8;
  778. r_ble_ll_hci_ev_rem_conn_parm_req = 0x40000fec;
  779. r_ble_ll_hci_ev_sca_update = 0x40000ff0;
  780. r_ble_ll_hci_ev_send_adv_set_terminated = 0x40000ff4;
  781. r_ble_ll_hci_ev_send_scan_req_recv = 0x40000ff8;
  782. r_ble_ll_hci_ev_send_scan_timeout = 0x40000ffc;
  783. r_ble_ll_hci_ev_send_vendor_err = 0x40001000;
  784. r_ble_ll_hci_event_send = 0x40001004;
  785. r_ble_ll_hci_ext_scan_set_enable = 0x40001008;
  786. r_ble_ll_hci_get_num_cmd_pkts = 0x4000100c;
  787. r_ble_ll_hci_info_params_cmd_proc = 0x40001010;
  788. r_ble_ll_hci_init = 0x40001014;
  789. r_ble_ll_hci_init_support_cmd_base_on_lmp_ver = 0x40001018;
  790. r_ble_ll_hci_is_event_enabled = 0x4000101c;
  791. r_ble_ll_hci_is_le_event_enabled = 0x40001020;
  792. r_ble_ll_hci_le_cmd_send_cmd_status = 0x40001028;
  793. r_ble_ll_hci_le_encrypt = 0x4000102c;
  794. r_ble_ll_hci_le_rand = 0x40001030;
  795. r_ble_ll_hci_le_rd_max_data_len = 0x40001034;
  796. r_ble_ll_hci_le_rd_sugg_data_len = 0x40001038;
  797. r_ble_ll_hci_le_read_bufsize = 0x4000103c;
  798. r_ble_ll_hci_le_read_supp_states = 0x40001044;
  799. r_ble_ll_hci_le_set_def_phy = 0x40001048;
  800. r_ble_ll_hci_le_wr_sugg_data_len = 0x4000104c;
  801. r_ble_ll_hci_link_ctrl_cmd_proc = 0x40001050;
  802. r_ble_ll_hci_npl_init = 0x40001054;
  803. r_ble_ll_hci_post_gen_dhkey_cmp_evt = 0x40001058;
  804. r_ble_ll_hci_post_rd_p256_pubkey_cmp_evt = 0x4000105c;
  805. r_ble_ll_hci_rd_bd_addr = 0x40001060;
  806. r_ble_ll_hci_rd_local_supp_cmd = 0x40001064;
  807. r_ble_ll_hci_rd_local_supp_feat = 0x40001068;
  808. r_ble_ll_hci_rd_local_version = 0x4000106c;
  809. r_ble_ll_hci_scan_set_enable = 0x40001070;
  810. r_ble_ll_hci_send_adv_report = 0x40001074;
  811. r_ble_ll_hci_send_dir_adv_report = 0x40001078;
  812. r_ble_ll_hci_send_ext_adv_report = 0x4000107c;
  813. r_ble_ll_hci_send_legacy_ext_adv_report = 0x40001080;
  814. r_ble_ll_hci_send_noop = 0x40001084;
  815. r_ble_ll_hci_set_adv_data = 0x40001088;
  816. r_ble_ll_hci_set_le_event_mask = 0x4000108c;
  817. r_ble_ll_hci_set_scan_rsp_data = 0x40001090;
  818. r_ble_ll_hci_status_params_cmd_proc = 0x40001094;
  819. r_ble_ll_hci_vs_cmd_proc = 0x40001098;
  820. r_ble_ll_hci_vs_rd_static_addr = 0x4000109c;
  821. r_ble_ll_hw_err_timer_cb = 0x400010a0;
  822. r_ble_ll_hw_error = 0x400010a4;
  823. r_ble_ll_init_alloc_conn_comp_ev = 0x400010ac;
  824. r_ble_ll_init_get_conn_comp_ev = 0x400010b0;
  825. r_ble_ll_is_addr_empty = 0x400010b8;
  826. r_ble_ll_is_controller_busy = 0x400010bc;
  827. r_ble_ll_is_on_resolv_list = 0x400010c0;
  828. r_ble_ll_is_our_devaddr = 0x400010c4;
  829. r_ble_ll_is_rpa = 0x400010c8;
  830. r_ble_ll_is_valid_adv_mode = 0x400010cc;
  831. r_ble_ll_is_valid_own_addr_type = 0x400010d0;
  832. r_ble_ll_is_valid_public_addr = 0x400010d4;
  833. r_ble_ll_is_valid_random_addr = 0x400010d8;
  834. r_ble_ll_misc_options_set = 0x400010e0;
  835. r_ble_ll_modify_sca = 0x400010e4;
  836. r_ble_ll_pdu_max_tx_octets_get = 0x400010ec;
  837. r_ble_ll_pdu_tx_time_get = 0x400010f0;
  838. r_ble_ll_phy_to_phy_mode = 0x400010f4;
  839. r_ble_ll_qa_enable = 0x400010f8;
  840. r_ble_ll_rand = 0x400010fc;
  841. r_ble_ll_rand_data_get = 0x40001100;
  842. r_ble_ll_rand_init = 0x4000110c;
  843. r_ble_ll_rand_prand_get = 0x40001110;
  844. r_ble_ll_rand_sample = 0x40001114;
  845. r_ble_ll_rand_start = 0x40001118;
  846. r_ble_ll_read_local_p256_pub_key = 0x4000111c;
  847. r_ble_ll_read_rf_path_compensation = 0x40001120;
  848. r_ble_ll_read_supp_features = 0x40001124;
  849. r_ble_ll_read_supp_states = 0x40001128;
  850. r_ble_ll_resolv_clear_all_pl_bit = 0x40001134;
  851. r_ble_ll_resolv_clear_all_wl_bit = 0x40001138;
  852. r_ble_ll_resolv_enable_cmd = 0x40001140;
  853. r_ble_ll_resolv_enabled = 0x40001144;
  854. r_ble_ll_resolv_gen_rpa = 0x40001150;
  855. r_ble_ll_resolv_get_addr_pointer = 0x40001154;
  856. r_ble_ll_resolv_get_index = 0x40001158;
  857. r_ble_ll_resolv_get_irk_pointer = 0x4000115c;
  858. r_ble_ll_resolv_get_list = 0x40001160;
  859. r_ble_ll_resolv_get_priv_addr = 0x40001164;
  860. r_ble_ll_resolv_get_rpa_tmo = 0x40001168;
  861. r_ble_ll_resolv_irk_nonzero = 0x40001170;
  862. r_ble_ll_resolv_list_add = 0x40001174;
  863. r_ble_ll_resolv_list_chg_allowed = 0x40001178;
  864. r_ble_ll_resolv_list_clr = 0x4000117c;
  865. r_ble_ll_resolv_list_find = 0x40001180;
  866. r_ble_ll_resolv_list_read_size = 0x40001184;
  867. r_ble_ll_resolv_list_reset = 0x40001188;
  868. r_ble_ll_resolv_local_addr_rd = 0x40001190;
  869. r_ble_ll_resolv_peer_addr_rd = 0x40001194;
  870. r_ble_ll_resolv_peer_rpa_any = 0x40001198;
  871. r_ble_ll_resolv_reset = 0x4000119c;
  872. r_ble_ll_resolv_rpa = 0x400011a0;
  873. r_ble_ll_resolv_rpa_timer_cb = 0x400011a4;
  874. r_ble_ll_resolv_set_local_rpa = 0x400011a8;
  875. r_ble_ll_resolv_set_peer_rpa = 0x400011ac;
  876. r_ble_ll_resolv_set_rpa_tmo = 0x400011b0;
  877. r_ble_ll_resolve_set_priv_mode = 0x400011b4;
  878. r_ble_ll_rxpdu_alloc = 0x400011b8;
  879. r_ble_ll_scan_add_scan_rsp_adv = 0x400011bc;
  880. r_ble_ll_scan_adv_decode_addr = 0x400011c0;
  881. r_ble_ll_scan_aux_data_ref = 0x400011c4;
  882. r_ble_ll_scan_aux_data_unref = 0x400011c8;
  883. r_ble_ll_scan_can_chg_whitelist = 0x400011cc;
  884. r_ble_ll_scan_check_periodic_sync = 0x400011d0;
  885. r_ble_ll_scan_classify_filter_aux_init = 0x400011d4;
  886. r_ble_ll_scan_classify_filter_init = 0x400011d8;
  887. r_ble_ll_scan_common_init = 0x400011dc;
  888. r_ble_ll_scan_continue_en = 0x400011e0;
  889. r_ble_ll_scan_dup_check_ext = 0x400011e8;
  890. r_ble_ll_scan_dup_check_legacy = 0x400011ec;
  891. r_ble_ll_scan_dup_move_to_head = 0x400011f0;
  892. r_ble_ll_scan_dup_new = 0x400011f4;
  893. r_ble_ll_scan_dup_update_ext = 0x400011f8;
  894. r_ble_ll_scan_dup_update_legacy = 0x400011fc;
  895. r_ble_ll_scan_enabled = 0x40001200;
  896. r_ble_ll_scan_end_adv_evt = 0x40001204;
  897. r_ble_ll_scan_ext_initiator_start = 0x4000120c;
  898. r_ble_ll_scan_get_addr_data_from_legacy = 0x40001210;
  899. r_ble_ll_scan_get_addr_from_ext_adv = 0x40001214;
  900. r_ble_ll_scan_get_cur_sm = 0x40001218;
  901. r_ble_ll_scan_get_ext_adv_report = 0x4000121c;
  902. r_ble_ll_scan_get_local_rpa = 0x40001220;
  903. r_ble_ll_scan_get_next_adv_prim_chan = 0x40001224;
  904. r_ble_ll_scan_get_peer_rpa = 0x40001228;
  905. r_ble_ll_scan_have_rxd_scan_rsp = 0x4000122c;
  906. r_ble_ll_scan_initiator_start = 0x40001234;
  907. r_ble_ll_scan_is_inside_window = 0x40001238;
  908. r_ble_ll_scan_move_window_to = 0x4000123c;
  909. r_ble_ll_scan_npl_reset = 0x40001240;
  910. r_ble_ll_scan_parse_auxptr = 0x40001244;
  911. r_ble_ll_scan_parse_ext_hdr = 0x40001248;
  912. r_ble_ll_scan_record_new_adv = 0x40001250;
  913. r_ble_ll_scan_refresh_nrpa = 0x40001254;
  914. r_ble_ll_scan_reset = 0x40001258;
  915. r_ble_ll_scan_rx_pkt_in = 0x4000125c;
  916. r_ble_ll_scan_rx_pkt_in_restore_addr_data = 0x40001268;
  917. r_ble_ll_scan_rxed = 0x4000126c;
  918. r_ble_ll_scan_send_truncated = 0x40001274;
  919. r_ble_ll_scan_set_peer_rpa = 0x4000127c;
  920. r_ble_ll_scan_set_perfer_addr = 0x40001280;
  921. r_ble_ll_scan_sm_start = 0x40001288;
  922. r_ble_ll_scan_sm_stop = 0x4000128c;
  923. r_ble_ll_scan_time_hci_to_ticks = 0x40001290;
  924. r_ble_ll_scan_update_aux_data = 0x40001294;
  925. r_ble_ll_scan_whitelist_enabled = 0x40001298;
  926. r_ble_ll_set_default_privacy_mode = 0x4000129c;
  927. r_ble_ll_set_default_sync_transfer_params = 0x400012a0;
  928. r_ble_ll_set_public_addr = 0x400012ac;
  929. r_ble_ll_set_random_addr = 0x400012b0;
  930. r_ble_ll_set_sync_transfer_params = 0x400012b4;
  931. r_ble_ll_state_get = 0x400012b8;
  932. r_ble_ll_state_set = 0x400012bc;
  933. r_ble_ll_sync_adjust_ext_hdr = 0x400012c0;
  934. r_ble_ll_sync_cancel = 0x400012c4;
  935. r_ble_ll_sync_cancel_complete_event = 0x400012c8;
  936. r_ble_ll_sync_check_acad = 0x400012cc;
  937. r_ble_ll_sync_check_failed = 0x400012d0;
  938. r_ble_ll_sync_enabled = 0x400012dc;
  939. r_ble_ll_sync_established = 0x400012ec;
  940. r_ble_ll_sync_filter_enabled = 0x400012f0;
  941. r_ble_ll_sync_find = 0x400012f4;
  942. r_ble_ll_sync_get_cur_sm = 0x400012f8;
  943. r_ble_ll_sync_get_handle = 0x400012fc;
  944. r_ble_ll_sync_get_sm = 0x40001300;
  945. r_ble_ll_sync_info_event = 0x40001304;
  946. r_ble_ll_sync_init = 0x40001308;
  947. r_ble_ll_sync_list_add = 0x4000130c;
  948. r_ble_ll_sync_list_clear = 0x40001310;
  949. r_ble_ll_sync_list_empty = 0x40001314;
  950. r_ble_ll_sync_list_get_free = 0x40001318;
  951. r_ble_ll_sync_list_remove = 0x4000131c;
  952. r_ble_ll_sync_list_search = 0x40001320;
  953. r_ble_ll_sync_list_size = 0x40001324;
  954. r_ble_ll_sync_lost_event = 0x40001328;
  955. r_ble_ll_sync_next_event = 0x4000132c;
  956. r_ble_ll_sync_on_list = 0x40001330;
  957. r_ble_ll_sync_periodic_ind = 0x40001338;
  958. r_ble_ll_sync_phy_mode_to_aux_phy = 0x4000133c;
  959. r_ble_ll_sync_phy_mode_to_hci = 0x40001340;
  960. r_ble_ll_sync_reserve = 0x4000134c;
  961. r_ble_ll_sync_reset = 0x40001350;
  962. r_ble_ll_sync_reset_sm = 0x40001354;
  963. r_ble_ll_sync_send_per_adv_rpt = 0x4000135c;
  964. r_ble_ll_sync_send_sync_ind = 0x40001360;
  965. r_ble_ll_sync_send_truncated_per_adv_rpt = 0x40001364;
  966. r_ble_ll_sync_sm_clear = 0x40001368;
  967. r_ble_ll_sync_terminate = 0x4000136c;
  968. r_ble_ll_sync_transfer = 0x40001370;
  969. r_ble_ll_sync_transfer_get = 0x40001374;
  970. r_ble_ll_sync_transfer_received = 0x40001378;
  971. r_ble_ll_trace_u32 = 0x40001384;
  972. r_ble_ll_trace_u32x2 = 0x40001388;
  973. r_ble_ll_trace_u32x3 = 0x4000138c;
  974. r_ble_ll_tx_flat_mbuf_pducb = 0x40001390;
  975. r_ble_ll_update_max_tx_octets_phy_mode = 0x4000139c;
  976. r_ble_ll_usecs_to_ticks_round_up = 0x400013a0;
  977. r_ble_ll_utils_calc_access_addr = 0x400013a4;
  978. r_ble_ll_utils_calc_dci_csa2 = 0x400013a8;
  979. r_ble_ll_utils_calc_num_used_chans = 0x400013ac;
  980. r_ble_ll_utils_calc_window_widening = 0x400013b0;
  981. r_ble_ll_utils_csa2_perm = 0x400013b4;
  982. r_ble_ll_utils_csa2_prng = 0x400013b8;
  983. r_ble_ll_utils_remapped_channel = 0x400013bc;
  984. r_ble_ll_whitelist_add = 0x400013c0;
  985. r_ble_ll_whitelist_chg_allowed = 0x400013c4;
  986. r_ble_ll_whitelist_read_size = 0x400013cc;
  987. r_ble_ll_write_rf_path_compensation = 0x400013d8;
  988. r_ble_lll_adv_aux_schedule = 0x400013e0;
  989. r_ble_lll_adv_aux_schedule_first = 0x400013e4;
  990. r_ble_lll_adv_aux_schedule_next = 0x400013e8;
  991. r_ble_lll_adv_aux_scheduled = 0x400013ec;
  992. r_ble_lll_adv_aux_set_start_time = 0x400013f0;
  993. r_ble_lll_adv_coex_dpc_calc_pti_update_itvl = 0x400013f4;
  994. r_ble_lll_adv_coex_dpc_process_pri = 0x400013f8;
  995. r_ble_lll_adv_coex_dpc_process_sec = 0x400013fc;
  996. r_ble_lll_adv_coex_dpc_pti_get = 0x40001400;
  997. r_ble_lll_adv_coex_dpc_update = 0x40001404;
  998. r_ble_lll_adv_coex_dpc_update_on_adv_start = 0x40001408;
  999. r_ble_lll_adv_coex_dpc_update_on_aux_scheduled = 0x4000140c;
  1000. r_ble_lll_adv_coex_dpc_update_on_data_updated = 0x40001410;
  1001. r_ble_lll_adv_coex_dpc_update_on_event_end = 0x40001414;
  1002. r_ble_lll_adv_coex_dpc_update_on_event_scheduled = 0x40001418;
  1003. r_ble_lll_adv_done = 0x4000141c;
  1004. r_ble_lll_adv_event_done = 0x40001424;
  1005. r_ble_lll_adv_event_rmvd_from_sched = 0x40001428;
  1006. r_ble_lll_adv_ext_estimate_data_itvl = 0x4000142c;
  1007. r_ble_lll_adv_get_sec_pdu_len = 0x40001430;
  1008. r_ble_lll_adv_make_done = 0x40001438;
  1009. r_ble_lll_adv_periodic_done = 0x4000143c;
  1010. r_ble_lll_adv_periodic_event_done = 0x40001440;
  1011. r_ble_lll_adv_periodic_rmvd_from_sched = 0x40001444;
  1012. r_ble_lll_adv_periodic_schedule_first = 0x40001448;
  1013. r_ble_lll_adv_pri_schedule_tx_pdu = 0x40001458;
  1014. r_ble_lll_adv_reschedule_event = 0x4000145c;
  1015. r_ble_lll_adv_reschedule_periodic_event = 0x40001460;
  1016. r_ble_lll_adv_sec_done = 0x40001468;
  1017. r_ble_lll_adv_sec_event_done = 0x4000146c;
  1018. r_ble_lll_adv_sec_schedule_next_aux = 0x40001470;
  1019. r_ble_lll_adv_secondary_tx_start_cb = 0x40001474;
  1020. r_ble_lll_adv_sm_deinit = 0x40001478;
  1021. r_ble_lll_adv_sm_event_init = 0x4000147c;
  1022. r_ble_lll_adv_sm_event_restore = 0x40001480;
  1023. r_ble_lll_adv_sm_event_store = 0x40001484;
  1024. r_ble_lll_adv_sm_init = 0x40001488;
  1025. r_ble_lll_adv_sm_reset = 0x4000148c;
  1026. r_ble_lll_adv_start = 0x40001490;
  1027. r_ble_lll_adv_stop = 0x40001494;
  1028. r_ble_lll_adv_sync_next_scheduled = 0x40001498;
  1029. r_ble_lll_adv_sync_schedule = 0x4000149c;
  1030. r_ble_lll_adv_sync_tx_done = 0x400014a0;
  1031. r_ble_lll_adv_sync_tx_end = 0x400014a4;
  1032. r_ble_lll_adv_sync_tx_start_cb = 0x400014a8;
  1033. r_ble_lll_adv_tx_done = 0x400014ac;
  1034. r_ble_lll_adv_tx_start_cb = 0x400014b0;
  1035. r_ble_lll_adv_update_rsp_offset = 0x400014b4;
  1036. r_ble_lll_aux_scan_cb = 0x400014b8;
  1037. r_ble_lll_aux_scan_drop = 0x400014bc;
  1038. r_ble_lll_aux_scan_drop_event_cb = 0x400014c0;
  1039. r_ble_lll_calc_us_convert_tick_unit = 0x400014c4;
  1040. r_ble_lll_conn_can_send_next_pdu = 0x400014cc;
  1041. r_ble_lll_conn_check_opcode_matched = 0x400014d0;
  1042. r_ble_lll_conn_coex_dpc_process = 0x400014d4;
  1043. r_ble_lll_conn_coex_dpc_pti_get = 0x400014d8;
  1044. r_ble_lll_conn_coex_dpc_update = 0x400014dc;
  1045. r_ble_lll_conn_coex_dpc_update_on_event_end = 0x400014e0;
  1046. r_ble_lll_conn_coex_dpc_update_on_event_scheduled = 0x400014e4;
  1047. r_ble_lll_conn_coex_dpc_update_on_event_started = 0x400014e8;
  1048. r_ble_lll_conn_cth_flow_alloc_credit = 0x400014ec;
  1049. r_ble_lll_conn_current_sm_over = 0x400014f4;
  1050. r_ble_lll_conn_event_end_timer_cb = 0x40001508;
  1051. r_ble_lll_conn_event_is_over = 0x40001510;
  1052. r_ble_lll_conn_event_start_cb = 0x40001514;
  1053. r_ble_lll_conn_free_rx_mbuf = 0x40001518;
  1054. r_ble_lll_conn_get_addr_info_from_rx_buf = 0x4000151c;
  1055. r_ble_lll_conn_get_ce_end_time = 0x40001520;
  1056. r_ble_lll_conn_get_next_sched_time = 0x40001524;
  1057. r_ble_lll_conn_halt = 0x4000152c;
  1058. r_ble_lll_conn_master_common_init = 0x40001530;
  1059. r_ble_lll_conn_master_new = 0x40001534;
  1060. r_ble_lll_conn_module_reset = 0x40001540;
  1061. r_ble_lll_conn_pre_process = 0x40001548;
  1062. r_ble_lll_conn_recv_ack = 0x40001554;
  1063. r_ble_lll_conn_recv_valid_packet = 0x40001558;
  1064. r_ble_lll_conn_reset_pending_sched = 0x4000155c;
  1065. r_ble_lll_conn_sched_next_anchor = 0x40001564;
  1066. r_ble_lll_conn_sched_next_event = 0x40001568;
  1067. r_ble_lll_conn_sm_new = 0x40001574;
  1068. r_ble_lll_conn_sm_npl_deinit = 0x40001578;
  1069. r_ble_lll_conn_sm_npl_init = 0x4000157c;
  1070. r_ble_lll_conn_superversion_timer_cb = 0x40001580;
  1071. r_ble_lll_conn_timeout = 0x40001584;
  1072. r_ble_lll_conn_update_anchor = 0x40001588;
  1073. r_ble_lll_conn_update_conn_ind_params = 0x4000158c;
  1074. r_ble_lll_conn_update_tx_buffer = 0x40001594;
  1075. r_ble_lll_deinit = 0x40001598;
  1076. r_ble_lll_dtm_calculate_itvl = 0x4000159c;
  1077. r_ble_lll_dtm_ctx_free = 0x400015a0;
  1078. r_ble_lll_dtm_end_test = 0x400015a8;
  1079. r_ble_lll_dtm_ev_rx_restart_cb = 0x400015ac;
  1080. r_ble_lll_dtm_ev_tx_resched_cb = 0x400015b0;
  1081. r_ble_lll_dtm_reset = 0x400015b8;
  1082. r_ble_lll_dtm_rx_create_ctx = 0x400015bc;
  1083. r_ble_lll_dtm_rx_isr_end = 0x400015c0;
  1084. r_ble_lll_dtm_rx_isr_start = 0x400015c4;
  1085. r_ble_lll_dtm_rx_pkt_in = 0x400015c8;
  1086. r_ble_lll_dtm_rx_sched_cb = 0x400015cc;
  1087. r_ble_lll_dtm_rx_start = 0x400015d0;
  1088. r_ble_lll_dtm_rx_test = 0x400015d4;
  1089. r_ble_lll_dtm_set_next = 0x400015d8;
  1090. r_ble_lll_dtm_tx_done = 0x400015e0;
  1091. r_ble_lll_dtm_tx_sched_cb = 0x400015e4;
  1092. r_ble_lll_dtm_tx_test = 0x400015e8;
  1093. r_ble_lll_dtm_wfr_timer_exp = 0x400015ec;
  1094. r_ble_lll_event_rx_pkt = 0x400015f0;
  1095. r_ble_lll_ext_scan_coex_dpc_process = 0x400015f4;
  1096. r_ble_lll_ext_scan_coex_dpc_pti_get = 0x400015f8;
  1097. r_ble_lll_ext_scan_coex_dpc_update = 0x400015fc;
  1098. r_ble_lll_ext_scan_coex_dpc_update_on_start = 0x40001600;
  1099. r_ble_lll_hci_dtm_rx_test = 0x40001604;
  1100. r_ble_lll_hci_dtm_rx_test_v2 = 0x40001608;
  1101. r_ble_lll_hci_dtm_tx_test = 0x4000160c;
  1102. r_ble_lll_hci_dtm_tx_test_ext = 0x40001610;
  1103. r_ble_lll_hci_dtm_tx_test_v2 = 0x40001614;
  1104. r_ble_lll_hci_dtm_tx_test_v2_ext = 0x40001618;
  1105. r_ble_lll_init = 0x4000161c;
  1106. r_ble_lll_init_pre_process = 0x40001620;
  1107. r_ble_lll_per_adv_coex_dpc_calc_pti_update_itvl = 0x40001628;
  1108. r_ble_lll_per_adv_coex_dpc_process = 0x4000162c;
  1109. r_ble_lll_per_adv_coex_dpc_pti_get = 0x40001630;
  1110. r_ble_lll_per_adv_coex_dpc_update = 0x40001634;
  1111. r_ble_lll_per_adv_coex_dpc_update_on_data_updated = 0x40001638;
  1112. r_ble_lll_per_adv_coex_dpc_update_on_scheduled = 0x4000163c;
  1113. r_ble_lll_per_adv_coex_dpc_update_on_start = 0x40001640;
  1114. r_ble_lll_reset = 0x40001644;
  1115. r_ble_lll_rfmgmt_enable_now = 0x40001658;
  1116. r_ble_lll_rfmgmt_is_enabled = 0x40001660;
  1117. r_ble_lll_rfmgmt_release = 0x40001664;
  1118. r_ble_lll_rfmgmt_scan_changed = 0x40001670;
  1119. r_ble_lll_rfmgmt_sched_changed = 0x40001674;
  1120. r_ble_lll_rfmgmt_set_sleep_cb = 0x40001678;
  1121. r_ble_lll_rfmgmt_ticks_to_enabled = 0x4000167c;
  1122. r_ble_lll_rx_pdu_in = 0x40001688;
  1123. r_ble_lll_rx_pkt_in = 0x4000168c;
  1124. r_ble_lll_rx_pkt_isr = 0x40001690;
  1125. r_ble_lll_scan_abort_aux_sched = 0x40001694;
  1126. r_ble_lll_scan_aux_data_free = 0x40001698;
  1127. r_ble_lll_scan_chk_resume = 0x4000169c;
  1128. r_ble_lll_scan_clean_cur_aux_data = 0x400016a0;
  1129. r_ble_lll_scan_coex_event_cb = 0x400016a4;
  1130. r_ble_lll_scan_common_init = 0x400016a8;
  1131. r_ble_lll_scan_deinit = 0x400016ac;
  1132. r_ble_lll_scan_duration_period_timers_restart = 0x400016b0;
  1133. r_ble_lll_scan_duration_period_timers_stop = 0x400016b4;
  1134. r_ble_lll_scan_duration_timer_cb = 0x400016b8;
  1135. r_ble_lll_scan_event_proc = 0x400016bc;
  1136. r_ble_lll_scan_ext_adv_init = 0x400016c0;
  1137. r_ble_lll_scan_has_sent_scan_req = 0x400016c8;
  1138. r_ble_lll_scan_npl_reset = 0x400016d4;
  1139. r_ble_lll_scan_npl_restore = 0x400016d8;
  1140. r_ble_lll_scan_npl_store = 0x400016dc;
  1141. r_ble_lll_scan_period_timer_cb = 0x400016e0;
  1142. r_ble_lll_scan_process_adv_in_isr = 0x400016e4;
  1143. r_ble_lll_scan_req_backoff = 0x400016ec;
  1144. r_ble_lll_scan_sched_next_aux = 0x40001700;
  1145. r_ble_lll_scan_sched_remove = 0x40001704;
  1146. r_ble_lll_scan_start = 0x40001708;
  1147. r_ble_lll_scan_start_rx = 0x4000170c;
  1148. r_ble_lll_scan_timer_cb = 0x40001718;
  1149. r_ble_lll_sched_adv_new = 0x4000171c;
  1150. r_ble_lll_sched_adv_resched_pdu = 0x40001720;
  1151. r_ble_lll_sched_adv_reschedule = 0x40001724;
  1152. r_ble_lll_sched_aux_scan = 0x40001728;
  1153. r_ble_lll_sched_conn_overlap = 0x4000172c;
  1154. r_ble_lll_sched_conn_reschedule = 0x40001730;
  1155. r_ble_lll_sched_dtm = 0x40001738;
  1156. r_ble_lll_sched_execute_item = 0x40001744;
  1157. r_ble_lll_sched_init = 0x40001748;
  1158. r_ble_lll_sched_insert_if_empty = 0x4000174c;
  1159. r_ble_lll_sched_is_overlap = 0x40001750;
  1160. r_ble_lll_sched_master_new = 0x40001754;
  1161. r_ble_lll_sched_next_time = 0x40001758;
  1162. r_ble_lll_sched_overlaps_current = 0x4000175c;
  1163. r_ble_lll_sched_periodic_adv = 0x40001760;
  1164. r_ble_lll_sched_rmv_elem = 0x40001764;
  1165. r_ble_lll_sched_rmv_elem_type = 0x40001768;
  1166. r_ble_lll_sched_run = 0x4000176c;
  1167. r_ble_lll_sched_scan_req_over_aux_ptr = 0x40001770;
  1168. r_ble_lll_sched_slave_new = 0x40001774;
  1169. r_ble_lll_sched_stop = 0x40001778;
  1170. r_ble_lll_sched_sync = 0x4000177c;
  1171. r_ble_lll_sched_sync_overlaps_current = 0x40001780;
  1172. r_ble_lll_sync_chain_start_cb = 0x40001788;
  1173. r_ble_lll_sync_coex_dpc_process = 0x4000178c;
  1174. r_ble_lll_sync_coex_dpc_pti_get = 0x40001790;
  1175. r_ble_lll_sync_coex_dpc_update = 0x40001794;
  1176. r_ble_lll_sync_current_sm_over = 0x40001798;
  1177. r_ble_lll_sync_deinit = 0x4000179c;
  1178. r_ble_lll_sync_event_end_cb = 0x400017a4;
  1179. r_ble_lll_sync_get_event_end_time = 0x400017ac;
  1180. r_ble_lll_sync_init = 0x400017b4;
  1181. r_ble_lll_sync_new = 0x400017b8;
  1182. r_ble_lll_sync_reset = 0x400017bc;
  1183. r_ble_lll_sync_reset_sm = 0x400017c0;
  1184. r_ble_lll_sync_rmvd_from_sched = 0x400017c4;
  1185. r_ble_lll_sync_schedule_chain = 0x400017cc;
  1186. r_ble_lll_sync_stop = 0x400017d0;
  1187. r_ble_lll_sync_trnasfer_sched = 0x400017d4;
  1188. r_ble_phy_access_addr_get = 0x400017d8;
  1189. r_ble_phy_calculate_rxtx_ifs = 0x400017dc;
  1190. r_ble_phy_calculate_rxwindow = 0x400017e0;
  1191. r_ble_phy_calculate_txrx_ifs = 0x400017e4;
  1192. r_ble_phy_check_bb_status = 0x400017e8;
  1193. r_ble_phy_complete_rx_info = 0x400017ec;
  1194. r_ble_phy_data_make = 0x400017f4;
  1195. r_ble_phy_disable = 0x400017f8;
  1196. r_ble_phy_disable_irq = 0x400017fc;
  1197. r_ble_phy_disable_whitening = 0x40001800;
  1198. r_ble_phy_enable_whitening = 0x40001804;
  1199. r_ble_phy_encrypt_disable = 0x40001808;
  1200. r_ble_phy_get_current_phy = 0x40001810;
  1201. r_ble_phy_get_packet_counter = 0x40001814;
  1202. r_ble_phy_get_packet_status = 0x40001818;
  1203. r_ble_phy_get_pyld_time_offset = 0x4000181c;
  1204. r_ble_phy_get_rx_phy_mode = 0x40001820;
  1205. r_ble_phy_get_seq_end_st = 0x40001824;
  1206. r_ble_phy_max_data_pdu_pyld = 0x40001830;
  1207. r_ble_phy_mode_config = 0x40001834;
  1208. r_ble_phy_mode_convert = 0x40001838;
  1209. r_ble_phy_mode_write = 0x4000183c;
  1210. r_ble_phy_module_init = 0x40001844;
  1211. r_ble_phy_reset_bb_monitor = 0x4000184c;
  1212. r_ble_phy_resolv_list_disable = 0x40001850;
  1213. r_ble_phy_resolv_list_enable = 0x40001854;
  1214. r_ble_phy_restart_sequence = 0x40001858;
  1215. r_ble_phy_rx_set_start_time_forcibly = 0x4000185c;
  1216. r_ble_phy_rxpdu_copy = 0x40001860;
  1217. r_ble_phy_seq_encrypt_enable = 0x40001864;
  1218. r_ble_phy_seq_encrypt_set_pkt_cntr = 0x40001868;
  1219. r_ble_phy_sequence_end_isr = 0x4000186c;
  1220. r_ble_phy_sequence_get_mode = 0x40001870;
  1221. r_ble_phy_sequence_is_running = 0x40001874;
  1222. r_ble_phy_sequence_is_waiting_rsp = 0x40001878;
  1223. r_ble_phy_sequence_single_end = 0x4000187c;
  1224. r_ble_phy_sequence_tx_end_invoke = 0x40001880;
  1225. r_ble_phy_sequence_update_conn_ind_params = 0x40001884;
  1226. r_ble_phy_set_coex_pti = 0x4000188c;
  1227. r_ble_phy_set_conn_ind_pdu = 0x40001890;
  1228. r_ble_phy_set_conn_mode = 0x40001894;
  1229. r_ble_phy_set_dev_address = 0x40001898;
  1230. r_ble_phy_set_rx_pwr_compensation = 0x4000189c;
  1231. r_ble_phy_set_single_packet_rx_sequence = 0x400018ac;
  1232. r_ble_phy_set_single_packet_tx_sequence = 0x400018b0;
  1233. r_ble_phy_set_tx_rx_transition = 0x400018b4;
  1234. r_ble_phy_set_txend_cb = 0x400018b8;
  1235. r_ble_phy_setchan = 0x400018bc;
  1236. r_ble_phy_start_rx_immediately = 0x400018c0;
  1237. r_ble_phy_state_get = 0x400018c4;
  1238. r_ble_phy_timer_config_start_time = 0x400018c8;
  1239. r_ble_phy_timer_start_now = 0x400018cc;
  1240. r_ble_phy_timer_stop = 0x400018d0;
  1241. r_ble_phy_tx_set_start_time = 0x400018d4;
  1242. r_ble_phy_txpwr_set = 0x400018dc;
  1243. r_ble_phy_update_ifs = 0x400018e8;
  1244. r_ble_phy_xcvr_state_get = 0x400018ec;
  1245. r_ble_plf_set_log_level = 0x400018f0;
  1246. r_ble_rtc_wake_up_cpu_init = 0x400018f4;
  1247. r_ble_rtc_wake_up_state_clr = 0x400018f8;
  1248. r_ble_vendor_hci_register = 0x400018fc;
  1249. r_bt_rf_coex_cfg_set = 0x40001900;
  1250. r_bt_rf_coex_coded_txrx_time_upper_lim = 0x40001904;
  1251. r_bt_rf_coex_dft_pti_set = 0x40001908;
  1252. r_bt_rf_coex_hook_deinit = 0x4000190c;
  1253. r_bt_rf_coex_hook_init = 0x40001910;
  1254. r_bt_rf_coex_hook_st_set = 0x40001914;
  1255. r_bt_rf_coex_hooks_p_set_default = 0x40001918;
  1256. r_btdm_disable_adv_delay = 0x4000191c;
  1257. r_btdm_switch_phy_coded = 0x40001920;
  1258. r_esp_wait_disabled = 0x40001924;
  1259. r_get_be16 = 0x40001928;
  1260. r_get_be24 = 0x4000192c;
  1261. r_get_be32 = 0x40001930;
  1262. r_get_be64 = 0x40001934;
  1263. r_get_le16 = 0x40001938;
  1264. r_get_le24 = 0x4000193c;
  1265. r_get_le32 = 0x40001940;
  1266. r_get_le64 = 0x40001944;
  1267. r_get_local_irk_offset = 0x40001948;
  1268. r_get_local_rpa_offset = 0x4000194c;
  1269. r_get_max_skip = 0x40001950;
  1270. r_get_peer_id_offset = 0x40001954;
  1271. r_get_peer_irk_offset = 0x40001958;
  1272. r_get_peer_rpa_offset = 0x4000195c;
  1273. r_hal_timer_disable_irq = 0x4000196c;
  1274. r_hal_timer_process = 0x40001978;
  1275. r_hal_timer_read = 0x4000197c;
  1276. r_hal_timer_read_tick = 0x40001980;
  1277. r_hal_timer_set_cb = 0x40001984;
  1278. r_hal_timer_start = 0x4000198c;
  1279. r_hal_timer_stop = 0x40001994;
  1280. r_hal_timer_task_start = 0x40001998;
  1281. r_ll_assert = 0x4000199c;
  1282. r_mem_init_mbuf_pool = 0x400019a0;
  1283. r_mem_malloc_mbuf_pool = 0x400019a4;
  1284. r_mem_malloc_mbufpkt_pool = 0x400019a8;
  1285. r_mem_malloc_mempool = 0x400019ac;
  1286. r_mem_malloc_mempool_ext = 0x400019b0;
  1287. r_mem_malloc_mempool_gen = 0x400019b4;
  1288. r_mem_pullup_obj = 0x400019b8;
  1289. r_os_cputime_get32 = 0x400019c0;
  1290. r_os_cputime_ticks_to_usecs = 0x400019c4;
  1291. r_os_cputime_timer_init = 0x400019c8;
  1292. r_os_cputime_timer_relative = 0x400019cc;
  1293. r_os_cputime_timer_start = 0x400019d0;
  1294. r_os_cputime_timer_stop = 0x400019d4;
  1295. r_os_cputime_usecs_to_ticks = 0x400019d8;
  1296. r_os_mbuf_adj = 0x400019dc;
  1297. r_os_mbuf_appendfrom = 0x400019e4;
  1298. r_os_mbuf_cmpf = 0x400019e8;
  1299. r_os_mbuf_cmpm = 0x400019ec;
  1300. r_os_mbuf_concat = 0x400019f0;
  1301. r_os_mbuf_copydata = 0x400019f4;
  1302. r_os_mbuf_copyinto = 0x400019f8;
  1303. r_os_mbuf_dup = 0x400019fc;
  1304. r_os_mbuf_extend = 0x40001a00;
  1305. r_os_mbuf_free = 0x40001a04;
  1306. r_os_mbuf_free_chain = 0x40001a08;
  1307. r_os_mbuf_get = 0x40001a0c;
  1308. r_os_mbuf_get_pkthdr = 0x40001a10;
  1309. r_os_mbuf_leadingspace = 0x40001a14;
  1310. r_os_mbuf_len = 0x40001a18;
  1311. r_os_mbuf_off = 0x40001a1c;
  1312. r_os_mbuf_pack_chains = 0x40001a20;
  1313. r_os_mbuf_pool_init = 0x40001a24;
  1314. r_os_mbuf_prepend = 0x40001a28;
  1315. r_os_mbuf_prepend_pullup = 0x40001a2c;
  1316. r_os_mbuf_pullup = 0x40001a30;
  1317. r_os_mbuf_trailingspace = 0x40001a34;
  1318. r_os_mbuf_trim_front = 0x40001a38;
  1319. r_os_mbuf_widen = 0x40001a3c;
  1320. r_os_memblock_from = 0x40001a40;
  1321. r_os_memblock_get = 0x40001a44;
  1322. r_os_memblock_put_from_cb = 0x40001a4c;
  1323. r_os_mempool_clear = 0x40001a50;
  1324. r_os_mempool_ext_clear = 0x40001a54;
  1325. r_os_mempool_ext_init = 0x40001a58;
  1326. r_os_mempool_init = 0x40001a60;
  1327. r_os_mempool_is_sane = 0x40001a68;
  1328. r_os_mqueue_get = 0x40001a74;
  1329. r_os_mqueue_init = 0x40001a78;
  1330. r_os_mqueue_put = 0x40001a7c;
  1331. r_os_msys_count = 0x40001a80;
  1332. r_os_msys_get = 0x40001a84;
  1333. r_os_msys_get_pkthdr = 0x40001a88;
  1334. r_os_msys_num_free = 0x40001a8c;
  1335. r_os_msys_register = 0x40001a90;
  1336. r_os_msys_reset = 0x40001a94;
  1337. r_pri_phy_valid = 0x40001a98;
  1338. r_put_be16 = 0x40001a9c;
  1339. r_put_be24 = 0x40001aa0;
  1340. r_put_be32 = 0x40001aa4;
  1341. r_put_be64 = 0x40001aa8;
  1342. r_put_le16 = 0x40001aac;
  1343. r_put_le24 = 0x40001ab0;
  1344. r_put_le32 = 0x40001ab4;
  1345. r_put_le64 = 0x40001ab8;
  1346. r_rtc0_timer_handler = 0x40001abc;
  1347. r_sdkconfig_get_opts = 0x40001ac0;
  1348. r_sdkconfig_set_opts = 0x40001ac4;
  1349. r_sec_phy_valid = 0x40001ac8;
  1350. r_swap_buf = 0x40001acc;
  1351. r_swap_in_place = 0x40001ad0;
  1352. /* Data (.data, .bss, .rodata) */
  1353. ble_lll_dtm_module_env_p = 0x3fcdffc4;
  1354. g_ble_lll_dtm_prbs15_data = 0x3ff4fee4;
  1355. g_ble_lll_dtm_prbs9_data = 0x3ff4fde4;
  1356. g_channel_rf_to_index = 0x3ff4fdbc;
  1357. g_ble_lll_rfmgmt_data = 0x3fcdff7c;
  1358. g_ble_sleep_enter_cb = 0x3fcdff78;
  1359. g_ble_sleep_exit_cb = 0x3fcdff74;
  1360. ble_lll_sched_env_p = 0x3fcdff70;
  1361. ble_ll_env_p = 0x3fcdff6c;
  1362. g_ble_ll_pdu_header_tx_time_ro = 0x3ff4fdb4;
  1363. ble_ll_adv_env_p = 0x3fcdff68;
  1364. ble_ll_conn_env_p = 0x3fcdff64;
  1365. ble_ll_conn_required_phy_mask = 0x3ff4fdb0;
  1366. ble_ll_valid_conn_phy_mask = 0x3ff4fdaf;
  1367. ble_ll_hci_env_p = 0x3fcdff60;
  1368. g_debug_le_private_key = 0x3ff4fd6c;
  1369. g_ecc_key = 0x3fcdfefc;
  1370. ble_ll_rand_env_p = 0x3fcdfef8;
  1371. ble_ll_resolv_env_p = 0x3fcdfef4;
  1372. g_ble_ll_resolve_hdr = 0x3fcdfeec;
  1373. g_device_mode_default = 0x3fcdfe68;
  1374. ble_ll_scan_classify_filter_aux_check_cb = 0x3fcdfee8;
  1375. ble_ll_scan_classify_filter_check_cb = 0x3fcdfee4;
  1376. ble_ll_scan_env_p = 0x3fcdfee0;
  1377. g_ble_ll_supp_cmds_ro = 0x3ff4fd3c;
  1378. ble_ll_sync_env_p = 0x3fcdfedc;
  1379. g_ble_sca_ppm_tbl_ro = 0x3ff4fd2c;
  1380. priv_config_opts = 0x3fcdfe48;
  1381. ble_hci_uart_reset_cmd = 0x3ff4fd28;
  1382. ble_hci_trans_env_p = 0x3fcdfed8;
  1383. ble_hci_trans_mode = 0x3fcdfe44;
  1384. ble_hci_trans_funcs_ptr = 0x3fcdfed4;
  1385. r_ble_lll_stub_funcs_ptr = 0x3fcdfed0;
  1386. r_ble_stub_funcs_ptr = 0x3fcdfecc;
  1387. r_ext_funcs_p = 0x3fcdfec8;
  1388. r_npl_funcs = 0x3fcdfec4;
  1389. ble_hw_env_p = 0x3fcdfec0;
  1390. ble_phy_module_env_p = 0x3fcdfebc;
  1391. g_ble_phy_chan_freq_ro = 0x3ff4fd00;
  1392. g_ble_phy_mode_pkt_start_off_ro = 0x3ff4fcf8;
  1393. g_ble_phy_rxtx_ifs_compensation_ro = 0x3ff4fce8;
  1394. g_ble_phy_t_rxaddrdelay_ro = 0x3ff4fce4;
  1395. g_ble_phy_t_rxenddelay_ro = 0x3ff4fce0;
  1396. g_ble_phy_t_txdelay_ro = 0x3ff4fcdc;
  1397. g_ble_phy_t_txenddelay_ro = 0x3ff4fcd8;
  1398. g_ble_phy_txrx_ifs_compensation_ro = 0x3ff4fcc8;
  1399. hal_timer_env_p = 0x3fcdfeb8;
  1400. r_osi_coex_funcs_p = 0x3fcdfeb4;
  1401. bt_rf_coex_hooks = 0x3fcdfeac;
  1402. bt_rf_coex_hooks_p = 0x3fcdfea8;
  1403. coex_hook_st_group_tab = 0x3ff4fcbc;
  1404. coex_hook_st_group_to_coex_schm_st_tab = 0x3ff4fcb8;
  1405. s_ble_act_count_by_group = 0x3fcdfea4;
  1406. s_ble_coex_st_map = 0x3fcdfe90;
  1407. bt_rf_coex_cfg_cb = 0x3fcdfe74;
  1408. bt_rf_coex_cfg_p = 0x3fcdfe70;
  1409. bt_rf_coex_cfg_rom = 0x3ff4fc9c;
  1410. bt_rf_coex_pti_dft_p = 0x3fcdfe6c;
  1411. bt_rf_coex_pti_dft_rom = 0x3fcdfe04;
  1412. conn_dynamic_pti_param_rom = 0x3ff4fc84;
  1413. conn_phy_coded_max_data_time_param_rom = 0x3ff4fc80;
  1414. ext_adv_dynamic_pti_param_rom = 0x3ff4fc4c;
  1415. ext_scan_dynamic_param_rom = 0x3ff4fc14;
  1416. legacy_adv_dynamic_pti_param_rom = 0x3ff4fbf4;
  1417. per_adv_dynamic_pti_param_rom = 0x3ff4fbd8;
  1418. sync_dynamic_param_rom = 0x3ff4fbc0;
  1419. g_ble_plf_log_level = 0x3fcdfe00;
  1420. g_msys_pool_list = 0x3fcdfdf8;
  1421. g_os_mempool_list = 0x3fcdfdf0;
  1422. /***************************************
  1423. Group rom_pp
  1424. ***************************************/
  1425. /* Functions */
  1426. esp_pp_rom_version_get = 0x40001ad4;
  1427. RC_GetBlockAckTime = 0x40001ad8;
  1428. ebuf_list_remove = 0x40001adc;
  1429. /*esf_buf_alloc = 0x40001ae0;*/
  1430. /*esf_buf_alloc_dynamic = 0x40001ae4;*/
  1431. /*esf_buf_recycle = 0x40001ae8;*/
  1432. GetAccess = 0x40001aec;
  1433. hal_mac_is_low_rate_enabled = 0x40001af0;
  1434. hal_mac_tx_get_blockack = 0x40001af4;
  1435. hal_mac_tx_set_ppdu = 0x40001af8;
  1436. ic_get_trc = 0x40001afc;
  1437. /* ic_mac_deinit = 0x40001b00; */
  1438. ic_mac_init = 0x40001b04;
  1439. ic_interface_enabled = 0x40001b08;
  1440. is_lmac_idle = 0x40001b0c;
  1441. /*lmacAdjustTimestamp = 0x40001b10;*/
  1442. lmacDiscardAgedMSDU = 0x40001b14;
  1443. /*lmacDiscardMSDU = 0x40001b18;*/
  1444. lmacEndFrameExchangeSequence = 0x40001b1c;
  1445. lmacIsIdle = 0x40001b20;
  1446. lmacIsLongFrame = 0x40001b24;
  1447. /*lmacMSDUAged = 0x40001b28;*/
  1448. lmacPostTxComplete = 0x40001b2c;
  1449. lmacProcessAllTxTimeout = 0x40001b30;
  1450. lmacProcessCollisions = 0x40001b34;
  1451. lmacProcessRxSucData = 0x40001b38;
  1452. lmacReachLongLimit = 0x40001b3c;
  1453. lmacReachShortLimit = 0x40001b40;
  1454. lmacRecycleMPDU = 0x40001b44;
  1455. lmacRxDone = 0x40001b48;
  1456. /*lmacSetTxFrame = 0x40001b4c;*/
  1457. lmacTxDone = 0x40001b50;
  1458. lmacTxFrame = 0x40001b54;
  1459. mac_tx_set_duration = 0x40001b58;
  1460. mac_tx_set_htsig = 0x40001b5c;
  1461. mac_tx_set_plcp0 = 0x40001b60;
  1462. mac_tx_set_plcp1 = 0x40001b64;
  1463. mac_tx_set_plcp2 = 0x40001b68;
  1464. /* pm_check_state = 0x40001b6c; */
  1465. pm_disable_dream_timer = 0x40001b70;
  1466. pm_disable_sleep_delay_timer = 0x40001b74;
  1467. pm_dream = 0x40001b78;
  1468. pm_mac_wakeup = 0x40001b7c;
  1469. pm_mac_sleep = 0x40001b80;
  1470. pm_enable_active_timer = 0x40001b84;
  1471. pm_enable_sleep_delay_timer = 0x40001b88;
  1472. pm_local_tsf_process = 0x40001b8c;
  1473. pm_set_beacon_filter = 0x40001b90;
  1474. pm_is_in_wifi_slice_threshold = 0x40001b94;
  1475. pm_is_waked = 0x40001b98;
  1476. pm_keep_alive = 0x40001b9c;
  1477. /* pm_on_beacon_rx = 0x40001ba0; */
  1478. pm_on_data_rx = 0x40001ba4;
  1479. pm_on_tbtt = 0x40001ba8;
  1480. /* pm_parse_beacon = 0x40001bac;*/
  1481. /* pm_process_tim = 0x40001bb0; */
  1482. /*pm_rx_beacon_process = 0x40001bb4;*/
  1483. /* pm_rx_data_process = 0x40001bb8; */
  1484. /*pm_sleep = 0x40001bbc;*/
  1485. pm_sleep_for = 0x40001bc0;
  1486. /* pm_tbtt_process = 0x40001bc4; */
  1487. ppAMPDU2Normal = 0x40001bc8;
  1488. /*ppAssembleAMPDU = 0x40001bcc;*/
  1489. ppCalFrameTimes = 0x40001bd0;
  1490. ppCalSubFrameLength = 0x40001bd4;
  1491. /*ppCalTxAMPDULength = 0x40001bd8;*/
  1492. ppCheckTxAMPDUlength = 0x40001bdc;
  1493. ppDequeueRxq_Locked = 0x40001be0;
  1494. ppDequeueTxQ = 0x40001be4;
  1495. ppEmptyDelimiterLength = 0x40001be8;
  1496. ppEnqueueRxq = 0x40001bec;
  1497. ppEnqueueTxDone = 0x40001bf0;
  1498. ppGetTxQFirstAvail_Locked = 0x40001bf4;
  1499. ppGetTxframe = 0x40001bf8;
  1500. ppMapTxQueue = 0x40001bfc;
  1501. ppProcTxSecFrame = 0x40001c00;
  1502. ppProcessRxPktHdr = 0x40001c04;
  1503. ppProcessTxQ = 0x40001c08;
  1504. ppRecordBarRRC = 0x40001c0c;
  1505. lmacRequestTxopQueue = 0x40001c10;
  1506. lmacReleaseTxopQueue = 0x40001c14;
  1507. ppRecycleAmpdu = 0x40001c18;
  1508. ppRecycleRxPkt = 0x40001c1c;
  1509. ppResortTxAMPDU = 0x40001c20;
  1510. ppResumeTxAMPDU = 0x40001c24;
  1511. /*ppRxFragmentProc = 0x40001c28;*/
  1512. /* ppRxPkt = 0x40001c2c; */
  1513. ppRxProtoProc = 0x40001c30;
  1514. ppSearchTxQueue = 0x40001c34;
  1515. ppSearchTxframe = 0x40001c38;
  1516. ppSelectNextQueue = 0x40001c3c;
  1517. ppSubFromAMPDU = 0x40001c40;
  1518. ppTask = 0x40001c44;
  1519. ppTxPkt = 0x40001c48;
  1520. ppTxProtoProc = 0x40001c4c;
  1521. ppTxqUpdateBitmap = 0x40001c50;
  1522. pp_coex_tx_request = 0x40001c54;
  1523. pp_hdrsize = 0x40001c58;
  1524. pp_post = 0x40001c5c;
  1525. pp_process_hmac_waiting_txq = 0x40001c60;
  1526. rcGetAmpduSched = 0x40001c64;
  1527. rcUpdateRxDone = 0x40001c68;
  1528. rc_get_trc = 0x40001c6c;
  1529. rc_get_trc_by_index = 0x40001c70;
  1530. rcAmpduLowerRate = 0x40001c74;
  1531. rcampduuprate = 0x40001c78;
  1532. rcClearCurAMPDUSched = 0x40001c7c;
  1533. rcClearCurSched = 0x40001c80;
  1534. rcClearCurStat = 0x40001c84;
  1535. /*rcGetSched = 0x40001c88;*/
  1536. rcLowerSched = 0x40001c8c;
  1537. rcSetTxAmpduLimit = 0x40001c90;
  1538. /* rcTxUpdatePer = 0x40001c94;*/
  1539. rcUpdateAckSnr = 0x40001c98;
  1540. /*rcUpdateRate = 0x40001c9c;*/
  1541. rcUpdateTxDone = 0x40001ca0;
  1542. rcUpdateTxDoneAmpdu2 = 0x40001ca4;
  1543. rcUpSched = 0x40001ca8;
  1544. rssi_margin = 0x40001cac;
  1545. rx11NRate2AMPDULimit = 0x40001cb0;
  1546. TRC_AMPDU_PER_DOWN_THRESHOLD = 0x40001cb4;
  1547. TRC_AMPDU_PER_UP_THRESHOLD = 0x40001cb8;
  1548. trc_calc_duration = 0x40001cbc;
  1549. trc_isTxAmpduOperational = 0x40001cc0;
  1550. trc_onAmpduOp = 0x40001cc4;
  1551. TRC_PER_IS_GOOD = 0x40001cc8;
  1552. trc_SetTxAmpduState = 0x40001ccc;
  1553. trc_tid_isTxAmpduOperational = 0x40001cd0;
  1554. trcAmpduSetState = 0x40001cd4;
  1555. wDevCheckBlockError = 0x40001cd8;
  1556. wDev_AppendRxBlocks = 0x40001cdc;
  1557. wDev_DiscardFrame = 0x40001ce0;
  1558. wDev_GetNoiseFloor = 0x40001ce4;
  1559. wDev_IndicateAmpdu = 0x40001ce8;
  1560. /*wDev_IndicateFrame = 0x40001cec;*/
  1561. wdev_mac_reg_load = 0x40001cf0;
  1562. wdev_mac_reg_store = 0x40001cf4;
  1563. wdev_mac_special_reg_load = 0x40001cf8;
  1564. wdev_mac_special_reg_store = 0x40001cfc;
  1565. wdev_mac_wakeup = 0x40001d00;
  1566. wdev_mac_sleep = 0x40001d04;
  1567. /* wDev_ProcessFiq = 0x40001d08; */
  1568. /*wDev_ProcessRxSucData = 0x40001d0c;*/
  1569. wdevProcessRxSucDataAll = 0x40001d10;
  1570. wdev_csi_len_align = 0x40001d14;
  1571. ppDequeueTxDone_Locked = 0x40001d18;
  1572. ppProcTxDone = 0x40001d1c;
  1573. /*pm_tx_data_done_process = 0x40001d20;*/
  1574. config_is_cache_tx_buf_enabled = 0x40001d24;
  1575. //ppMapWaitTxq = 0x40001d28;
  1576. ppProcessWaitingQueue = 0x40001d2c;
  1577. ppDisableQueue = 0x40001d30;
  1578. pm_allow_tx = 0x40001d34;
  1579. wdev_is_data_in_rxlist = 0x40001d38;
  1580. ppProcTxCallback = 0x40001d3c;
  1581. pm_is_open = 0x40001d40;
  1582. pm_wake_up = 0x40001d44;
  1583. pm_wake_done = 0x40001d48;
  1584. pm_disable_disconnected_sleep_delay_timer = 0x40001d4c;
  1585. pm_enable_disconnected_sleep_delay_timer = 0x40001d50;
  1586. hal_mac_get_txq_state = 0x40001d54;
  1587. hal_mac_clr_txq_state = 0x40001d58;
  1588. hal_mac_tx_set_cca = 0x40001d5c;
  1589. hal_mac_set_txq_invalid = 0x40001d60;
  1590. hal_mac_txq_disable = 0x40001d64;
  1591. hal_mac_is_txq_enabled = 0x40001d68;
  1592. hal_mac_get_txq_pmd = 0x40001d6c;
  1593. lmacDiscardFrameExchangeSequence = 0x40001d70;
  1594. lmacDisableTransmit = 0x40001d74;
  1595. lmacProcessTxTimeout = 0x40001d78;
  1596. /*lmacProcessTxSuccess = 0x40001d7c;*/
  1597. lmacProcessCollision = 0x40001d80;
  1598. lmacProcessTxRtsError = 0x40001d84;
  1599. lmacProcessCtsTimeout = 0x40001d88;
  1600. /* lmacProcessTxComplete = 0x40001d8c;*/
  1601. lmacProcessAckTimeout = 0x40001d90;
  1602. lmacProcessTxError = 0x40001d94;
  1603. lmacProcessTxseckiderr = 0x40001d98;
  1604. rcReachRetryLimit = 0x40001d9c;
  1605. lmacProcessShortRetryFail = 0x40001da0;
  1606. lmacEndRetryAMPDUFail = 0x40001da4;
  1607. ppFillAMPDUBar = 0x40001da8;
  1608. rcGetRate = 0x40001dac;
  1609. ppReSendBar = 0x40001db0;
  1610. lmacProcessLongRetryFail = 0x40001db4;
  1611. lmacRetryTxFrame = 0x40001db8;
  1612. lmacProcessCollisions_task = 0x40001dbc;
  1613. /*lmacProcessTxopQComplete = 0x40001dc0;*/
  1614. lmacInitAc = 0x40001dc4;
  1615. /*lmacInit = 0x40001dc8;*/
  1616. mac_tx_set_txop_q = 0x40001dcc;
  1617. /*hal_init = 0x40001dd0;*/
  1618. hal_mac_rx_set_policy = 0x40001dd4;
  1619. hal_mac_set_bssid = 0x40001dd8;
  1620. mac_rx_policy_init = 0x40001ddc;
  1621. /*mac_txrx_init = 0x40001de0;*/
  1622. mac_rxbuf_init = 0x40001de4;
  1623. mac_last_rxbuf_init = 0x40001de8;
  1624. hal_attenna_init = 0x40001dec;
  1625. hal_timer_update_by_rtc = 0x40001df0;
  1626. hal_coex_pti_init = 0x40001df4;
  1627. lmac_stop_hw_txq = 0x40001df8;
  1628. ppDirectRecycleAmpdu = 0x40001dfc;
  1629. esp_wifi_internal_set_rts = 0x40001e00;
  1630. esp_wifi_internal_get_rts = 0x40001e04;
  1631. /*ppTxFragmentProc = 0x40001e08;*/
  1632. /*esf_buf_setup = 0x40001e0c;*/
  1633. hal_agreement_add_rx_ba = 0x40001e10;
  1634. hal_agreement_del_rx_ba = 0x40001e14;
  1635. /*hal_crypto_set_key_entry = 0x40001e18;*/
  1636. hal_crypto_get_key_entry = 0x40001e1c;
  1637. hal_crypto_clr_key_entry = 0x40001e20;
  1638. config_get_wifi_task_stack_size = 0x40001e24;
  1639. pp_create_task = 0x40001e28;
  1640. hal_set_sta_tsf_wakeup = 0x40001e2c;
  1641. hal_set_rx_beacon_pti = 0x40001e30;
  1642. /* pm_start = 0x40001e34; */
  1643. /* pm_stop = 0x40001e38; */
  1644. hal_disable_sta_tbtt = 0x40001e3c;
  1645. ppCalTxopDur = 0x40001e40;
  1646. wDev_IndicateCtrlFrame = 0x40001e44;
  1647. hal_enable_sta_tbtt = 0x40001e48;
  1648. hal_set_sta_tbtt = 0x40001e4c;
  1649. /* pm_update_next_tbtt = 0x40001e50;*/
  1650. /* pm_set_sleep_type = 0x40001e54; */
  1651. wDev_Rxbuf_Init = 0x40001e58;
  1652. wDev_Rxbuf_Deinit = 0x40001e5c;
  1653. ppCalTkipMic = 0x40001e60;
  1654. wDev_SnifferRxData = 0x40001e64;
  1655. hal_crypto_enable = 0x40001e68;
  1656. hal_crypto_disable = 0x40001e6c;
  1657. wDev_Insert_KeyEntry = 0x40001e70;
  1658. wDev_remove_KeyEntry = 0x40001e74;
  1659. rc_enable_trc = 0x40001e78;
  1660. rc_set_per_conn_fix_rate = 0x40001e7c;
  1661. wdev_csi_rx_process = 0x40001e80;
  1662. wDev_SnifferRxAmpdu = 0x40001e84;
  1663. hal_mac_tsf_reset = 0x40001e88;
  1664. dbg_lmac_statis_dump = 0x40001e8c;
  1665. dbg_lmac_rxtx_statis_dump = 0x40001e90;
  1666. dbg_lmac_hw_statis_dump = 0x40001e94;
  1667. dbg_lmac_diag_statis_dump = 0x40001e98;
  1668. dbg_lmac_ps_statis_dump = 0x40001e9c;
  1669. pp_timer_do_process = 0x40001ea0;
  1670. rcUpdateAMPDUParam = 0x40001ea4;
  1671. rcUpdatePhyMode = 0x40001ea8;
  1672. rcGetHighestRateIdx = 0x40001eac;
  1673. //pm_tx_null_data_done_process = 0x40001eb0;
  1674. //pm_tx_data_process = 0x40001eb4;
  1675. /* pm_attach = 0x40001eb8; */
  1676. /* pm_coex_schm_process = 0x40001ebc; */
  1677. ppInitTxq = 0x40001ec0;
  1678. pp_attach = 0x40001ec4;
  1679. pp_deattach = 0x40001ec8;
  1680. //pm_on_probe_resp_rx = 0x40001ecc;
  1681. hal_set_sta_tsf = 0x40001ed0;
  1682. ic_update_sta_tsf = 0x40001ed4;
  1683. ic_tx_pkt = 0x40001ed8;
  1684. //pm_send_probe_stop = 0x40001edc;
  1685. pm_send_probe_start = 0x40001ee0;
  1686. pm_on_coex_schm_process_restart = 0x40001ee4;
  1687. hal_mac_set_rxq_policy = 0x40001ee8;
  1688. hal_sniffer_enable = 0x40001eec;
  1689. hal_sniffer_disable = 0x40001ef0;
  1690. /*hal_sniffer_rx_set_promis = 0x40001ef4;*/
  1691. hal_sniffer_rx_clr_statistics = 0x40001ef8;
  1692. hal_sniffer_set_promis_misc_pkt = 0x40001efc;
  1693. tsf_hal_set_tsf_enable = 0x40001f00;
  1694. tsf_hal_set_tsf_disable = 0x40001f04;
  1695. tsf_hal_is_tsf_enabled = 0x40001f08;
  1696. tsf_hal_set_modem_wakeup_early_time = 0x40001f0c;
  1697. tsf_hal_get_counter_value = 0x40001f10;
  1698. tsf_hal_set_counter_value = 0x40001f14;
  1699. tsf_hal_get_time = 0x40001f18;
  1700. tsf_hal_set_time = 0x40001f1c;
  1701. tsf_hal_set_tbtt_enable = 0x40001f20;
  1702. tsf_hal_set_tbtt_disable = 0x40001f24;
  1703. tsf_hal_set_tbtt_intr_enable = 0x40001f28;
  1704. tsf_hal_set_tbtt_intr_disable = 0x40001f2c;
  1705. tsf_hal_set_tbtt_soc_wakeup_enable = 0x40001f30;
  1706. tsf_hal_set_tbtt_soc_wakeup_disable = 0x40001f34;
  1707. tsf_hal_set_tbtt_start_time = 0x40001f38;
  1708. tsf_hal_set_tbtt_early_time = 0x40001f3c;
  1709. tsf_hal_set_tbtt_interval = 0x40001f40;
  1710. tsf_hal_get_tbtt_interval = 0x40001f44;
  1711. tsf_hal_set_timer_enable = 0x40001f48;
  1712. tsf_hal_set_timer_disable = 0x40001f4c;
  1713. tsf_hal_set_timer_target = 0x40001f50;
  1714. tsf_hal_get_timer_target = 0x40001f54;
  1715. tsf_hal_set_timer_intr_enable = 0x40001f58;
  1716. tsf_hal_set_timer_intr_disable = 0x40001f5c;
  1717. tsf_hal_set_timer_soc_wakeup_enable = 0x40001f60;
  1718. tsf_hal_set_timer_soc_wakeup_disable = 0x40001f64;
  1719. pm_disconnected_wake = 0x40001f68;
  1720. pm_get_connectionless_status = 0x40001f6c;
  1721. pm_update_by_connectionless_status = 0x40001f70;
  1722. pm_connectionless_wake_interval_timeout_process = 0x40001f74;
  1723. pm_connectionless_wake_window_timeout_process = 0x40001f78;
  1724. /* Data (.data, .bss, .rodata) */
  1725. our_instances_ptr = 0x3ff4fbbc;
  1726. pTxRx = 0x3fcdfdec;
  1727. lmacConfMib_ptr = 0x3fcdfde8;
  1728. our_wait_eb = 0x3fcdfde4;
  1729. our_tx_eb = 0x3fcdfde0;
  1730. pp_wdev_funcs = 0x3fcdfddc;
  1731. g_osi_funcs_p = 0x3fcdfdd8;
  1732. wDevCtrl_ptr = 0x3fcdfdd4;
  1733. g_wdev_last_desc_reset_ptr = 0x3ff4fbb8;
  1734. wDevMacSleep_ptr = 0x3fcdfdd0;
  1735. g_lmac_cnt_ptr = 0x3fcdfdcc;
  1736. our_controls_ptr = 0x3ff4fbb4;
  1737. pp_sig_cnt_ptr = 0x3fcdfdc8;
  1738. g_eb_list_desc_ptr = 0x3fcdfdc4;
  1739. s_fragment_ptr = 0x3fcdfdc0;
  1740. if_ctrl_ptr = 0x3fcdfdbc;
  1741. g_intr_lock_mux = 0x3fcdfdb8;
  1742. g_wifi_global_lock = 0x3fcdfdb4;
  1743. s_wifi_queue = 0x3fcdfdb0;
  1744. pp_task_hdl = 0x3fcdfdac;
  1745. s_pp_task_create_sem = 0x3fcdfda8;
  1746. s_pp_task_del_sem = 0x3fcdfda4;
  1747. g_wifi_menuconfig_ptr = 0x3fcdfda0;
  1748. xphyQueue = 0x3fcdfd9c;
  1749. ap_no_lr_ptr = 0x3fcdfd98;
  1750. rc11BSchedTbl_ptr = 0x3fcdfd94;
  1751. rc11NSchedTbl_ptr = 0x3fcdfd90;
  1752. rcLoRaSchedTbl_ptr = 0x3fcdfd8c;
  1753. BasicOFDMSched_ptr = 0x3fcdfd88;
  1754. trc_ctl_ptr = 0x3fcdfd84;
  1755. g_pm_cnt_ptr = 0x3fcdfd80;
  1756. g_pm_ptr = 0x3fcdfd7c;
  1757. g_pm_cfg_ptr = 0x3fcdfd78;
  1758. g_esp_mesh_quick_funcs_ptr = 0x3fcdfd74;
  1759. g_txop_queue_status_ptr = 0x3fcdfd70;
  1760. g_mac_sleep_en_ptr = 0x3fcdfd6c;
  1761. g_mesh_is_root_ptr = 0x3fcdfd68;
  1762. g_mesh_topology_ptr = 0x3fcdfd64;
  1763. g_mesh_init_ps_type_ptr = 0x3fcdfd60;
  1764. g_mesh_is_started_ptr = 0x3fcdfd5c;
  1765. g_config_func = 0x3fcdfd58;
  1766. g_net80211_tx_func = 0x3fcdfd54;
  1767. g_timer_func = 0x3fcdfd50;
  1768. s_michael_mic_failure_cb = 0x3fcdfd4c;
  1769. wifi_sta_rx_probe_req = 0x3fcdfd48;
  1770. g_tx_done_cb_func = 0x3fcdfd44;
  1771. g_per_conn_trc = 0x3fcdfd28;
  1772. s_encap_amsdu_func = 0x3fcdfd24;
  1773. bars = 0x3fcdfc84;
  1774. eb_txdesc_space = 0x3fcdfbf4;
  1775. eb_space = 0x3fcdfb54;
  1776. g_pd_mac_in_light_sleep = 0x3fcdfb50;
  1777. s_fix_rate_mask = 0x3fcdfb4c;
  1778. s_fix_rate = 0x3fcdfb44;
  1779. g_wdev_csi_rx = 0x3fcdfb40;
  1780. g_wdev_csi_rx_ctx = 0x3fcdfb3c;
  1781. BcnSendTick = 0x3fcdfb38;
  1782. g_pp_timer_info_ptr = 0x3fcdfb34;
  1783. rcP2P11NSchedTbl_ptr = 0x3fcdfb30;
  1784. rcP2P11GSchedTbl_ptr = 0x3fcdfb2c;
  1785. rc11GSchedTbl_ptr = 0x3fcdfb28;
  1786. /***************************************
  1787. Group rom_net80211
  1788. ***************************************/
  1789. /* Functions */
  1790. esp_net80211_rom_version_get = 0x40001f7c;
  1791. ampdu_dispatch = 0x40001f80;
  1792. ampdu_dispatch_all = 0x40001f84;
  1793. ampdu_dispatch_as_many_as_possible = 0x40001f88;
  1794. ampdu_dispatch_movement = 0x40001f8c;
  1795. ampdu_dispatch_upto = 0x40001f90;
  1796. chm_is_at_home_channel = 0x40001f94;
  1797. cnx_node_is_existing = 0x40001f98;
  1798. cnx_node_search = 0x40001f9c;
  1799. ic_ebuf_recycle_rx = 0x40001fa0;
  1800. ic_ebuf_recycle_tx = 0x40001fa4;
  1801. ic_reset_rx_ba = 0x40001fa8;
  1802. ieee80211_align_eb = 0x40001fac;
  1803. ieee80211_ampdu_reorder = 0x40001fb0;
  1804. ieee80211_ampdu_start_age_timer = 0x40001fb4;
  1805. ieee80211_encap_esfbuf = 0x40001fb8;
  1806. ieee80211_is_tx_allowed = 0x40001fbc;
  1807. ieee80211_output_pending_eb = 0x40001fc0;
  1808. /* ieee80211_output_process = 0x40001fc4; */
  1809. ieee80211_set_tx_desc = 0x40001fc8;
  1810. /*sta_input = 0x40001fcc;*/
  1811. wifi_get_macaddr = 0x40001fd0;
  1812. wifi_rf_phy_disable = 0x40001fd4;
  1813. wifi_rf_phy_enable = 0x40001fd8;
  1814. ic_ebuf_alloc = 0x40001fdc;
  1815. ieee80211_classify = 0x40001fe0;
  1816. ieee80211_copy_eb_header = 0x40001fe4;
  1817. ieee80211_recycle_cache_eb = 0x40001fe8;
  1818. ieee80211_search_node = 0x40001fec;
  1819. roundup2 = 0x40001ff0;
  1820. ieee80211_crypto_encap = 0x40001ff4;
  1821. /* ieee80211_crypto_decap = 0x40001ff8; */
  1822. ieee80211_decap = 0x40001ffc;
  1823. ieee80211_set_tx_pti = 0x40002000;
  1824. wifi_is_started = 0x40002004;
  1825. ieee80211_gettid = 0x40002008;
  1826. ieee80211_ccmp_decrypt = 0x4000200c;
  1827. ieee80211_ccmp_encrypt = 0x40002010;
  1828. ccmp_encap = 0x40002014;
  1829. ccmp_decap = 0x40002018;
  1830. tkip_encap = 0x4000201c;
  1831. tkip_decap = 0x40002020;
  1832. wep_encap = 0x40002024;
  1833. wep_decap = 0x40002028;
  1834. dbg_hmac_rxtx_statis_dump = 0x4000202c;
  1835. dbg_hmac_statis_dump = 0x40002030;
  1836. /* ieee80211_send_action_vendor_spec = 0x40002034; */
  1837. ieee80211_vnd_lora_ie_size = 0x40002048;
  1838. ieee80211_vnd_ie_size = 0x4000204c;
  1839. ieee80211_add_ssid = 0x40002050;
  1840. ieee80211_add_rates = 0x40002054;
  1841. ieee80211_add_xrates = 0x40002058;
  1842. ieee80211_is_ht_cipher = 0x4000205c;
  1843. ieee80211_setup_lr_rates = 0x40002068;
  1844. ieee80211_ht_node_init = 0x4000206c;
  1845. ieee80211_is_support_rate = 0x40002070;
  1846. ieee80211_setup_rates = 0x40002074;
  1847. ieee80211_is_lr_only = 0x40002078;
  1848. ieee80211_setup_phy_mode = 0x4000207c;
  1849. ieee80211_sta_is_connected = 0x40002080;
  1850. current_task_is_wifi_task = 0x40002084;
  1851. wifi_get_init_state = 0x40002088;
  1852. /* ieee80211_timer_process = 0x4000208c; */
  1853. /* cnx_coexist_timeout = 0x40002090; */
  1854. /* sta_recv_mgmt = 0x40002094;*/
  1855. ieee80211_send_setup = 0x40002098;
  1856. //ieee80211_send_probereq = 0x4000209c;
  1857. sta_auth_shared = 0x400020a4;
  1858. /* cnx_coexist_timeout_process = 0x400020ac; */
  1859. ieee80211_alloc_challenge = 0x400020b0;
  1860. cnx_assoc_timeout = 0x400020b4;
  1861. ieee80211_vnd_ie_set = 0x400020b8;
  1862. ieee80211_vnd_lora_ie_set = 0x400020bc;
  1863. ieee80211_add_wme_param = 0x400020c0;
  1864. ieee80211_add_dsparams = 0x400020c4;
  1865. ieee80211_add_csa = 0x400020c8;
  1866. /*ieee80211_add_extcap = 0x400020cc;*/
  1867. ieee80211_regdomain_get_country = 0x400020d0;
  1868. ieee80211_add_countryie = 0x400020d4;
  1869. ieee80211_amsdu_adjust_head = 0x400020dc;
  1870. ieee80211_amsdu_adjust_last_length = 0x400020e0;
  1871. ieee80211_amsdu_send_check = 0x400020e4;
  1872. ieee80211_amsdu_encap_check = 0x400020e8;
  1873. ieee80211_amsdu_length_check = 0x400020ec;
  1874. ieee80211_encap_amsdu = 0x400020f0;
  1875. ieee80211_output_raw_process = 0x400020f4;
  1876. ieee80211_raw_frame_sanity_check = 0x400020fc;
  1877. ieee80211_crypto_aes_128_cmac_encrypt = 0x40002100;
  1878. ieee80211_alloc_tx_buf = 0x40002108;
  1879. /* ieee80211_output_do = 0x4000210c; */
  1880. /* ieee80211_send_nulldata = 0x40002110; */
  1881. ieee80211_setup_robust_mgmtframe = 0x40002114;
  1882. ieee80211_encap_null_data = 0x4000211c;
  1883. ieee80211_send_deauth = 0x40002120;
  1884. ieee80211_alloc_deauth = 0x40002124;
  1885. ieee80211_send_proberesp = 0x40002128;
  1886. ieee80211_getcapinfo = 0x40002130;
  1887. sta_rx_csa = 0x40002134;
  1888. /* sta_recv_sa_query_resp = 0x40002144; */
  1889. ieee80211_set_max_rate = 0x4000214c;
  1890. ic_set_sta = 0x40002150;
  1891. ieee80211_parse_wpa = 0x40002158;
  1892. ieee80211_add_assoc_req_ies = 0x40002160;
  1893. ieee80211_add_probe_req_ies = 0x40002164;
  1894. /* Data (.data, .bss, .rodata) */
  1895. net80211_funcs = 0x3fcdfb24;
  1896. g_scan = 0x3fcdfb20;
  1897. g_chm = 0x3fcdfb1c;
  1898. g_ic_ptr = 0x3fcdfb18;
  1899. g_hmac_cnt_ptr = 0x3fcdfaf4;
  1900. g_tx_cacheq_ptr = 0x3fcdfb14;
  1901. s_netstack_free = 0x3fcdfb10;
  1902. mesh_rxcb = 0x3fcdfb0c;
  1903. sta_rxcb = 0x3fcdfb08;
  1904. ccmp_ptr = 0x3fcdfb04;
  1905. s_wifi_nvs_ptr = 0x3fcdfb00;
  1906. tkip_ptr = 0x3fcdfafc;
  1907. wep_ptr = 0x3fcdfaf8;
  1908. g_hmac_cnt_ptr = 0x3fcdfaf4;
  1909. g_misc_nvs = 0x3fcdfaf0;
  1910. s_wifi_init_state = 0x3fcdfac0;
  1911. s_wifi_task_hdl = 0x3fcdfaec;
  1912. in_rssi_adjust = 0x3fcdfae8;
  1913. rssi_saved = 0x3fcdfae0;
  1914. rssi_index = 0x3fcdfadc;
  1915. /* s_sa_query_retries = 0x3fcdfad8; */
  1916. /* s_sa_query_success = 0x3fcdfad5; */
  1917. g_sta_connected_flag = 0x3fcdfad4;
  1918. wpa_crypto_funcs_ptr = 0x3fcdfad0;
  1919. s_netstack_ref = 0x3fcdfacc;
  1920. sta_csa_timer_ptr = 0x3fcdfac8;
  1921. /* s_trans_id = 0x3fcdfac4; */
  1922. /***************************************
  1923. Group rom_coexist
  1924. ***************************************/
  1925. /* Functions */
  1926. esp_coex_rom_version_get = 0x40002168;
  1927. coex_bt_release = 0x4000216c;
  1928. coex_bt_request = 0x40002170;
  1929. coex_core_ble_conn_dyn_prio_get = 0x40002174;
  1930. coex_core_event_duration_get = 0x40002178;
  1931. coex_core_pti_get = 0x4000217c;
  1932. coex_core_release = 0x40002180;
  1933. coex_core_request = 0x40002184;
  1934. coex_core_status_get = 0x40002188;
  1935. coex_core_timer_idx_get = 0x4000218c;
  1936. coex_event_duration_get = 0x40002190;
  1937. coex_hw_timer_disable = 0x40002194;
  1938. coex_hw_timer_enable = 0x40002198;
  1939. coex_hw_timer_set = 0x4000219c;
  1940. coex_schm_interval_set = 0x400021a0;
  1941. coex_schm_lock = 0x400021a4;
  1942. coex_schm_unlock = 0x400021a8;
  1943. coex_status_get = 0x400021ac;
  1944. coex_wifi_release = 0x400021b0;
  1945. esp_coex_ble_conn_dynamic_prio_get = 0x400021b4;
  1946. /*coex_hw_timer_tick_get = 0x400021b8;*/
  1947. /* Data (.data, .bss, .rodata) */
  1948. coex_env_ptr = 0x3fcdfabc;
  1949. coex_pti_tab_ptr = 0x3fcdfab8;
  1950. coex_schm_env_ptr = 0x3fcdfab4;
  1951. coexist_funcs = 0x3fcdfab0;
  1952. g_coa_funcs_p = 0x3fcdfaac;
  1953. g_coex_param_ptr = 0x3fcdfaa8;
  1954. /***************************************
  1955. Group rom_phy
  1956. ***************************************/
  1957. /* Functions */
  1958. phy_param_addr = 0x400021bc;
  1959. phy_get_romfuncs = 0x400021c0;
  1960. chip729_phyrom_version = 0x400021c4;
  1961. chip729_phyrom_version_num = 0x400021c8;
  1962. rom_get_rc_dout = 0x400021cc;
  1963. rc_cal = 0x400021d0;
  1964. phy_analog_delay_cal = 0x400021d4;
  1965. phy_rx_rifs_en = 0x400021d8;
  1966. phy_current_level_set = 0x400021dc;
  1967. phy_bbpll_en_usb = 0x400021e0;
  1968. phy_bt_power_track = 0x400021e4;
  1969. /* phy_xpd_tsens = 0x400021e8); Link this function in phy_lib, no longer link the rom one.*/
  1970. bb_wdt_rst_enable = 0x400021ec;
  1971. bb_wdt_int_enable = 0x400021f0;
  1972. bb_wdt_timeout_clear = 0x400021f4;
  1973. bb_wdt_get_status = 0x400021f8;
  1974. rom_enter_critical_phy = 0x400021fc;
  1975. rom_exit_critical_phy = 0x40002200;
  1976. rom_bb_bss_cbw40 = 0x40002204;
  1977. rom_set_chan_reg = 0x40002208;
  1978. abs_temp = 0x4000220c;
  1979. set_chan_cal_interp = 0x40002210;
  1980. loopback_mode_en = 0x40002214;
  1981. get_data_sat = 0x40002218;
  1982. phy_byte_to_word = 0x4000221c;
  1983. phy_get_rx_freq = 0x40002220;
  1984. i2c_master_reset = 0x40002224;
  1985. chan14_mic_enable = 0x40002228;
  1986. chan14_mic_cfg = 0x4000222c;
  1987. set_adc_rand = 0x40002230;
  1988. phy_set_most_tpw = 0x40002234;
  1989. phy_get_most_tpw = 0x40002238;
  1990. esp_tx_state_out = 0x4000223c;
  1991. phy_get_adc_rand = 0x40002240;
  1992. phy_internal_delay = 0x40002244;
  1993. phy_ftm_comp = 0x40002248;
  1994. phy_11p_set = 0x4000224c;
  1995. phy_freq_mem_backup = 0x40002250;
  1996. ant_dft_cfg = 0x40002254;
  1997. ant_wifitx_cfg = 0x40002258;
  1998. ant_wifirx_cfg = 0x4000225c;
  1999. ant_bttx_cfg = 0x40002260;
  2000. ant_btrx_cfg = 0x40002264;
  2001. phy_chan_dump_cfg = 0x40002268;
  2002. phy_enable_low_rate = 0x4000226c;
  2003. phy_disable_low_rate = 0x40002270;
  2004. phy_dig_reg_backup = 0x40002274;
  2005. phy_chan_filt_set = 0x40002278;
  2006. phy_rx11blr_cfg = 0x4000227c;
  2007. set_cca = 0x40002280;
  2008. set_rx_sense = 0x40002284;
  2009. rx_gain_force = 0x40002288;
  2010. rom_phy_en_hw_set_freq = 0x4000228c;
  2011. rom_phy_dis_hw_set_freq = 0x40002290;
  2012. wr_rf_freq_mem = 0x40002294;
  2013. freq_i2c_write_set = 0x40002298;
  2014. write_pll_cap_mem = 0x4000229c;
  2015. pll_dac_mem_update = 0x400022a0;
  2016. pll_cap_mem_update = 0x400022a4;
  2017. get_rf_freq_cap = 0x400022a8;
  2018. get_rf_freq_init = 0x400022ac;
  2019. freq_get_i2c_data = 0x400022b0;
  2020. freq_i2c_data_write = 0x400022b4;
  2021. set_chan_freq_hw_init = 0x400022b8;
  2022. set_chan_freq_sw_start = 0x400022bc;
  2023. rom_get_i2c_read_mask = 0x400022c0;
  2024. rom_get_i2c_mst0_mask = 0x400022c4;
  2025. rom_get_i2c_hostid = 0x400022c8;
  2026. rom_chip_i2c_readReg_org = 0x400022cc;
  2027. rom_chip_i2c_readReg = 0x400022d0;
  2028. rom_i2c_paral_set_mst0 = 0x400022d4;
  2029. rom_i2c_paral_set_read = 0x400022d8;
  2030. rom_i2c_paral_read = 0x400022dc;
  2031. rom_i2c_paral_write = 0x400022e0;
  2032. rom_i2c_paral_write_num = 0x400022e4;
  2033. rom_i2c_paral_write_mask = 0x400022e8;
  2034. rom_i2c_readReg = 0x400022ec;
  2035. rom_chip_i2c_writeReg = 0x400022f0;
  2036. rom_i2c_writeReg = 0x400022f4;
  2037. rom_i2c_readReg_Mask = 0x400022f8;
  2038. rom_i2c_writeReg_Mask = 0x400022fc;
  2039. rom_set_txcap_reg = 0x40002300;
  2040. i2c_sar2_init_code = 0x40002304;
  2041. phy_i2c_init1 = 0x40002308;
  2042. phy_i2c_init2 = 0x4000230c;
  2043. phy_get_i2c_data = 0x40002310;
  2044. bias_reg_set = 0x40002314;
  2045. i2c_rc_cal_set = 0x40002318;
  2046. i2c_bbpll_set = 0x4000231c;
  2047. rom_phy_xpd_rf = 0x40002320;
  2048. phy_wakeup_init_rom = 0x40002324;
  2049. register_chipv7_phy_init_param = 0x40002328;
  2050. phy_reg_init = 0x4000232c;
  2051. phy_close_rf_rom = 0x40002330;
  2052. rom_pbus_force_mode = 0x40002334;
  2053. rom_pbus_rd_addr = 0x40002338;
  2054. rom_pbus_rd_shift = 0x4000233c;
  2055. rom_pbus_force_test = 0x40002340;
  2056. rom_pbus_rd = 0x40002344;
  2057. rom_pbus_debugmode = 0x40002348;
  2058. rom_pbus_workmode = 0x4000234c;
  2059. rom_pbus_set_rxgain = 0x40002350;
  2060. rom_pbus_xpd_rx_off = 0x40002354;
  2061. rom_pbus_xpd_rx_on = 0x40002358;
  2062. rom_pbus_xpd_tx_off = 0x4000235c;
  2063. rom_pbus_xpd_tx_on = 0x40002360;
  2064. rom_pbus_set_dco = 0x40002364;
  2065. rom_set_loopback_gain = 0x40002368;
  2066. rom_txcal_debuge_mode = 0x4000236c;
  2067. rom_txcal_work_mode = 0x40002370;
  2068. set_pbus_mem = 0x40002374;
  2069. rom_pwdet_sar2_init = 0x40002378;
  2070. rom_en_pwdet = 0x4000237c;
  2071. rom_get_sar_sig_ref = 0x40002380;
  2072. rom_pwdet_tone_start = 0x40002384;
  2073. rom_get_tone_sar_dout = 0x40002388;
  2074. rom_get_fm_sar_dout = 0x4000238c;
  2075. rom_txtone_linear_pwr = 0x40002390;
  2076. rom_get_power_db = 0x40002394;
  2077. rom_meas_tone_pwr_db = 0x40002398;
  2078. rom_pkdet_vol_start = 0x4000239c;
  2079. rom_read_sar_dout = 0x400023a0;
  2080. rom_read_sar2_code = 0x400023a4;
  2081. rom_get_sar2_vol = 0x400023a8;
  2082. rom_get_pll_vol = 0x400023ac;
  2083. rom_tx_pwctrl_bg_init = 0x400023b0;
  2084. rom_phy_pwdet_always_en = 0x400023b4;
  2085. rom_phy_pwdet_onetime_en = 0x400023b8;
  2086. linear_to_db = 0x400023bc;
  2087. rom_disable_agc = 0x400023c0;
  2088. rom_enable_agc = 0x400023c4;
  2089. rom_disable_wifi_agc = 0x400023c8;
  2090. rom_enable_wifi_agc = 0x400023cc;
  2091. rom_write_gain_mem = 0x400023d0;
  2092. rom_bb_bss_cbw40_dig = 0x400023d4;
  2093. rom_cbw2040_cfg = 0x400023d8;
  2094. rom_mac_tx_chan_offset = 0x400023dc;
  2095. rom_tx_paon_set = 0x400023e0;
  2096. rom_i2cmst_reg_init = 0x400023e4;
  2097. rom_bt_gain_offset = 0x400023e8;
  2098. rom_fe_reg_init = 0x400023ec;
  2099. rom_mac_enable_bb = 0x400023f0;
  2100. rom_bb_wdg_cfg = 0x400023f4;
  2101. rom_fe_txrx_reset = 0x400023f8;
  2102. rom_set_rx_comp = 0x400023fc;
  2103. rom_write_chan_freq = 0x40002400;
  2104. rom_agc_reg_init = 0x40002404;
  2105. rom_bb_reg_init = 0x40002408;
  2106. rom_write_txrate_power_offset = 0x4000240c;
  2107. rom_open_i2c_xpd = 0x40002410;
  2108. rom_txiq_set_reg = 0x40002414;
  2109. rom_rxiq_set_reg = 0x40002418;
  2110. rom_phy_bbpll_cal = 0x4000241c;
  2111. phy_disable_cca = 0x40002420;
  2112. phy_enable_cca = 0x40002424;
  2113. force_txon = 0x40002428;
  2114. set_txclk_en = 0x4000242c;
  2115. set_rxclk_en = 0x40002430;
  2116. start_tx_tone_step = 0x40002434;
  2117. stop_tx_tone = 0x40002438;
  2118. bb_wdg_test_en = 0x4000243c;
  2119. noise_floor_auto_set = 0x40002440;
  2120. read_hw_noisefloor = 0x40002444;
  2121. iq_corr_enable = 0x40002448;
  2122. bt_tx_dig_gain = 0x4000244c;
  2123. wifi_tx_dig_reg = 0x40002450;
  2124. wifi_agc_sat_gain = 0x40002454;
  2125. phy_ant_init = 0x40002458;
  2126. phy_set_bbfreq_init = 0x4000245c;
  2127. wifi_fbw_sel = 0x40002460;
  2128. phy_rx_sense_set = 0x40002464;
  2129. tx_state_set = 0x40002468;
  2130. phy_close_pa = 0x4000246c;
  2131. bt_filter_reg = 0x40002470;
  2132. phy_freq_correct = 0x40002474;
  2133. set_pbus_reg = 0x40002478;
  2134. wifi_rifs_mode_en = 0x4000247c;
  2135. rfagc_disable = 0x40002480;
  2136. rom_restart_cal = 0x40002484;
  2137. rom_write_rfpll_sdm = 0x40002488;
  2138. rom_wait_rfpll_cal_end = 0x4000248c;
  2139. rom_rfpll_set_freq = 0x40002490;
  2140. rom_rfpll_cap_init_cal = 0x40002494;
  2141. rom_set_rfpll_freq = 0x40002498;
  2142. rom_write_pll_cap = 0x4000249c;
  2143. rom_read_pll_cap = 0x400024a0;
  2144. mhz2ieee = 0x400024a4;
  2145. chan_to_freq = 0x400024a8;
  2146. set_rf_freq_offset = 0x400024ac;
  2147. set_channel_rfpll_freq = 0x400024b0;
  2148. rfpll_cap_correct = 0x400024b4;
  2149. phy_set_freq = 0x400024b8;
  2150. correct_rfpll_offset = 0x400024bc;
  2151. pll_vol_cal = 0x400024c0;
  2152. chip_v7_set_chan_misc = 0x400024c4;
  2153. chip_v7_set_chan = 0x400024c8;
  2154. chip_v7_set_chan_offset = 0x400024cc;
  2155. chip_v7_set_chan_ana = 0x400024d0;
  2156. set_chanfreq = 0x400024d4;
  2157. rom_rxiq_cover_mg_mp = 0x400024d8;
  2158. rom_rfcal_rxiq = 0x400024dc;
  2159. rom_get_rfcal_rxiq_data = 0x400024e0;
  2160. rom_pbus_rx_dco_cal = 0x400024e4;
  2161. rom_rxdc_est_min = 0x400024e8;
  2162. rom_pbus_rx_dco_cal_1step = 0x400024ec;
  2163. rom_set_lb_txiq = 0x400024f0;
  2164. rom_set_rx_gain_cal_iq = 0x400024f4;
  2165. rom_set_rx_gain_cal_dc = 0x400024f8;
  2166. iq_est_enable = 0x400024fc;
  2167. iq_est_disable = 0x40002500;
  2168. dc_iq_est = 0x40002504;
  2169. set_cal_rxdc = 0x40002508;
  2170. rxiq_get_mis = 0x4000250c;
  2171. spur_reg_write_one_tone = 0x40002510;
  2172. spur_cal = 0x40002514;
  2173. spur_coef_cfg = 0x40002518;
  2174. gen_rx_gain_table = 0x4000251c;
  2175. wr_rx_gain_mem = 0x40002520;
  2176. set_rx_gain_param = 0x40002524;
  2177. set_rx_gain_table = 0x40002528;
  2178. rom_tester_wifi_cali = 0x4000252c;
  2179. esp_recover_efuse_data = 0x40002530;
  2180. /* bt_track_pll_cap = 0x40002534;*/
  2181. rfpll_cap_track = 0x40002538;
  2182. phy_param_track = 0x4000253c;
  2183. txpwr_correct = 0x40002540;
  2184. txpwr_cal_track = 0x40002544;
  2185. /* tx_pwctrl_background = 0x40002548;*/
  2186. bt_track_tx_power = 0x4000254c;
  2187. wifi_track_tx_power = 0x40002550;
  2188. rom_code_to_temp = 0x40002554;
  2189. rom_tsens_index_to_dac = 0x40002558;
  2190. rom_tsens_index_to_offset = 0x4000255c;
  2191. rom_tsens_dac_cal = 0x40002560;
  2192. rom_tsens_code_read = 0x40002564;
  2193. rom_tsens_temp_read = 0x40002568;
  2194. rom_temp_to_power = 0x4000256c;
  2195. tsens_read_init = 0x40002570;
  2196. get_temp_init = 0x40002574;
  2197. rom_txiq_cover = 0x40002578;
  2198. rom_rfcal_txiq = 0x4000257c;
  2199. rom_get_power_atten = 0x40002580;
  2200. rom_tx_pwctrl_init_cal = 0x40002584;
  2201. bt_txdc_cal = 0x40002588;
  2202. bt_txiq_cal = 0x4000258c;
  2203. txiq_cal_init = 0x40002590;
  2204. txdc_cal_init = 0x40002594;
  2205. txdc_cal_v70 = 0x40002598;
  2206. txiq_get_mis_pwr = 0x4000259c;
  2207. pwdet_ref_code = 0x400025a0;
  2208. pwdet_code_cal = 0x400025a4;
  2209. rfcal_txcap = 0x400025a8;
  2210. tx_cap_init = 0x400025ac;
  2211. rfcal_pwrctrl = 0x400025b0;
  2212. tx_pwctrl_init = 0x400025b4;
  2213. bt_tx_pwctrl_init = 0x400025b8;
  2214. bt_txpwr_freq = 0x400025bc;
  2215. rom_txbbgain_to_index = 0x400025c0;
  2216. rom_index_to_txbbgain = 0x400025c4;
  2217. rom_bt_index_to_bb = 0x400025c8;
  2218. rom_bt_bb_to_index = 0x400025cc;
  2219. rom_bt_get_tx_gain = 0x400025d0;
  2220. rom_get_tx_gain_value = 0x400025d4;
  2221. rom_wifi_get_tx_gain = 0x400025d8;
  2222. rom_set_tx_gain_mem = 0x400025dc;
  2223. rom_get_rate_fcc_index = 0x400025e0;
  2224. rom_get_chan_target_power = 0x400025e4;
  2225. rom_wifi_tx_dig_gain = 0x400025e8;
  2226. rom_wifi_set_tx_gain = 0x400025ec;
  2227. rom_bt_set_tx_gain = 0x400025f0;
  2228. wifi_11g_rate_chg = 0x400025f4;
  2229. bt_chan_pwr_interp = 0x400025f8;
  2230. bt_tx_gain_init = 0x400025fc;
  2231. /* Data (.data, .bss, .rodata) */
  2232. phy_param_rom = 0x3fcdfaa4;
  2233. /***************************************
  2234. Group rom_btbb
  2235. ***************************************/
  2236. /* Functions */
  2237. bt_agc_gain_offset = 0x40002600;
  2238. bt_agc_gain_max = 0x40002604;
  2239. bt_set_rx_comp = 0x40002608;
  2240. bt_agc_gain_set = 0x4000260c;
  2241. bt_agc_rssi_thresh = 0x40002610;
  2242. bt_agc_target_set = 0x40002614;
  2243. bt_agc_restart_set = 0x40002618;
  2244. bt_agc_recorrect_set = 0x4000261c;
  2245. bt_agc_detect_set = 0x40002620;
  2246. bt_bb_rx_correlator_set = 0x40002624;
  2247. bt_bb_rx_dpo_set = 0x40002628;
  2248. bt_bb_rx_filter_sel = 0x4000262c;
  2249. bt_bb_rx_set1 = 0x40002630;
  2250. bt_bb_v2_rx_set = 0x40002634;
  2251. bt_bb_v2_tx_set = 0x40002638;
  2252. bt_bb_tx_cca_set = 0x4000263c;
  2253. bt_bb_tx_cca_period = 0x40002640;
  2254. bt_bb_tx_cca_fifo_reset = 0x40002644;
  2255. bt_bb_tx_cca_fifo_empty = 0x40002648;
  2256. bt_bb_tx_cca_fifo_full = 0x4000264c;
  2257. bt_bb_tx_cca_fifo_count = 0x40002650;
  2258. bt_bb_tx_cca_fifo_read = 0x40002654;
  2259. coex_pti_v2 = 0x40002658;
  2260. bt_bb_set_le_tx_on_delay = 0x4000265c;
  2261. bt_bb_set_corr_thresh_le = 0x40002660;
  2262. /***************************************
  2263. Group rom_mbedtls md5
  2264. ***************************************/
  2265. mbedtls_md5_starts_ret = 0x40002be4;
  2266. mbedtls_md5_update_ret = 0x40002be8;
  2267. mbedtls_md5_finish_ret = 0x40002bec;